TPS92390RHBR [TI]
具有 4 个 200mA 通道的升压/SEPIC 高调光性能 LED 驱动器 | RHB | 32 | -40 to 125;型号: | TPS92390RHBR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 4 个 200mA 通道的升压/SEPIC 高调光性能 LED 驱动器 | RHB | 32 | -40 to 125 驱动 驱动器 |
文件: | 总78页 (文件大小:3050K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS92390
ZHCSMJ2 –MARCH 2021
具有四个200mA 通道的TPS92390 升压/SEPIC 高调光性能LED 驱动器
1 特性
3 说明
• 输入电压工作范围:3V 至48V
• 四路高精度电流阱
TPS92390 是一款具有升压控制器的汽车类 高效 LED
驱动器。四路高精度电流阱支持根据使用的通道数自动
调整相移。可通过 I²C 接口或 PWM 输入对 LED 亮度
进行全局控制。
– 各电流阱直流电流高达200mA
– 电流匹配度为1%(典型值)
– 使用152Hz LED 输出PWM 频率时,调光比为
32000:1
– 使用I2C 或PWM 输入时,最高16 位LED 调
光分辨率
升压控制器具有基于 LED 电流阱余量电压的自适应输
出电压控制。该特性可在所有条件下将升压电压调节到
能够满足需要的最低水平,从而最大限度降低功耗。凭
借宽范围可调频率, TPS92390 可避免调幅(AM) 射频
波段的干扰。
– 可配置8 个LED 灯串
• 自动移相PWM 调光
TPS92390 支持内置混合PWM 调光和模拟电流调光,
从而可降低 EMI、延长 LED 使用寿命并提高总光学效
率。
• 12 位模拟调光
• 开关频率为100kHz 至2.2MHz
• 升压扩频功能可降低EMI
• 升压同步输入,可通过外部时钟设置升压开关频率
• 最高48V VOUT 升压或SEPIC 直流/直流控制器
器件信息
器件型号(1)
TPS92390
封装尺寸(标称值)
封装
– 开关频率为100kHz 至2.2MHz
– 升压扩频功能可降低EMI
– 升压同步输入,可通过外部时钟设置升压开关频
率
QFN (32)
5mm × 5mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
• 多种故障诊断功能
2 应用
为以下应用提供背光:
• 显示器
• 电视
• 医疗显示
• 控制面板中的工业背光系统
• 工业PC
• 测试和测量设备
L
95
90
85
RISENSE
VIN
VOUT
CIN
COUT
SD
VSENSE_N
VSENSE_P
GD
PGND
ISNS
UVLO
ISNSGND
FB
TPS92390
VDD
C1N
LED_GND
C1P
OUT1
OUT2
OUT3
OUT4
CPUMP
80
VOUT = 29 V
VOUT = 36 V
SGND
EN
VOUT = 42 V
VOUT = 46 V
PWM
INT
BST_FSET
PWM_FSET
75
SDA
SCL
0
10
20
30
40
50
60
Brightness (%)
70
80 90 100
LED_SET
ISET
BST_SYNC
MODE
D007
系统效率
简化版原理图
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SNVSBY7
TPS92390
ZHCSMJ2 –MARCH 2021
www.ti.com.cn
Table of Contents
7.5 Programming............................................................ 37
7.6 Register Maps...........................................................40
8 Application and Implementation..................................55
8.1 Application Information............................................. 55
8.2 Typical Applications.................................................. 55
9 Power Supply Recommendations................................68
10 Layout...........................................................................69
10.1 Layout Guidelines................................................... 69
10.2 Layout Example...................................................... 70
11 Device and Documentation Support..........................71
11.1 Device Support........................................................71
11.2 接收文档更新通知................................................... 71
11.3 支持资源..................................................................71
11.4 Trademarks............................................................. 71
11.5 静电放电警告...........................................................71
11.6 术语表..................................................................... 71
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................6
6.6 Logic Interface Characteristics ...................................9
6.7 Timing Requirements for I2C Interface ...................... 9
6.8 Typical Characteristics..............................................10
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagram.........................................12
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................36
Information.................................................................... 72
4 Revision History
注:以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
March 2021
*
Initial Release
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5 Pin Configuration and Functions
32 31 30 29 28 27 26 25
LED_GND
LED_GND
OUT4
1
2
3
4
5
6
24
23
22
C1N
EN
VDD
LED_GND
OUT3
21 SD
DAP
20 VSENSE_N
19 VSENSE_P
OUT2
18
17
OUT1
UVLO
MODE
7
8
INT
9
10 11 12 13 14 15 16
图5-1. RHB Package 32-PIN QFN Top View
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表5-1. QFN Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
LED_GND
Analog
Analog
Analog
GND
LED ground connection.
2
LED_GND
OUT4
LED_GND
OUT3
OUT2
OUT1
INT
LED ground connection.
3
LED current sink output. If unused tie to ground.
LED ground connection.
4
5
Analog
Analog
Analog
Analog
Analog
Analog
LED current sink output. If unused tie to ground.
LED current sink output. If unused tie to ground.
LED current sink output. If unused tie to ground.
6
7
8
Device fault interrupt output, open drain. A 10-kΩpullup resistor is recommended.
SDA for I2C interface. A 10-kΩpullup resistor is recommended.
SCL for I2C interface. A 10-kΩpullup resistor is recommended.
9
SDA
10
SCL
Input for synchronizing boost. When synchronization is not used, connect this pin to ground
to disable spread spectrum or to VDD to enable spread spectrum.
11
BST_SYNC
Analog
12
13
14
15
16
17
18
19
PWM
SGND
Analog
GND
PWM input for brightness control. Tie to GND if unused.
Signal ground.
LED_SET
PWM_FSET
BST_FSET
MODE
Analog
Analog
Analog
Analog
Analog
Analog
LED string configuration through external resistor. Do not leave floating.
LED dimming frequency setup through external resistor. Do not leave floating.
Boost switching frequency setup through external resistor. Do not leave floating.
Dimming mode setup through external resistor. Do not leave floating.
Input voltage sense for programming input UVLO threshold through external resistor to VIN.
Pin for input voltage detection for OVP protection and positive input for input current sense.
UVLO
VSENSE_P
Negative input for input current sense. If input current sense is not used, please tie to
VSENSE_P pin.
20
21
22
VSENSE_N
SD
Analog
Analog
Power
Power line FET control. Open Drain output. If unused, leave this pin floating.
Power supply input for internal analog and digital circuit. Connect a 10-uF capacitor between
the VDD pin to GND.
VDD
23
24
25
EN
Analog
Analog
Analog
Enable input.
C1N
C1P
Negative input for charge pump flying capacitor. If feature not used leave this pin floating.
Positive input for charge pump flying capacitor. If feature not used leave this pin floating.
Charge pump output pin. Connect to VDD if charge pump is not used. A 4.7-µF decoupling
capacitor is recommended on CPUMP pin.
26
CPUMP
Power
27
GD
PGND
ISNS
Analog
GND
Gate driver output for external N-FET.
Power ground.
28
29
Analog
GND
Boost current sense pin.
30
ISNSGND
ISET
Current sense resistor GND.
LED full-scale current setup through external resistor.
Boost feedback input.
31
Analog
Analog
GND
32
FB
DAP
LED_GND
LED ground connection.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
VSENSE
_P + 0.3
Voltage on pins
Voltage on pins
Voltage on pins
VSENSE_N, SD, UVLO
V
V
V
VSENSE_P, FB , OUT1 to OUT4
52
6
C1N, C1P, VDD, EN, ISNS, ISNS_GND, INT, MODE, PWM_FSET, BST_FSET,
LED_SET, ISET, GD and CPUMP
VDD +
0.3
PWM, BST_SYNC, SDA, SCL
Continuous power dissipation(3)
V
–0.3
Internally
Limited
W
Ambient temperature, TA(4)
Junction temperature, TJ(4)
Lead temperature (soldering)
Storage temperature, Tstg
125
150
260
150
–40
–40
°C
°C
°C
Thermal
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages are with respect to the potential at the GND pins.
(3) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typical)
and disengages at TJ = 150°C (typical).
(4) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature
may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature
(TJ-MAX = 150°C), the power dissipation of the device in the application (P), the junction-to-board thermal resistance and the
temperature difference between the system board and the ambient (ΔtBA), which is given by the following equation: TA-MAX = TJ-MAX
(ΘJB × P) - ΔtBA
–
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
Electrostatic
V(ESD)
Corner pins (1, 19, 20 and 38)
Other pins
V
Charged device model (CDM), per AEC
Q100-011
discharge
±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
48
UNIT
VSENSE_P, VSENSE_N, SD, UVLO
FB , OUT1 to OUT4
3
12
0
48
ISNS, ISNSGND
0
0
5.5
5.5
5.5
5.5
125
Voltage on
pins
V
EN, PWM, INT, SDA, SCL, BST_SYNC
VDD
3.3
3.3/5
5
3
C1N, C1P, CPUMP,GD
Ambient temperature, TA
0
Thermal
°C
–40
(1) All voltages are with respect to the potential at the GND pins.
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UNIT
6.4 Thermal Information
Device
QFN
32-PIN
32.9
19.6
6.8
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ΨJT
6.8
ΨJB
RθJC(bot)
1.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design.
6.5 Electrical Characteristics
Limits apply over the full operation temperature range –40°C ≤TA ≤+125°C , unless otherwise speicified. VIN = 12 V, VDD
= 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
General Electrical Characteristics
IQ
Shutdown mode current, VDD pin
EN = L
1
5
µA
FSW = 303 kHz, PWM = H, BOOST-FET
IPD25N06S4L-30, Charge Pump
Disabled
IQ
Active mode current, VDD pin(1)
15
65
mA
FSW = 2200 kHz, PWM = H, BOOST-
FET IPD25N06S4L-30, Charge Pump
Disabled
IQ
IQ
IQ
Active mode current, VDD pin(1)
Active mode current, VDD pin(1)
Active mode current, VDD pin(1)
40
20
65
75
91
mA
mA
mA
FSW = 303 kHz, PWM = H, BOOST-FET
IPD25N06S4L-30, Charge Pump Enabled
FSW = 2200 kHz, PWM = H, BOOST-
FET IPD25N06S4L-30, Charge Pump
Enabled
104
CPUMP and LDO Electrical Characteristics
VCPUMP Voltage accuracy
VDD = 3.0 to 3.6 V; ILOAD = 1 to 50 mA
4.8
5
5.2
V
fCP
CP switching frequency
387
417
447
kHz
VCPUMP_
VCPUMP UVLO threshold
VCPUMP falling edge
VCPUMP rising edge
3.95
4.15
0.1
4.2
4.4
4.4
4.6
V
V
UVLO
VCPUMP_
VCPUMP UVLO threshold
VCPUMP UVLO hysteresis
Charge pump startup time
UVLO
VCPUMP_
0.2
V
HYS
TSTART_U
CCPUMP = 10 µF
1000
2000
µs
P
Protection Electrical Characteristics
VDDUVLO
VDD UVLO threshold
VDD falling
VDD rising
2.68
2.8
2.92
3.0
V
V
V
V
_F
VDDUVLO
VDD UVLO threshold
_R
VDDUVLO
VDD UVLO hysteresis
0.1
_H
VINUVLO_
UVLO pin threshold
VUVLO falling
0.753
0.777
0.801
TH
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6.5 Electrical Characteristics (continued)
Limits apply over the full operation temperature range –40°C ≤TA ≤+125°C , unless otherwise speicified. VIN = 12 V, VDD
= 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IUVLO
UVLO pin bias current
VUVLO = VUVLO_TH + 50v mV
µA
–5
VINOVP_T
OVP threshold
VSENSE_P rising
40.8
43
1.7
45.2
V
V
H
VINOVP_H
OVP hysteresis
Input OCP threshold
YS
VINOCP_T
187
150
220
253
180
mV
RISENSE = 20 mΩ
H
TSD
TSD
Thermal shutdown threshold(1)
Thermal shutdown hysteresis(1)
Temperature rising
165
20
°C
°C
ISD_LEAKA
SD leakage current
SD pull down current
VSD = 48 V
1
µA
GE
ISD
250
325
1.423
1.76
400
µA
V
RSD = 20 kΩ
VFB_OVPL FB pin - Boost OVP low threshold
VFB_OVPH FB pin - Boost OVP high threshold
VFB_UVP FB pin - Boost OCP threshold
V
0.886
V
VBST_OVP
Discharge pin - Boost OVP high threshold
48.5
100
50
1
51.8
V
H
Input PWM Electrical Characteristics
IPWM_LEA
PWM leakage current
VPWM = 5 V
µA
Hz
ns
KAGE
fPWM_IN
PWM input frequency
20000
200
tPWM_MIN
PWM input minimum on-time
Direct PWM mode
_ON
tPWM_MIN
Phase Shift PWM mode, Hybrid mode,
Current Dimming mode
PWM input minimum on-time
PWM input resolution
200
16
220
ns
bit
bit
_ON
PWM_IN
fPWM_IN = 100 Hz
fPWM_IN = 20 kHz
RES
PWM_IN
PWM input resolution
10
RES
LED Current Sink and LED PWM Electrical Characteristics
ILEAKAGE Leakage current on OUTx OUTx = VOUT = 45 V, EN= L
0.1
1.21
200
2.5
µA
V
VISET
IMAX
ISET voltage
1.17
1.25
Maximum LED sink current
OUTx
mA
VISET_UVL
ISET pin undervoltage
ISET Resistor range
0.97
15.6
1
1.03
104
V
O
RISET
IOUT = 30 mA to 200 mA
kΩ
mA
LED current limit when ISET pin short to
GND
ILED_LIMIT
280
RISET = 15.6 kΩ, IOUT = 150 mA, PWM =
IACC
LED sink current accuracy
LED sink current matching
4
%
%
–4
100%
RISET = 15.6 kΩ, IOUT = 150 mA, PWM =
100%
IMATCH
1
3.5
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6.5 Electrical Characteristics (continued)
Limits apply over the full operation temperature range –40°C ≤TA ≤+125°C , unless otherwise speicified. VIN = 12 V, VDD
= 3.3 V
PARAMETER
LED dimming frequency
LED dimming frequency
LED dimming frequency
LED dimming frequency
LED dimming frequency
LED dimming frequency
LED dimming frequency
LED dimming frequency
Dimming ratio
TEST CONDITIONS
PWM_FSET = 3.92 kΩ
MIN
141
TYP
152
MAX
163
UNIT
fDIM
fDIM
fDIM
fDIM
fDIM
fDIM
fDIM
fDIM
DIM
DIM
283
305
327
PWM_FSET = 4.75 kΩ
PWM_FSET = 5.76 kΩ
PWM_FSET = 7.87 kΩ
PWM_FSET = 11 kΩ
PWM_FSET = 17.8 kΩ
PWM_FSET = 42.4 kΩ
PWM_FSET = 124 kΩ
fPWM_OUT = 152 Hz
567
610
653
1135
2270
4541
9082
18163
1221
1307
2612
5225
10450
20899
Hz
2441
4883
9766
19531
32000:1
1000:1
Dimming ratio
fPWM_OUT = 4.88 kHz
VHEADRO
LED sink headroom
0.7
0.8
5.4
V
V
V
OM
VHEADRO
LED sink headroom hysteresis
LED internal short threshold
LED short to ground threshold
OM_HYS
VLEDSHO
RT
VSHORTG
0.24
200
V
ND
tPWM_OUT LED output minimum pulse
ns
Boost Converter Electrical Characteristics
fSW
fSW
fSW
fSW
fSW
fSW
fSW
fSW
VISNS
Switching Frequency
Switching Frequency
Switching Frequency
Switching Frequency
Switching Frequency
Switching Frequency
Switching Frequency
Switching Frequency
External FET current limit
93
186
100
200
107
214
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
mV
BST_FSET = 7.87 kΩ
BST_FSET = 4.75 kΩ
BST_FSET = 5.76 kΩ
BST_FSET = 3.92 kΩ
BST_FSET = 11 kΩ
281
303
325
372
400
428
465
500
535
1690
1860
2066
180
1818
2000
2222
200
1946
2140
2378
220
BST_FSET = 17.8 kΩ
BST_FSET = 42.4 kΩ
BST_FSET = 124 kΩ
VISNS threshold, RSENSE= 15 to 50 mΩ
VDD = 3.3 V
ISEL_MAX IDAC maximum current
36.4
38.7
40.2
µA
VGD/(RDS_ON + total resistance to gate
input of SW FET) must not be higher than
2.5 A
RDS_ONH RDSON of high-side FET to gate driver
1.4
Ω
VGD/(RDS_ON + total resistance to gate
input of SW FET) must not be higher than
2.5 A
RDS_ONL RDSON of low-side FET to gate driver
tSTARTUP Start-up time
0.75
50
Ω
Delay from beginning of boost Soft-start
to when LED drivers can begin
ms
TON
Minimum switch on-time
Minimum switch off time
150
150
ns
ns
TOFF
(1) This specification is not ensured by ATE
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6.6 Logic Interface Characteristics
Limits apply over the full operation temperature range –40°C ≤TA ≤+125°C , unless otherwise speicified. VIN = 12 V, VDD
= 5 V, VEN = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUT EN
VENIL
VENIH
RENPD
EN logic low threshold
0.4
V
V
EN logic high threshold
1.2
EN pin internal pull down resistance
1
MΩ
LOGIC INPUT SDA, SCL, BST_SYNC and PWM
VIL
VIH
Logic low threshold
Logic high threshold
VDD = 3.3 V and 5 V
0.4
V
V
VDD = 3.3 V and 5 V
1.2
LOGIC OUTPUT SDA, INT
VOL Output level low
ILEAKAGE Output leakage current
I = 3 mA
0.2
0.4
1
V
V = 3.3 V
µA
6.7 Timing Requirements for I2C Interface
Limits apply over the full operation temperature range –40°C ≤TA ≤+125°C , unless otherwise speicified. VIN = 12 V, VDD
= 5 V, VEN = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kHz
µs
fSCLK
1
Clock frequency
400
Hold time (repeated) START condition
Clock low time
0.6
1.3
600
600
50
2
µs
3
Clock high time
ns
4
Set-up time for a repeated START condition
Data hold time
ns
5
ns
6
Data setup time
100
ns
7
Rise time of SDA and SCL
Fall time of SDA and SCL
Set-up time for STOP condition
Bus free time between a STOP and a START condition
300
300
ns
8
ns
9
600
1.3
ns
10
µs
SDA
10
8
7
6
1
7
2
8
4
9
SCL
1
5
3
图6-1. I2C Timing Diagram
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6.8 Typical Characteristics
Unless otherwise specified: CIN = COUT = 2 × 10-μF ceramic and 2 × 33-μF electrolytic, VDD = 3.3 V, charge
pump enabled, TA = 25°C
100
95
90
85
80
75
100
95
90
85
80
75
70
65
60
VIN = 9 V
VIN = 9 V
VIN = 12 V
VIN = 16 V
VIN = 24 V
VIN = 12 V
VIN = 16 V
VIN = 24 V
0
10
20
30
40
Brightness (%)
50
60
70
80
90 100
0
10
20
30
40
Brightness (%)
50
60
70
80
90 100
D001
D002
8 LEDs/string
6 strings
150 mA/string
8 LEDs/string
6 strings
150 mA/string
ƒSW = 303 kHz
ƒSW = 2.2 MHz
L1 = 22 µH
L1 = 10 µH
图6-2. Boost Efficiency
图6-3. Boost Efficiency
90
85
80
75
70
65
60
55
85
80
75
70
65
60
55
50
VIN = 6 V
VIN = 12 V
VIN = 17 V
VIN = 6 V
VIN = 12 V
VIN = 17 V
0
10
20
30
40
Brightness (%)
50
60
70
80
90 100
0
10
20
30
40
Brightness (%)
50
60
70
80
90 100
D003
D004
2 LEDs/string
150 mA/string
6 strings
2 LEDs/string
150 mA/string
6 strings
ƒSW = 303 kHz
L1 = 10 µH, L2 = 15 µH
ƒSW = 2.2 MHz
L1 = L2 = 4.7 µH
图6-4. SEPIC Efficiency
图6-5. SEPIC Efficiency
150
120
90
60
30
0
2.5
2.0
1.5
1.0
0.5
0.0
15 mA
25 mA
50 mA
80 mA
120 mA
150 mA
0
8192 16384 24576 32768 40960 49152 57344 65536
Brightness Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Brightness Code
D005
D006
图6-6. Current Linearity
图6-7. Current Matching
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7 Detailed Description
7.1 Overview
The TPS92390 device is a high-voltage LED driver for large screen display LED backlight applications. PWM
input is used for brightness control by default. Alternatively, the brightness can also be controlled by I2C
Interface.
The boost frequency, LED PWM frequency, and LED string current are configured with external resistors through
the BST_FSET, PWM_FSET, and ISET pins. The INT pin is used to report faults to the system. Fault interrupt
status can be cleared with the I2C interface, or is cleared on the falling edge of the EN pin.
The TPS92390 supports pure PWM dimming. The six LED current drivers provide up to 200 mA per output and
can be tied together to support higher current LEDs. The maximum output current of the LED drivers is set with
the ISET resistor and can be optionally scaled by the LEDx_CURRENT[11:0] register bits with I2C interface. The
LED output PWM frequency is set with a PWM_FSET resistor. The number of connected LED strings is
configured by the LED_SET resistor, and the device automatically selects the corresponding phase shift mode.
For example, if the device is set to 4-strings mode, each LED output is phase shifted by 90 degrees with each
other(= 360 / 4). Unused outputs, which must be connected to GND, will be disabled and excluded from adaptive
voltage and won't generate any LED faults.
A resistor divider connected from VOUT to the FB pin sets the maximum voltage of the boost. For best efficiency,
the boost voltage is adapted automatically to the minimum necessary level needed to drive the LED strings by
monitoring all the LED output voltages continuously. The switching frequency of the boost regulator can be set
between 100 kHz and 2.2 MHz by the BST_FSET resistor. The boost has a start-up feature that reduces the
peak current from the power-line during start-up. The TPS92390 can also control a power-line FET to reduce
battery leakage when disabled and provide isolation and protection in the event of a fault.
Fault detection features of TPS92390 include:
• Open-string and shorted LED detection
– LED fault detection prevents system overheating in case of open or short in some of the LED strings
• LED short-to-ground detection
• ISET/BST_FSET/PWM_FSET/LED_SET/MODE resistor out-of-range detection
• Boost overcurrent
• Boost overvoltage
• Device undervoltage protection (VDD UVLO)
– Threshold sensing from VDD pin
• VIN input overvoltage protection (VIN OVP)
– Threshold sensing from VSENSE_P pin
• VIN input undervoltage protection (VIN UVLO)
– Threshold sensing from UVLO pin
• VIN input overcurrent protection (VIN OCP)
– Threshold sensing across voltage between VSENSE_P pin and VSENSE_N pin
• Thermal shutdown in case of die overtemperature
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7.2 Functional Block Diagram
SD
VSENSE_N
VSENSE_P
GD
Powerline
FET
Control
PGND
ISNS
ISNSGND
FB
+
Boost
Controller
UVLO
œ
VDD
C1N
Charge
Pump
C1P
CPUMP
PWM_FSET
BST_FSET
OSC
20 MHz
OTP
OUT1
OUT2
MODE
ADC
OUT3
OUT4
LED_SET
EN
BOOST
CONTROL
PWM
BST_SYNC
LED_GND
ISET
INT
SDA
SCL
LED
Current
Setting
I2C
Analog Blocks
VREF, TSD
SGND
7.3 Feature Description
7.3.1 Control Interface
Device control interface includes:
• EN is the enable input for the TPS92390 device.
• PWM is the default input to control the brightness of all current sinks by duty cycle.
• INT is an open-drain fault output indicating fault condition detection.
• SDA and SCL are data and clock line for I2C interface to control the brightness of all current sinks and read
back the fault conditions for diagnosis.
• BST_SYNC is used to input an external clock for the boost switching frequency and control the internal boost
clock mode.
– The external clock is auto detected at start-up and, if missing, the internal clock is used.
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– Optionally, the BST_SYNC can be tied to VDD to enable the boost spread spectrum function or tied to
GND to disable it.
• ISET pin to set the maximum LED current level per string.
7.3.2 Function Setting
Device parameter setting includes:
• BST_FSET pin is used to set the boost switching frequency through a resistor to signal ground.
• PWM_FSET pin is used to set the LED output PWM dimming frequency through a resistor to signal ground.
• MODE pin is used to set the dimming mode via an external resistor to signal ground.
• LED_SET pin is used to set the LED configuration through a resistor to signal ground.
• ISET pin is used to set the maximum LED current level per OUTx pin.
7.3.3 Device Supply (VDD)
All internal analog and digital blocks of TPS92390 are biased from external supply from VDD pin. Either a typical
5-V or 3.3-V supply rail is able to supply VDD from previous linear regulator or DC/DC converter with at least
200-mA current capability.
7.3.4 Enable (EN)
The TPS92390 only turns on when the input voltage of EN pin is above the voltage threshold (VENIH) and turns
off when the voltage of EN pin is below the threshold (VENIL). All analog and digital blocks start operating once
the TPS92390 is enabled by asserting EN pin. The SD pin is floating, I2C interface and Fault detection are not
active if the EN pin is de-asserted.
7.3.5 Charge Pump
An integrated regulated charge pump can be used to supply the gate drive for the external FET of the boost
controller. The charge pump is enabled or disabled by automatically detecting whether VDD and CPUMP pin are
connected together. If VDD is < 4.5 V then use the charge pump to generate a 5-V gate voltage to drive the
external boost switching FET. To use the charge pump, a 2.2-µF capacitor is placed between C1N and C1P. If
the charge pump is not required, C1N and C1P could be left unconnected and CPUMP pins tied to VDD. A 4.7-
µF CPUMP capacitor is used to store energy for the gate driver. The CPUMP capacitor is required to be used in
both charge pump enabled and disabled conditions and must be placed as close as possible to the CPUMP
pins. 图7-1and 图7-2 show required connections for both use cases.
VIN
3 to 48V
L
VOUT
CIN
COUT
SD
GD
PGND
ISNS
VSENSE_N
VSENSE_P
VDD
3.3V
ISNSGND
FB
VDD
CVDD
C1N
CFLY
C1P
CPUMP
CPUMP
图7-1. Charge Pump Enabled Circuit
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VIN
L
VOUT
3 to 48V
CIN
COUT
SD
GD
VSENSE_N
VSENSE_P
PGND
ISNS
VDD
5V
ISNSGND
FB
VDD
CVDD
C1N
C1P
CPUMP
CPUMP
图7-2. Charge Pump Disabled Circuit
If the charge pump is enabled, the CPCAP_STATUS bit shows whether a fly capacitor was detected and the
CP_STATUS bit shows status of any charge pump faults and generates an INT signal. The CP_INT_EN bit can
be used to prevent the charge-pump fault from causing an interrupt on the INT pin.
7.3.6 Boost Controller
The TPS92390 current-mode-controlled boost DC/DC controller generates the anode voltage for the LEDs. The
boost is a current-mode-controlled topology with a cycle by cycle current limit. The boost converter senses the
switch current and across the external sense resistor connected between ISNS and ISNSGND. A 20-mΩ sense
resistor results in a 10-A cycle by cycle current limit. The sense resistor value could vary from 15 mΩ to 50 mΩ
depending on the application. Maximum boost voltage is configured with external FB-pin resistor divider
connected between VOUT and FB. The FB-divider equation is described in 节7.3.6.3.
VOUT
VIN
COUT
CIN
CPUMP
Adaptive
voltage
control
R1
R2
+
GM
œ
VREF
FB
GD
+
COMP
œ
R
S
Q
Q
PGND
OVP
OCP
TSD
BOOST OSCILLATOR
ADC
BST_FSET
CURRENT RAMP
GENERATOR
OFF/BLANK TIME
PULSE GENERATOR
ISNS
+
MUX
GM
œ
ꢀ
BST_SYNC
ISNSGND
图7-3. Boost Controller Block Diagram
The boost switching frequency is adjustable from 100 kHz to 2.2 MHz via an external resistor at BST_FSET (see
表7-1). Resistor with 1% accuracy is needed to ensure proper operation.
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表7-1. Boost Frequency Selection
BOOST FREQUENCY (kHz)
R_BST_FSET (kΩ)
3.92
400
4.75
5.76
7.87
11
200
303
100
500
17.8
42.2
124
1818
2000
2222
7.3.6.1 Boost Cycle-by-Cycle Current Limit
The voltage between ISNS and ISNSGND is used for both boost DC/DC controller's current sensing and cycle-
by-cycle current limit settings. When the cycle-by-cycle current limit is reached, the controller will turn off the
switching MOSFET immediately and turn on it again in next siwtching cycle. This cycle-by-cycle current limit
could be used as a common protection for all related DC/DC components (inductor, schottky diode and switching
MOSFET) to avoid current running over their max limit. Cycle-by-Cycle current limit won't trigger any faults of the
device.
V
ISNS
ICYCLE_LIMIT
=
RSENSE
(1)
where
• VISNS = 200 mV
7.3.6.2 Controller Min On/Off Time
The device boost DC/DC controller has minimum on/off time as below table. Minimum off time should be
specially taken care in system design. The SW node rising time plus falling time should be higher than minimum
off time to avoid controller not turning off the MOSFET.
表7-2. Controller Minimum On/Off Time
Frequency (kHz)
100 to 500
Minimum Switch OFF Time (ns)
Minimum Switch ON Time (ns)
150
40
150
110
1818 to 2222
7.3.6.3 Boost Adaptive Voltage Control
The TPS92390 boost DC/DC converter generates the anode voltage for the LEDs. During normal operation,
boost output voltage is adjusted automatically based on the LED current sink headroom voltages. This is called
adaptive boost control. The number of used LED outputs is set by LED_SET pin and only the active LED outputs
are monitored to control the adaptive boost voltage. Any LED strings with open or short faults are also removed
from the adaptive voltage control loop. The LED driver pin voltages are periodically monitored by the control loop
and the boost voltage is raised if any of the LED outputs falls below the VHEADROOM threshold. The boost voltage
is lowered until any of the LED outputs touch the VHEADROOM threshold. See 图 7-4 for how the boost voltage
automatically scales based on the OUTx-pin voltage, VHEADROOM and VHEADROOM_HYS
.
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Boost
Increases
voltage
Boost
decreases voltage
No actions
OUT1~4 PIN
VOLTAGE
The lowest channel
voltage touches
VHEADROOM threshold
No output is close to
VHEADROOM threshold
One output is lower than
VHEADROOM threshold
VLEDSHORT
VHEADROOM+VHEADROOM_HYS
VHEADROOM
Normal
Conditions
Dynamic
Conditions
图7-4. Adaptive Boost Voltage Control Loop Function
The resistive divider (R1, R2) defines both the minimum and maximum adaptive boost voltage levels. The
feedback circuit operates the same in boost and SEPIC topologies. Choose maximum boost voltage based on
the maximum LED string voltage specification. Before the LED drivers are active, the boost starts up to the initial
boost level. The initial boost voltage is approximately in the 88% point of minimum to maximum boost voltage.
Once the LED driver channels are active, the boost output voltage is adjusted automatically based on OUTx pin
voltages. The FB pin resistor divider also scales the boost OVP, OCP levels and the LED short level in HUD
application.
7.3.6.3.1 FB Divider Using Two-Resistor Method
A typical FB-pin circuit uses a two-resistor divider circuit between the boost output voltage and ground.
VOUT
VIN
COUT
CIN
CPUMP
R1
+
VREF
GD
GM
œ
+
COMP
œ
R
S
Q
Q
FB
PGND
R2
+
BSTOVPH
BSTOVPL
BSTOCP
OVP
OCP
TSD
VOVPH
VOVPL
œ
+
œ
œ
VUVP
+
CURRENT RAMP
GENERATOR
ISNS
+
Pulse
Generator
ISEL[10:0]
GM
œ
ꢀ
ISNSGND
图7-5. Two-Resistor FB Divider Circuit
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Maximum boost voltage can be calculated with Equation 2. The maximum boost voltage can be reached during
OPEN string detection or if all LED strings are left disconnected.
≈
∆
«
’
R1
R2
VBOOST _MAX =ISEL _MAX ìR +
+1 ì V
÷
1
REF
◊
(2)
where
• VREF= 1.21 V
• ISEL_MAX = 38.7 µA
• R1 / R2 normal recommended range is 7~15
The minimum boost voltage must be less than the minimum LED string voltage. Minimum boost voltage is
calculated with Equation 3:
≈
∆
«
’
R
VBOOST_MIN
=
1 +1 ì V
÷
REF
R2
◊
(3)
where
• VREF = 1.21 V
When the boost OVP_LOW level is reached, the boost controller stops switching the boost FET and the
BSTOVPL_STATUS bit is set. The LED drivers are still active during this condition, and the boost resumes
normal switching operation once the boost output level falls. The boost OVP low voltage threshold changes
dynamically with current boost voltage. It is calculated in Equation 4:
≈
∆
«
’
R
VBOOST_OVPL = VBOOST
+
1 +1 ì(V
- VREF
)
÷
FB_OVPL
R2
◊
(4)
where
• VFB_OVPL = 1.423 V
• VREF = 1.21 V
When the boost OVP_HIGH level is reached the boost controller enters fault recovery mode, and the
BSTOVPH_STATUS bit is set. The boost OVP high-voltage threshold also changes dynamically with current
boost voltage and is calculated in Equation 5:
≈
∆
«
’
R
VBOOST_OVPH = VBOOST
+
1 +1 ì(VFB_OVPH - VREF
)
÷
R2
◊
(5)
where
• VFB_OVPH = 1.76 V
• VREF = 1.21 V
When the boost UVP level is reached the boost controller starts a 110-ms OCP counter. The TPS92390 device
enters the fault recovery mode and sets the BSTOCP_STATUS bit if the boost voltage does not rise above the
UVP threshold before the timer expires. The boost UVP voltage threshold also changes dynamically with current
boost voltage and is calculated in Equation 6:
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≈
∆
«
’
R
VBOOST_UVP = VBOOST
-
1 +1 ì(VREF - VUVP
)
÷
R2
◊
(6)
where
• VUVP = 0.886 V
• VREF = 1.21 V
7.3.6.3.2 FB Divider Using Three-Resistor Method
A FB-pin circuit using a three-resistor divider circuit can be used for applications where less than 200-kΩ
resistors are required.
VOUT
VIN
COUT
CIN
CPUMP
R1
+
GM
VREF
R3
GD
+
COMP
œ
œ
R
S
Q
Q
FB
PGND
R2
+
BSTOVPH
BSTOVPL
BSTOCP
OVP
OCP
TSD
VOVPH
VOVPL
œ
+
œ
œ
VUVP
+
CURRENT RAMP
GENERATOR
ISNS
+
Pulse
Generator
ISEL[10:0]
GM
œ
ꢀ
ISNSGND
图7-6. Three-Resistor FB Divider Circuit
Maximum boost voltage can be calculated with Equation 7. The maximum boost voltage can be reached during
OPEN string detection or if all LED strings are left disconnected.
≈
∆
«
’
≈
∆
«
’
R1 ìR
R2
R
VBOOST_MAX
=
3 +R +R ìI
+
1 +1 ìV
÷
÷
1
3
SEL_MAX
REF
R2
◊
◊
(7)
where
• VREF = 1.21 V
• ISEL_MAX = 38.7 µA
• R1 / R2 normal recommended range is 7 to 15
The minimum boost voltage must be less than the minimum LED string voltage. Minimum boost voltage is
calculated in Equation 8:
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≈
∆
«
’
R
VBOOST_MIN
=
1 +1 ì V
÷
REF
R2
◊
(8)
When the boost OVP_LOW level is reached the boost controller stops switching the boost FET, and the
BSTOVPL_STATUS bit is set. The LED drivers are still active during this condition, and the boost resumes
normal switching operation once the boost output level falls. The boost OVP low voltage threshold changes
dynamically with current boost voltage. It is calculated in Equation 9:
≈
∆
«
’
R
VBOOST_OVPL = VBOOST
+
1 +1 ì(V
- VREF
)
÷
FB_OVPL
R2
◊
(9)
where
• VFB_OVPL= 1.423 V
• VREF= 1.21 V
When the boost OVP_LOW level is reached the boost controller enters fault recovery mode, and the
BSTOVPH_STATUS bit is set. The boost OVP high-voltage threshold also changes dynamically with current
boost voltage and is calculated in Equation 10:
≈
∆
«
’
R
VBOOST_OVPH = VBOOST
+
1 +1 ì(VFB_OVPH - VREF
)
÷
R2
◊
(10)
where
• VFB_OVPH = 1.76 V
• VREF= 1.21 V
When the boost UVP level is reached the boost controller starts a 110-ms OCP counter. The TPS92390 device
enters the fault recovery mode and sets the BSTOCP_STATUS bit if the boost voltage does not rise above the
UVP threshold before the timer expires. The boost UVP voltage threshold also changes dynamically with current
boost voltage and is calculated in Equation 11:
≈
∆
«
’
R
VBOOST_UVP = VBOOST
-
1 +1 ì(VREF - VUVP
)
÷
R2
◊
(11)
where
• VUVP = 0.886 V
• VREF= 1.21 V
7.3.6.3.3 FB Divider Using External Compensation
The device has internal compensation network to keep the DC-DC control loop in good stability in most cases.
However, an additional external compensation network could also be added on FB-pin to offer more flexibility in
loop design or solving some extreme use-cases.
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VOUT
VIN
COUT
CIN
CPUMP
R1
+
GM
VREF
R4
R3
GD
+
COMP
œ
œ
R
S
Q
Q
FB
PGND
R2
CCOMP
+
BSTOVPH
BSTOVPL
BSTOCP
OVP
OCP
TSD
VOVPH
VOVPL
œ
+
œ
œ
VUVP
+
CURRENT RAMP
GENERATOR
ISNS
+
Pulse
Generator
ISEL[10:0]
GM
œ
ꢀ
ISNSGND
图7-7. External Compensation Network
This network will create one additional pole and one additional zero in the loop.
1
fPOLE_COMP
=
2p
(R ||R ) +R C
1
2
4
COMP
(12)
(13)
1
fZERO_COMP
=
2pR4CCOMP
It could be noted that R3 doesn't take part in the compensation. So this external compensation network could be
both used in two-divider netwrok and T-divider network with no equation change.
In real application, for example, when DC-DC loop has stability concern, putting the additional pole in 1 kHz and
the additional zero in 2 kHz will suppress the loop gain by approximately 6 dB after 2 kHz. This will benefit gain
margin and phase margin a lot.
7.3.6.4 Boost Sync and Spread Spectrum
Spread spectrum function could be enabled when BST_SYNC pin is high and disabled when BST_SYNC pin is
low.
If an external CLK signal is on the BST_SYNC pin, the boost controller can be clocked by this signal. If the clock
disappears later, the boost continues operation at the frequency defined by RBST_FSET resistor, and the
spread spectrum function will be enabled or disabled depending on the final pin level of BST_SYNC.
表7-3. Boost Synchronization Mode
BST_SYNC PIN LEVEL
Low (GND)
BOOST CLOCK MODE
Spread spectrum disabled
Spread spectrum enabled
High (VDDIO)
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表7-3. Boost Synchronization Mode (continued)
BST_SYNC PIN LEVEL
BOOST CLOCK MODE
100-kHz to 2222-kHz clock frequency
Spread spectrum disabled, external synchronization mode
If using the external BST_SYNC input, the RBST_SET resistor should be chosen the closest boost frequency
options with the external frequency.
The spread spectrum function helps to reduce EMI noise around the switching frequency and its harmonic
frequencies. The internal spread spectrum function modulates the boost frequency ±3.3% to 7.2% from the
central frequency with a 200-Hz to 1.2-kHz modulation frequency. The switching frequency variation is
programmable by SPREAD_RANGE register, and the modulation frequency is programmable by
SPREAD_MOD_FREQ register. The spread-spectrum function cannot be used when an external
synchronization clock is used.
表7-4. Spread Spectrum Frequency Range
SPREAD_RANGE (Binary)
SWITCHING FREQUENCY VARIATION
00
±3.3%
±4.3%
±5.3%
±7.2%
01
10 (Default)
11
表7-5. Spread Spectrum Modulation Frequency
SPREAD_MOD_FREQ (Binary)
MODULATION FREQUENCY
00 (Default)
200 Hz
500 Hz
800 Hz
1200 Hz
01
10
11
7.3.6.5 Light Load Mode
The DC-DC controller will enter into light load mode in below condition:
• VIN voltage is very close to VOUT
• Loading current is very low
• PWM pulse width is very short
When DC-DC converter enters into light load mode, it stops switching occasionally to make sure output voltage
won't rise up too much. It could also be called as PFM mode, since the DC-DC converter switching frequency
will change in this mode.
7.3.7 LED Current Sinks
7.3.7.1 LED Output Current Setting
The maximum output LED current is set by an external resistor value. For the application only using external
resistor RISET to set the maximum LED current for each string, the Equation 14 is used to calculate the current
setting of all strings:
1.21V
ILED
=
ì2580
RISET
(14)
The LEDx_CURRENT[11:0] registers can also be used to adjust strings current down from this maximum. The
default value for LEDx_CURRENT[11:0] registers is the maximum 0xFFF(4095). Equation 15 is used to calculate
the current setting of an individual string:
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≈
∆
«
’
1.21V
RISET
LED_CURRENT[11:0]
4095
≈
’
ILED
=
ì2580 ì
÷
∆
«
÷
◊
◊
(15)
For high accuracy of LED current, the ILED current is recommended to set in range from 30 mA to 200 mA. So
the RISET value is in the range from 15.6 kΩto 104 kΩ.
OUT1
OUT1 Current Sink
VDD
EXTERNAL
CURRENT
SETTING
ISET
EA
R
RISET
OUT2
OUT3
OUT4
OUT2 Current Sink
OUT3 Current Sink
OUT4 Current Sink
图7-8. LED Driver Current Setting Circuit
7.3.7.2 LED Output String Configuration
The Four LED driver channels of the TPS92390 device is configured by the LED_SET resistor, which supports
applications using one to Four LED strings. Resistor with 1% accuracy is needed to ensure proper operation.
The driver channels can also be tied together in groups of one, two or three. This allows the TPS92390 device to
drive two 400-mA LED strings, or one 800-mA LED string. The LED strings are always appropriately phase
shifted for their string configuration. This reduces the ripple seen at the boost output, which allows smaller output
capacitors and reduces audible ringing in the capacitors. Phase shift increases the load frequency, which can
move potential capacitor noise above the audible band while still keeping PWM frequency low to support a
higher dimming ratio.
When the TPS92390 device is firstly powered on, the string configuration is configured by the LED_SET resistor
and the phases of each channel are automatically configured. The LED string configuration must not be changed
unless the TPS92390 is powered off in shutdown state. The unused LEDx pins should be tied to ground.
表7-6. LED Output String Configuration
AUTOMATIC
PHASE SHIFT
CONFIGURATION
OUT1
OUT2
OUT3
OUT4
R_LED_SET (kΩ)
3.92
4 Channels
3 Channels
2 Channels
2 Channels
1 Channels
200 mA
200 mA
200 mA
200 mA
200 mA
200 mA
200 mA
200 mA
200 mA
90°
4.75
5.76
7.87
11
(Tied to GND)
(Tied to GND)
120°
(Tied to GND)
180°
400 mA
400 mA
180°
800 mA
None
7.3.7.3 LED Output PWM Clock Generation
The LED PWM frequency is asynchronous from the input PWM frequency. The LED PWM frequency is
generated from the internal 20-MHz oscillator and can be set to eight discrete frequencies from 152 Hz to 19.531
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kHz. The PWM dimming resolution is highest when the lowest PWM frequency is used. The PWM_FSET resistor
determines the LED PWM frequency based on 表7-8. PWM resolution in 表7-8 is with PWM dither disabled.
7.3.8 Brightness Control
The TPS92390 supports global brightness control for all LED strings through either duty cycle input on PWM pin
or register by I2C bus. An internal 20-MHz clock is used for generating PWM outputs.
7.3.8.1 Brightness Control Signal Path
The BRT_MODE register selects whether the input to the display brightness path is the PWM input pin or
DISP_BRT register. PWM input control will be the default setup after power on. The brightness control signal
path diagram is shown in 图7-9
The display brightness path has sloper function that can be enabled. By default the sloper function is enabled.
The sloper and dither function also can be programmable by I2C control. The sloper function is described in 节
7.3.8.7, and the dither function is described in 节7.3.8.9.
MODE Resistor
OUT1
DITHER_SELECT[3:0]
OUT2
MODE Resistor
OUT3
OUT4
PWM
Detector
LED
DRIVER
MUX
PWM
BRT_MODE[1:0]
MUX
PWM
GENERATOR
PHASE
SHIFT
Dither
HYBIRD
DIMMING
SLOPER
REGISTERS
PWM_FSET Resistor
I2C
ADV_SLOPE_EN
SLOPE_SELECT[2:0]
DISPLAY
BRIGHTNESS
AUTO_LED_STRING_CFG[3:0]
PWM_FSET Resistor
CURRENT
MULTIPLIER
LED_
CURRENT
ISET Resistor
图7-9. TPS92390 Brightness Path Diagram
7.3.8.2 Dimming Mode
Dimming mode can be adjusted via an external resistor to MODE pin (see 表 7-7). Resistor with 1% accuracy is
needed to ensure proper operation.
表7-7. Dimming Mode Configuration
MODE
I2C Address
0x3B
R_MODE (kΩ)
3.92
4.75
5.76
7.87
11
Phase-shift PWM Mode
Hybrid Mode
0x3B
Current Dimming Mode
Direct PWM Mode
Phase-shift PWM Mode
Hybrid Mode
0x3B
0x3B
0x3A
17.8
42.2
124
0x3A
Current Dimming Mode
Direct PWM Mode
0x3A
0x3A
7.3.8.3 LED Dimming Frequency
The LED dimming frequency is asynchronous from the input PWM frequency for phase-shift PWM mode and
hybrid dimming mode. The LED dimming frequency is generated from the internal 20-MHz oscillator and can be
set to eight discrete frequencies from 152 Hz to 19.531 kHz. The PWM dimming resolution is highest when the
lowest PWM frequency is used. The PWM_FSET resistor determines the LED Dimming frequency based on 表
7-8. Resistor with 1% accuracy is needed to ensure proper operation. PWM resolution in 表 7-8 is with PWM
dither disabled.
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表7-8. LED PWM Frequency Selection
LED PWM FREQUENCY (Hz)
PWM DIMMING RESOLUTION (bits)
R_PWM_FSET (kΩ)
3.92
4.75
5.76
7.87
11
152
305
16
16
15
14
13
12
11
10
610
1221
2441
4883
9766
19531
17.8
42.2
124
7.3.8.4 Phase-Shift PWM Mode
In Phase-Shift PWM mode, all current active channels are turned on and off at LED dimming frequency with a
constant delay. However, the number of used channels or channel groups determine the phase delay time
between two neighboring channels as shown in 图7-10.
DISPLAY_BRT
0xFFFF
0xBFFF
0x7FFF
0x3FFF
0x1FFF
0x0FFF
0x07FF
D=100%
D=75%
D=50%
D=25%
D=12.5%
D=6.25%
D=3.125%
PWM
Input
TON
TPWM
LED Dimming Frequency
ILED1
ILED2
ILED3
ILED4
Phase-shift Mode
图7-10. Phase-shift Dimming Diagram
7.3.8.5 Hybrid Mode
In addition to phase-shift PWM dimming, TPS92390 supports a hybrid-dimming mode. Hybrid dimming combines
PWM and current modes for brightness control for the display brightness path. By using hybrid dimming,
dimming ratio could be increased by another 8 times. In hybrid mode, PWM dimming is used for low brightness
range of brightness, and current dimming is used for high brightness levels as shown in 图 7-11. Current
dimming control enables improved optical efficiency due to increased LED efficiency at lower currents. PWM
dimming control at low brightness levels ensures linear and accurate control. Hybrid mode can be selected
through resistor value at MODE pin as 表 7-7. The PWM and current modes transition threshold can be set at
12.5% or at 0% brightness. The latter selection allows for pure current dimming control mode.
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DISPLAY_BRT
0xFFFF
0xBFFF
0x7FFF
0x3FFF
0x1FFF
0x0FFF
0x07FF
D=100%
D=75%
D=50%
D=25%
D=12.5%
D=6.25%
D=3.125%
PWM
Input
TON
TPWM
100% ILED
75%
50%
ILED
D=50%
D=25%
25%
LED Dimming Frequency
12.5%
0A
12.5% Hybird Mode
图7-11. Hybrid Dimming Diagram
7.3.8.6 Direct PWM Mode
In direct PWM mode, all active channels are turned on and off and are synchronized with the input PWM signal.
D=100%
D=80%
D=60%
D=50%
D=25%
D=12.5%
D=6.25%
PWM
Input
TON
TPWM
100% ILED
ILED
0A
Direct PWM Mode
图7-12. Direct PWM Dimming Diagram
7.3.8.7 Sloper
An optional sloper function makes the transition from one brightness value to another optically smooth. By
default the advanced sloper is enabled with a 200-ms linear sloper duration. Transition time between two
brightness values is programmed with the SLOPE_SELECT[2:0] bits (when 000, sloper is disabled). With
advanced sloper enabled the brightness changes are further smoothed to be more pleasing to the human eye.
Advanced slope is enabled with ADV_SLOPE_ENABLE register bit.
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Brightness
Sloper Input
Time
Brightness
Sloper Output
Advanced Slope
Linear Slope
Slope Time
Time
图7-13. Brightness Sloper
7.3.8.8 PWM Detector Hysteresis
PWM detector has an internal hysteresis function. It means when PWM input is used (except direct PWM mode),
PWM output duty cycle will change only when PWM input on-time changes by more than 6.4us. This is to avoid
the PWM duty cycle sampling error due to the onboard PWM signal's rising/falling time.
7.3.8.9 Dither
The number of brightness steps when using LED output PWM dimming is equal to the 20-MHz oscillator
frequency divided by the LED PWM frequency (set by PWM_FSET resistor). The PWM duty cycle dither is a
function the TPS92390 uses to increase the number of brightness dimming steps beyond this oscillator clock
limitation. The dither function modulates the LED driver output duty cycle over time to create more possible
average brightness levels. The DITHER_SELECT[3:0] register bits control the level of dither, disabled, 1, 2, 3 or
4 bits using the I2C interface. By default the dither is disabled.
When the 1-bit dither is selected, to support higher brightness resolution, the width of every second PWM pulse
could be increased by one LSB (one 20-MHz clock period). When the 3-bit dither is selected, within a sequence
of 8 PWM periods the number of pulses with increased length varies depending on the dither value: dither value
000 - all 8 pulses at default length; 001 - one of the 8 pulses is longer; 010 - two of the 8 pulses are longer, and
so forth, until at 111 - seven of the 8 pulses have increased length. 图 7-14 shows one example of PWM output
dither.
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50.00225%
100 Hz
Input PWM
1.2 kHz LED
PWM
Without Dither
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
1.2 kHz LED
PWM
With 3bit Dither
50.006%
50.006%
50.006%
图7-14. PWM Dither Example
The dither block also helps in low brightness scenario when dimming ratio is limited by LED PWM output
frequency and the LED output pulse is less than the minimum pulse width (200 ns). In such scenario, the dither
block will skip some of the PWM pulses to reduce the brightness further, enabling high dimming ratio. The end
result is that the LED PWM frequency is reduced as more and more minimum pulses are skipped or dithered
out. At the same time, dither block will also guarantee that the minimum LED PWM frequency is not less than
152 Hz to ensure no brightness flickering. 图7-15 shows how the dither works in low brightness scenario.
100 Hz
Input PWM
300 ns = 0.003%
300 ns = 0.003%
200 ns
No
Pulse
200 ns
No
Pulse
305 Hz LED PWM
With Minimum Pulse
Dither
3.2 ms
3.2 ms
3.2 ms
3.2 ms
Average Brightness = 0.003%
图7-15. Minimum Brightness Dither Example
7.3.9 Protection and Fault Detections
The TPS92390 device includes fault detections for LED open, short and short-to-GND conditions, boost input
undervoltage, overvoltage and overcurrent, boost output overvoltage and overcurrent, VDD undervoltage, die
overtemperature and external components. The host can monitor the status of the faults in registers
SUPPLY_FAULT_STATUS, BOOST_FAULT_STATUS and LED_STATUS.
7.3.9.1 Supply Faults
7.3.9.1.1 VIN Undervoltage Faults (VINUVLO)
The TPS92390 device supports VIN undervoltage and overvoltage protection. The undervoltage threshold is
programmable through external resistor divider on UVLO pin. If during operation of the TPS92390 device, the
UVLO pin voltage falls below the UVLO falling level (0.787 V typical), the boost, LED outputs, and power-line
FET will be turned off, and the device will enter STANDBY mode. The VINUVLO_STATUS bit is also set in the
SUPPLY_FAULT_STATUS register, and the INT pin is triggered. When the UVLO voltage rises above the rising
threshold level the TPS92390 exits STANDBY and begins the start-up sequence.
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VIN
L
VOUT
3 to 48V
CIN
COUT
SD
VSENSE_N
VSENSE_P
GD
PGND
ISNS
R4
R5
UVLO
3.3V/5V
ISNSGND
FB
VDD
SGND
图7-16. VIN UVLO Setting Circuit
The following equation is used to calculate the UVLO threshold for VIN rising edge:
R4
VINUVLO_RISING = (
+1)ìVINUVLO_TH
R5
(16)
where
• VINUVLO_TH = 0.787 V
The hysteresis of UVLO threshold can be designed and calculated with the following equation.
VINHYST = R4 ìIUVLO
(17)
where
• IUVLO = 5 µA
So the following equation can be used for UVLO threshold for VIN falling edge:
VINUVLO_FALLING = VINUVLO_RISING-VINHYST
(18)
The bottom resistors, R5 of voltage divider is able to be disconnected to the GND through an additional external
N-type of FET as 图 7-17. This design is to minimize the current leakage from VIN in shutdown mode to extend
the battery life.
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VIN
3 to 48V
L
VOUT
CIN
COUT
SD
VSENSE_N
VSENSE_P
GD
PGND
ISNS
R4
R5
UVLO
3.3V/5V
EN
ISNSGND
FB
VDD
SGND
图7-17. VIN UVLO Setting Circuit Without Current Leakage Path
7.3.9.1.2 VIN Overvoltage Faults (VINOVP)
The overvoltage threshold for VIN rising edge is internal fixed at typical 43 V. If during TPS92390 operation,
VSENSE_P pin voltage rises above the OVP rising threshold, boost, LED outputs, and power-line FET will be
turned off, and the device will enter STANDBY mode. The VINOVP_STATUS bit will also be set in the
SUPPLY_FAULT_STATUS register, and the INT pin will be triggered. When the VSENSE_P pin voltage falls
below the falling threshold level, the TPS92390 exits STANDBY and begins the start-up sequence.
7.3.9.1.3 VDD Undervoltage Faults (VDDUVLO)
If during TPS92390 device operation VDD falls below VDDUVLO falling level, boost, power-line FET, and LED
outputs are turned off, and the device enters STANDBY mode. The VDDUVLO_STATUS fault bit will be set in
the SUPPLY_FAULT_STATUS register, and the INT pin will be triggered. The TPS92390 restarts automatically to
ACTIVE mode when VDD rises above VDDUVLO rising threshold.
7.3.9.1.4 VIN OCP Faults (VINOCP)
If during TPS92390 device operation voltage drop on RISENSE resistor rises above 220 mV, boost, power-line
FET, and LED outputs are turned off, and the device enters Fault Recovery mode and then attempt to restart 100
ms after fault occurs. The VINOCP_STATUS fault bit are set in the SUPPLY_FAULT_STATUS register, and the
INT pin is triggered.
VINOCP_ TH
IVIN_OCP
=
RISENSE
(19)
where
• VINOCP_TH = 220 mV
7.3.9.1.4.1 VIN OCP Current Limit vs. Boost Cycle-by-Cycle Current Limit
VIN OCP current limit is totally different from boost cycle-by-cycle current limit.
Boost cycle-by-cycle current limit is to protect the DC/DC components (inductor, schottky diode and switching
MOSFET) in normal scenario, avoiding current running over their max limit. The normal scenario means when
loading has sharp change or input voltage has sharp change. It won't trigger any device fault.
VIN OCP current limit is to protect system from ciritical system hazard (e.g, inductor short, switching MOSFET
short). It will trigger the device to shutdown all the LED channels and enter into fault recovery state.
VIN OCP current limit should be always greater than boost cycle-by-cycle current limit. This means RISENSE
should be always no smaller than RSENSE
.
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7.3.9.1.5 Charge Pump Faults (CPCAP, CP)
If during TPS92390 device operation voltage of CPUMP pin falls below typical 4.2-V, boost, power-line FET, and
LED outputs are turned off, and the device enters Fault Recovery mode and then attempt to restart 100 ms after
fault occurs. The CP_STATUS fault bit will beset in the SUPPLY_FAULT_STATUS register, and the INT pin are
triggered.
If during TPS92390 device initialization, the charge pump fly capacitor is disconnected or shorted, charge pump
are turned off. In result, boost, power-line FET, and LED outputs are turned off, and the device enters Fault
Recovery mode and then attempt to restart 100 ms after fault occurs. Both CPCAP_STATUS and CP_STATUS
fault bits are set in the SUPPLY_FAULT_STATUS register, and the INT pin are triggered.
7.3.9.1.6 CRC Error Faults (CRCERR)
If during TPS92390 device initialization, the factory default configuration for registers, options and trim bits are
not corrected loaded from memory, TPS92390 keeps operating normally, unless other fault criteria is triggered.
The CRCERR_STATUS fault bit are set in the SUPPLY_FAULT_STATUS register and the INT pin are triggered.
7.3.9.2 Boost Faults
7.3.9.2.1 Boost Overvoltage Faults (BSTOVPL, BSTOVPH)
Boost overvoltage is detected if the FB pin voltage exceeds the VFB_OVPL threshold. When boost overvoltage is
detected, BSTOVPL_STATUS bit will be set in the BOOST_FAULT_STATUS register. The boost FET stops
switching, and the output voltage will be automatically limited. If the BSTOVPL_STATUS bit is continually set
(that is, reappears after clearing), it may indicate an loop issue in the application. Boost overvoltage low is
monitored during device Boost Softstart and Normal mode.
A second boost overvoltage high fault is detected if the FB pin voltage exceeds the VFB_OVPH threshold or the
DISCHARGE pin voltage exceeds the VBST_OVPH. The TPS92390 device enters the fault recovery state to
protect system damage from a high boost voltage. When boost overvoltage is detected, BSTOVPH_STATUS bit
is set in the BOOST_FAULT_STATUS register. A fault interrupt is also generated. The device enters Fault
Recovery mode and then attempt to restart after 100 ms. Boost overvoltage high is monitored during Boost
Softstart and Normal mode.
7.3.9.2.2 Boost Overcurrent Faults (BSTOCP)
Boost overcurrent is detected if the FB pin voltage drops below the VUVP threshold for 110 ms. If the boost
overcurrent timer expires before the output voltage recovers, the BSTOCP_STATUS bit is set in the
BOOST_FAULT_STATUS register. The fault recovery state is entered, and a fault interrupt is generated. The
device will enter Fault Recovery mode and then attempt to restart after 100 ms. If the BSTOCP_STATUS bit is
permanently set, it may indicate an issue in the application. Boost overcurrent is monitored from the boost start,
and fault may trigger during boost start-up.
7.3.9.2.3 LEDSET Resistor Missing Faults (LEDSET)
The LEDSET resistor missing or invalid is detected if the resistor is not assembled or not valid value as
requested during the initialization. The TPS92390 device defaults to 4-channel/200-mA configuration if the
LEDSET resistor is missing or invalid. The LEDSET_STATUS fault bit is set in the BOOST_FAULT_STATUS
register. The LEDSET resistor missing or invalid fault will not be monitored after initialization, so that the
TPS92390 is operating in the configuration determined during initialization even though the LEDSET resistor is
missing or invalid after initialization.
7.3.9.2.4 MODE Resistor Missing Faults (MODESEL)
The MODE resistor missing or invalid is detected if the resistor is not assembled or not valid value as requested
during the initialization. TPS92390 defaults to phase-shift PWM mode with I2C address 0x3A if the MODE
resistor is missing or invalid. The MODESEL_STATUS fault bit will be set in the BOOST_FAULT_STATUS
register. The MODE resistor missing or invalid fault is not monitored after initialization, so that the TPS92390
operates in the mode determined during initialization even though the MODE resistor is missing or invalid after
initialization.
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7.3.9.2.5 FSET Resistor Missing Faults (FSET)
The FSET resistor missing or invalid for both BOOST_FSET and PWM_FSET is detected if any one of them is
not assembled or not a valid value as requested during the initialization. TPS92390 defaults the switching
frequency of boost to 400 kHz if BOOST_FSET resistor is missing or invalid, or PWM dimming frequency to 305
Hz if PWM_FSET resistor is missing or invalid. The FSET_STATUS fault bit is set in the
BOOST_FAULT_STATUS register. The FSET resistor missing or invalid fault is not monitored after initialization,
so that the TPS92390 device operates at the boost switching frequency and the PWM dimming frequency
determined during initialization even though the FSET resistor is missing or invalid after initialization.
7.3.9.2.6 ISET Resistor Out of Range Faults (ISET)
If the ISET pin resistor is shorted to GND during normal operation, the maximum current for each LED channel
can be calculated in Equation 20:
LED_CURRENT[11:0]
≈
’
ILED_ISET_FAULT = ILED_LIMIT
ì
∆
«
÷
◊
4095
(20)
where
• ILED_LIMIT = 280 mA
LED_CURRENT[11:0] register will be automatically modified to 1/4 of latest programmed data. if it is not
programmed after device enabling, the default value of LED_CURRENT[11:0] register is 0xFFF and
automatically modified to 0x3FF after the fault occurs. If ISET pin voltage returns back to above 1.1 V, the
LED_CURRENT[11:0] register data automatically returns to latest programmed data. The ISET_STATUS fault bit
will be set in the BOOST_FAULT_STATUS register and the INT pin is triggered.
7.3.9.2.7 Thermal Shutdown Faults (TSD)
If the die temperature of TPS92390 reaches the thermal shutdown threshold TSD, the boost, power-line FET, and
LED outputs on TPS92390 shuts down to protect the device from damage. Fault status bit TSD_STATUS bit will
be set, and the INT pin will be triggered. The device restarts the power-line FET, the boost, and LED outputs
when temperature drops by TSD_HYS amount.
7.3.9.3 LED Faults
7.3.9.3.1 Open LED Faults (OPEN_LED)
During normal boost operation, boost voltage is raised if any of the used LED outputs falls below the
LED_DRV_HEADROOM threshold level. Open LED fault is detected if boost output voltage has reached the
maximum and at least one LED output is still below the threshold. The open string is then disconnected from the
boost adaptive control loop and its output is disabled. Any LED fault sets the status bit LED_STATUS and an
interrupt is generated unless LED interrupt is disabled. The detail of open LED faults can be read from bits
OPEN_LED and LEDx_FAULT (x = 1...4). These bits maintain their value until device power-down. But the
LED_STATUS bit could be cleared by the interrupt clearing procedure. If a new LED fault is detected,
LED_STATUS is set and an interrupt generated again.
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OUT1~4 PIN
VOLTAGE
Open LED fault
when
VBOOST = MAX
Short LED fault ( at least one
output should be between
LOW_COMP and MID COMP)
No actions
Short LED
Fault
Open LED Fault
LED Short to
GND Fault
VLEDSHORT
VHEADROOM+VHEADROOM_HYS
VHEADROOM
VSHORTGND
Normal
Fault Conditions
Conditions
图7-18. LED Open and Short Detection Logic
7.3.9.3.2 Short LED Faults (SHORT_LED)
Short LED fault is detected if one or more LED outputs are above the VLEDSHORT typical 5.4 V and at least one
LED output is inside the normal operation window (see 图 7-18). Shorted string is disconnected from the boost
adaptive control loop and the LED PWM output is disabled. LED_STATUS status bit is set and an interrupt
generated similarly as in open LED case. Detailed shorted LED fault can be read from bits SHORT_LED and
LEDx_FAULT (x = 1...4), indicating the faulty LED) in LED_FAULT_STATUS register.
In HUD application, when output channels are connected as groups and only one or two groups are active, one
more special condition will trigger the short LED fault. This is when boost adaptive voltage comes to minimum
and one of the LED channels voltage is still higher than VHEADROOM + VHEADROOM_HYS
.
7.3.9.3.3 LED Short to GND Faults (GND_LED)
During boost soft start and normal boost operation, if LED output is lower than VSHORTGND for 20 ms, device
turns off the corresponding LED output channel and output a typical 6-mA current for 300-µs period again. After
this operation, if output voltage is still lower than VHEADROOM, LED short to GND fault will be reported.
If LED short to GND is reported, boost, LED outputs and power-line FET is turned off, the device will enter Fault
Recovery mode. LED_STATUS bit is set and an interrupt generated similarly as in open LED case. LED short to
GND fault reason can be read from bits LED_GND and LEDx_FAULT (x = 1...4) in LED_FAULT_STATUS
register. These bits maintain their value until device powers are down while the LED_STATUS bit is cleared by
the interrupt clearing procedure.
7.3.9.3.4 Invalid LED String Faults (INVSTRING)
During device initialization, any of un-used LED outputs pins are checked whether connected to GND or not. If
they are not connected to GND as expected, the TPS92390 reports invalid string fault and tries to function
normally if possible. The INVSTRING_STATUS fault bit is set in the LED_FAULT_STATUS register, and the INT
pin is triggered. The LEDSET resistor missing or invalid fault is not detected after initialization, so that the
TPS92390 operates in the configuration determined during initialization even though the LEDSET resistor is
missing or invalid after initialization.
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7.3.9.3.5 I2C Timeout Faults
If chip receives I2C command without STOP signal for 500 ms, I2C communication block auto resets and waits
for the next command. I2C_ERROR_STATUS fault bit is set in the LED_FAULT_STATUS register, and the INT
pin is triggered.
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7.3.9.4 Overview of the Fault and Protection Schemes
表7-9. Fault and Protection Schemes
TRIGGER FAULT
ENTER FAULT
RECOVERY
FAULT NAME
STATUS BIT
CONDITION
INTERRUPT
ACTION
Device goes to standby and then attempts to
restart once the input voltage rises above
threshold.
VIN undervoltage
VINUVLO_STATUS
UVLO voltage falls below 0.787 V.
Yes
Yes
Device goes to standby and waits until input
voltage falls below threshold before restarting.
VIN overvoltage
VDD undervoltage
VIN overcurrent
Charge pump fault
VINOVP_STATUS
VDDUVLO_STATUS
VINOCP_STATUS
CP_STATUS
VIN voltage rises above 43 V.
Yes
Yes
Yes
Yes
Yes
No
VDD level falls below VDDUVLO
threshold.
Device restarts once VDD level rises above
VDDUVLO threshold.
Device goes to Fault Recovery and then attempts
to restart 100 ms after fault occurs.
Voltage across RISENSE exceeds 220 mV.
Charge pump voltage level is abnormal.
Yes
Yes
Device goes to Fault Recovery and then attempts
to restart 100 ms after fault occurs.
Charge pump is disabled. Charge pump fault will
be reported. Device tries to keep normal
operation.
Charge pump components
missing
CPCAP_STATUS
Charge pump is missing components.
Yes
Yes
No
No
Defaults to internal clock frequency selected by
BST_FSET resistor. If BST_SYNC input is held
high then spread spectrum is enabled. If
BST_SYNC input is held low then spread
spectrum is disabled.
Device is enabled while a valid external
SYNC clock is running. Then SYNC
stops or changes to frequency < 75 kHz.
Boost sync clock invalid
fault
BSTSYNC_STATUS
Factory default configuration for registers,
options and trim bits are not correctly
loaded from memory.
CRC error
CRCERR_STATUS
BSTOVPLOW_STATUS
BSTOVPH_STATUS
Yes
No
No
No
Device functions normally, if possible.
Boost stops switching until boost voltage level
falls. The device remains in normal mode with
LED drivers operational.
FB pin voltage rises above VFB_OVPL
level.
Boost OVP low
Boost OVP high
FB pin voltage rises above VFB_OVPH
level or DISCHARGE pin voltage rises
Device goes to Fault Recovery and waits until
output voltage falls below threshold before
restarting.
Yes
Yes
above VBST_OVPH
.
FB pin voltages falls below VUVP level for
110 ms.
Device goes to Fault Recovery and then attempts
to start 100 ms after fault occurs.
Boost overcurrent
BSTOCP_STATUS
LEDSET_STATUS
MODESEL_STATUS
Yes
No
No
Yes
No
No
LEDSET detection fault
MODE detection fault
LEDSET resistor missing or invalid.
MODE resistor missing or invalid.
Defaults to 4-channel / 200mA configuration.
Defaults to phase-shift PWM mode, I2C address
is 0x3A.
Device keeps operating at 400-kHz switching
frequency for boost converter and 305 Hz for
PWM dimming frequency.
BST_FSET or PWM_FSET resistor are
missing or an invalid value.
FSET detection fault
FSET_STATUS
No
No
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表7-9. Fault and Protection Schemes (continued)
TRIGGER FAULT
INTERRUPT
ENTER FAULT
RECOVERY
FAULT NAME
STATUS BIT
CONDITION
ACTION
ISET pin voltage is pulled down to below
1V due to ISET pin resistor shorted to
GND
LED_CURRENT[11:0] is written to 0x3FF. Total
LED current limited to 70 mA.
ISET resistor fault
Thermal shutdown
Open LED string
ISET_STATUS
Yes
Yes
Yes
No
Junction temperature rises above TSD
threshold.
Device goes to standby and then attempts to
restart once die temperature falls below threshold.
TSD_STATUS
Yes
No
Headroom voltage on one or more
channels is below minimum level and
boost has adapted to maximum level.
Faulted LED string is disabled and removed from
adaptive boost control loop. String is re-enabled
next power cycle.
LED_STATUS
OPEN_LED
Headroom voltage on one or more
channels is above the
SHORTED_LED_THRESHOLD for > 5
ms while the headroom of at least one
channel is still below this threshold.
Faulted LED string is disabled and removed from
adaptive boost control loop. String is re-enabled
next power cycle.
LED_STATUS_SHORT_L
ED
LED internal short
Yes
No
During PL FET SOFT START, voltage of
one or more used LED output is below
VHEADROOM when small test current is
injected.
LED_STATUS_GND_LE
D
Device goes to Fault Recovery and then attempts
to restart 100 ms after fault occurs.
LED short to GND
In BOOST_SU and Normal Stage,
voltage of one or more used LED output
is below VSHORTGND.and keeps still when
the corresponding channel is off and
small test current is injected.
Yes
Yes
Configured unused LED output is
detected not short to GND.
Invalid LED string detected INVSTRING_STATUS
I2C timeout I2C_ERROR_STATUS
Yes
Yes
No
No
Device functions normally, if possible.
Device receives I2C command without
STOP signal for 500 ms.
Device functions normally and waits for the next
I2C command.
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7.4 Device Functional Modes
7.4.1 State Diagram
SHUTDOWN
VDD > VDDUVLO
EN = High
DEVICE INIT
15 ms
STANDBY
100ms
FAULT
PL FET
SOFTSTART
FAULT RECOVERY
25 ms
FAULT
BOOST
SOFTSTART
50 ms
FAULT
All LED channel have been disabled
due to open or short faults
NORMAL
LATCH FAULT
EN = 0
EN = 0
图7-19. State Machine Diagram
7.4.2 Shutdown
When EN is pulled low, boost, power-line FET, and LED outputs are turned off, and the device tries to discharge
the boost output for 400 ms. After this, the device is totally turned off.
7.4.3 Device Initialization
After POR is released device initialization begins. During this state the LDO is started up, EEPROM default and
trim configurations are loaded, LEDSET, MODE, BOOST_FSET and PWM_FSET resistors are detected.
7.4.4 Standby Mode
Starting from Standby mode, the device can be accessed with I2C to change any configuration registers.
Standby Mode is immediately switched to Power-line FET Soft Start mode if there's no fault.
7.4.5 Power-line FET Soft Start
Power-line FET is gradually enabled during this 25ms long state. Boost input and output capacitors are charged
to VIN level. VIN faults for OCP, OVP, and UVP and fault for LED short to GND are enabled.
7.4.6 Boost Start-Up
Boost voltage is ramped to initial boost voltage level with reduced current limit for 50 ms. All boost faults are now
enabled.
7.4.7 Normal Mode
LED drivers are enabled when brightness is greater than zero. All LED faults are active.
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7.4.8 Fault Recovery
Some critical faults can trigger fault recover state. LED drivers, boost converter, and power-line FET are disabled
for 100 ms, and the device attempts to restart from standby mode if EN is still high and brightness is greater than
zero.
7.4.9 Latch Fault
If all LED strings are disabled due to faults then the TPS92390 enters the latch fault mode. This state can be
exited only by pulling the EN pin low.
7.4.10 Start-Up Sequence
PL FET
DEVICE
NORMAL
SHUTDOWN
SHUTDOWN
STANDBY
BOOST SOFTSTART
INIT
SOFTSTART
VIN
EN
VDD
PWM
INPUT
VINIT
BOOST
VOUT
VIN
LEDx
图7-20. Start-Up Sequence Diagram
7.5 Programming
7.5.1 I2C-Compatible Interface
The TPS92390 device supports I2C interface to access and change the configuration. The 7-bit base slave
address is 0x3A or 0x3B. The address could be configured through the resistor settings of MODE pin.
Write I2C transactions are made up of 4 bytes. The first byte includes the 7-bit slave address and Write bit. The
7-bit slave address selects the TPS92390 slave device. The second byte is eight bits register address. The last
two bytes are the 16-bit register value.
Read I2C transactions are made up of 5 bytes. The first byte includes the 7-bit slave address and Write bit. The
7-bit slave address selects the TPS92390 slave device. The second byte is eight bits register address. The third
byte includes the 7-bit slave address and Read bit. The last two bytes are the 16-bit register value returned from
the slave.
where
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• W bit = 1
图7-21. I2C Write
where
• R bit = 0
• W bit = 1
图7-22. I2C Read
7.5.2 Programming Examples
7.5.2.1 General Configuration Registers
The TPS92390 does not require any serial interface configuration. It can be simply controlled with the EN pin
and PWM pin. Most of the device configuration is accomplished using external resistor values. If I2C interface is
available then extended configuration is possible. The configuration registers can be written from standby state
to normal state as shown in 表7-10.
表7-10. Configuration Registers
REGISTER NAME
ADV_SLOPE_ENABLE
FUNCTION
Enables advance sloper S-shape smoothing function.
DITHER_SELECT
SLOPE_SELECT
BRT_MODE
Selects up to 3 bits of PWM dither for added dimming resolution.
Selects duration for linear brightness sloper.
Selects PWM pin or DISPLAY_BRT register for brightness control.
Selects up to 2 bits boost switching frequency spread spectrum range.
Selects up to 2 bits boost switching frequency spread spectrum modulation frequency.
Enables pseudo random modulation for boost switching spread spectrum frequency.
SPREAD_RANGE
SPREAD_MOD_FREQ
SPREAD_PSEUDO_EN
7.5.2.2 Clearing Fault Interrupts
The TPS92390 has an INT pin to alert the host when a fault occurs. If I2C interface is available, the Interrupt
Fault Status registers can be read back to learn which fault(s) have been detected. These status bits are located
in the SUPPLY_STATUS, BOOST_STATUS and LED_STATUS registers. Each interrupt status has a STATUS bit
and a CLEAR bit. To clear a fault interrupt status a 1 must be written to both the STATUS bit and CLEAR bit at
the same time.
7.5.2.3 Disabling Fault Interrupts
By default, most of the TPS92390 faults trigger the INT pin. Each fault has two INT_EN bits. These bits are
located in the SUPPLY_INT_EN, BOOST_INT_EN, and LED_INT_EN registers. If the INT_EN bit is read and
returns 2b'10, the INT pin is triggered when that fault occurs. The fault interrupt can be disabled by writing 2b'01
to its INT_EN bits, or it can be enabled by writing 2b'11 to its INT_EN bits. There is also a GLOBAL fault interrupt
that can be disabled to prevent any faults from triggering the INT pin.
7.5.2.4 Diagnostic Registers
The TPS92390 contains several diagnostic registers than can be read with the serial interface for debugging or
additional device information. 表7-11 is a summary of the available registers.
表7-11. Diagnostic Registers
REGISTER NAME
FSM_LIVE_STATUS
PWM_INPUT_STATUS
FUNCTION
Current state of the functional state machine
Measured 16-bit duty cycle of the PWM pin input
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表7-11. Diagnostic Registers (continued)
REGISTER NAME
FUNCTION
LED_PWM_STATUS
16-bit LED PWM duty cycle from state machine
12-bit LED current DAC value from state machine
LED_CURRENT_STATUS
10-bit value for adaptive boost voltage target —value is linear between
VBOOST_MIN and VBOOST_MAX calculations
VBOOST_STATUS
MODE_SEL_CFG
LED_STRING_CFG
BOOST_FREQ_SEL
PWM_FREQ_SEL
Dimming mode configuration from MODE detection
LED string phase configuration from LEDSET detection
Boost switching frequency value from BST_FSET detection
LED PWM frequency value from PWM_FSET detection
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7.6 Register Maps
7.6.1 FullMap Registers
表 7-12 lists the memory-mapped registers for the FullMap registers. All register offset addresses not listed in 表
7-12 should be considered as reserved locations and the register contents should not be modified.
表7-12. FULLMAP Registers
Offset
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
Acronym
Register Name
Section
Go
BRT_CONTROL
Display Brightness
LED Current
LED_CURR_CONFIG
USER_CONFIG1
Go
User Config 1
Go
USER_CONFIG2
User Config 2
Go
SUPPLY_INT_EN
Supply Interrupt Enable
Boost Interrupt Enable
LED Interrupt Enable
Supply Fault Status
Boost Fault Status
Go
BOOST_INT_EN
Go
LED_INT_EN
Go
SUPPLY_STATUS
Go
BOOST_STATUS
Go
LED_STATUS
LED Fault Status
Go
FSM_DIAGNOSTICS
PWM_INPUT_DIAGNOSTICS
PWM_OUTPUT_DIAGNOSTICS
LED_CURR_DIAGNOSTICS
ADAPT_BOOST_DIAGNOSTICS
AUTO_DETECT_DIAGNOSTICS
Device State Diagnostics
PWM Input Diagnostics
PWM Output Diagnostics
LED Current Diagnostics
Adaptive Boost Diagnostics
Auto Detect Diagnostics
Go
Go
Go
Go
Go
Go
Complex bit access types are encoded to fit into small table cells. 表 7-13 shows the codes that are used for
access types in this section.
表7-13. FullMap Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
Value after reset or the default
value
–n
7.6.1.1 BRT_CONTROL Register (Offset = 00h) [reset = 0h]
BRT_CONTROL is shown in 图7-23 and described in 表7-14.
Return to Summary Table.
图7-23. BRT_CONTROL Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DISPLAY_BRT
R/W-0h
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表7-14. BRT_CONTROL Register Field Descriptions
Bit
Field
DISPLAY_BRT
Type
Reset
Description
15-0
R/W
0h
Display Brightness Register
7.6.1.2 LED_CURR_CONFIG Register (Offset = 02h) [reset = 0FFFh]
LED_CURR_CONFIG is shown in 图7-24 and described in 表7-15.
Return to Summary Table.
图7-24. LED_CURR_CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
LED_CURRENT
R/W-FFFh
表7-15. LED_CURR_CONFIG Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
15-12
11-0
RESERVED
LED_CURRENT
0h
These bits are reserved.
FFFh
LED current control for all LED outputs
7.6.1.3 USER_CONFIG1 Register (Offset = 04h) [reset = 8A3h]
USER_CONFIG1 is shown in 图7-25 and described in 表7-16.
Return to Summary Table.
图7-25. GROUPING1 Register
15
14
13
12
11
10
9
1
8
0
RESERVED
BRT_MODE
R/W-0h
SPREAD_PSE
UDO_EN
SPREAD_MOD_FREQ
SPREAD_RANGE
R/W-0h
7
R/W-0h
R/W-0h
R/W-2h
6
5
4
3
2
SLOPE_SELECT
DITHER_SELECT
ADV_SLOPE_E
NABLE
RESERVED
R/W-5h
R/W-0h
R/W-1h
R/W-1h
表7-16. USER_CONFIG1 Register Field Descriptions
Bit
15
14
Field
Type
Reset
Description
RESERVED
R/W
0h
This bit is reserved.
SPREAD_PSEUDO_EN
R/W
0h
0h = Pseudo Random SS disabled
1h = Pseudo Random SS enabled
13-12
SPREAD_MOD_FREQ
SPREAD_RANGE
R/W
0h
Boost spread spectrum modulation frequency
0h = 200 Hz
1h = 500 Hz
2h = 800 Hz
3h = 1.2 kHz
11-10
R/W
2h
OSC_BST spread spectrum range
0h = 3.3%
1h = 4.3%
2h = 5.3%
3h = 7.2%
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表7-16. USER_CONFIG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
9-8
BRT_MODE
R/W
0h
Select PWM pin or DISPLAY_BRT register for brightness controll
0h = Brightness controlled by PWM input
1h = Reserved
2h = Brightness controlled by DISPLAY_BRT register
3h = Reserved
7-5
SLOPE_SELECT
R/W
5h
Select duration for linear brightness sloper
0h = Disabled
1h = 1 ms
2h = 2 ms
3h = 50 ms
4h = 100 ms
5h = 200 ms
6h = 300 ms
7h = 500 ms
Times are for linear slope mode. Advanced sloper will increase
durations while adding additional smoothing to brightness transitions.
1 ms and 2 ms sloper times are intended to be used only in linear
mode. 50 ms to 500 ms sloper durations may be used with or without
advanced sloper function.
4-2
DITHER_SELECT
R/W
0h
Dither mode select
0h = Dither Disabled
1h = 1-bit Dither
2h = 2-bit Dither
3h = 3-bit Dither
4h = 4-bit Dither
1
0
ADV_SLOPE_ENABLE
RESERVED
R/W
R/W
1h
1h
0h = Linear Sloping
1h = Advanced Sloping
This bit is reserved.
7.6.1.4 USER_CONFIG2 Register (Offset = 06h) [reset = 100h]
USER_CONFIG2 is shown in 图7-26 and described in 表7-17.
Return to Summary Table.
图7-26. USER_CONFIG2 Register
15
14
13
12
11
10
2
9
1
8
RESERVED
EN_LED_GND_
DETECT
R/W-0h
4
R/W-1h
0
7
6
5
3
RESERVED
R/W-0h
RESERVED
RESERVED
LED4_SHORT_ LED3_SHORT_ LED2_SHORT_ LED1_SHORT_
DISABLE
DISABLE
DISABLE
DISABLE
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表7-17. USER_CONFIG2 Register Field Descriptions
Bit
15-9
Field
Type
Reset
Description
RESERVED
R/W
0h
These bits are reserved.
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表7-17. USER_CONFIG2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
8
EN_LED_GND_DETECT R/W
1h
Enable LED short to ground detection during Boost_SS and normal
stage
0h = Disable
1h = Enable
7-6
5
RESERVED
RESERVED
RESERVED
R/W
R/W
R/W
0h
0h
0h
0h
These bits must write 0 for normal operation.
This bit must write 0 for normal operation.
This bit must write 0 for normal operation.
4
3
LED4_SHORT_DISABLE R/W
LED3_SHORT_DISABLE R/W
LED2_SHORT_DISABLE R/W
LED1_SHORT_DISABLE R/W
Disable LED string4 internal short fault.
0h = Enable
1h = Disable
2
1
0
0h
0h
0h
Disable LED string3 internal short fault.
0h = Enable
1h = Disable
Disable LED string2 internal short fault.
0h = Enable
1h = Disable
Disable LED string1 internal short fault.
0h = Enable
1h = Disable
7.6.1.5 SUPPLY_INT_EN Register (Offset = 08h) [reset = 2AAAh]
SUPPLY_INT_EN is shown in 图7-27 and described in 表7-18.
Return to Summary Table.
图7-27. SUPPLY_INT_EN Register
15
14
13
12
11
10
2
9
8
RESERVED
R/W-0h
CP_INT_EN
R/W-2h
CPCAP_INT_EN
R/W-2h
BSTSYNC_INT_EN
R/W-2h
7
6
5
4
3
1
0
VINOCP_INT_EN
R/W-2h
VDDUVLO_INT_EN
R/W-2h
VINOVP_INT_EN
R/W-2h
VINUVLO_INT_EN
R/W-2h
表7-18. SUPPLY_INT_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R/W
0h
15-14
13-12
These bits are reserved.
BSTSYNC_INT_EN
R/W
2h
Missing boost sync interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
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表7-18. SUPPLY_INT_EN Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
11-10
CP_INT_EN
R/W
2h
Charge pump interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
9-8
7-6
5-4
3-2
1-0
CPCAP_INT_EN
VINOCP_INT_EN
VDDUVLO_INT_EN
VINOVP_INT_EN
VINUVLO_INT_EN
R/W
R/W
R/W
R/W
R/W
2h
2h
2h
2h
2h
Charge pump cap missing interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
VIN over-current interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
VDD under-voltage interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
VIN over-voltage interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
VIN under-voltage interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
7.6.1.6 BOOST_INT_EN Register (Offset = 0Ah) [reset = A028h]
BOOST_INT_EN is shown in 图7-28 and described in 表7-19.
Return to Summary Table.
图7-28. BOOST_INT_EN Register
15
14
13
12
11
10
9
8
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图7-28. BOOST_INT_EN Register (continued)
TSD_INT_EN
ISET_INT_EN
LEDSET_INT_EN
MODE_INT_EN
R/W-2h
R/W-2h
R/W-2h
R/W-2h
7
6
5
4
3
2
1
0
FSET_INT_EN
R/W-2h
BSTOCP_INT_EN
R/W-2h
BSTOVPH_INT_EN
R/W-2h
Reserved
R/W-0h
表7-19. BOOST_INT_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
15-14
13-12
11-10
9-8
TSD_INT_EN
R/W
2h
Thermal shutdown interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
ISET_INT_EN
R/W
R/W
R/W
R/W
R/W
2h
0h
0h
0h
2h
ISET resistor short to ground interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
LEDSET_INT_EN
MODE_INT_EN
FSET_INT_EN
BSTOCP_INT_EN
Missing LEDSET resistor interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
Missing MODE resistor interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
7-6
Missing FSET resistor interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
5-4
Boost over-current interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
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表7-19. BOOST_INT_EN Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-2
BSTOVPH_INT_EN
R/W
2h
Boost over-voltage high interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
1-0
Reserved
R/W
0h
These bits are reserved.
7.6.1.7 LED_INT_EN Register (Offset = 0Ch) [reset = AAh]
LED_INT_EN is shown in 图7-29 and described in 表7-20.
Return to Summary Table.
图7-29. LED_INT_EN Register
15
14
13
12
11
10
2
9
1
8
0
RESERVED
R/W-0h
7
6
5
4
3
GLOBAL_INT_EN
I2C_ERROR_INT_EN
R/W-2h
INVSTRING_INT_EN
R/W-2h
VINUVP_INT_EN
R/W-2h
R/W-2h
表7-20. LED_INT_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
RESERVED
R/W
0h
These bits are reserved.
7-6
5-4
3-2
GLOBAL_INT_EN
R/W
R/W
R/W
2h
2h
2h
Global interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
I2C_ERROR_INT_EN
I2C time out interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
INVSTRING_INT_EN
Invalid LED string configuration interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
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表7-20. LED_INT_EN Register Field Descriptions (continued)
Bit
Field
LED_INT_EN
Type
Reset
Description
1-0
R/W
2h
LED open/internal short/short to GND interrupt enable
Read:
0h = Interrupt is currently disabled
2h = Interrupt is currently enabled
Write:
1h = Disable interrupt
3h = Enable interrupt
7.6.1.8 SUPPLY_STATUS Register (Offset = 0Eh) [reset = 0h]
SUPPLY_STATUS is shown in 图7-30 and described in 表7-21.
Return to Summary Table.
图7-30. SUPPLY_STATUS Register
15
14
13
12
11
10
9
8
CP_STATUS
CP_CLEAR
CPCAP_STATU CPCAP_CLEA
CRCERR_STAT CRCERR_CLE BSTSYNC_STA BSTSYNC_CLE
S
R
US
AR
TUS
AR
R/W-0h
7
R/W-0h
6
R/W-0h
5
R/W-0h
4
R/W-0h
3
R/W-0h
2
R/W-0h
1
R/W-0h
0
VINOCP_STAT VINOCP_CLEA VDDUVLO_ST VDDUVLO_CL VINOVP_STAT VINOVP_CLEA VINUVLO_STA VINUVLO_CLE
US
R
ATUS
EAR
US
R
TUS
AR
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表7-21. SUPPLY_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
CRCERR_STATUS
CRCERR_CLEAR
BSTSYNC_STATUS
BSTSYNC_CLEAR
CP_STATUS
R/W
0h
CRC error fault status
0h = No fault
1h = Fault
14
13
12
11
10
9
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
CRC error fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
Missing boost sync fault status
0h = No fault
1h = Fault
Missing boost sync fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
Charge pump fault status
0h = No fault
1h = Fault
CP_CLEAR
Charge pump fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
CPCAP_STATUS
Missing charge pump fault status
0h = No fault
1h = Fault
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表7-21. SUPPLY_STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
8
CPCAP_CLEAR
R/W
0h
Missing charge pump fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
7
6
5
4
3
2
1
0
VINOCP_STATUS
VINOCP_CLEAR
VDDUVLO_STATUS
VDDUVLO_CLEAR
VINOVP_STATUS
VINOVP_CLEAR
VINUVLO_STATUS
VINUVLO_CLEAR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
VIN over-current fault status
0h = No fault
1h = Fault
VIN over-current fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
VDD under-voltage fault status
0h = No fault
1h = Fault
VDD under-voltage fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
VIN over-voltage fault status
0h = No fault
1h = Fault
VIN over-voltage fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
VIN under-voltage fault status
0h = No fault
1h = Fault
VIN under-voltage fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
7.6.1.9 BOOST_STATUS Register (Offset = 10h) [reset = 0h]
BOOST_STATUS is shown in 图7-31 and described in 表7-22.
Return to Summary Table.
图7-31. BOOST_STATUS Register
15
14
13
12
11
10
9
8
TSD_STATUS
TSD_CLEAR
ISET_STATUS ISET_CLEAR LEDSET_STAT LEDSET_CLEA MODESEL_ST MODESEL_CL
US
R/W-0h
3
R
R/W-0h
2
ATUS
R/W-0h
1
EAR
R/W-0h
0
R/W-0h
7
R/W-0h
6
R/W-0h
5
R/W-0h
4
FSET_STATUS FSET_CLEAR BSTOCP_STAT BSTOCP_CLE BSTOVPH_STA BSTOVPH_CL BSTOVPL_STA BSTOVPL_CLE
US
AR
TUS
EAR
TUS
AR
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表7-22. BOOST_STATUS Register Field Descriptions
Bit
Field
TSD_STATUS
Type
Reset
Description
15
R/W
0h
Thermal shutdown fault status
0h = No fault
1h = Fault
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表7-22. BOOST_STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
14
TSD_CLEAR
R/W
0h
Thermal shutdown fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
13
12
11
10
9
ISET_STATUS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
ISET resistor short to ground fault status
0h = No fault
1h = Fault
ISET_CLEAR
ISET resistor short to ground fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
LEDSET_STATUS
LEDSET_CLEAR
MODESEL_STATUS
MODESEL_CLEAR
FSET_STATUS
Missing LED resistor fault status
0h = No fault
1h = Fault
Missing LED resistor fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
Missing MODE SEL resistor fault status
0h = No fault
1h = Fault
8
Missing MODE SEL resistor fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
7
Missing boost FSET resistor fault status
0h = No fault
1h = Fault
6
FSET_CLEAR
Missing boost FSET resistor fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
5
BSTOCP_STATUS
BSTOCP_CLEAR
BSTOVPH_STATUS
BSTOVPH_CLEAR
BSTOVPL_STATUS
BSTOVPL_CLEAR
Boost over-current fault status
0h = No fault
1h = Fault
4
Boost over-current fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
3
Boost OVP high fault status
0h = No fault
1h = Fault
2
Boost OVP high fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
1
Boost OVP low fault status
0h = No fault
1h = Fault
0
Boost OVP low fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status
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7.6.1.10 LED_STATUS Register (Offset = 12h) [reset = 0h]
LED_STATUS is shown in 图7-32 and described in 表7-23.
Return to Summary Table.
图7-32. LED_STATUS Register
15
14
13
12
11
10
9
8
RESERVED
I2C_ERROR_S I2C_ERROR_C INVSTRING_S INVSTRING_C LED_STATUS
LED_CLEAR
GND_LED
TATUS
R/W-0h
6
LEAR
R/W-0h
5
TATUS
R/W-0h
4
LEAR
R/W-0h
3
R/W-0h
7
R/W-0h
2
R/W-0h
1
R-0h
0
SHORT_LED
R-0h
OPEN_LED
R-0h
RESERVED
R-0h
RESERVED
R-0h
LED4_FAULT
R-0h
LED3_FAULT
R-0h
LED2_FAULT
R-0h
LED1_FAULT
R-0h
表7-23. LED_STATUS Register Field Descriptions
Bit
15
14
Field
RESERVED
Type
R/W
R/W
Reset
Description
0h
This bit is reserved
I2C_ERROR_STATUS
I2C_ERROR_CLEAR
INVSTRING_STATUS
INVSTRING_CLEAR
LED_STATUS
0h
I2C time out fault status
0h = No fault
1h = Fault
13
12
11
10
9
R/W
R/W
R/W
R/W
R/W
R
0h
0h
0h
0h
0h
0h
0h
I2C time out fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
Invalid string configuration fault status
0h = No fault
1h = Fault
Invalid string configuration fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
LED open/internal short/short to GND fault status
0h = No fault
1h = Fault
LED_CLEAR
LED open/internal short/short to GND fault clear
Write "1" to both Status bit and Clear bit at the same time to clear
interrupt register status and interrupt pin status
8
GND_LED
LED short to GND fault status
0h = No fault
1h = Fault
7
SHORT_LED
R
LED internal short Status
0h = No Fault
1h = Fault
Status is cleared with LED_STATUS bit
6
OPEN_LED
R
0h
LED open fault status
0h = No fault
1h = Fault
Status is cleared with LED_STATUS bit
5
4
RESERVED
RESERVED
R
R
0h
0h
This bit must write 0 for normal operation.
This bit must write 0 for normal operation.
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表7-23. LED_STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
LED4_FAULT
LED3_FAULT
LED2_FAULT
LED1_FAULT
R
0h
LED 4 Status
0h = No Fault
1h = Fault
2
1
0
R
R
R
0h
0h
0h
LED 3 Status
0h = No Fault
1h = Fault
LED 2 Status
0h = No Fault
1h = Fault
LED 1 Status
0h = No Fault
1h = Fault
7.6.1.11 FSM_DIAGNOSTICS Register (Offset = 14h) [reset = 0h]
FSM_DIAGNOSTICS is shown in 图7-33 and described in 表7-24.
Return to Summary Table.
图7-33. FSM_DIAGNOSTICS Register
15
7
14
13
5
12
11
10
9
1
8
0
RESERVED
R-0h
6
4
3
2
RESERVED
R-0h
FSM_LIVE_STATUS
R-0h
表7-24. FSM_DIAGNOSTICS Register Field Descriptions
Bit
Field
Type
Reset
Description
15-5
4-0
RESERVED
R
0h
These bits are reserved
FSM_LIVE_STATUS
R
0h
Current state of the functional state machine
0h = DISABLED
1h = LDO_STARTUP
2h = OTP_READ
3h = STANDBY
4h-Fh = BOOST_STARTUP
10h = NORMAL
11h = SHUTDOWN
12h = FAULT_RECOVERY
13h = ALL_LED_FAULT
7.6.1.12 PWM_INPUT_DIAGNOSTICS Register (Offset = 16h) [reset = 0h]
PWM_INPUT_DIAGNOSTICS is shown in 图7-34 and described in 表7-25.
Return to Summary Table.
图7-34. PWM_INPUT_DIAGNOSTICS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWM_INPUT_STATUS
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图7-34. PWM_INPUT_DIAGNOSTICS Register (continued)
R-0h
表7-25. PWM_INPUT_DIAGNOSTICS Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
PWM_INPUT_STATUS
R
0h
16-bit value for detected duty cycle of PWM input signal.
7.6.1.13 PWM_OUTPUT_DIAGNOSTICS Register (Offset = 18h) [reset = 0h]
PWM_OUTPUT_DIAGNOSTICS is shown in 图7-35 and described in 表7-26.
Return to Summary Table.
图7-35. PWM_OUTPUT_DIAGNOSTICS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWM_OUTPUT_STATUS
R-0h
表7-26. PWM_OUTPUT_DIAGNOSTICS Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
PWM_OUTPUT_STATUS
R
0h
16-bit value for configured duty cycle of PWM output signal.
7.6.1.14 LED_CURR_DIAGNOSTICS Register (Offset = 1Ah) [reset = 0h]
LED_CURR_DIAGNOSTICS is shown in 图7-36 and described in 表7-27.
Return to Summary Table.
图7-36. LED_CURR_DIAGNOSTICS Register
15
7
14
6
13
12
11
10
9
8
0
RESERVED
R-0h
LED_CURRENT_STATUS
R-0h
5
4
3
2
1
LED_CURRENT_STATUS
R-0h
表7-27. LED_CURR_DIAGNOSTICS Register Field Descriptions
Bit
Field
RESERVED
Type
Reset
Description
15-12
11-0
R
0h
These bits are reserved.
LED_CURRENT_STATUS R
0h
12-bit Current DAC Code that Brightness path is driving to OUT1-4
output.
7.6.1.15 ADAPT_BOOST_DIAGNOSTICS Register (Offset = 1Ch) [reset = 0h]
ADAPT_BOOST_DIAGNOSTICS is shown in 图7-37 and described in 表7-28.
Return to Summary Table.
图7-37. ADAPT_BOOST_DIAGNOSTICS Register
15
7
14
6
13
RESERVED
R-0h
12
11
10
9
8
0
VBOOST_STATUS
R-0h
1
5
4
3
2
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图7-37. ADAPT_BOOST_DIAGNOSTICS Register (continued)
VBOOST_STATUS
R-0h
表7-28. ADAPT_BOOST_DIAGNOSTICS Register Field Descriptions
Bit
Field
Type
Reset
Description
15-11
RESERVED
R
0h
These bits are reserved.
10-0
VBOOST_STATUS
R
0h
11-bit Boost Voltage Code that Adaptive Voltage Control Loop
sending to Analog Boost Block.
In two-resistor method, Boost Output Voltage =((1+R1/R2)*1.21V)+
(R1*18.9nA*VBOOST_STATUS)
7.6.1.16 AUTO_DETECT_DIAGNOSTICS Register (Offset = 1Eh) [reset = 0h]
AUTO_DETECT_DIAGNOSTICS is shown in 图7-38 and described in 表7-29.
Return to Summary Table.
图7-38. AUTO_DETECT_DIAGNOSTICS Register
15
RESERVED
R-0h
14
6
13
12
11
RESERVED
R-1h
10
9
8
0
AUTO_PWM_FREQ_SEL
AUTO_LED_STRING_CFG
R-0h
5
R-0h
1
7
4
3
2
RESERVED
AUTO_BOOST_FREQ_SEL
R-0h
MODE_SEL
R-0h
R-0h
表7-29. AUTO_DETECT_DIAGNOSTICS Register Field Descriptions
Bit
15
Field
Type
Reset
Description
RESERVED
R
0h
This bit is reserved
14-12
AUTO_PWM_FREQ_SEL
R
0h
LED PWM frequency value from PWM_SEL resistor detection
0h = 152 Hz
1h = 305 Hz
2h = 610 Hz
3h = 1221 Hz
4h = 2441 Hz
5h = 4883 Hz
6h = 9766 Hz
7h = 19531 Hz
11
RESERVED
R
R
1h
0h
This bit is reserved
10-8
AUTO_LED_STRING_CF
G
LED string configuration from LED_SET resistor detection
0h = 4 separate strings
1h = 3 separate strings
2h = 2 separate strings
3h = 4 channel outputs connected in 2 groups to drive 2 strings
4h = 4 channel outputs connected together to drive 1 string
7-6
RESERVED
R
0h
These bits are reserved
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表7-29. AUTO_DETECT_DIAGNOSTICS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-3
AUTO_BOOST_FREQ_S
EL
R
0h
Boost switching frequency value from PWM_FSET resistor detection
0h = 100 kHz
1h = 200 kHz
2h = 303 kHz
3h = 400 kHz
4h = 500 kHz
5h = 1818 kHz
6h = 2000 kHz
7h = 2222 kHz
2-0
MODE_SEL
R
0h
LED dimming MODE value from MODE detection
0h = PWM mode, I2C address 0x3B
1h = 12.5% hybrid dimming mode, I2C address 0x3B
2h = Constant current mode, I2C address 0x3B
3h = Direct PWM, I2C address 0x3B
4h = PWM mode, I2C address 0x3A
5h = 12.5% hybrid dimming mode, I2C address 0x3A
6h = Constant current mode, I2C address 0x3A
7h = Direct PWM, I2C address 0x3A
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPS92390 device is designed for automotive applications, and an input voltage VIN is intended to be
connected to the vehicle battery. Depending on the input voltage, the device may be used in either boost mode
or SEPIC mode. The device is internally powered from the VDD pin, and voltage must be in 2.7-V to 5.5-V
range. The device has flexible configurability through external components or by an I2C interface. If the VDD
voltage is not high enough to drive an external nMOSFET gate, an internal charge pump must be used to power
the gate driver (GD pin).
8.2 Typical Applications
8.2.1 Full Feature Application for Display Backlight
图 8-1 shows a full application for the TPS92390 device in a boost topology. It supports 6 LED strings in display
mode, each at 150 mA, with an automatic 60° phase shift. Brightness control register is used for LED dimming
method through I2C communication. The charge pump is enabled for a 400-kHz boost switching frequency with
spread spectrum.
L
RISENSE
VIN
VOUT
CIN
COUT
SD
VSENSE_N
VSENSE_P
GD
PGND
ISNS
UVLO
ISNSGND
FB
TPS92390
VDD
C1N
LED_GND
C1P
OUT1
OUT2
OUT3
OUT4
CPUMP
SGND
EN
PWM
INT
BST_FSET
PWM_FSET
SDA
SCL
LED_SET
ISET
BST_SYNC
MODE
图8-1. Full Feature Application for Display Backlight
8.2.1.1 Design Requirements
This typical LED-driver application is designed to meet the parameters listed in 表8-1:
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表8-1. TPS92390 Full-Feature Design Parameters
DESIGN PARAMETER
VALUE
VIN voltage range
5 Vto 20 V (Quiescent Voltage)
VDD voltage
3.3 V
LED strings configuration
Charge pump
4 strings, 7 LEDs in series
Enabled
Brightness control
Output configuration
LED string current
Boost frequency
Inductor
I2C
OUT1 to OUT4 are in phase shift mode (90°)
150 mA
400 kHz
22 µH at 6.5-A saturation current
RISENSE
20 mΩ
Power-line FET
RSENSE
Enabled
30 mΩ
Input/Output capacitors
Spread spectrum
CIN and COUT: 1 × 33-µF electrolytic + 1 × 10-µF ceramic
Enabled
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Inductor Selection
There are a few things to consider when choosing an inductor: inductance, current rating, and DC resistance
(DCR). 表 8-2 shows recommended inductor values for each operating frequency. The TPS92390 device
automatically sets internal boost compensation controls depending on the selected switching frequency.
表8-2. Inductance Values for Boost Switching Frequencies
SW FREQUENCY (kHz)
INDUCTANCE (µH)
100
200
47
33
22
22
22
10
10
10
303
400
500
1818
2000
2222
The current rating of inductor must be at least 25% higher than maximum boost switching current ISW(max), which
can be calculated with Equation 21. TI recommends to use an inductor with low DCR to achieve good efficiency.
Efficiency varies with load condition, switching frequency, and components. 80% can be used as a typical
estimation. 65% efficiency needs to take into account in extreme condition.
IOUT(max)
DIL
2
ISW(max)
=
+
1- D
(21)
where
• ΔIL = VIN(min) × D / ƒSW × L
• D = 1 –VIN(min) × η/ VOUT
• ISW(max): Maximum switching current
• ΔIL: Inductor ripple current
• IOUT(max): Maximum output current
• D: Boost duty cycle
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• VIN(min): Minimum input voltage
• ƒSW: Minimum switching frequency of the converter
• L: Inductance
• VOUT: Output voltage
• η: Efficiency of boost converter
8.2.1.2.2 Output Capacitor Selection
Recommended voltage rating for output capacitors is 50% higher than maximum output voltage level.
Capacitance value determines voltage ripple and boost stability. The DC-bias effect can reduce the effective
capacitance significantly, by up to 80%, a consideration for capacitance value selection. The conservative target
effective capacitance is 50 µF to achieve good phase and gain margin levels. A design table in product webpage
could be refered for the target effective capacitance in a certain application. TI recommends using 33-µF Al-
polymer electrolytic capacitor together with 10-µF ceramic capacitors in parallel to reduce ripple, increase
stability, and reduce ESR effect.
8.2.1.2.3 Input Capacitor Selection
Recommended input capacitance is the same as output capacitance although input capacitors are not as critical
to boost operation. Input capacitance can be reduced but must ensure enough filtering for input power.
8.2.1.2.4 Charge Pump Output Capacitor
TI recommends a ceramic capacitor with at least 10-V voltage rating for the output capacitor of the charge pump.
A 10-μF capacitor can be used for most applications.
8.2.1.2.5 Charge Pump Flying Capacitor
TI recommends a ceramic capacitor with at least 10-V voltage rating for the flying capacitor of the charge pump.
One 2.2-μF capacitor connecting C1P and C1N pins can be used for most applications.
8.2.1.2.6 Output Diode
A Schottky diode must be used for the boost output diode. Current rating must be at least 25% higher than the
maximum output current. Schottky diodes with a low forward drop and fast switching speeds are ideal for
increasing efficiency. At maximum current, the forward voltage must be as low as possible; less than 0.5 V is
recommended. Reverse breakdown voltage of the Schottky diode must be significantly larger than the output
voltage, 25% higher voltage rating is recommended. Do not use ordinary rectifier diodes, because slow switching
speeds and long recovery times cause efficiency and load regulation to suffer.
8.2.1.2.7 Switching FET
Gate-drive voltage for the FET is 5V. Switching FET is a critical component for determining power efficiency of
the boost converter. Several aspects need to be considered when selecting switching FET such as voltage and
current rating, RDSON, power dissipation, thermal resistance and rise/fall times. An N type MOSFET with at least
25% higher voltage rating than maximum output voltage must be used. Current rating of switching FET should
be same or higher than inductor rating. RDSON must be as low as possible, less than 20 mΩ is recommended.
Thermal resistance (RθJA) must also be low to dissipate heat from power loss on switching FET. In most cases,
a resistance is recommended between GD pin and Switching FET's gate terminal. It could be used to control the
rising/falling time of the switching FET. This gate resistance could offer the flexibility of balancing between EMC
performance and efficiency.
8.2.1.2.8 Boost Sense Resistor
The RSENSE resistor determines the boost overcurrent limit and is sensed every boost switching cycle. A high-
power 20-mΩ resistor can be used for sensing the boost SW current and setting maximum current limit at 10 A
(typical). RSENSE can be increased to lower this limit and can be calculated with Equation 22. In typical condition,
to avoid too much efficiency loss on RSENSE resistor, boost overcurrent limit is recommended to be set above 4A,
therefore RSENSE doesn't exceed 50 mΩ. Power rating can be calculated from the inductor current and sense
resistor resistance value.
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200 mV
RSENSE
=
IBOOST _OCP
(22)
where
• RSENSE: boost sense resistor (mΩ)
• IBOOST_OCP: boost overcurrent limit
8.2.1.2.9 Power-Line FET
A power line FET can be used to disconnect input power from boost input to protect the TPS92390 device and
boost components in case an overcurrent event occurs. A P type MOSFET is used for the power-line FET.
Voltage rating must be at least 25% higher than maximum input voltage level. Low RDSON is important to reduce
power loss on the FET — less than 20 mΩ is recommended. Current rating for the FET must be at least 25%
higher than input peak current. Minimum Gate-to-Source voltage (VGS) to turn on transistor fully must be less
than minimum input voltage; use a 20-kΩresistor between the pFET gate and source.
8.2.1.2.10 Input Current Sense Resistor
A high-power resistor can be used for sensing the boost input current. Overcurrent condition is detected when
the voltage across RISENSE reaches 220 mV. Typical 20-mΩsense resistor is used to set 11-A input current limit.
Sense resistor value can be increased to lower overcurrent limit for application as needed. Power rating can be
calculated from the input current and resistance value.
8.2.1.2.11 Feedback Resistor Divider
Feedback resistors RFB1 and RFB2 determine the maximum boost output level. Output voltage can be calculated
as in Equation 23:
≈
∆
«
’
VBG
VOUT_MAX
=
+ ISEL_MAX ì RFB1 + VBG
÷
RFB2
◊
(23)
where
• VBG = 1.21 V
• ISEL_MAX = 38.7 µA
• RFB1 / RFB2 normal recommended range is 7~15
8.2.1.2.12 Critical Components for Design
图 8-2 shows the critical part of circuitry: boost components, the TPS92390 internal charge pump for gate-driver
powering, and powering/grounding of TPS92390 . Schematic example is shown in 图8-2.
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L
RISENSE
VIN
VOUT
RSD
CIN
COUT
RG
SD
RFB1
RFB3
VSENSE_N
VSENSE_P
GD
PGND
ISNS
RUVLO1
RUVLO2
RFB2
RSENSE
UVLO
ISNSGND
FB
VDD
TPS92390
VDD
C1N
CVDD
C2x
LED_GND
C1P
CPUMP
OUT1
OUT2
OUT3
OUT4
CPUMP
SGND
EN
HOST
I2C
PWM
INT
RBST_FSET
RPWM_FSET
RLED_SET
BST_FSET
PWM_FSET
SDA
SCL
LED_SET
ISET
VDD
BST_SYNC
MODE
RISET
RMODE
图8-2. Critical Components for Full Feature Design
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表8-3. Recommended Component Values for Full Feature Design Example
REFERENCE DESIGNATOR
DESCRIPTION
20 mΩ, 3 W
20 kΩ, 0.1 W
30 mΩ, 3 W
NOTE
RISENSE
RSD
Input current sensing resistor
Power-line FET gate pullup resistor
Boost current sensing resistor
RSENSE
Gate resistor to control the rising/falling time
of nMOSFET for EMC
RG
15 Ω, 0.1 W
These UVLO resistor settings set the
VIN_UVLO rising voltage at 3.75 V,
VIN_UVLO falling voltage at 3.35 V
RUVLO1
RUVLO2
76.8 kΩ, 0.1 W
20.5 kΩ, 0.1 W
Not needed unless 100-kΩrestrictions on
resistors
RFB3
0 Ω, 0.1 W
RFB2
RFB1
Bottom feedback divider resistor
Top feedback divider resistor
100 kΩ, 0.1 W
910 kΩ, 0.1 W
3.92 kΩ, 0.1 W
20.8 kΩ, 0.1 W
RBST_FSET
RISET
Boost frequency set resistor (400 kHz)
Current set resistor (150 mA per channel)
Output PWM frequency set resistor (4.88kHz
PWM frequency to avoid audible noise)
RPWM_FSET
RMODE
17.8 kΩ, 0.1 W
3.92 kΩ, 0.1 W
Mode resistor (Phase-Shift PWM mode with
0x3B I2C address)
RLED_SET
CPUMP
C2X
LED_SET resistor (4channels configuration)
Charge-pump output capacitor
Flying capacitor
3.92 kΩ, 0.1 W
10-µF, 10-V ceramic
2.2-µF, 10-V ceramic
CVDD
CIN
4.7-µF + 0.1-µF, 10-V ceramic
1 × 33-µF, 50-V electrolytic + 1 × 10-µF, 50-V ceramic
1 × 33-µF, 50-V electrolytic + 1 × 10-µF, 50-V ceramic
22-μH saturation current 6.5 A
50 V, 6.5-A Schottky diode
VDD bypass capacitor
Boost input capacitor
Boost output capacitor
Boost inductor
COUT
L1
D1
Boost Schottky diode
Boost nMOSFET
Q1
60-V, 15-A nMOSFET
Q2
60-V, 15-A pMOSFET
Power-line FET
8.2.1.3 Application Curves
FLED_PWM = 305 Hz
Phase Shift 60°
6 Strings
图8-3. LED String Currents Showing Phase Shift
PWM Operation
150 mA/String
ƒSW = 400 kHz
CIN = COUT = 1 × 33 μF (electrolytic) + 1 × 10 μF (ceramic)
图8-4. Typical Start-Up
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8.2.2 Application With Basic/Minimal Operation
The TPS92390 needs only a few external components for basic functionality if material cost and PCB area for a
solution need to be minimized. In this example TPS92390 is configured with external components and no I2C
communication. The power-line FET is removed, as is input current sensing. Internal charge pump is not used,
and all external synchronization functions and special features are disabled. The 33-µF Al-polymer electrolytic
capacitor is removed for PCB area and height limitation. And boost external compensation is used to
compensate the removal of the 33-µF Al-polymer electrolytic capacitor.
L
VIN
VOUT
CIN
COUT
RG
SD
RFB1
VSENSE_N
VSENSE_P
GD
PGND
ISNS
RFB4
RFB2
CCOMP
RSENSE
UVLO
CVDD
ISNSGND
FB
VDD
TPS92390
VDD
C1N
LED_GND
C1P
CPUMP
OUT1
OUT2
OUT3
OUT4
CPUMP
SGND
EN
Remote
HOST
PWM
INT
BST_FSET
PWM_FSET
SDA
SCL
VDD
LED_SET
ISET
BST_SYNC
MODE
RISET
图8-5. Minimal Solution/Minimum Components Application
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8.2.2.1 Design Requirements
This typical LED-driver application is designed to meet the parameters listed in 表8-4:
表8-4. TPS92390 Minimal Solution Design Parameters
DESIGN PARAMETER
VIN voltage range
VALUE
3 Vto 20 V (Quiescent Voltage)
VDD voltage
5 V
LED strings configuration
Charge pump
4 strings, 7 LEDs in series
Disabled
Brightness control
Output configuration
LED string current
Boost frequency
Inductor
PWM
OUT1 to OUT4 are in phase shift mode (90°)
120 mA
400 kHz
22 µH at 6.5-A saturation current
RISENSE
20 mΩ
Power-line FET
RSENSE
Enabled
30 mΩ
Input/Output capacitors
Spread spectrum
Discharge function
CIN and COUT: 3 × 10-µF ceramic
Enabled
Enabled
8.2.2.2 Detailed Design Procedure
See Detailed Design Procedure.
8.2.2.3 Application Curves
See Application Curves.
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8.2.3 SEPIC Mode Application
When LED string voltage can be above and below the input voltage level, use the SEPIC configuration. In
SEPIC mode, the SW pin detects a maximum voltage equal to the sum of the input and output voltages, a
consideration when selecting components.
CS2
RS
VOUT
RISENSE
VIN
L1
CS1
RSD
COUT
CIN
L2
RG
SD
RFB1
VSENSE_N
VSENSE_P
GD
PGND
ISNS
RUVLO1
RUVLO2
RFB2
RSENSE
UVLO
ISNSGND
FB
VDD
TPS92390
VDD
C1N
CVDD
C2x
LED_GND
C1P
CPUMP
OUT1
OUT2
OUT3
OUT4
CPUMP
SGND
EN
HOST
I2C
PWM
RBST_FSET
RPWM_FSET
RLED_SET
INT
BST_FSET
SDA
SCL
PWM_FSET
LED_SET
ISET
VDD
BST_SYNC
MODE
RISET
RMODE
图8-6. SEPIC Mode with Three LEDs in Series
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8.2.3.1 Design Requirements
This typical LED-driver application is designed to meet the parameters listed in 表8-5:
表8-5. TPS92390 SEPIC Mode Design Parameters
DESIGN PARAMETER
VIN voltage range
VALUE
4.5 V to 20 V (quiescent voltage)
VDD voltage
3.3 V
LED strings configuration
Charge pump
3 strings, 3 LEDs in series
Enabled
Brightness control
Output configuration
LED string current
Boost frequency
Inductor
I2C
OUT1 to OUT3 are in phase shift PWM mode
80 mA
2.2 MHz
10 µH at 4-A saturation current
RISENSE
20 mΩ
Power-line FET
RSENSE
Enabled
50 mΩ
Input/Output capacitors
Spread spectrum
Discharge function
CIN and COUT: 1 × 33-µF electrolytic + 1 × 10-µF ceramic
Enabled
Enabled
.
8.2.3.2 Detailed Design Procedure
8.2.3.2.1 Inductor Selection
Inductance for both inductors can be selected from 表8-6, depending on operating frequency for the application.
Current rating is recommended to be at least 25% higher than maximum inductor peak current. Peak-to-peak
ripple current can be estimated to be approximately 40% of the maximum input current and and inductor peak
current can be calculated with Equation 24, Equation 25, and Equation 26:
表8-6. Inductance Values for SEPIC Switching
Frequencies
SW FREQUENCY (kHz)
INDUCTANCE (µH)
100
200
22
15
303
10
400
10
500
10
1818
2000
2222
4.7
4.7
4.7
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VOUT + VD
40%
2
≈
’
IL1(peak) = IOUT
ì
ì
1+
∆
«
÷
◊
V
IN(min)
(24)
where
• IL1(peak): Peak current for inductor 1
• IOUT: Maximum output current
• VOUT: Output voltage
• VD: Diode forward voltage drop
• VIN(min): Minimum input voltage
40%
≈
’
IL2(peak) = IOUT
ì
1+
∆
«
÷
◊
2
(25)
where
• IL2(peak): Peak current for inductor 2
• IOUT: Maximum output current
VOUT
DIL = I ì 40% = IOUT
ì
ì 40%
IN
V
IN(min)
(26)
where
• ΔIL: Inductor ripple current
• IIN: Input current
• VOUT: Output voltage
• VIN(min): Minimum input voltage
8.2.3.2.2 Coupling Capacitor Selection
The coupling capacitors Cs isolate the input from the output and provide protection against a shorted load. The
selection of SEPIC capacitors, Cs, depends mostly on the RMS current, which can be calculated with Equation
27. The capacitors must be rated for a large RMS current relative to the output power; TI recommends at least
25% higher rating for IRMS. When using uncoupled inductors, use one 10-µF ceramic capacitor in parallel with
one 33-µF electrolytic capacitor and series 2-Ω resistor. If coupled inductors are used, then use only one 10-µF
ceramic capacitor.
VOUT + VD
ICs(rms) = IOUT
ì
V
IN(min)
(27)
where
• ICs(rms): RMS current of Cs capacitor
• IOUT: Output current
• VOUT: Output voltage
• VD: Diode forward voltage drop
• VIN(min): Minimum input voltage
8.2.3.2.3 Output Capacitor Selection
See Detailed Design Procedure.
8.2.3.2.4 Input Capacitor Selection
See Detailed Design Procedure.
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8.2.3.2.5 Charge Pump Output Capacitor
See Detailed Design Procedure.
8.2.3.2.6 Charge Pump Flying Capacitor
See Detailed Design Procedure.
8.2.3.2.7 Switching FET
Gate-drive voltage for the FET is 5V. Use an N-type MOSFET for the switching FET. The switching FET for
SEPIC mode sees a maximum voltage of VIN(max) + VOUT, 25% higher rating is recommended. Current rating is
also recommended to be 25% higher than peak current, which can be calculated with Equation 28. RDSON must
be as low as possible — less than 20 mΩ is recommended. Thermal resistance (RθJA) must also be low to
dissipate heat from power loss on switching FET. Typical rise/fall time values recommended are less than 10 ns.
IQ1(peak) = IL1(peak) + IL2(peak)
(28)
where
• IQ1(peak): Peak current for switching FET
• IL1(peak): Peak current for inductor 1
• IIL2(peak): : Peak current for inductor 2 BOOST_OCP
8.2.3.2.8 Output Diode
A Schottky diode must be used for the SEPIC output diode. Current rating must be at least 25% higher than the
maximum current, which is the same as switch peak current. Schottky diodes with a low forward drop and fast
switching speeds are ideal for increasing efficiency. At maximum current, the forward voltage must be as low as
possible; TI recommends less than 0.5 V. Reverse breakdown voltage of the Schottky diode must be able to
withstand VIN(max) + VOUT(max); at least 25% higher voltage rating is recommended. Do not use ordinary rectifier
diodes, because slow switching speeds and long recovery times cause efficiency and load regulation to suffer.
8.2.3.2.9 Switching Sense Resistor
See Detailed Design Procedure.
8.2.3.2.10 Power-Line FET
See Detailed Design Procedure.
8.2.3.2.11 Input Current Sense Resistor
See Detailed Design Procedure.
8.2.3.2.12 Feedback Resistor Divider
Feedback resistors RFB1 and RFB2 determine the maximum boost output level. Output voltage can be calculated
as follows:
≈
∆
«
’
VBG
VOUT _MAX
=
+ ISEL_MAX ì RFB1 + VBG
÷
RFB2
◊
(29)
where
• VBG = 1.21 V
• ISEL_MAX = 38.7 µA
• RFB1 / RFB2 normal recommended range is 5~15 (recommended for SEPIC Mode)
8.2.3.2.13 Critical Components for Design
shows the critical part of circuitry: SEPIC components, the TPS92390 internal charge pump for gate-driver
powering, and powering/grounding of TPS92390. Schematic example is shown below.
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CS2
RS
VOUT
RISENSE
VIN
L1
CS1
RSD
COUT
CIN
L2
RG
SD
RFB1
VSENSE_N
VSENSE_P
GD
PGND
ISNS
RUVLO1
RUVLO2
RFB2
RSENSE
UVLO
ISNSGND
FB
VDD
TPS92390
VDD
C1N
CVDD
C2x
LED_GND
C1P
CPUMP
OUT1
OUT2
OUT3
OUT4
CPUMP
SGND
EN
HOST
I2C
PWM
RBST_FSET
RPWM_FSET
RLED_SET
INT
BST_FSET
SDA
SCL
PWM_FSET
LED_SET
ISET
VDD
BST_SYNC
MODE
RISET
RMODE
图8-7. SEPIC Mode with Three LEDs in Series
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表8-7. Recommended Components for SEPIC Design Example
REFERENCE DESIGNATOR
DESCRIPTION
20 mΩ, 1 W
20 kΩ, 0.1 W
50 mΩ, 1 W
NOTE
RISENSE
RSD
Input current sensing resistor
Power-line FET gate pullup resistor
Boost current sensing resistor
RSENSE
Gate resistor to control the rising/falling time
of nMOSFET for EMC
RG
15 Ω, 0.1 W
These UVLO resistor settings set the
VIN_UVLO rising voltage at 3.75 V,
VIN_UVLO falling voltage at 3.35 V
RUVLO1
RUVLO2
76.8 kΩ, 0.1 W
20.5 kΩ, 0.1 W
RFB2
RFB1
Bottom feedback divider resistor
Top feedback divider resistor
60 kΩ, 0.1 W
330 kΩ, 0.1 W
124 kΩ, 0.1 W
38.7 kΩ, 0.1 W
RBST_FSET
RISET
Boost frequency set resistor (2200 kHz)
Current set resistor (80 mA per channel)
Output PWM frequency set resistor (305-Hz
PWM frequency)
RPWM_FSET
RMODE
4.75 kΩ, 0.1 W
3.92 kΩ, 0.1 W
Mode resistor (Phase-Shift PWM mode with
0x3B I2C address)
RLED_SET
CPUMP
C2X
LED_SET resistor (3 channels configuration)
Charge-pump output capacitor
Flying capacitor
4.75 kΩ, 0.1 W
10-µF, 10-V ceramic
2.2-µF, 10-V ceramic
CVDD
CIN
4.7-µF + 0.1-µF, 10-V ceramic
1 × 33-µF, 50-V electrolytic + 1 × 10-µF, 50-V ceramic
1 × 33-µF, 50-V electrolytic + 1 × 10-µF, 50-V ceramic
10-µF, 50-V ceramic
VDD bypass capacitor
Boost input capacitor
Boost output capacitor
SEPIC coupling capacitor
SEPIC coupling capacitor
SEPIC resistor
COUT
CS1
CS2
33-µF, 50-V electrolytic
RS
2 Ω, 0.125 W
L1
4.7-µH saturation current 3 A
4.7-µH saturation current 3 A
50-V 10-A Schottky diode
SEPIC inductor
L2
SEPIC inductor
D1
SEPIC Schottky diode
SEPIC nMOSFET
Q1
60-V, 25-A nMOSFET
Q2
60-V, 30-A pMOSFET
Power-line FET
8.2.3.3 Application Curves
See Application Curves.
9 Power Supply Recommendations
The TPS92390 is designed to operate from a car battery. The VIN input must be protected from reverse voltage
and voltage dump condition over 48 V. The impedance of the input supply rail must be low enough that the input
current transient does not cause drop below VIN UVLO level. If the input supply is connected with long wires,
additional bulk capacitance may be required in addition to normal input capacitor.
The voltage range for VDD is 3 V to 5.5 V. A ceramic capacitor must be placed as close as possible to the VDD
pin. The boost gate driver is powered from the CPUMP pins. A ceramic capacitor must be placed as close to the
CPUMP pins as possible.
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10 Layout
10.1 Layout Guidelines
图 10-1 shows a layout recommendation for the TPS92390 used to illustrate the principles of good layout. This
layout can be adapted to the actual application layout if and where possible. It is important that all boost
components are close to each other and to the chip; the high-current traces must be wide enough. VDD must be
as noise-free as possible. Place a VDD bypass capacitor near the VDD and GND pins. A charge-pump capacitor,
boost input capacitors, and boost output capacitors must have closest VIAs to GND. Place the charge-pump
capacitors close to the device. The main points to guide the PCB layout design:
• Current loops need to be minimized:
– For low frequency the minimal current loop can be achieved by placing the boost components as close as
possible to each other. Input and output capacitor grounds need to be close to each other to minimize
current loop size.
– Minimal current loops for high frequencies can be achieved by making sure that the ground plane is intact
under the current traces. High frequency return currents follow the route with minimum impedance, which
is the route with minimum loop area, not necessarily the shortest path. Minimum loop area is formed when
return current flows just under the positive current route in the ground plane, if the ground plane is intact
under the route.
– For high frequency the copper area capacitance must be taken into account. For example, the copper
area for the drain of boost N-MOSFET is a tradeoff between capacitance and the cooling capacity of the
components.
• GND plane must be intact under the high-current-boost traces to provide shortest possible return path and
smallest possible current loops for high frequencies.
• Route boost output voltage (VOUT) to LEDs, FB pin & Discharge pin after output capacitors not straight from
the diode cathode.
• FB network should be placed as close as possible to the FB pin, not near boost output
• A small bypass capacitor (TI recommends a 39-pF capacitor) could be placed close to the FB pin and GND to
suppress high frequency noise
• VDD line must be separated from the high current supply path to the boost converter to prevent high
frequency ripple affecting the chip behavior.
• Capacitor connected to charge pump output CPUMP is recommended to have 10-µF capacitance. This
capacitor must be as close as possible to CPUMP pin. This capacitor provides a greater peak current for gate
driver and must be used even if the charge pump is disabled. If the charge pump is disabled, the VDD and
CPUMP pins must be tied together.
• Input and output capacitors need low-impedance grounding (wide traces with many vias to GND plane).
• Input/output ceramic capacitors have DC-bias effect. If the output capacitance is too low, it can cause boost
to become unstable under certain load conditions. DC bias characteristics should be obtained from the
component manufacturer; DC bias is not taken into account on component tolerance.
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10.2 Layout Example
pMOSFET
Input Sense Resistor
VBAT
Boost Inductor
RGS
CIN
GND
RUVLO1
GND
Schottky Diode
nMOSFET
C1P
CPUMP
BST_FSET
GND
PWM_FSET
LED_SET
RG
GD
PGND
ISNS
SGND
PWM
GND
ISNSGND
ISET
BST_SYNC
SCL
Sense Resistor
RISET
GND
COUT
RFB2
FB
SDA
RFB1
GND
图10-1. TPS92390 Layout Guidelines
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序,可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级,大至整个器件故障。精密的集成电路可能更容易受到损坏,这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS92390RHBR
ACTIVE
VQFN
RHB
32
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
92390
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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