TPSM831D31MOA_技术文档

TPSM831D31

ZHCSIO9A –AUGUST 2018 –REVISED JUNE 2021

TPSM831D31 8V 至14V 输入、0.25V 至1.52V 双路输出、

120A + 40A PMBus™ 电源模块

1 特性

3 说明

• 输入电压范围：8V 至14V

• 双路输出：120A（三相）+ 40A（一相）

• 输出电压范围：0.25 V 至1.52 V

– 可编程（阶跃为5mV）

– 差分遥感

– ±0.5% Vref 精度，具有遥感功能

• PMBus 接口

TPSM831D31 是一款 PMBus^™控制型双输出四相电

源模块，该电源模块将一个具有四个高效智能功率级的

高性能D-CAP+^™控制器组合在一个坚固耐用的热增强

型表面贴装封装中。用户提供输入和输出电容器以及一

些无源组件即可完成系统。第一个输出是能够提供高达

120A 连续输出电流的三相功率级。第二个输出是能够

提供高达40A 输出电流的单相功率级。

– 可编程V_OUT、UVLO、故障限制

– VIN、VOUT、IOUT、温度遥测

– 支持高达1MHz 的总线速度

– 片上非易失性配置存储器

PMBus 接口提供每个输出电压、UVLO、软启动、过

流和热关断参数的转换器配置。该接口具有遥测支持功

能，可报告实际输入电压、输出电压、输出电流和器件

温度。该器件可报告输入和输出功率。该器件支持标准

PMBus 警告和故障功能。该器件支持高达 1MHz 的

PMBus 通信速度，具有 1.8V 或 3.3V 逻辑电平，详见

SMBus 规范 V3.0 第 4.3 节。该模块器件支持 PMBus

1.3 规范中的一部分命令。

• 超快瞬态响应

• 开关频率范围：350 kHz 至700 kHz

• 15mm × 48mm 封装尺寸和12mm 高度

• 效率高达95%

• 双电源正常状态指示输出

• 过流、过压、过热保护

• IC 工作结温范围：–40°C 至125°C

• 工作环境温度范围：–40°C 至105°C

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TPSM831D31

QFM (28)

48.00mm × 15.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 具有双电源轨的高性能处理器/ASIC

• 网络处理器电源（Broadcom^®、Cavium^®、

Marvell^®、NXP^®）

• 高电流FPGA 电源（Intel^®、Xilinx^®）

• 高性能ARM 处理器电源

VOUTA 120 A

ASIC Core

V_IN

8 V to 14 V

TPSM831D31

PMBUS

VOUTB 40 A

ASIC I/O

简化版应用

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSDC9

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Table of Contents

7.2 Functional Block Diagram.........................................12

7.3 Feature Description...................................................13

7.4 Device Functional Modes..........................................17

7.5 Programming............................................................ 17

8 Application and Implementation..................................72

8.1 Application Information............................................. 72

8.2 Typical Application.................................................... 72

9 Power Supply Recommendations................................78

10 Layout...........................................................................78

10.1 Layout Guidelines................................................... 78

10.2 Layout Examples.................................................... 78

11 Device and Documentation Support..........................80

11.1 接收文档更新通知................................................... 80

11.2 支持资源..................................................................80

11.3 Trademarks............................................................. 80

11.4 静电放电警告...........................................................80

11.5 术语表..................................................................... 80

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings ....................................... 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information ...................................................6

6.5 Electrical Characteristics ............................................6

6.6 References: DAC .......................................................8

6.7 Telemetry ................................................................... 8

6.8 Current Sense and Calibration ...................................8

6.9 Logic Interface Pins: A_EN, A_PGOOD, B_EN,

B_PGOOD,RESET .......................................................9

6.10 Protections: OVP and UVP ......................................9

6.11 Typical Characteristics (V_IN= 12 V)........................ 10

7 Detailed Description......................................................12

7.1 Overview...................................................................12

Information.................................................................... 81

4 Revision History

Changes from Revision * (August 2018) to Revision A (June 2021)

Page

• 将数据表状态从预告信息更改为量产数据..........................................................................................................1

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

2

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5 Pin Configuration and Functions

GND

VIN

1

2

28

27

VOUT_A

GND

VIN

3

4

VOUT_A

PMBDAT

PMBCLK

PMBALERT

RESET

A_PGOOD

A_EN

26

25

24

23

22

21

20

19

GND

DNC

ADDR

B_PGOOD

B_EN

BVSP

BVSN

5

6

7

8

9

10

11

12

AVSP

AVSN

13

14

GND

VIN

18

VOUT_A

GND

VIN

15

16

17

VOUT_B

图5-1. MOA Package, 28-Pin QFM (Top View)

表5-1. Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

Connect a resistor from this pin to GND to set the desired PMBus address. Do not leave this pin

floating. See PMBus ADDRESS section.

ADDR

23

I

Active high enable input for VOUT_A. Asserting this pin high enables power conversion on the

VOUT_A channel.

A_EN

10

9

Open drain Power Good signal of the VOUT_A channel. This pin requires a pullup resistor. This

pin is pulled low when a shutdown fault occurs.

A_PGOOD

AVSN

O

I

Negative input of the remote voltage sense of channel A. Connect this pin to ground at the

VOUT_A load for best voltage regulation. Do not let this pin float.

12

11

21

22

19

Positive input of the remote voltage sense of channel A. Connect this pin to VOUT_A at the

load for best voltage regulation. Do not let this pin float.

AVSP

I

Active high enable input for VOUT_B. Asserting this pin high enables power conversion on the

VOUT_B channel.

B_EN

I

Open drain Power Good signal of the VOUT_B channel. This pin requires a pullup resistor. This

pin is pulled low when a shutdown fault occurs.

B_PGOOD

BVSN

O

I

Negative input of the remote voltage sense of channel B. Connect this pin to ground at the

VOUT_B load for best voltage regulation. Do not let this pin float.

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表5-1. Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

Positive input of the remote voltage sense of channel B. Connect this pin to VOUT_A at the

load for best voltage regulation. Do not let this pin float.

BVSP

20

I

Do not connect. This pin is connected to internal circuitry. Do not connect this pin to other signal

or voltage source. Connecting the pin to GND is recommended.

DNC

GND

24

—

1

3

Power ground of the device. Connect pins 1, 3, 13, and 15 to the bypass caps associated with

VIN. Connect pads 1, 3, 13, 15 to the PCB ground planes using multiple vias for optimal thermal

performance.

13

15

25

26

6

G

PMBCLK

I

PMBus serial clock interface. (Open Drain)

PMBDAT

5

I/O

PMBus bi-directional serial data interface. (Open Drain)

PMBus bi-directional ALERT pin interface. (Open Drain)

PMBALERT

7

Active low RESET input that resets the output voltage to its programmed BOOT voltage. This

pin requires a pullup resistor.

RESET

VIN

8

I

2

4

Input voltage. These pins provide voltage to the power conversion stages of the module.

Connect these pins to the PCB VIN planes using multiple vias for optimal thermal performance.

I

14

16

18

27

28

Output voltage of channel A. Connect these pins to the output A load. Connect external bypass

capacitors between these pins and GND pins 1, 3, and 13.

VOUT_A

VOUT_B

O

Output voltage of channel B. Connect this pin to the output B load. Connect external bypass

capacitors between this pin and GND pin 15.

17

(1) G = ground, I = input, O = output

4

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

19

UNIT

V

VIN

Input voltage⁽²⁾

ADDR, AVSP, BVSP, RESET, PMBCLK, PMBDAT

AGND, AVSN, BVSN

3.6

0.3

3.6

500

10

V

Output voltage^{(1) (2)}

Mechanical shock

Mechanical vibration

VOUT_A, VOUT_B, A_PGOOD, B_PGOOD, PMBALERT

Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted

Mil-STD-883D, Method 2007.2, 20 to 2000 Hz

V

G

Operating junction temperature, T_J

Storage temperature, T_STG

150

°C

–40

–55

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to the network ground terminal GND unless otherwise noted.

6.2 ESD Ratings

VALUE

±2500

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

8

NOM

MAX

14

UNIT

VIN

12

V

VOUT_A, VOUT_B, AVSP, BVSP

0.25

0

1.52

120

40

IOUTA

A

IOUTB

0

A

PMBCLK, PMBDAT, RESET pullup, A_PGOOD pullup, B_PGOOD pullup, PMBALERT pullup

Switching frequency

3.3

3.5

V

350

–40

400

700

125

105

kHz

°C

µF

Operating junction temperature, T_J

Operating ambient temperature, T_A

Ceramic

500

1000

1200

5500

400

External input capacitance, C_IN

Non-ceramic

Ceramic

External output capacitance, C_{OUT_A}

600

2750

200

Non-ceramic

Ceramic

External output capacitance, C_{OUT_B}

Non-ceramic

900

1800

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6.4 Thermal Information

TPSM831D31

THERMAL METRIC⁽⁴⁾

MOA (QFN)

28 PINS

5.5

UNIT

Natural Convection

200 LFM

°C/W

°C

R_θJA

Junction-to-ambient thermal resistance ⁽¹⁾

3.4

400 LFM

2.8

Junction-to-top characterization parameter ⁽²⁾

Junction-to-board characterization parameter ⁽³⁾

Thermal shutdown temperature (default setting)

0.3

ψ_JT

ψ_JB

T_SD

1.6

135

(1) The junction-to-ambient thermal resistance applies to devices soldered directly to a 100 mm x 150 mm, 8-layer PCB with 2 oz. copper.

(2) The junction-to-top board characterization parameter, ψ_JT, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (section 6 and 7). T_J= ψ_JT× Pdis + T_T; where Pdis is the power dissipated in the device and T_Tis

the temperature of the top of the inductor.

(3) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). T_J= ψ_JB× Pdis + T_B; where Pdis is the power dissipated in the device and T_B

is the temperature of the board 1 mm from the device.

(4) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report .

6.5 Electrical Characteristics

T_A= –40°C to +105°C, V_IN= 12 V, V_OUTA= V_AVSP= 1 V, V_OUTB= V_BVSP= 1 V, V_AVSN= V_BVSN= 0V, I_OUTA= I_OUTB= 0 A, F_SW

= 400 kHz, C_IN1= 24 × 22-µF, 25-V, 1210 ceramic, C_IN2= 2 × 470 µF, electrolytic bulk, C_OUTA1= 12 × 100 µF, 6.3-V, 1210

ceramic, C_OUTA2= 12 × 470 µF, 6.3 V, C_OUTB1= 4 × 100 µF, 6.3-V, 1210 ceramic, C_OUTB2= 4 × 470 µF, 6.3-V polymer bulk.

Minimum and maximum limits are specified through production test or design of the module/internal controller. Typical values

represent the most likely parametric norm and are provided for reference only (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT VOLTAGE

V_IN

Input voltage range

8

14

V

V_INincreasing (default setting)

7.25

6.5

8

UVLO

V_INundervoltage lockout

V_INdecreasing (default setting)

A_EN = B_EN = GND

V

I_IN(STBY)

Input standby current

mA

OUTPUT VOLTAGE

Boot voltage

5-mV DAC (default setting)

5-mV DAC

0.492

0.25

0.5

5

0.508

1.52

V

Programmable range

Programmable step size

Set-point voltage tolerance

Line regulation

5-mV DAC

mV

0.5%

5-mV DAC, 0.8 V ≤V_OUT≤1 V

8 V ≤V_IN≤14 V, I_OUT= 0 A

0 A ≤I_OUT≤120 A

–0.5%

V_{OUT_A}

0.1%

10

Load regulation

Output voltage ripple

Boot voltage

20-MHz bandwidth, I_OUT= 90 A

5-mV DAC (default setting)

5-mV DAC

mV

V

0.492

0.25

0.5

0.508

1.52

Programmable range

Programmable step size

Set-point voltage tolerance

Line regulation

V

5-mV DAC

5

mV

0.5%

5-mV DAC, 0.8 V ≤V_OUT≤1 V

8 V ≤V_IN≤14 V, I_OUT= 0 A

0 A ≤I_OUT≤120 A

–0.5%

V_{OUT_B}

0.1%

20

Load regulation

Output voltage ripple

20-MHz bandwidth, I_OUT= 30 A

mV

6

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T_A= –40°C to +105°C, V_IN= 12 V, V_OUTA= V_AVSP= 1 V, V_OUTB= V_BVSP= 1 V, V_AVSN= V_BVSN= 0V, I_OUTA= I_OUTB= 0 A, F_SW

= 400 kHz, C_IN1= 24 × 22-µF, 25-V, 1210 ceramic, C_IN2= 2 × 470 µF, electrolytic bulk, C_OUTA1= 12 × 100 µF, 6.3-V, 1210

ceramic, C_OUTA2= 12 × 470 µF, 6.3 V, C_OUTB1= 4 × 100 µF, 6.3-V, 1210 ceramic, C_OUTB2= 4 × 470 µF, 6.3-V polymer bulk.

Minimum and maximum limits are specified through production test or design of the module/internal controller. Typical values

represent the most likely parametric norm and are provided for reference only (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT CURRENT

Output current

Natural convection⁽²⁾

0

120

A

Overcurrent fault threshold

Per phase OCL level

Factory default setting (150% of I_OUTmax)

(default setting)

180

54

I_{OUT_A}

Overcurrent warning threshold Factory default setting (100% of I_OUTmax)

120

Output current

Natural convection⁽²⁾

0

40

Overcurrent fault threshold

Per Phase OCL level

Factory default setting (150% of I_OUTmax)

(default setting)

60

54

40

I_{OUT_B}

Overcurrent warning threshold Factory default setting (100% of I_OUTmax)

PERFORMANCE

I_{OUT_A}= 90 A, V_{OUT_B}disabled

Efficiency⁽¹⁾

92%

I_{OUT_B}= 30 A, V_{OUT_A}= disabled

TIMING

V_VBOOT> 0 V, no faults, TON_DELAY = 0xB1EC

VOUTA start-up time

t_STARTUPA

0.38

0.8

0.48

0.9

0.58

ms

(PAGE 0) (default setting)

V_VBOOT> 0 V, no faults, TON_DELAY = 0xB396

VOUTB start-up time

t_STARTUPB

t_VCCVID

1

500

92

ms

ns

(PAGE 1) (default setting)

VID change to VSP change

Rising-edge blanking time⁽³⁾

ACK of SetVID_x command to start of voltage ramp

MFR_SPEC_09<8:6> = 110b

(default setting)

t_{ON_BLANK}

53

72

2.5

VOUT_TRANSITION_RATE = 0xE028 (default

setting)

SL_SET

SL_SS

Slew rate setting⁽³⁾

mV/µs

AVSP and BVSP slew rate soft-

start⁽³⁾

MFR_SPEC_13<8> = 0b (default setting)

SL_SET/4

SWITCHING FREQUENCY

FREQUENCY_SWITCH = 0x0190 (VOUTA default

setting)

360

400

450

440

kHz

Switching frequency

f_SW

FREQUENCY_SWITCH = 0x01C2 (VOUTB default

setting)

405

350

495

700

kHz

Range⁽³⁾

(1) Phase shedding disabled.

(2) See SOA graph for derating over temperature.

(3) Applies to both VOUTA and VOUTB.

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6.6 References: DAC

Over recommended operating conditions. Minimum, typical and maximum values are specified through production test or

design of the internal controller (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_VIDSTP

VID step size⁽¹⁾

5 mV DAC: Change VID0 HI to LO to HI

5

mV

VOUT_SCALE_LOOP = 0xe808,

VOUT_SCALE_MONITOR = 0xe808

K_RATIO

Voltage divider ratio⁽¹⁾

V_OUToffset LSB⁽¹⁾

1.000

V_{OUT_TRIML}

MFR_SPECIFIC_05 = 0x01

MFR_SPECIFIC_05 = 0x1F

MFR_SPECIFIC_05 = 0xA0

MFR_SPECIFIC_05 = 0x5F

MFR_SPECIFIC_05 = 0xE0

0

37.5

1.25

38.75

–40

2.5

40

mV

–43.25

56.25

–63

–37.75

61.25

–57

V_{OUT_TRIMR}

V_OUToffset range

58.75

–60

(1) Applies to both VOUTA and VOUTB.

6.7 Telemetry

Over recommended operating conditions. Minimum, typical and maximum values are specified through production test or by

design of the module/internal controller (unless otherwise noted)

PARAMETER

TEST CONDITIONS

5-mV DAC : 0.25 V ≤V_VSP≤1.52 V

8 V ≤V_IN≤14 V

MIN

TYP

MAX

UNIT

V_{READ_VOUT}

V_{READ_VIN}

MFR_READ_VOUT accuracy

READ_VIN accuracy

12

mV

–12

±2.25%

±3%

Digital current monitor accuracy,

Rail A (READ_IOUT)

I_{MON_ACC_A}

I_OUT= 120 A

Digital current monitor accuracy,

Rail B (READ_IOUT)

I_{MON_ACC_B}

Temp

I_OUT= 40 A

±3%

0

READ_TEMP1

2

°C

–40°C ≤TSEN ≤150°C

–2

6.8 Current Sense and Calibration

Over recommended operating conditions. Typical values are specified through production test or design of the internal

controller (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Current monitor calibration offset

LSB (per-phase)

I_{MON_CAL_OF1}

I_{MON_CAL_OF2}

I_{MON_CAL_OF3}

I_{MON_CAL_OF4}

I_{MON_CAL_LSB}

I_{MON_CAL_GAIN}

IOUT_CAL_OFFSET resolution (per-phase)

0.125

A

IOUT_CAL_OFFSET = 0xE808 (per-phase)

IOUT_CAL_OFFSET = 0xEFF9 (per-phase)

1

A

Current monitor calibration offset

range (per-phase)

–0.875

Current monitor calibration offset

LSB (total)

IOUT_CAL_OFFSET resolution (total)

0.25

A

IOUT_CAL_OFFSET = 0xE820 (total)

IOUT_CAL_OFFSET = 0xEFE2 (total)

4

A

Current monitor calibration offset

range (total)

–3.75

Current monitor calibration gain

LSB

IOUT_CAL_GAIN resolution

0.3125%

IOUT_CAL_GAIN = 0xD131

IOUT_CAL_GAIN = 0xD150

4.7656

5.25

mΩ

Current monitor calibration gain

range

8

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6.9 Logic Interface Pins: A_EN, A_PGOOD, B_EN, B_PGOOD,RESET

Over recommended operating conditions. Minimum, typical and maximum values are specified through production test or

design of the internal controller (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R_RPGDL

I_VRTTLK

Open-drain pulldown resistance

V_{A_PGOOD}= V_{B_PGOOD}= 0.45 V

36

50

Ω

SDIO, A_PGOOD, B_PGOOD, Hi Z Leakage, 3.3-V

applied in off state

Open-drain leakage current

0.2

2

µA

–2

V_AENL

Channel A ENABLE logic low

Channel A ENABLE logic high

Channel A ENABLE hysteresis

Channel A ENABLE deglitch⁽¹⁾

Channel A I/O 1.1-V leakage

Channel B ENABLE logic low

Channel B ENABLE logic high

Channel B ENABLE hysteresis

Channel B ENABLE deglitch⁽¹⁾

0.7

V

V_AENH

V_AENHYS

t_AENDIG

I_AENH

0.8

0.028

0.2

0.05

0.07

V

µs

µA

V

V_{A_EN}= 1.1 V

25

V_BENL

0.7

V_BENH

V_BENHYS

t_BENDIG

0.8

0.028

0.2

V

0.05

0.07

1.5

V

µs

Channel A ENABLE low to

A_PGOOD low

t_AENVRRDYF

From A_EN low to A_PGOOD low

V_BENH= 1.1 V

µs

I_BENH

Channel B I/O 1.1-V leakage

RESET logic low

25

µA

V

V_RSTL

V_RSTH

t_RSTTDLY

0.8

RESET logic high⁽¹⁾

RESET delay time

1.09

V

1

µs

(1) Specified by design. Not production tested.

6.10 Protections: OVP and UVP

Over recommended operating conditions. Minimum, typical and maximum values are specified through production test or

design of the internal controller (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Measured at the VSP pin wrt VID code. Device

latches OFF.

V_RDYH5

V_RDYH0

330

400

mV

Tracking OVP

Measured at the VSP pin wrt VID code. Device

latches OFF.

140

200

2.5

mV

t_RDYDGLTO

t_RDYDGLTU

V_RDYL

VR_RDY deglitch time

Undervoltage protection⁽²⁾

See⁽¹⁾

µs

f_SW= 500 kHz

4

(V_VSP+ V_DROOP) with respect to VID

370

400

430

mV

Fixed overvoltage protection,

channel A⁽²⁾

V_AVSP> V_OVPfor 1 µs, ENABLE = HI or LO, PWM

to LO

V_OVPA

V_OVPB

2.75

1.9

2.86

V

Fixed overvoltage protection,

channel B⁽²⁾

V_BVSP> V_OVPfor 1 µs, ENABLE = HI or LO, PWM

to LO

1.85

1.95

(1) Time from VSP out of 200-mV or 400-mV VDAC boundary to VR_RDY low.

(2) Can be programmed with different configurations.

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6.11 Typical Characteristics (V_IN= 12 V)

100

95

90

85

80

75

70

100

95

90

85

80

75

70

V_OUT

1.5 V

1.2 V

1.0 V

0.85 V

V_OUT

1.5 V

1.2 V

1.0 V

0.85 V

0

5

10

15

20

25

Output Current (A)

30

35

40

0

10 20 30 40 50 60 70 80 90 100 110 120

Output Current (A)

D007

D001

图6-2. VOUTB Efficiency

图6-1. VOUTA Efficiency

16

14

12

10

8

7

6

5

4

3

2

1

V_OUT

1.5 V

1.2 V

1.0 V

0.85 V

V_OUT

1.5 V

1.2 V

1.0 V

0.85 V

6

4

2

0

10 20 30 40 50 60 70 80 90 100 110 120

Output Current (A)

5

10

15

20

25

Output Current (A)

30

35

40

D002

D008

图6-3. VOUTA Power Dissipation

图6-4. VOUTB Power Dissipation

1.004

1.003

1.002

1.001

1.000

0.999

0.998

0.997

0.996

1.004

1.003

1.002

1.001

1.000

0.999

0.998

0.997

0.996

V_OUT

1.0 V

V_OUT

1.0 V

0

10 20 30 40 50 60 70 80 90 100 110 120

Output Current (A)

0

5

10

15

20

25

Output Current (A)

30

35

40

D004

D010

图6-5. VOUTA Load Regulation

图6-6. VOUTB Load Regulation

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115

105

95

115

105

95

85

75

65

55

Airflow

400LFM

Airflow

400LFM

45

200LFM

100LFM

Nat conv

200LFM

100LFM

Nat conv

35

25

0

20

40

60

80

100

Output Current (A)

120

140

160

20

40

60

80

100

Output Current (A)

120

140

160

D022

D021

V_IN= 12 V

V_OUTA= V_OUTB= 0.8 V

All phases evenly loaded

V_IN= 12 V

V_OUTA= V_OUTB= 1.0 V

All phases evenly loaded

F_SW= 400 kHz

图6-8. Thermal Safe Operating Area

图6-7. Thermal Safe Operating Area

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7 Detailed Description

7.1 Overview

The TPSM831D31 is a PMBus-controlled, dual output 4-phase power module. Both outputs have a

programmable output voltage range of 0.25 V to 1.52 V. The first output is configured as a 3-phase power stage

that can deliver up to 120 A of output current. The second output is a single phase power stage that can deliver

up to 40 A of output current

7.2 Functional Block Diagram

TPSM831D31

Internal

Regultors

(5V/3.3V)

VIN

AVSP

AVSN

Remote

Sense

Amplifier

VOUTA

Loadline

Control

Programmable

Loop

BVSP

BVSN

VIN

Ramp

Generator

A_EN

B_EN

Mode Control,

Phase Manager,

FET Drivers

RESET

I²C Interface

CPU Logic,

Protection,

Status

A_PGOOD

Circuitry

B_PGOOD

Adaptive

On-Time

Control and

Current

Share

Circutry

VOUTB

PMBDATA

PMBCLK

AFE

ADC

DAC

NVM

PMBALERT

GND

ADDR

12

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7.3 Feature Description

7.3.1 DCAP+ Control

For high current applications, D-CAP+ control architecture, combines the benefits of D-CAP constant on-time

control with those of multiphase converters. D-CAP+ control ensures that inductor currents of individual phases

are fed back so the system has accurate droop control and good current-sharing performance as well an error

amplifier is utilized to improve DC accuracy over load and line.

图 7-1 illustrates the operational waveforms of D-CAP+ control architecture with 3 phases in steady state. By

using the adaptive on-time control concept, a pseudo fixed switching frequency of SW_CLK is generated by

comparing the summed inductor currents, ISUM, and the error amplifier output, EA, signal. By distributing the

switching signal to different phases, all phases can be perfectly interleaved in steady state. During load

transients, the switching frequency is varied to improve the transient performance as shown in 图 7-2. Variable

switching frequencies of different phases can be observed.

One important feature of a multiphase converter is the capability to dynamically add or drop the number of

operational phases based on load conditions. The goal is to optimize efficiency while maintaining good load

transient performance.

图7-1. 3-Phase Steady State Switching

图7-2. 3-Phase Transient Operation

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7.3.2 Setting the Load-Line (DROOP)

V

DAC

Slope of Loadline R

LL

V

= R x I

DROOP LL OUT

DROOP

I

OUT

图7-3. Load Line

The loadline can be set with VOUT_DROOP register via PMBus. The programmable range for channel A is

between 0 mΩ and 3.125 mΩ with 64 options, and the range for channel B is between 0 mΩ and 0.875 mΩ with

16 options to fulfill the requirements for different applications. See 表7-27 for the DC load line settings.

7.3.3 Start-Up Timing

The start-up time is the time from when a start condition is received (as programmed by the ON_OFF_CONFIG

command) until the output voltage starts to rise. The start-up time for both outputs can be programmed using the

TON_DELAY command as shown in 表7-1.

表7-1. Start-Up Time

START-UP TIME (ms)⁽¹⁾

MIN

0.38

0.8

TYP

0.48

0.9

MAX

0.58

1

TON_DELAY = 0xB1EC

TON_DELAY = 0xB396

TON_DELAY = 0xBAD1

TON_DELAY = 0xC26E

TON_DELAY = others

1.308 1.408 1.508

2.28

2.432 2.584

Invalid

(1) Channel A (PAGE 0); Channel B (PAGE 1)

7.3.4 Load Transitions

The TPSM831D31 achieves fast load transient performance using the inherent variable switching frequency

characteristics. When there is a sudden load increase, the output voltage rapidly drops, which forces the PWM

pulses to switch sooner and more frequently which causes the inductor current to rapidly increase. As the

inductor current reaches the new load current, the device reaches a steady-state operating condition and the

PWM switching resumes the steady-state frequency.

When there is a sudden load release, the output voltage rapidly rises, which forces the PWM pulses to be

delayed until the inductor current reaches the new load current. At that point, the switching resumes and steady-

state switching continues.

14

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7.3.5 Switching Frequency

The TPSM831D31 switching frequency can be selected from several values between 350 kHz to 700 kHz as

shown in 表7-2. The FREQUENCY_SWITCH command is used to select the desired switching frequency.

表7-2. Switching Frequency Select

FREQUENCY

SELECT (kHz)

COMMAND

350

400

FREQUENCY_SWITCH = 0x015E

FREQUENCY_SWITCH = 0x0190

(VOUTA factory default setting)

FREQUENCY_SWITCH = 0x01C2

(VOUTB factory default setting)

450

500

550

600

650

700

FREQUENCY_SWITCH = 0x01F4

FREQUENCY_SWITCH = 0x0226

FREQUENCY_SWITCH = 0x0258

FREQUENCY_SWITCH = 0x028A

FREQUENCY_SWITCH = 0x02BC

7.3.6 RESET Function

During adaptive voltage scaling (AVS) operation, the voltage may become falsely adjusted to be out of ASIC

operating range. The RESET function returns the voltage to the VBOOT voltage. When the voltage is out of

ASIC operating range, the ASIC issues a RESET signal to the TPSM831D31 device. The device senses this

signal and after a delay of greater than 1 µs, it sets an internal RESET_FAULT signal and sets

VOUT_COMMAND to VBOOT. The device pulls the output voltage to the VBOOT level with the slew rate set by

VOUT_TRANSITION_RATE command.

When the RESET pin signal goes high, the internal RESET_FAULT signal goes low.

表7-3. VBOOT

BOOT VOLTAGE SETTING (5-mV DAC)

MFR_SPEC_11<7:0> = 00h

MFR_SPEC_11<7:0> = 33h

MFR_SPEC_11<7:0> = 83h

MFR_SPEC_11<7:0> = 97h

MFR_SPEC_11<7:0> = BFh

BOOT VOLTAGE (V)

0.000

0.500

0.900

1.000

1.200

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7.3.7 VID Table

The DAC voltage VDAC can be changed via PMBus according to 表7-4.

表7-4. VID Table (5 mV DAC)

VID Hex

VALUE

DAC

STEP

VID Hex

VALUE

DAC

STEP

VID Hex

VALUE

DAC

STEP

VID Hex

VALUE

DAC

STEP

VID Hex

VALUE

DAC

STEP

VID Hex

DAC

STEP

VALUE

D7

D8

D9

DA

DB

DC

DD

DE

DF

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

0.000

0.250

0.255

0.260

0.265

0.270

0.275

0.280

0.285

0.290

0.295

0.300

0.305

0.310

0.315

0.320

0.325

0.330

0.335

0.340

0.345

0.350

0.355

0.360

0.365

0.370

0.375

0.380

0.385

0.390

0.395

0.400

0.405

0.410

0.415

0.420

0.425

0.430

0.435

0.440

0.445

0.450

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

0.460

0.465

0.470

0.475

0.480

0.485

0.490

0.495

0.500

0.505

0.510

0.515

0.520

0.525

0.530

0.535

0.540

0.545

0.550

0.555

0.560

0.565

0.570

0.575

0.580

0.585

0.590

0.595

0.600

0.605

0.610

0.615

0.620

0.625

0.630

0.635

0.640

0.645

0.650

0.655

0.660

0.665

56

57

58

59

5A

5B

5C

5D

5E

5F

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

0.675

0.680

0.685

0.690

0.695

0.700

0.705

0.710

0.715

0.720

0.725

0.730

0.735

0.740

0.745

0.750

0.755

0.760

0.765

0.770

0.775

0.780

0.785

0.790

0.795

0.800

0.805

0.810

0.815

0.820

0.825

0.830

0.835

0.840

0.845

0.850

0.855

0.860

0.865

0.870

0.875

0.880

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

0.890

0.895

0.900

0.905

0.910

0.915

0.920

0.925

0.930

0.935

0.940

0.945

0.950

0.955

0.960

0.965

0.970

0.975

0.980

0.985

0.990

0.995

1.000

1.005

1.010

1.015

1.020

1.025

1.030

1.035

1.040

1.045

1.050

1.055

1.060

1.065

1.070

1.075

1.080

1.085

1.090

1.095

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

1.105

1.110

1.115

1.120

1.125

1.130

1.135

1.140

1.145

1.150

1.155

1.160

1.165

1.170

1.175

1.180

1.185

1.190

1.195

1.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

1.240

1.245

1.250

1.255

1.260

1.265

1.270

1.275

1.280

1.285

1.290

1.295

1.300

1.305

1.310

1.320

1.325

1.330

1.335

1.340

1.345

1.350

1.355

1.360

1.365

1.370

1.375

1.380

1.385

1.390

1.395

1.400

1.405

1.410

1.415

1.420

1.425

1.430

1.435

1.440

1.445

1.450

1.455

1.460

1.465

1.470

1.475

1.480

1.485

1.490

1.495

1.500

1.505

1.510

1.515

1.520

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

16

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VID Hex

表7-4. VID Table (5 mV DAC) (continued)

DAC

VID Hex

VALUE

DAC

VID Hex

VALUE

DAC

VID Hex

VALUE

DAC

VID Hex

VALUE

DAC

STEP

VID Hex

VALUE

DAC

STEP

VALUE

STEP

2A

0.455

55

0.670

80

0.885

AB

1.100

D6

1.315

7.4 Device Functional Modes

7.4.1 Continuous Conduction Mode

The TPSM831D31 device operates in continuous conduction mode (CCM) at a fixed frequency. As programmed

from the factory, phase shedding is disabled and can be enabled with a PMBus command. To begin power

conversion, the EN signal and/or OPERATION command must be asserted high. Following a fault that stops

power conversion, the enable contol must be pulled low and then re-asserted high to resume power conversion.

7.4.2 Operation With EN Signal Control

According to a bit value in the ON_OFF_CONFIG register, the TPSM831D31 device can be commanded to use

the EN pin to enable or disable power conversion, regardless of the state of the OPERATION command. The

TPSM831D31 is factory programmed to use the EN pin only. When the EN pin is pulled low, power conversion

stops immediately without first waiting for a turn-off delay or actively ramping down the output voltage.

7.4.3 Operation With OPERATION Control

According to a bit value in the ON_OFF_CONFIG register, the TPSM831D31 device can be commanded to use

the OPERATION command to enable or disable conversion, regardless of the state of the EN signal.

7.4.4 Operation With EN and OPERATION Control

According to a bit value in the ON_OFF_CONFIG register, the TPSM831D31 device can be commanded to

require both the assertion of the EN pin, and the OPERATION command to enable or disable conversion.

7.5 Programming

7.5.1 PMBus Connections

The TPSM831D31 device can support either 100-kHz class, 400-kHz class or 1-MHz class operation, with 1.8-V

or 3.3-V logic levels. Connection for the PMBus interface should follow the DC specifications given in Section 4.3

of the System Management Bus (SMBus) Specification V3.0 . The complete SMBus specification is available

from the SMBus website, smbus.org.

7.5.2 PMBus Address Selection

The PMBus slave address is set by the voltage on the ADDR pin and is selected with a resistor from the ADDR

pin to GND. Refer to 表7-5.

Note that TPSM831D31 uses 7 bit addressing, per the SMBus specification. Users communicating to the device

using generic I²C drivers should be aware that these 7 bits occupy the most significant bits of the first byte in

each transaction, with the least significant bit being the data direction bit (0 for write operations, 1 for read

operations). That is, for read transactions, the address byte is A₆A₅A₄A₃A₂A₁A₀1 and for write operations the

address byte is A₆A₅A₄A₃A₂A₁A₀0. Refer to the SMBus specification for more information.

表7-5. PMBus Slave Address Selection

V_ADDR(V)

PMBus Address

(7 bit binary)

PMBus Address

(7 bit decimal)

I²C Address Byte

(Write Operation)

I²C Address Byte

(Read Operation)

R_ADDRL(kΩ)

A₆A₅A₄A₃A₂A₁A₀

1011000b

1011001b

1011010b

1011011b

1011100b

1011101b

88d

89d

90d

91d

92d

93d

0

B0h

B2h

B4h

B6h

B8h

BAh

B1h

B3h

B5h

B7h

B9h

BBh

≤0.039 V

0.073 V ± 15 mV

0.122 V ± 15 mV

0.171 V ± 15 mV

0.219 V ± 15 mV

0.268 V ± 15 mV

0.453

0.768

1.13

1.47

1.87

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表7-5. PMBus Slave Address Selection (continued)

V_ADDR(V)

PMBus Address

(7 bit binary)

PMBus Address

(7 bit decimal)

I²C Address Byte

(Write Operation)

I²C Address Byte

(Read Operation)

R_ADDRL(kΩ)

A₆A₅A₄A₃A₂A₁A₀

0.317 V ± 15 mV

0.366 V ± 15 mV

0.415 V ± 15 mV

0.464 V ± 15 mV

0.513 V ± 15 mV

0.562 V ± 15 mV

0.610 V ± 15 mV

0.660 V ± 15 mV

0.708 V ± 15 mV

0.757 V ± 15 mV

0.806 V ± 15 mV

0.854 V ± 15 mV

0.903 V ± 15 mV

0.952 V ± 15 mV

1.000 V ± 15 mV

1.050 V ± 15 mV

1.098 V ± 15 mV

1.147 V ± 15 mV

1.196 V ± 15 mV

1.245 V ± 15 mV

1.294 V ± 15 mV

1.343 V ± 15 mV

1.392 V ± 15 mV

1.440 V ± 15 mV

1.489 V ± 15 mV

1.540 V ± 15 mV

1011110b

1011111b

1100000b

1100001b

1100010b

1100011b

1100100b

1100101b

1100110b

1100111b

1101000b

1101001b

1101010b

1101011b

1101100b

1101101b

1101110b

1101111b

1110000b

1110001b

1110010b

1110011b

1110100b

1110101b

1110110b

1110111b

94d

95d

2.32

2.74

3.24

3.74

4.32

4.99

5.62

6.34

7.15

8.06

9.09

10.0

11.3

12.7

14.3

16.2

18.2

20.5

23.7

27.4

31.6

37.4

45.3

54.9

69.8

95.3

BCh

BEh

C0h

C2h

C4h

C6h

C8h

CAh

CCh

CEh

D0h

D2h

D4h

D6h

D8h

DAh

DCh

DEh

E0h

E2h

E4h

E6h

E8h

EAh

ECh

EEh

BDh

BFh

C1h

C3h

C5h

C7h

C9h

CBh

CDh

CFh

D1h

D3h

D5h

D7h

D9h

DBh

DDh

DFh

E1h

E3h

E5h

E7h

E9h

EBh

EDh

EFh

96d

97d

98d

99d

100d

101d

102d

103d

104d

105d

106d

107d

108d

109d

110d

111d

112d

113d

114d

115d

116d

117d

118d

119d

18

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7.5.3 Supported Commands

The table below summarizes the PMBus commands supported by the TPSM831D31. Only selected commands,

which are most commonly used during device configuration and usage are reproduced in this document. For a

full set of register maps, refer to the accompanying Technical Reference Manual for the controller (TPS53681)

used internal to this device.

DEFAULT VALUE

R/W,

NVM

DEFAULT

BEHAVIOR

CMD

COMMAND NAME

DESCRIPTION

Ch. A

Ch. B

PAGE 0 PAGE 1

Selects which channel subsequent PMBus

commands address

All commands

address Channel A

00h PAGE

RW

RW,

N/A

Conversion

disabled. Margin

None.

Enable or disable each channel, enter or

exit margin.

01h OPERATION

00h

17h

00h

17h

Configure the combination of OPERATION,

and enable pin required to enable power

conversion for each channel.

AVR_EN/BEN pins

NVM only.

02h ON_OFF_CONFIG

Clears all fault status registers to 00h and

releases PMB_ALERT

03h CLEAR_FAULT

04h PHASE

W

Write-only

N/A

00h

Selects which phase of the active channel

subsequent PMBus commands address

Commands

address all phases.

RW

FFh

Used to control writing to the volatile

operating memory (PMBus and restore from

NVM).

Writes to all

commands are

allowed

10h WRITE_PROTECT

RW

Stores all current storable register settings

into NVM as new defaults.

11h STORE_DEFAULT_ALL

W

Write-only

N/A

Restores all storable register settings from

NVM.

12h RESTORE_DEFAULT_ALL

Provides a way for a host system to

determine key PMBus capabilities of the

device.

1 MHz, PEC,

PMB_ALERT

Supported

19h CAPABILITY

R

D0h

SMBALERT_MASK

1Bh

Selects which faults/status bits may to

assert PMB_ALERT

RW,

All bits may assert

00h

(STATUS_VOUT)

NVM PMB_ALERT

SMBALERT_MASK

1Bh

Selects which faults/status bits may to

assert PMB_ALERT

RW,

All bits may assert

(STATUS_IOUT)

NVM PMB_ALERT

LOW_VIN does not

assert

PMB_ALERT

SMBALERT_MASK

1Bh

Selects which faults/status bits may to

assert PMB_ALERT

RW,

NVM

08h

(STATUS_INPUT)

SMBALERT_MASK

1Bh

Selects which faults/status bits may to

assert PMB_ALERT

RW,

All bits may assert

00h

(STATUS_TEMPERATURE)

NVM PMB_ALERT

SMBALERT_MASK

1Bh

Selects which faults/status bits may to

assert PMB_ALERT

RW,

All bits may assert

(STATUS_CML)

NVM PMB_ALERT

SMBALERT_MASK

1Bh

Selects which faults/status bits may to

assert PMB_ALERT

RW,

All bits may assert

(STATUS_MFR_SPECIFIC)

NVM PMB_ALERT

VID mode.

5 mV Step (Ch A),

20h VOUT_MODE

Read-only output mode indicator

R⁽¹⁾

27h

5 mV Step (Ch B)

RW,

0.500 V (Ch A)

21h VOUT_COMMAND

24h VOUT_MAX

Output voltage target

0033h

00FFh

0033h

00FFh

NVM 0.500 V (Ch B)

RW, 1.520 V (Ch A)

NVM 1.520 V (Ch B)

Sets the maximum output voltage

Load the unit with the voltage to which the

output is to be changed when OPERATION

command is set to “Margin High”.

0.000 V (CH A)

RW

25h VOUT_MARGIN_HIGH

26h VOUT_MARGIN_LOW

0000h

0.000 V (Ch B)

Load the unit with the voltage to which the

output is to be changed when OPERATION

command is set to “Margin Low”.

0.000 V (CH A)

RW

0.000 V (Ch B)

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DEFAULT VALUE

R/W,

NVM

DEFAULT

BEHAVIOR

CMD

COMMAND NAME

DESCRIPTION

Ch. A

Ch. B

PAGE 0 PAGE 1

Used to set slew rate settings for output

voltage updates

RW,

2.5 mV/µs (Ch A)

27h VOUT_TRANSITION_RATE

28h VOUT_DROOP

E028h

D000h

E028h

D000h

NVM 2.5 mV/µs (Ch B)

The VOUT_DROOP sets the rate, in mV/A

(mΩ) at which the output voltage decreases

(or increases) with increasing (or

decreasing) output current for use with

Adaptive Voltage Positioning

RW,

NVM

0.000 mΩ(Ch A)

0.000 mΩ(Ch B)

RW,

1.000 (Ch A)

29h VOUT_SCALE_LOOP

2Ah VOUT_SCALE_MONITOR

2Bh VOUT_MIN

Used for scaling the VID code

E808h

0000h

0190h

E808h

0000h

01C2h

NVM 1.000 (Ch B)

RW, 1.000 (Ch A)

NVM 1.000 (Ch B)

RW, 0.000 V (Ch A)

NVM 0.000 V (Ch B)

RW, 400 kHz (Ch A)

Used for scaling output voltage telemetry

Sets the minimum output voltage

Sets the switching frequency

33h FREQUENCY_SWITCH

35h VIN_ON

NVM 450 kHz (Ch B)

Sets value of input voltage at which the

device should start power conversion.

RW,

7.25 V

NVM

F01Dh

Sets the ratio of voltage at the current sense

pins to the sensed current.

RW,

NVM

5.0625 mΩ(Ch A)

5.0625 mΩ(Ch B)

38h IOUT_CAL_GAIN

D144h

E800h

D144h

E800h

0.000 A (Ch A)

0.000 A (Ch B)

(All Phases)

Used to null offsets in the output current

sensing circuit

RW,

NVM

39h IOUT_CAL_OFFSET

Sets the value of the sensed output voltage

which triggers an output overvoltage fault

1.520 V (Ch A)

1.520 V (Ch B)

40h VOUT_OV_FAULT_LIMIT

41h VOUT_OV_FAULT_RESPONSE

44h VOUT_UV_FAULT_LIMIT

45h VOUT_UV_FAULT_RESPONSE

46h IOUT_OC_FAULT_LIMIT

47h IOUT_OC_FAULT_RESPONSE

4Ah IOUT_OC_WARN_LIMIT

4Fh OT_FAULT_LIMIT

R

00FFh

80h

00FFh

80h

Sets the converter response to an output

overvoltage event

Shutdown, do not

restart

Sets the value of the sensed output voltage

which triggers an output undervoltage fault

0.000 V (Ch A)

0.000 V (Ch B)

R

0000h

80h

0000h

80h

Sets the converter response to an output

undervoltage event

RW,

Shutdown, do not

NVM restart

Sets the output overcurrent fault limit, in

amperes

RW,

180 A (Ch A)

00B4h

C0h

003Ch

C0h

NVM⁽¹⁾60 A (Ch B)

RW,

Shutdown, do not

NVM restart

Defines the overcurrent fault response

Sets the output overcurrent warning limit, in

amperes

RW,

120 A (Ch A)

0078h

0087h

80h

0028h

0087h

80h

NVM⁽¹⁾40 A (Ch B)

Sets the output overtemperature fault limit,

in degrees Celsius.

RW,

135 °C (Ch A)

NVM⁽¹⁾135 °C (Ch B)

RW, Shutdown, do not

NVM restart

50h OT_FAULT_RESPONSE

51h OT_WARN_LIMIT

Defines the overtemperature fault response

Sets the output overtemperature warning

limit, in degrees Celsius.

105 °C (Ch A)

105 °C (Ch B)

RW

0069h

RW,

NVM

55h VIN_OV_FAULT_LIMIT

56h VIN_OV_FAULT_RESPONSE

59h VIN_UV_FAULT_LIMIT

5Ah VIN_UV_FAULT_RESPONSE

5Bh IIN_OC_FAULT_LIMIT

Sets the VIN overvoltage fault limit, in volts

Defines the VIN overvoltage fault response

Sets the VIN undervoltage fault limit, in volts

Defines the VIN undervoltage fault response

17.000 V

0011h

Continue

Uninterrupted

R

00h

F80Dh

C0h

RW,

NVM

6.500 V

Shutdown, do not

restart

R

Sets the input current overcurrent fault limit,

in amperes

RW,

NVM

40.0 A

F850h

20

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CMD

DEFAULT VALUE

R/W,

NVM

DEFAULT

BEHAVIOR

COMMAND NAME

DESCRIPTION

Ch. A

Ch. B

PAGE 0 PAGE 1

Shutdown, do not

restart

5Ch IIN_OC_FAULT_RESPONSE

5Dh IIN_OC_WARN_LIMIT

Defines the input overcurrent fault response

R

C0h

Sets the input current overcurrent warning

limit, in amperes

RW,

NVM

32.0 A

F840h

Sets the time, in milliseconds, from when a

start condition is received (as programmed

by the ON_OFF_CONFIG command) until

the output voltage starts to rise

RW,

0.480 ms (Ch A)

60h TON_DELAY

B1ECh

B396h

NVM 0.896 ms (Ch B)

The PIN_OP_WARN_LIMIT command sets

the value of the input power, in watts, that

causes a warning that the input power is

high

6Bh PIN_OP_WARN_LIMIT

RW

450 W

08E1h

78h STATUS_BYTE

79h STATUS_WORD

7Ah STATUS_VOUT

7Bh STATUS_IOUT

7Ch STATUS_INPUT

7Dh STATUS_TEMPERATURE

7Eh STATUS_CML

80h STATUS_MFR_SPECIFIC

88h READ_VIN

PMBus read-only status and flag bits.

Returns the input voltage in volts

RW

R

Current Status

N/A

89h READ_IIN

Returns the input current in amperes

Returns the output voltage in VID format

Returns the output current in amperes

R

8Bh READ_VOUT

R

N/A

8Ch READ_IOUT

R

Returns the highest power stage

temperature in °C

8Dh READ_TEMPERATURE_1

R

Current Status

N/A

96h READ_POUT

97h READ_PIN

Returns the output power in Watts

Returns the input power in Watts

R

Current Status

N/A

33h

Returns the version of the PMBus

specification to which this device complies

PMBus 1.3

Part I, Part II

98h PMBUS_REVISION

99h MFR_ID

R

Loads the unit with bits that contain the

manufacturer’s ID

RW,

NVM

TI

5449h

4331h

0001h

1207h

Loads the unit with bits that contain the

manufacturer’s model number

RW,

3+1 Phase

9Ah MFR_MODEL

9Bh MFR_REVISION

NVM Configuration

Loads the unit with bits that contain the

manufacturer’s model revision

RW,

Rev 1.0

NVM

Loads the unit with bits that contain the

manufacture date

RW,

9Dh MFR_DATE

9Eh MFR_SERIAL

ADh IC_DEVICE_ID

July 2018

NVM

NVM Checksum

R

NVM checksum

TPSM831D31

679E8B7Dh

81h

Returns a number indicating the part

number of the device

Returns a number indicating the device

revision

AEh IC_DEVICE_REV

B0h USER_DATA_00

B1h USER_DATA_01

B2h USER_DATA_02

B3h USER_DATA_03

R

Rev 1.0

Current

00h

RW

Factory Default

Settings

Used for batch NVM programming.

NVM configuration

RW Current

NVM configuration

RW Current

NVM configuration

RW Current

NVM configuration

Factory Default

Settings

Factory Default

Settings

Factory Default

Settings

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DEFAULT VALUE

R/W,

NVM

DEFAULT

BEHAVIOR

CMD

COMMAND NAME

DESCRIPTION

Ch. A

Ch. B

PAGE 0 PAGE 1

RW

Current

Factory Default

Settings

B4h USER_DATA_04

B5h USER_DATA_05

B6h USER_DATA_06

B7h USER_DATA_07

B8h USER_DATA_08

B9h USER_DATA_09

BAh USER_DATA_10

BBh USER_DATA_11

BCh USER_DATA_12

Used for batch NVM programming.

NVM configuration

RW Current

NVM configuration

RW Current

NVM configuration

RW Current

NVM configuration

RW Current

NVM configuration

RW Current

NVM configuration

RW Current

NVM configuration

RW Current

NVM configuration

RW Current

NVM configuration

Factory Default

Settings

Factory Default

Settings

Factory Default

Settings

Factory Default

Settings

Factory Default

Settings

Factory Default

Settings

Factory Default

Settings

Factory Default

Settings

Configures per-phase overcurrent levels,

current share thresholds, and other

miscellaneous settings.

RW

Misc. configuration,

D0h MFR_SPECIFIC_00

003Eh

203Dh

NVM See register maps

Returns information regarding current

imbalance warnings for each phase

D3h MFR_SPECIFIC_03

D4h MFR_SPECIFIC_04

R

Current status

1.25 mV offset

N/A

Returns the output voltage for the active

channel, in linear format

Used to trim the output voltage of the active

channel, by applying an offset to the

currently selected VID code.

RW

D5h MFR_SPECIFIC_05

D6h MFR_SPECIFIC_06

01h

NVM (Ch A and Ch B)

Configures dynamic load line options for

both channels, and selects Auto-DCM

operation.

RW Misc. configuration,

NVM See register maps

0605h

1000h

Misc. configuration,

Configures the internal loop compensation

for both channels.

RW

D7h MFR_SPECIFIC_07

D8h MFR_SPECIFIC_08

D9h MFR_SPECIFIC_09

See to register

NVM

0906h

00h

01C6h

00h

maps

Used to identify catastrophic faults which

occur first, and store this information to NVM

RW

Current status

NVM

Used to configure non-linear transient

performance enhancements such as

undershoot reduction (USR)

RW

Misc. configuration,

46C5h

06C7h

NVM See register maps

Used to configure input current sensing, and

set the maximum output current

RW

Misc. configuration,

DAh MFR_SPECIFIC_10

DBh MFR_SPECIFIC_11

DCh MFR_SPECIFIC_12

C878h

33h

0028h

33h

NVM See register maps

RW VID 051d (Ch A)

NVM VID 051d (Ch B)

RW Misc. configuration,

NVM See register maps

Boot-up VID code for each channel

Used to configure input current sensing and

other miscellaneous settings

C570h

07F0

Used to configure output voltage slew rates,

DAC stepsize, and other miscellaneous

settings.

RW

Misc. configuration,

DDh MFR_SPECIFIC_13

9CE5h

00E5h

NVM See register maps

Used to configure dynamic phase shedding,

and compensation ramp amplitude, and

dynamic ramp amplitude during USR, and

different power states

RW

Misc. configuration,

DEh MFR_SPECIFIC_14

DFh MFR_SPECIFIC_15

0007h

1FFAh

0007h

0000h

NVM See register maps

RW

Misc. configuration,

Used to configure dynamic phase shedding.

NVM See register maps

22

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CMD

DEFAULT VALUE

R/W,

NVM

DEFAULT

BEHAVIOR

COMMAND NAME

DESCRIPTION

Ch. A

Ch. B

PAGE 0 PAGE 1

Used to set the maximum operational phase

number, on-the-fly.

RW

Misc. configuration,

Hardware

Configured

E4h MFR_SPECIFIC_20

F0h MFR_SPECIFIC_32

FAh MFR_SPECIFIC_42

NVM See register maps

Used to set the input over-power warning

NVM Security

RW

450 W

00E1h

0000h

RW

NVM

NVM Security Key

(1) NVM-backed bits in the MFR_SPECIFIC or USER_DATA commands affect the reset value of these commands. Refer to the individual

register maps for more detail.

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7.5.4 Commonly Used PMBus Commands

The following sections describe the most commonly used PMBus commands and their usage in the

configuration, operation and testing of TPSM831D31 power solutions:

• Voltage, Current, Power, and Temperature Readings

• Output Current Sense and Calibration

• Output Voltage Margin Testing

• Loop Compensation

• Converter Protection and Response

• Dynamic Phase Shedding

• NVM Programming

• NVM Security

• Black Box Fault Recording

• Board Identification and Inventory Tracking

• Status Reporting

7.5.5 Voltage, Current, Power, and Temperature Readings

Using an internal ADC, the TPSM831D31 provides a full set of telemetry capabilities, allowing the user to read

back critical information about the converter's input voltage, input current, input power, output voltage, output

current, output power and temperature. The table below summarizes the available commands and their formats.

Register maps for each command are included.

表7-6. Telemetry Functions

Command

Description

Format

Units

Channel/Phase

Shared, Channel A and

B

READ_VIN

READ_IIN

Input voltage telemetry

Linear

V

Shared, Channel A and

B

Input current telemetry

Linear

VID

A

VID Code

A

READ_VOUT

READ_IOUT

Output voltage telemetry (VID format)

Output current telemetry

Per Channel

Per Channel and Per

Phase

Linear

Per Channel, Highest

phase temperature only

READ_TEMPERATURE_1

READ_POUT

Power stage temperature telemetry

Output power telemetry

Linear

°C

W

V

Per Channel

Shared, Channel A and

B

READ_PIN

Input power telemetry

MFR_SPECIFIC_04

Output voltage telemetry (linear format)

Per Channel

7.5.5.1 (88h) READ_VIN

The READ_VIN command returns the input voltage in volts. The two data bytes are formatted in the Linear Data

format. The refresh rate is 1200 µs. The device accesses this command through Read Word transactions, and is

shared between channel A and channel B.

READ_VIN

15

R

14

R

13

12

R

11

R

10

R

9

8

R

READ_VIN_EXP

READ_VIN_MAN

7

6

5

4

3

2

1

0

R

READ_VIN_MAN

LEGEND: R/W = Read/Write; R = Read only

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表7-7. READ_VIN Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

10:0

READ_VIN_EXP

READ_VIN_MAN

R

Current Status

Linear two's complement format exponent.

Linear two's complement format mantissa.

R

7.5.5.2 (89h) READ_IIN

The READ_IIN command returns the input current in amperes. The refresh rate is 100 µs. The two data bytes

are formatted in the Linear Data format. The device accesses this command through Read Word transactions,

and is shared between channel A and channel B.

READ_IIN

15

R

14

R

13

12

R

11

R

10

R

9

8

R

READ_IIN_EXP

READ_IIN_MAN

7

6

5

4

3

2

1

0

R

READ_IIN_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-8. READ_IIN Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

READ_IIN_EXP

R

Current Status

Linear two's complement format exponent.

Linear two's complement format mantissa.

10:0

READ_IIN_MAN

R

Current Status

7.5.5.3 (8Bh) READ_VOUT

The READ_VOUT command returns the actual, measured output voltage. The two data bytes are formatted in

the VID Data format, and the refresh rate is 1200 us. The device accesses this command through Read Word

transactions. READ_VOUT is a paged register. In order to access READ_VOUT command for channel A, PAGE

must be set to 00h. In order to access READ_VOUT register for channel B, PAGE must be set to 01h.

READ_VOUT

15

R

14

R

13

R

12

11

R

0

10

R

9

R

0

8

R

0

R

0

7

6

5

4

3

2

1

0

R

READ_VOUT_VID

LEGEND: R/W = Read/Write; R = Read only

表7-9. READ_VOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

READ_VOUT_VID

R

Current Status

Output voltage, VID format

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7.5.5.4 (8Ch) READ_IOUT

The READ_IOUT command returns the output current in amperes.

READ_IOUT is a linear format command.

READ_IOUT is a paged register. In order to access READ_IOUT for channel A, PAGE must be set to 00h. In

order to access the READ_IOUT register for channel B, PAGE must be set to 01h. For simultaneous access of

channels A and B, the PAGE command must be set to FFh. READ_IOUT is also a phased register. Depending

on the configuration of the design, for channel A, PHASE must be set to 00h to access Phase 1, 01h to access

Phase 2, etc... PHASE must be set to FFh to access all phases simultaneously. PHASE may also be set to 80h

to readack the total phase current (sum of all active phase currents for the active channel) measurement, as

described in 节7.5.6. Note that READ_IOUT is only a phased command for Channel A (PAGE 0).

The READ_IOUT command must be accessed through Read Word transactions.

READ_IOUT

15

R

14

R

13

12

11

10

R

9

8

R

READ_IOUT_EXP

READ_IOUT_MAN

7

6

5

4

3

2

1

0

R

READ_IOUT_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-10. READ_IOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

READ_IOUT_EXP

R

Current Status

Linear two's complement format exponent.

Linear two's complement format mantissa.

10:0

READ_IOUT_MAN

R

Current Status

Attempts to write to this command results in invalid transactions. The device ignores the invalid data, sets the

appropriate flags in STATUS_CML and STATUS_WORD, and asserts the PMB_ALERT signal to notify the

system host of an invalid transaction.

7.5.5.5 (8Dh) READ_TEMPERATURE_1

The READ_TEMPERATURE_1 command returns the temperature in degree Celsius. The two data bytes are

formatted in the Linear Data format. The refresh rate is 1200 µs.

READ_TEMPERATURE_1 is a linear format command.

READ_TEMPERATURE_1 is a paged register. In order to access OPERATION command for channel A,

READ_TEMPERATURE_1 must be set to 00h. In order to access READ_TEMPERATURE_1 register for

channel B, PAGE must be set to 01h. For simultaneous access of channels A and B, the PAGE command must

be set to FFh.

The READ_TEMPERATURE_1 command must be accessed through Read Word transactions.

READ_TEMPERATURE_1

15

R

14

R

13

12

11

10

R

9

8

R

READ_TEMP_EXP

READ_TEMP_MAN

7

6

5

4

3

2

1

0

R

READ_TEMP_MAN

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LEGEND: R/W = Read/Write; R = Read only

表7-11. READ_TEMPERATURE_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

10:0

READ_TEMP_EXP

READ_TEMP_MAN

R

Current Status

Linear two's complement format exponent.

Linear two's complement format mantissa.

R

Attempts to write to this command results in invalid transactions. The device ignores the invalid data, sets the

appropriate flags in STATUS_CML and STATUS_WORD, and asserts the PMB_ALERT signal to notify the

system host of an invalid transaction

7.5.5.6 (96h) READ_POUT

The READ_POUT command returns the calculated output power, in watts for the active channel. The refresh

rate is 1200 µs.

READ_POUT is a linear format command.

READ_POUT is a paged register. In order to access READ_POUT command for channel A, PAGE must be set

to 00h. In order to access READ_POUT register for channel B, PAGE must be set to 01h. For simultaneous

access of channels A and B, the PAGE command must be set to FFh.

The READ_POUT command must be accessed through Read Word transactions.

READ_POUT

15

R

14

R

13

12

11

10

R

9

8

R

READ_POUT_EXP

READ_POUT_MAN

7

6

5

4

3

2

1

0

R

READ_POUT_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-12. READ_POUT Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

READ_POUT_EXP

R

Current Status

Linear two's complement format exponent.

Linear two's complement format mantissa.

10:0

READ_POUT_MAN

R

Attempts to write to this command results in invalid transactions. The device ignores the invalid data, sets the

appropriate flags in STATUS_CML and STATUS_WORD, and asserts the PMB_ALERT signal to notify the

system host of an invalid transaction

7.5.5.7 (97h) READ_PIN

The READ_PIN command returns the calculated input power. The refresh rate is 1200 µs.

READ_PIN is a linear format command.

The READ_PIN command must be accessed through Read Word transactions.

The READ_PIN command is shared between Channel A and Channel B. All transactions to this command

affects both channels regardless of the PAGE command.

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READ_PIN

15

R

14

R

13

12

R

11

R

10

R

9

8

R

READ_PIN_EXP

READ_PIN_MAN

7

6

5

4

3

2

1

0

R

READ_PIN_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-13. READ_PIN Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

10:0

READ_PIN_EXP

READ_PIN_MAN

R

Current Status

Linear two's complement format exponent.

Linear two's complement format mantissa.

R

7.5.5.8 (D4h) MFR_SPECIFIC_04

The MFR_SPECIFIC_04 command is used to return the output voltage for the active channel, in the linear

format (READ_VOUT uses VID format).

The MFR_SPECIFIC_04 command must be accessed through Read Word transactions.

MFR_SPECIFIC_04 is a Linear format command.

MFR_SPECIFIC_04 is a paged register. In order to access MFR_SPECIFIC_04 command for channel A, PAGE

must be set to 00h. In order to access the MFR_SPECIFIC_04 register for channel B, PAGE must be set to 01h.

MFR_SPECIFIC_04

15

R

14

R

13

12

11

10

R

9

8

R

VOUT_LIN_EXP

VOUT_LIN_MAN

7

6

5

4

3

2

1

0

R

VOUT_LIN_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-14. MFR_SPECIFIC_04 Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

10:0

VOUT_LIN_EXP

VOUT_LIN_MAN

R

Current Status

Linear format two's complement exponent.

Linear format two's complement mantissa.

R

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7.5.6 Output Current Sense and Calibration

The READ_IOUT command may be used to read the individual phase currents, and the total channel current.

7.5.6.1 Reading Individual Phase Currents

Using the PAGE and PHASE commands, the TPSM831D31 can be configured to return output current

information for each individual phase. The examples below demonstrate this process:

Example #1: Read back the output current of Channel A, First Phase

1. Select Channel A. Write PAGE to 00h

2. Select first phase. Write PHASE to 00h

3. Read READ_IOUT

Example #2: Read back the output current of Channel B, Second Phase

1. Select Channel B. Write PAGE to 01h

2. Select second phase. Write PHASE to 01h

3. Read READ_IOUT

7.5.6.1.1 Reading Total Current

When the PHASE command is set to 80h, the TPSM831D31 device is configured to return the total channel

current (sum of individual phase currents) in response to the READ_IOUT command.

7.5.6.1.2

Example: Read the Total Output Current of Channel A

1. Select Channel A. Write PAGE to 00h

2. Select total current measurement. Write PHASE to 80h

3. Read READ_IOUT

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7.5.7 Output Voltage Margin Testing

The TPSM831D31 provides several commands to enable voltage margin testing.

The upper two MARGIN bits in the OPERATION command can be used to toggle the active channel between

three states:

1. Margin None (MARGIN = 0000b). The output voltage target is equal to VOUT_COMMAND.

2. Margin Low (MARGIN = 01xxb). The output voltage target is equal to VOUT_MARGIN_LOW.

3. Margin High (MARGIN = 10xxb). The output voltage target is equal to VOUT_MARGIN_HIGH.

In order to use OPERATION, the active channel must be configured for to respect the OPERATION command,

via ON_OFF_CONFIG. Output voltage transitions occur at the slew rate defined by VOUT_TRANSITION_RATE.

表7-15. Slew Rate Settings

PARAMETER

TEST CONDITIONS

MIN

5

TYP

6

MAX

UNIT

VOUT_TRANSITION_RATE = 0xE050

VOUT_TRANSITION_RATE = 0xE0A0

VOUT_TRANSITION_RATE = 0xE0F0

VOUT_TRANSITION_RATE = 0xE140

VOUT_TRANSITION_RATE = 0xE190

VOUT_TRANSITION_RATE = 0xE1E0

VOUT_TRANSITION_RATE = 0xE230

VOUT_TRANSITION_RATE = 0xE280

VOUT_TRANSITION_RATE = 0xE005

VOUT_TRANSITION_RATE = 0xE00A

VOUT_TRANSITION_RATE = 0xE00F

VOUT_TRANSITION_RATE = 0xE014

VOUT_TRANSITION_RATE = 0xE019

VOUT_TRANSITION_RATE = 0xE01E

VOUT_TRANSITION_RATE = 0xE023

VOUT_TRANSITION_RATE = 0xE028

VOUT_TRANSITION_RATE = others

7

mV/µs

10

12

18

24

30

36

42

48

14 mV/µs

mV/µs

15

20

25

30

35

40

SL_SETSlew rate setting

0.3125

0.625

0.9375

1.25

1.5625

1.875

2.1875

2.5

Invalid data

SL_SET

AVSP and BVSP slew rate

SL_F

mV/µs

SetVID_Fast

SL_SET/ 4

SL_SET/ 2

SL_SET/ 4

SL_SET/ 16

mV/µs

SL_S1

AVSP and BVSP slew rate slow

MFR_SPEC_13<8> = 0b

MFR_SPEC_13<8> = 1b

AVSP and BVSP slew rate slew

rate soft-start

SL_SS

The lower two MARGIN bits in the OPERATION command select overvoltage or undervoltage fault handling

during margin testing:

1. Ignore Faults (MARGIN = xx01b) . Overvoltage and undervoltage faults do not trigger during margin tests.

2. Act on Faults (MARGIN = xx10b). Overvoltage and undervoltage faults trigger during margin tests.

Example: Output Voltage Margin Testing (Ignore Faults)

1. Write to the PAGE command to select the desired channel (E.g. PAGE = 00h for channel A).

2. Write VOUT_COMMAND to the desired VID code during Margin None operation.

3. Write VOUT_MARGIN_LOW to the desired VID code during Margin Low operation.

4. Write VOUT_MARGIN_HIGH to the desired VID code during Margin High operation.

5. Write MFR_SPECIFIC_02 to 01h to ensure that the PMBus interface has control of the output voltage.

6. Set the CMD bit in OPERATION to 1b to ensure the device is configured to respect the OPERATION

command.

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7. Margin None. Write OPERATION to 80h.

8. Margin Low. Write OPERATION to 94h.

9. Margin High. Write OPERATION to A4h.

7.5.7.1 (01h) OPERATION

The OPERATION command is used to turn the device output on or off in conjunction with the input from the

AVR_EN pin for channel A, and BEN pin for channel B, acc ording to the configuration of the ON_OFF_CONFIG

command. It is also used to set the output voltage to the upper or lower MARGIN levels.

OPERATION is a paged register. In order to access OPERATION command for channel A, PAGE must be set to

00h. In order to access OPERATION register for channel B, PAGE must be set to 01h. For simultaneous access

of channels A and B, the PAGE command must be set to FFh.

The OPERATION command must be accessed through Read Byte/Write Byte transactions.

OPERATION

7

6

R

0

5

4

3

2

1

RW

0

RW

0

RW

ON

RW

MARGIN

LEGEND: R/W = Read/Write; R = Read only

表7-16. OPERATION Register Field Descriptions

Bit

Field

Type

Reset

Description

Enable/disable power conversion for the currently selected

channel(s) according to the PAGE command, when the

ON_OFF_CONFIG command is configured to require input from

the ON bit for output control. Note that there may be several

other requirements that must be satisfied before the currently

selected channel(s) can begin converting power (e.g. input

voltages above UVLO thresholds, AVR_EN/BEN pins high if

required by ON_OFF_CONFIG, etc...)

7

ON

RW

0b

0b: Disable power conversion

1b: Enable power conversion

Set the output voltage to either the value selected by the

VOUT_MARGIN_HIGH or MARGIN_LOW commands, for the

currently selected channel(s), according to the PAGE command.

0000b: Margin Off. Output voltage is set to the value of

VOUT_COMMAND

0101b: Margin Low (Ignore Fault). Output voltage is set to the

value of VOUT_MARGIN_LOW.

5:2

MARGIN

RW

0000b

0110b: Margin Low (Act on Fault). Output voltage is set to the

value of VOUT_MARGIN_LOW.

1001b: Margin High (Ignore Fault). Output voltage is set to the

value of VOUT_MARGIN_HIGH

1010b: Margin High (Act on Fault). Output voltage is set to the

value of VOUT_MARGIN_HIGH.

1:0

0

RW

00b

These bits are writeable but should always be set to 00b.

Note that the VOUT_MAX_WARN bit in STATUS_VOUT can be caused by a margin operation, if "Act on Fault"

is selected, and the VOUT_MARGIN_HIGH/VOUT_MARGIN_LOW value loaded by the margin operation

exceeds the value of VOUT_COMMAND.

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7.5.7.2 (26h) VOUT_MARGIN_LOW

The VOUT_MARGIN_LOW command loads the unit with the voltage to which the output is to be changed when

the OPERATION command is set to “Margin Low”.

VOUT_MARGIN_LOW is a VID format command. The VOUT_MARGIN_LOW command must be accessed

through Read Word/Write Word transactions.

VOUT_MARGIN_LOW is a paged register. In order to access VOUT_MARGIN_LOW for channel A, PAGE must

be set to 00h. In order to access the VOUT_MARGIN_LOW register for channel B, PAGE must be set to 01h.

For simultaneous access of channels A and B, the PAGE command must be set to FFh.

VOUT_MARGIN_LOW

15

R

14

R

13

R

12

11

R

0

10

R

9

R

0

8

R

0

R

0

7

6

5

4

3

2

1

0

RW

VOUT_MARGL_VID

LEGEND: R/W = Read/Write; R = Read only

表7-17. VOUT_MARGIN_LOW Register Field Descriptions

Bit

Field

Type

Reset

Description

Used to set the output voltage to be loaded when the active

PAGE is set to Margin Low, in VID format.

7:0

VOUT_MARGL_VID

RW

00h

7.5.7.3 (25h) VOUT_MARGIN_HIGH

The VOUT_MARGIN_HIGH command loads the unit with the voltage to which the output is to be changed when

the OPERATION command is set to “Margin High”.

VOUT_MARGIN_HIGH is a VID format command. The VOUT_MARGIN_HIGH command must be accessed

through Read Word/Write Word transactions.

VOUT_MARGIN_HIGH is a paged register. In order to access VOUT_MARGIN_HIGH for channel A, PAGE

must be set to 00h. In order to access the VOUT_MARGIN_HIGH register for channel B, PAGE must be set to

01h. For simultaneous access of channels A and B, the PAGE command must be set to FFh.

VOUT_MARGIN_HIGH

15

R

14

R

13

R

12

11

R

0

10

R

9

R

0

8

R

0

R

0

7

6

5

4

3

2

1

0

RW

VOUT_MARGH_VID

LEGEND: R/W = Read/Write; R = Read only

表7-18. VOUT_MARGIN_HIGH Register Field Descriptions

Bit

Field

Type

Reset

Description

Used to set the output voltage to be loaded when the active

PAGE is set to Margin High, in VID format.

7:0

VOUT_MARGH_VID

RW

00h

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7.5.8 Loop Compensation

The TPSM831D31 provides several options for tuning the output voltage feedback and response to transients.

These may be configured by programming the MFR_SPECIFIC_07, VOUT_DROOP, and MFR_SPECIFIC_14.

Several such parameters may be configured through these commands:

• DC Load Line - Selects the DC shift in output voltage corresponding to increased output current. The DC

load line affects both the final value the output voltage settles to, as well as the settling time. Use the

VOUT_DROOP command to select the DC load line.

• Integration Time Constant - In order to maintain DC accuracy, the control loop includes an integration

stage. Use MFR_SPECIFIC_07 to select the integration time constant.

• Integration Path Gain - The gain of the integration and AC paths may be selected independently. The AC

and DC gains both affect the small-signal bandwidth of the converter. Use MFR_SPECIFIC_07 to select the

integration path gain.

• AC Load Line - Selects the AC response to output voltage error. The AC load line affects the settling and

response time following a load transient event. MFR_SPECIFIC_07 Use the MFR_SPECIFIC_07 command

to select the AC load line.

• AC Path Gain - The gain of the integration and AC paths may be selected independently. The AC and DC

gains both affect the small-signal bandwidth of the converter. Use MFR_SPECIFIC_07 to select the AC path

gain.

• Ramp Amplitude - Smaller ramp settings result in faster response, but may also lead to increased frequency

jitter. Likewise, large ramp settings result in lower frequency jitter, but may be slightly slower to respond to

changing conditions. The ramp setting also affects the small-signal bandwidth of the converter. Use

MFR_SPECIFIC_14 to select the ramp high setting.

表7-19. Dynamic Integration and Undershoot Reduction (T_A= 25°C)

PARAMETER

TEST CONDITIONS

MFR_SPEC_12<10:8> = 000b;

MFR_SPEC_12<10:8> = 001b;

MFR_SPEC_12<10:8> = 010b;

MFR_SPEC_12<10:8> = 011b;

MFR_SPEC_12<10:8> = 100b;

MFR_SPEC_12<10:8> = 101b;

MFR_SPEC_12<10:8> = 110b;

MFR_SPEC_12<10:8> = 111b;

MFR_SPEC_12<7:4> = 0000b;

MFR_SPEC_12<7:4> = 0001b;

MFR_SPEC_12<7:4> = 0010b;

MFR_SPEC_12<7:4> = 0011b;

MFR_SPEC_12<7:4> = 0100b;

MFR_SPEC_12<7:4> = 0101b;

MFR_SPEC_12<7:4> = 0110b;

MFR_SPEC_12<7:4> = 0111b;

MFR_SPEC_12<7:4> = 1000b;

MFR_SPEC_12<7:4> = 1001b;

MFR_SPEC_12<7:4> = 1010b;

MFR_SPEC_12<7:4> = 1011b;

MFR_SPEC_12<7:4> = 1100b;

MFR_SPEC_12<7:4> = 1101b;

MFR_SPEC_12<7:4> = 1110b;

MFR_SPEC_12<7:4> = 1111b;

MIN

TYP

100

150

200

250

300

350

400

OFF

1

MAX

116

175

230

285

345

400

455

UNIT

mV

µs

90

135

175

225

270

315

360

Dynamic integration voltage

setting

V_DYN

2

µs

3

µs

4

µs

5

µs

6

µs

7

µs

8

µs

Dynamic integration time

constant

t_DINT

12

13

14

15

16

17

18

19

µs

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表7-19. Dynamic Integration and Undershoot Reduction (T_A= 25°C) (continued)

PARAMETER

TEST CONDITIONS

MFR_SPEC_09<14:12> = 000b;

MFR_SPEC_09<14:12> = 001b;

MFR_SPEC_09<14:12> = 010b;

MFR_SPEC_09<14:12> = 011b;

MFR_SPEC_09<14:12> = 100b;

MFR_SPEC_09<14:12> = 101b;

MFR_SPEC_09<14:12> = 110b;

MFR_SPEC_09<14:12> = 111b;

MFR_SPEC_09<2:0> = 000b;

MFR_SPEC_09<2:0> = 001b;

MFR_SPEC_09<2:0> = 010b;

MFR_SPEC_09<2:0> = 011b;

MFR_SPEC_09<2:0> = 100b;

MFR_SPEC_09<2:0> = 101b;

MFR_SPEC_09<2:0> = 110b;

MFR_SPEC_09<2:0> = 111b;

MFR_SPEC_09<5> = 0b;

MIN

120

155

190

230

265

300

335

TYP

140

180

220

260

300

340

380

OFF

90

MAX

UNIT

mV

160

205

245

290

335

375

420

mV

V_USR2

USR level 2 voltage setting

mV

70

100

130

160

185

215

240

110

140

170

205

240

270

305

mV

120

150

180

210

240

270

OFF

3

mV

V_USR1

USR level 1 voltage setting

mV

phases

mV

Maximum phase added in USR

level 1

PH_USR1

MFR_SPEC_09<5> = 1b;

4

MFR_SPEC_09<4:3> = 00b;

MFR_SPEC_09<4:3> = 01b;

MFR_SPEC_09<4:3> = 10b;

MFR_SPEC_09<4:3> = 11b;

2

5

9

15

20

25

10

mV

Dynamic integration/USR voltage

hysteresis

V_OUSRHYS

10

15

mV

20

mV

表7-20. Ramp Selections

TEST CONDITIONS

PARAMETER

MIN

30

TYP

40

MAX

55

UNIT

mV

MFR_SPEC_14<2:0> = 000b

MFR_SPEC_14<2:0> = 001b

MFR_SPEC_14<2:0> = 010b

MFR_SPEC_14<2:0> = 011b

MFR_SPEC_14<2:0> = 100b

MFR_SPEC_14<2:0> = 101b

MFR_SPEC_14<2:0> = 110b

MFR_SPEC_14<2:0> = 111b

70

80

95

110

150

190

230

270

305

120

160

200

240

280

320

135

175

215

255

300

335

V_RAMP

RAMP Setting

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7.5.8.1 (D7h) MFR_SPECIFIC_07

The MFR_SPECIFIC_07 command is used to configure the internal loop compensation for both channels. The

MFR_SPECIFIC_07 command must be accessed through Write Word/Read Word transactions.

MFR_SPECIFIC_07 is a paged register. In order to access MFR_SPECIFIC_07 command for channel A, PAGE

must be set to 00h. In order to access the MFR_SPECIFIC_07 register for channel B, PAGE must be set to 01h.

MFR_SPECIFIC_07

15

R

14

R

13

12

11

10

9

8

RW

0

INT_GAIN

INT_TC

7

6

5

4

3

2

1

0

RW

AC_GAIN

ACLL

LEGEND: R/W = Read/Write; R = Read only

表7-21. MFR_SPECIFIC_07 Register Field Descriptions

Bit

15:14

13:12

11:8

7:6

Field

Type

Reset

Description

Not used

INT_GAIN

INT_TC

AC_GAIN

ACLL

R

0

Not used and set to 0.

Integration path gain. See 表7-22.

RW

NVM

Integration time constant. See 表7-23.

AC path gain. See 表7-24.

5:0

AC Load Line. See 表7-25.

表7-22. Integration path gain settings

INT_GAIN (binary)

Integration path gain (V/V)

00b

01b

10b

11b

2 × AC_GAIN

1 × AC_GAIN

0.66 × AC_GAIN

0.5 × AC_GAIN

表7-23. Integration time constant settings

INT_TC (binary)

Time constant (µs)

0000b

5

0001b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

1010b

1011b

1100b

1101b

1110b

10

15

20

25

30

35

40

1

2

3

4

5

6

7

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表7-23. Integration time constant settings (continued)

INT_TC (binary)

Time constant (µs)

1111b

8

表7-24. AC path gain settings

AC_GAIN (binary)

AC path gain (V/V)

00b

01b

10b

11b

1

1.5

2

0.5

表7-25. AC load line settings

Bin

0

ACLL (hex)

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

Bin

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

ACLL (hex)

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

AC Load line (mΩ)

0.0000

0.1250

0.2500

0.3125

0.3750

0.4375

0.5000

0.5625

0.6250

0.7500

0.7969

0.8125

0.8281

0.8438

0.8594

0.8750

0.8906

0.9063

0.9219

0.9375

0.9531

0.9688

0.9844

1.000

1.6250

1.7500

1.8750

1.9375

2.000

1

2

3

4

5

2.0625

2.1250

2.1875

2.2500

2.375

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

2.4218

2.4375

2.4531

2.4687

2.4843

2.5000

2.5156

2.5312

2.5468

2.5625

2.5781

2.5937

2.609

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

2.625

1.0156

1.0313

1.0469

1.0625

1.1250

1.2500

1.3750

1.5000

2.6406

2.6562

2.6718

2.6875

2.750

2.875

3.000

3.125

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7.5.8.2 (28h) VOUT_DROOP

The VOUT_DROOP command sets the rate, in mV/A (mΩ) at which the output voltage decreases (or increases)

with increasing (or decreasing) output current for use with adaptive voltage positioning. This is also referred to as

the DC Load Line (DCLL).

VOUT_DROOP is a linear format command. The VOUT_DROOP command must be accessed through Read

Word/Write Word transactions.

VOUT_DROOP is a paged register. In order to access VOUT_DROOP for channel A, PAGE must be set to 00h.

In order to access the VOUT_DROOP register for channel B, PAGE must be set to 01h. For simultaneous

access of channels A and B, the PAGE command must be set to FFh.

VOUT_DROOP

15

R

14

R

13

12

11

10

9

RW

8

R

RW

VDROOP_EXP

VDROOP_MAN

7

6

5

4

3

2

1

0

RW

VDROOP_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-26. VOUT_DROOP Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

VDROOP_EXP

R

11010b

Linear two's complement fixed exponent, –6. LSB = 0.015625 mΩ

Linear two's complement mantissa. See table of acceptable values

below, note that Channel A and Channel B support different

acceptable values of VOUT_DROOP.

10:0

VDROOP_MAN

RW

NVM

The table below summarizes the acceptable values of VOUT_DROOP for channel A and channel B. Attempts to

write any value other than those specified in the table below are treated as invalid data. The device ignores

invalid data, sets the appropriate flags in STATUS_CML and STATUS_WORD and asserts the PMB_ALERT to

notify the system host of an invalid transaction.

表7-27. Acceptable VOUT_DROOP Values

DC Load Line

VOUT_DROOP

(hex)

Supported by

Channel A

Supported by

Channel B

Bin

(mΩ)

0

1

D000h

D008h

D010h

D014h

D018h

D01Ch

D020h

D024h

D028h

D030h

D033h

D034h

D035h

D036h

D037h

Yes

0

0.125

0.25

2

3

0.3125

0.375

0.4375

0.5

4

5

6

7

0.5625

0.625

0.7031

0.7969

0.8125

0.8281

0.8438

0.8594

8

9

10

11

12

13

14

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表7-27. Acceptable VOUT_DROOP Values (continued)

DC Load Line

VOUT_DROOP

(hex)

Supported by

Channel A

Supported by

Channel B

Bin

(mΩ)

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

D038h

D039h

D03Ah

D03Bh

D03Ch

D03Dh

D03Eh

D03Fh

D040h

D041h

D042h

D043h

D044h

D048h

D050h

D058h

D060h

D068h

D070h

D078h

D07Ch

D080h

D084h

D088h

D08Ch

D090h

D098h

D09Bh

D09Ch

D09Dh

D09Eh

D09Fh

D0A0h

D0A1h

D0A2h

D0A3h

D0A4h

D0A5h

D0A6h

D0A7h

D0A8h

D0A9h

D0AAh

D0ABh

D0ACh

Yes

No

0.875

0.8906

0.9063

0.9219

0.9375

0.9531

0.9688

0.9844

1

1.0156

1.0313

1.0469

1.0625

1.125

1.25

1.375

1.5

1.625

1.75

1.875

1.9375

2

2.0625

2.125

2.1875

2.25

2.328

2.4218

2.4375

2.4531

2.4687

2.4843

2.5

2.5156

2.5312

2.5468

2.5625

2.5781

2.5937

2.609

2.625

2.6406

2.6562

2.6718

2.6875

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表7-27. Acceptable VOUT_DROOP Values (continued)

DC Load Line

VOUT_DROOP

(hex)

Supported by

Channel A

Supported by

Channel B

Bin

(mΩ)

60

61

62

63

D0B0h

D0B8h

D0C0h

D0C8h

Yes

No

2.75

2.875

3

3.125

7.5.9 Converter Protection and Response

The TPSM831D31 supports a variety of power supply protection features. The table below summarizes these

protection features, and their related PMBus registers. See the following sections for more details.

表7-28. TPSM831D31 Protection and Response

Threshold

Response

Command Name

Default Value

Command Name

Default Value

Output Voltage

1.520 V (Ch A)

1.520 V (Ch B)

Shutdown,

do not restart

Over-Voltage Protection

VOUT_OV_FAULT_LIMIT

VOUT_MAX

VOUT_OV_FAULT_RESPONSE

VOUT_UV_FAULT_RESPONSE

Maximum Allowed Output

Voltage

1.520 V (Ch A)

1.520 V (Ch B)

Refer to Register Description

0.000 V (Ch A)

0.000 V (Ch B)

Shutdown,

do not restart

Under-Voltage Protection

VOUT_UV_FAULT_LIMIT

VOUT_MIN

Minimum Allowed Output

Voltage

0.000 V (Ch A)

0.000 V (Ch B)

Refer to Register Description

Output Current

180 A (Ch A)

60 A (Ch B)

Shutdown,

do not restart

Over-Current Protection

IOUT_OC_FAULT_LIMIT

IOUT_OC_WARN_LIMIT

IOUT_OC_FAULT_RESPONSE

N/A. Warning Only.

120 A (Ch A)

40 A (Ch B)

Over-Current Warning

Input Voltage

Turn-On Threshold

VIN_ON

7.25 V

N/A

Continue

Uninterrupted

Over-Voltage Protection

VIN_OV_FAULT_LIMIT

17.000 V

VIN_OV_FAULT_RESPONSE

Shutdown,

do not restart

Under-Voltage Protection

Input Current

VIN_UV_FAULT_LIMIT

6.50 V

VIN_UV_FAULT_RESPONSE

Shutdown,

do not restart

Over-Current Protection

IIN_OC_FAULT_LIMIT

IIN_OC_WARN_LIMIT

40.0 A

32.0 A

IIN_OC_FAULT_RESPONSE

N/A. Warning Only

Over-Current Warning

Temperature

Over-Temperature

Protection

135 °C (Ch A)

135 °C (Ch B)

Shutdown,

do not restart

OT_FAULT_LIMIT

OT_FAULT_RESPONSE

N/A. Warning Only.

105 °C (Ch A)

105 °C (Ch B)

Over-Temperature Warning OT_WARN_LIMIT

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7.5.10 Output Overvoltage Protection and Response

The output overvoltage thresholds track the configured maximum output voltage, VOUT_MAX, with a fixed

offset, and may be read back in VID format via the read-only VOUT_OV_FAULT_LIMIT command. The converter

response to an overvoltage fault is configured by the read-only VOUT_OV_FAULT_RESPONSE command.

7.5.10.1 (40h) VOUT_OV_FAULT_LIMIT

The VOUT_OV_FAULT_LIMIT is used to read back the value of the output voltage measured at the sense or

output pins that causes an output overvoltage fault in VID format. VOUT_OV_FAULT_LIMIT is a VID format

command, and must be accessed through Read Word/Write Word transactions. VOUT_OV_FAULT_LIMIT is a

paged register. In order to access VOUT_OV_FAULT_LIMIT for channel A, PAGE must be set to 00h. In order to

access the VOUT_OV_FAULT_LIMIT register for channel B, PAGE must be set to 01h. For simultaneous access

of channels A and B, the PAGE command must be set to FFh.

VOUT_OV_FAULT_LIMIT

15

R

14

R

13

R

12

11

R

0

10

R

9

R

0

8

R

0

R

0

7

6

5

4

3

2

1

0

R

VO_OVF_VID

LEGEND: R/W = Read/Write; R = Read only

表7-29. VOUT_OV_FAULT_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

VO_OVF_VID

R

See below.

Read-only overvoltage fault limit, in VID format.

When the 5-mV DAC mode VID table is selected via MFR_SPECIFIC_13, the device sets

VOUT_OV_FAULT_LIMIT register to FFh. When the 10-mV DAC mode VID table is enabled, the device

determines VOUT_OV_FAULT_LIMIT according to the value of VOUT_MAX, and applies a fixed offset value.

7.5.10.2 (41h) VOUT_OV_FAULT_RESPONSE

The VOUT_OV_FAULT_RESPONSE instructs the device on what action to take in response to an output

overvoltage fault. The VOUT_OV_FAULT_RESPONSE command must be accessed through Read Byte

transactions. The VOUT_OV_FAULT_RESPONSE command is shared between Channel A and Channel B. All

transactions to this command affects both channels regardless of the PAGE command.

Upon triggering the over-voltage fault, the device is latched off, and:

• sets the VOUT_OV_FAULT bit in the STATUS_BYTE

• sets the VOUT bit in the STATUS_WORD

• sets the VOUT_OV_FAULT bit in the STATUS_VOUT register, and

• notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not set)

VOUT_OV_FAULT_RESPONSE

7

6

5

4

3

2

1

0

R

VO_OV_RESP

LEGEND: R/W = Read/Write; R = Read only

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表7-30. VOUT_OV_FAULT_RESPONSE Register Field Descriptions

Bit

Field

Type

Reset

Description

80h: Latch-off and do not restart. To clear a shutdown event due to a fault event,

the user must toggle the AVR_EN/BEN pin and/or the ON bit in OPERATION, per

the settings in ON_OFF_CONFIG, or power cycle the bias power to the V3P3 pin

of the controller device.

7:0

VO_OV_RESP

R

80h

7.5.11 Maximum Allowed Output Voltage Setting

The VOUT_MAX command sets an upper limit on the output voltage that the unit may be commanded to,

regardless of an other commands or combinations. The intent of this command is to provide a safeguard against

a user accidentally setting the output voltage to a possibly destructive level.

7.5.11.1 (24h) VOUT_MAX

The VOUT_MAX command sets an upper limit on the output voltage that the unit may be commanded to,

regardless of an other commands or combinations. The intent of this command is to provide a safeguard against

a user accidentally setting the output voltage to a possibly destructive level. VOUT_MAX is a VID format

command, and must be accessed through Read Word/Write Word transactions. VOUT_MAX is a paged register.

In order to access VOUT_MAX for channel A, PAGE must be set to 00h. In order to access the

VOUT_COMMAND register for channel B, PAGE must be set to 01h. For simultaneous access of channels A

and B, the PAGE command must be set to FFh.

The device detects that an attempt has been made to program the output to a voltage greater than the value set

by the VOUT_MAX command. Attempts to program the output voltage greater than VOUT_MAX can include

VOUT_COMMAND attempts, and margin events while the VOUT_MARGIN_HIGH/VOUT_MARGIN_LOW

values exceed the value of VOUT_MAX. The device treats these events as warning conditions and not as fault

conditions. If an attempt is made to program the output voltage higher than the limit set by the VOUT_MAX

command, the device:

• clamps the commanded output voltage to VOUT_MAX,

• sets the OTHER bit in the STATUS_BYTE,

• sets the VOUT bit in the STATUS_WORD,

• sets the VOUT_MAX warning bit in the STATUS_VOUT register, and

• notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not set).

It is important for the user to program this register according to the maximum output voltage the device can

support.

VOUT_MAX

15

R

14

R

13

R

12

11

R

0

10

R

9

R

0

8

R

0

R

0

7

6

5

4

3

2

1

0

RW

VOUT_MAX_VID

LEGEND: R/W = Read/Write; R = Read only

表7-31. VOUT_MAX Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

VOUT_MAX_VID

RW

NVM

Used to set the maximum VOUT of the device in VID format.

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7.5.12 Output Undervoltage Protection and Response

The output undervoltage protection threshold is configured based on commanded output voltage,

VOUT_COMMAND, including the shift due to the DC load line, and a fixed offset. The undervoltage threshold

may be read back in VID format via the read-only VOUT_UV_FAULT_LIMIT command. The converter response

to an overvoltage fault is configured by the read-only VOUT_UV_FAULT_RESPONSE command.

7.5.12.1 (44h) VOUT_UV_FAULT_LIMIT

The VOUT_UV_FAULT_LIMIT is used to read back the value of the output voltage measured at the sense or

output pins that causes an output undervoltage fault in VID format. VOUT_UV_FAULT_LIMIT is a VID format

command, and must be accessed through Read Word transactions. VOUT_UV_FAULT_LIMIT is a paged

register. In order to access VOUT_UV_FAULT_LIMIT for channel A, PAGE must be set to 00h. In order to

access the VOUT_UV_FAULT_LIMIT register for channel B, PAGE must be set to 01h. For simultaneous access

of channels A and B, the PAGE command must be set to FFh.

VOUT_UV_FAULT_LIMIT

15

R

14

R

13

R

12

11

R

0

10

R

9

R

0

8

R

0

R

0

7

6

5

4

3

2

1

0

R

VO_UVF_VID

LEGEND: R/W = Read/Write; R = Read only

表7-32. VOUT_UV_FAULT_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

VO_UVF_VID

R

See below.

Read-only undervoltage fault limit, in VID format.

7.5.12.2 (45h) VOUT_UV_FAULT_RESPONSE

The VOUT_UV_FAULT_RESPONSE instructs the device on what action to take in response to an output

undervoltage fault.

Upon triggering the undervoltage fault, the device:

• sets the OTHER bit in the STATUS_BYTE

• sets the VOUT bit in the STATUS_WORD

• sets the VOUT_UV_FAULT bit in the STATUS_VOUT register, and

• notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not set)

The VOUT_UV_FAULT_RESPONSE command must be accessed through Read Byte/Write Byte transactions.

The VOUT_UV_FAULT_RESPONSE command is shared between Channel A and Channel B. All transactions to

this command affects both channels regardless of the PAGE command.

VOUT_UV_FAULT_RESPONSE

7

6

5

4

3

2

1

0

RW

VO_UV_RESP

LEGEND: R/W = Read/Write; R = Read only

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表7-33. VOUT_UV_FAULT_RESPONSE Register Field Descriptions

Bit

Field

Type

Reset

Description

00h: Ignore. The controller sets the appropriate status bits, and alerts the host, and

continues converting power.

BAh: Shutdown and restart. The controller shuts down the channel on which the fault

occurred, and attempts to restart after a delay of 20 ms. This process occurs

continuously until the condition causing the fault has been removed, or the controller

has been disabled.

7:0

VO_UV_RESP

RW

NVM

80h: Latch-off and do not restart. To clear a shutdown event due to a fault event, the

user must toggle the AVR_EN/BEN pin and/or the ON bit in OPERATION, per the

settings in ON_OFF_CONFIG, or power cycle the bias power to the V3P3 pin of the

controller device.

7.5.13 Minimum Allowed Output Voltage Setting

The VOUT_MIN command sets a lower bound on the output voltage to which the unit can be commanded,

regardless of any other commands or combinations. The intent of this command is to provide a safeguard

against a user accidentally setting the output voltage to a possibly destructive level rather than to be the primary

output under voltage protection.

7.5.13.1 (2Bh) VOUT_MIN

The VOUT_ MIN command sets a lower bound on the output voltage to which the unit can be commanded,

regardless of any other commands or combinations. The intent of this command is to provide a safeguard

against a user accidentally setting the output voltage to a possibly destructive level rather than to be the primary

output under voltage protection. VOUT_MIN is a VID format command, and must be accessed through Read

Word/Write Word transactions. VOUT_MIN is a paged register. In order to access VOUT_MIN for channel A,

PAGE must be set to 00h. In order to access the VOUT_MIN register for channel B, PAGE must be set to 01h.

For simultaneous access of channels A and B, the PAGE command must be set to FFh.

If an attempt is made to program the output voltage lower than the limit set by this command, the device:

• clamps the commanded output voltage to VOUT_MIN

• sets the OTHER bit in the STATUS_BYTE

• sets the VOUT bit in the STATUS_WORD

• sets the VOUT_MIN warning bit in the STATUS_VOUT register, and

• notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not set).

VOUT_MIN

15

R

14

R

13

R

12

R

11

R

0

10

R

9

R

0

8

R

0

7

6

5

4

3

2

1

0

RW

VOUT_MIN_VID

LEGEND: R/W = Read/Write; R = Read only

表7-34. VOUT_MIN Register Field Descriptions

Bit

Field

Type

Reset

Description

Sets a lower bound for output voltage programming for the

active PAGE, is set to in VID format.

7:0

VOUT_MIN_VID

RW

NVM

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7.5.14 Output Overcurrent Protection and Response

Overcurrent thresholds are configured using the IOUT_OC_FAULT_LIMIT. When the overcurrent fault threshold

is reached, the converter will respond according to the settings in IOUT_OC_FAULT_RESPONSE. The

IOUT_OC_WARN_LIMIT may also be used to configure an information-only overcurrent warning, which triggers

prior to an overcurrent fault. Note, that the MFR_SPECIFIC_00 command, not listed below, also contains

settings for per-phase overcurrent limits. Refer to the device Technical Reference Manual for more information.

7.5.14.1 (46h) IOUT_OC_FAULT_LIMIT

The IOUT_OC_FAULT_LIMIT command sets the value of the total output current, in amperes, that causes the

over-current detector to indicate an over-current fault condition. The command has two data bytes and the data

format is Linear as shown in the table below. The units are amperes. IOUT_OC_FAULT_LIMIT is a linear format

command, and must be accessed through Read Word/Write Word transactions. IOUT_OC_FAULT_LIMIT is a

paged register. In order to access IOUT_OC_FAULT_LIMIT command for channel A, PAGE must be set to 00h.

In order to access IOUT_OC_FAULT_LIMIT register for channel B, PAGE must be set to 01h. For simultaneous

access of channels A and B, the PAGE command must be set to FFh.

IOUT_OC_FAULT_LIMIT

15

R

14

R

13

R

12

11

10

9

8

R

RW

IOOCF_EXP

IOOCF_MAN

7

6

5

4

3

2

1

0

RW

IOOCF_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-35. IOUT_OC_FAULT_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

IOOCF_EXP

R

00000b

Linear two's complement exponent, 0. LSB = 1.0 A

10:0

IOOCF_MAN

RW

See below.

Linear two's complement mantissa

At power-on, or after a RESTORE_DEFAULT_ALL operation, the device loads the IOUT_OC_FAULT_LIMIT

command with the value of IOUT_MAX × 1.50. The IOUT_MAX bits for each channel are stored in

MFR_SPECIFIC_10 (PAGE 0 for channel A, PAGE 1 for channel B). IOUT_OC_FAULT_LIMIT may be changed

during operation, but returns to this value on reset.

7.5.14.2 (4Ah) IOUT_OC_WARN_LIMIT

The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes the over-

current detector to indicate an over-current warning condition. IOUT_OC_WARN_LIMIT is a linear format

command, and must be accessed through Read Word/Write Word transactions. IOUT_OC_WARN_LIMIT is a

paged register. In order to access IOUT_OC_WARN_LIMIT command for channel A, PAGE must be set to 00h.

In order to access IOUT_OC_WARN_LIMIT register for channel B, PAGE must be set to 01h. For simultaneous

access of channels A and B, the PAGE command must be set to FFh.

Upon triggering the overcurrent warning, the device:

• sets the OTHER bit in the STATUS_BYTE

• sets the IOUT bit in the STATUS_WORD

• sets the IOUT Over current Warning bit in the STATUS_IOUT register, and

• notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not set)

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IOUT_OC_WARN_LIMIT

15

R

14

R

13

R

12

11

10

9

8

R

RW

IOOCW_EXP

IOOCW_MAN

7

6

5

4

3

2

1

0

RW

IOOCW_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-36. IOUT_OC_WARN_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

10:0

IOOCW_EXP

IOOCW_MAN

R

00000b

See below.

Linear two's complement exponent, 0. LSB = 1.0 A

Linear two's complement mantissa.

RW

At power-on, or after a RESTORE_DEFAULT_ALL operation, the device loads the IOUT_OC_WARN_LIMIT

command with the value of IOUT_MAX. The IOUT_MAX bits for each channel are stored in MFR_SPECIFIC_10

(PAGE 0 for channel A, PAGE 1 for channel B). IOUT_OC_WARN_LIMIT may be changed during operation, but

returns to this value on reset.

7.5.14.3 (47h) IOUT_OC_FAULT_RESPONSE

The IOUT_OC_FAULT_RESPONSE instructs the device on what action to take in response to an output over-

current fault. The IOUT_OC_FAULT_RESPONSE command must be accessed through Read Byte/Write Byte

transactions. The IOUT_OC_FAULT_RESPONSE command is shared between Channel A and Channel B. All

transactions to this command affects both channels regardless of the PAGE command.

备注

IOUT_OC_WARN_LIMIT maximum default value is 180A for VOUTA and 60A for VOUTB. If an

application maximum load current is less than 180A, IOUT_OC_WARN_LIMIT needs to change as the

default maximum load current value is restored each time after power-on or

RESTORE_DEFAULT_ALL operation.

Upon triggering the over-current fault, the device is latched off, and:

• sets the IOUT_OC_FAULT bit in the STATUS_BYTE

• sets the IOUT bit in the STATUS_WORD

• sets the IOUT_OC_FAULT bit in the STATUS_IOUT register, and

• notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not set)

IOUT_OC_FAULT_RESPONSE

7

6

5

4

3

2

1

0

RW

IO_OC_RESP

LEGEND: R/W = Read/Write; R = Read only

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表7-37. IOUT_OC_FAULT_RESPONSE Register Field Descriptions

Bit

Field

Type

Reset

Description

C0h: Latch-off and do not restart. To clear a shutdown event due to a fault event, the

user must toggle the AVR_EN/BEN pin and/or the ON bit in OPERATION, per the

settings in ON_OFF_CONFIG, or power cycle the bias power to the V3P3 pin of the

controller device.

7:0

IO_OC_RESP

RW

NVM

FAh: Shutdown and restart. The controller will shutdown the channel on which the

fault occurred, and attempt to restart 20ms later. This will occur continuously until the

condition causing the fault has disappeared, or the controller has been disabled.

7.5.14.4 Per Phase Overcurrent Limit Thresholds

表7-38. OCL

PARAMETER

TEST CONDITIONS

MIN

12.5

16.5

20.5

24.5

28.5

32.5

36.5

40.5

44.5

48.5

52.5

56.5

60.5

64.5

68.5

72.5

12

TYP

14.5

18.5

22.5

26.5

30.5

34.5

38.5

42.5

46.5

50.5

54.5

58.5

62.5

66.5

70.5

74.5

14

MAX

16.5

20.5

24.5

28.5

32.5

36.5

40.5

44.5

48.5

52.5

56.5

60.5

64.5

68.5

72.5

76.5

16

UNIT

A

MFR_SPEC_00<3:0>, (PAGE0) = 0000b

MFR_SPEC_00<3:0>, (PAGE0) = 0001b

MFR_SPEC_00<3:0>, (PAGE0) = 0010b

MFR_SPEC_00<3:0>, (PAGE0) = 0011b

MFR_SPEC_00<3:0>, (PAGE0) = 0100b

MFR_SPEC_00<3:0>, (PAGE0) = 0101b

MFR_SPEC_00<3:0>, (PAGE0) = 0110b

MFR_SPEC_00<3:0>, (PAGE0) = 0111b

MFR_SPEC_00<3:0>, (PAGE0) = 1000b

MFR_SPEC_00<3:0>, (PAGE0) = 1001b

MFR_SPEC_00<3:0>, (PAGE0) = 1010b

MFR_SPEC_00<3:0>, (PAGE0) = 1011b

MFR_SPEC_00<3:0>, (PAGE0) = 1100b

MFR_SPEC_00<3:0>, (PAGE0) = 1101b

MFR_SPEC_00<3:0>, (PAGE0) = 1110b

MFR_SPEC_00<3:0>, (PAGE0) = 1111b

MFR_SPEC_00<3:0>, (PAGE1) = 0000b

MFR_SPEC_00<3:0>, (PAGE1) = 0001b

MFR_SPEC_00<3:0>, (PAGE1) = 0010b

MFR_SPEC_00<3:0>, (PAGE1) = 0011b

MFR_SPEC_00<3:0>, (PAGE1) = 0100b

MFR_SPEC_00<3:0>, (PAGE1) = 0101b

MFR_SPEC_00<3:0>, (PAGE1) = 0110b

MFR_SPEC_00<3:0>, (PAGE1) = 0111b

MFR_SPEC_00<3:0>, (PAGE1) = 1000b

MFR_SPEC_00<3:0>, (PAGE1) = 1001b

MFR_SPEC_00<3:0>, (PAGE1) = 1010b

MFR_SPEC_00<3:0>, (PAGE1) = 1011b

MFR_SPEC_00<3:0>, (PAGE1) = 1100b

MFR_SPEC_00<3:0>, (PAGE1) = 1101b

MFR_SPEC_00<3:0>, (PAGE1) = 1110b

MFR_SPEC_00<3:0>, (PAGE1) = 1111b

Phase OCL levels for Channel A

(ACSPx-VREF), valley current

limit

I_OCLAx

16

18

20

22

24

26

28

30

32

34

36

38

40

Phase OCL levels for Channel B

(BCSPx-VREF), valley current

limit

40

42

44

I_OCLBx

44

46

48

50

52

54

56

58

60

62

64

66

68

70

72

74

76

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7.5.15 Input Under-Voltage Lockout (UVLO)

The TPSM831D31 may not start converting power until the power stage input voltage reaches the level specified

by VIN_ON.

7.5.15.1 (35h) VIN_ON

The VIN_ON command sets the value of the input voltage, in Volts, at which the unit should start power

conversion. This command has two data bytes encoded in linear data format, and must be accessed through

Read Word/Write Word transactions. The VIN_ON command is shared between Channel A and Channel B. All

transactions to this command will affect both channels regardless of the PAGE command. The supported range

for VIN_ON is from 4.0 V volts to 11.25 Volts.

VIN_ON

15

R

14

R

13

R

12

R

11

R

10

9

8

RW

VINON_EXP

VINON_MAN

7

6

5

4

3

2

1

0

RW

VINON_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-39. VIN_ON Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

VINON_EXP

R

11110b

Linear two's complement exponent, –2. LSB = 0.25 V

Linear two's complement mantissa. See the table of acceptable values

below.

10:0

VINON_MAN

RW

NVM

表7-40. Acceptable Values of VIN_ON

VIN_ON (hex)

Turn-On Voltage (V)

F01Dh

7.25

8.25

F021h

F025h

9.25

F029h

10.25

11.25

F02Dh

表7-41. VIN Undervoltage Fault Limits

VIN_UV_FAULT_LIMIT (hex)

Fault Threshold (V)

F80Fh

F811h

F813h

F815h

F817h

7.5

8.5

9.5

10.5

11.5

7.5.16 Input Over-Voltage Protection and Response

The TPSM831D31 provides protection from input transients via the VIN_OV_FAULT_LIMIT and

VIN_OV_FAULT_RESPONSE commands.

7.5.16.1 (55h) VIN_OV_FAULT_LIMIT

The VIN_OV_FAULT_LIMIT command sets the value of the input voltage that causes an input overvoltage fault.

VIN_OV_FAULT_LIMIT is a linear format command, and must be accessed through Read Word/Write Word

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transactions. The VIN_OV_FAULT_LIMIT command is shared between Channel A and Channel B. All

transactions to this command will affect both channels regardless of the PAGE command.

VIN_OV_FAULT_LIMIT

15

R

14

R

13

R

12

11

10

9

RW

8

R

RW

VIN_OVF_EXP

VIN_OVF_MAN

7

6

5

4

3

2

1

0

RW

VIN_OVF_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-42. VIN_OV_FAULT_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

VIN_OVF_EXP

R

00000b

Linear two's complement exponent, 0. LSB = 1 V

Linear two's complement mantissa. Valid values of the mantissa

range from 0d to 31d.

10:0

VIN_OVF_MAN

RW

NVM

7.5.16.2 (56h) VIN_OV_FAULT_RESPONSE

The VIN_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an input

overvoltage fault. The VIN_OV_FAULT_RESPONSE command must be accessed through Read Byte

transactions. The VIN_OV_FAULT_RESPONSE command is shared between Channel A and Channel B. All

transactions to this command will affect both channels regardless of the PAGE command.

In response to the VIN_OV_LIMIT being exceeded, the device:

• sets the OTHER bit in the STATUS_BYTE

• sets the INPUT bit in the upper byte of the STATUS_WORD

• sets the VIN_OV_FAULT bit in the STATUS_INPUT register, and

• notifies the host (assert the PMB_ALERT signal, if the corresponding mask bit in SMBALERT_MASK is not

set)

VIN_OV_FAULT_RESPONSE

7

6

5

4

3

2

1

0

R

VI_OVF_RESP

LEGEND: R/W = Read/Write; R = Read only

表7-43. VIN_OV_FAULT_RESPONSE Register Field Descriptions

Bit

Field

Type

Reset

Description

00h: Ignore. The controller will set the appropriate status bits,

and alert the host, but continue converting power.

7:0

VI_OVF_RESP

R

00h

7.5.17 Input Undervoltage Protection and Response

The TPSM831D31 provides protection from input transients via the VIN_UV_FAULT_LIMIT and

VIN_UV_FAULT_RESPONSE commands.

7.5.17.1 (59h) VIN_UV_FAULT_LIMIT

The VIN_UV_FAULT_LIMIT command sets the value of the input voltage that causes an Input Under voltage

Fault. This fault is masked until the input exceeds the value set by the VIN_ON command for the first time, and

the unit has been enabled. VIN_UV_FAULT_LIMIT is a linear format command, and must be accessed through

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Read Word/Write Word transactions. The VIN_UV_FAULT_LIMIT command is shared between Channel A and

Channel B. All transactions to this command will affect both channels regardless of the PAGE command.

VIN_UV_FAULT_LIMIT

15

14

13

RW

12

11

10

9

RW

8

RW

VIN_UVF_EXP

VIN_UVF_MAN

7

6

5

4

3

2

1

0

RW

VIN_UVF_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-44. VIN_UV_FAULT_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

NVM

Description

15:11

10:0

VIN_UVF_EXP

VIN_UVF_MAN

RW

Linear two's complement exponent. See the table of acceptable values below.

Linear two's complement mantissa. See the table of acceptable values below.

RW

表7-45. Acceptable Values of VIN_UV_FAULT_LIMIT

VIN_UV_FAULT_LIMIT (hex)

VIN UVF Limit (V)

F80Dh

F80Fh

F811h

F813h

F815h

F817h

6.5

7.5

8.5

9.5

10.5

11.5

7.5.17.2 (5Ah) VIN_UV_FAULT_RESPONSE

The VIN_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an input

overvoltage fault. The VIN_UV_FAULT_RESPONSE command must be accessed through Read Byte

transactions. The VIN_UV_FAULT_RESPONSE command is shared between Channel A and Channel B. All

transactions to this command will affect both channels regardless of the PAGE command.

In response to the VIN_UV_LIMIT being exceeded, the device:

• sets the OTHER bit in the STATUS_BYTE

• sets the INPUT bit in the upper byte of the STATUS_WORD

• sets the VIN_UV_FAULT bit in the STATUS_INPUT register, and

• notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not set)

VIN_UV_FAULT_RESPONSE

7

6

5

4

3

2

1

0

R

VI_UVF_RESP

LEGEND: R/W = Read/Write; R = Read only

表7-46. VIN_UV_FAULT_RESPONSE Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

VI_UVF_RESP

R

C0h

C0h: Shutdown and restart when the fault condition is no longer present.

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7.5.18 Input Overcurrent Protection and Response

Input overcurrent protection is configured via the IIN_OC_FAULT_LIMIT, IIN_OC_WARN_LIMIT and

IIN_OC_FAULT_RESPONSE commands.

7.5.18.1 (5Bh) IIN_OC_FAULT_LIMIT

The IIN_OC_FAULT_LIMIT command sets the value of the input current, in amperes, that causes the input over

current fault condition. IIN_OC_FAULT_LIMIT is a linear format command, and must be accessed through Read

Word/Write Word transactions. The IIN_OC_FAULT_LIMIT command is shared between Channel A and Channel

B. All transactions to this command will affect both channels regardless of the PAGE command.

IIN_OC_FAULT_LIMIT

15

R

14

R

13

R

12

11

10

9

8

R

RW

IIN_OCF_EXP

IIN_OCF_MAN

7

6

5

4

3

2

1

0

RW

IIN_OCF_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-47. IIN_OC_FAULT_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

IIN_OCF_EXP

R

11111b

Linear two's complement format exponent, –1. LSB = 0.5 A.

Linear two's complement format mantissa. Acceptable values

range from 0d (0 A) to 127d (63.5 A).

10:0

IIN_OCF_MAN

RW

See below.

During operation, the IIN_OC_FAULT_LIMIT may be changed to any valid value, as specified above. The

IIN_OC_FAULT_LIMIT command has only limited NVM backup. The table below summarizes the values that

IIN_OC_FAULT_LIMIT may be restored to following a reset, or RESTORE_DEFAULT_ALL operation.

表7-48. IIN_OC_FAULT_LIMIT reset values

IIN_OC_FAULT_LIMIT during

NVM store operation

IIN_OC_FAULT_LIMIT following

Reset/Restore Operation

Hex Value

F810h

F820h

8 A

16 A

24 A

32 A

40 A

48 A

56 A

63.5 A

16 A

F830h

24 A

F840h

32 A

40 A

F850h

F860h

48 A

F870h

56 A

F87Fh

63.5 A

Any other valid data

7.5.18.2 (5Dh) IIN_OC_WARN_LIMIT

The IIN_OC_WARN_LIMIT command sets the value of the input current, in amperes, that causes the input

overcurrent warning condition. The IIN_OC_WARN_LIMIT command must be accessed through Read Word/

Write Word transactions. The IIN_OC_WARN_LIMIT command is shared between Channel A and Channel B. All

transactions to this command will affect both channels regardless of the PAGE command.

Upon triggering the over-current warning, the device:

• sets the OTHER bit in the STATUS_BYTE

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• sets the INPUT bit in the STATUS_WORD

• sets the IIN_Over-current Warning bit in the STATUS_INPUT register, and

• notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not set)

IIN_OC_WARN_LIMIT

15

R

14

R

13

R

12

11

10

R

9

8

R

IIN_OCW_EXP

IIN_OCW_MAN

7

6

5

4

3

2

1

0

R

RW

IIN_OCW_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-49. IIN_OC_FAULT_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

IIN_OCW_EXP

R

11111b

Linear two's complement format exponent, –1. LSB = 0.5 A.

Linear two's complement format mantissa. Acceptable values

range from 0d (0 A) to 127d (63.5 A).

10:0

IIN_OCW_MAN

RW

See below.

During operation, the IIN_OC_FAULT_LIMIT may be changed to any valid value, as specified above. The

IIN_OC_FAULT_LIMIT command has only limited NVM backup. The table below summarizes the values that

IIN_OC_FAULT_LIMIT may be restored to following a reset, or RESTORE_DEFAULT_ALL operation.

表7-50. IIN_OC_WARN_LIMIT reset values

IIN_OC_WARN_LIMIT during

NVM store operation

IIN_OC_WARN_LIMIT following

Reset/Restore Operation

Hex Value

F810h

F820h

8 A

16 A

24 A

32 A

40 A

48 A

56 A

63.5 A

16 A

F830h

24 A

F840h

32 A

40 A

F850h

F860h

48 A

F870h

56 A

F87Fh

63.5 A

Any other valid data

7.5.18.3 (5Ch) IIN_OC_FAULT_RESPONSE

The IIN_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an input

over-current fault. IIN_OC_FAULT_RESPONSE command must be accessed through Read Byte transactions.

The IIN_OC_FAULT_RESPONSE command is shared between Channel A and Channel B. All transactions to

this command will affect both channels regardless of the PAGE command.

Upon triggering the input over-current fault, the device is latched off, and:

• sets the OTHER bit in the STATUS_BYTE

• sets the INPUT bit in the STATUS_WORD

• sets the IIN_OC_FAULT bit in the STATUS_INPUT register, and

• notifies the host (asserts PMB_ALERT and VR_FAULT, if the corresponding mask bit in SMBALERT_MASK

is not set)

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IIN_OC_FAULT_RESPONSE

7

6

5

4

3

2

1

0

R

IIN_OC_RESP

LEGEND: R/W = Read/Write; R = Read only

表7-51. IIN_OC_FAULT_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

C0h: Latch-off and do not restart. To clear a shutdown event due

to a fault event, the user must toggle the AVR_EN/BEN pin

and/or the ON bit in OPERATION, per the settings in

ON_OFF_CONFIG, or power cycle the bias power to the V3P3

pin of the controller device.

7:0

IIN_OC_RESP

R

C0h

7.5.19 Overtemperature Protection and Response

Overtemperature protection is configured via the OT_FAULT_LIMIT, OT_WARN_LIMIT and

OT_FAULT_RESPONSE commands.

7.5.19.1 (4Fh) OT_FAULT_LIMIT

The OT_FAULT_LIMIT command sets the value of the temperature limit, in degrees Celsius, that causes an

overtemperature fault condition when the sensed temperature from the external sensor exceeds this limit. The

default value is selected inMFR_SPECIFIC_13, using the OTF_DFLT bit. Refer to the device Technical

Reference Manual for more information. OT_FAULT_LIMIT is a linear format command, and must be accessed

through Read Word/Write Word transactions. OT_FAULT_LIMIT is a paged register. In order to access

OT_FAULT_LIMIT command for channel A, PAGE must be set to 00h. In order to access OT_FAULT_LIMIT

register for channel B, PAGE must be set to 01h. For simultaneous access of channels A and B, the PAGE

command must be set to FFh.

OT_FAULT_LIMIT

15

R

14

R

13

R

12

11

10

9

8

R

RW

OTF_EXP

OTF_MAN

7

6

5

4

3

2

1

0

RW

OTF_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-52. OT_FAULT_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

OTF_EXP

R

00000b

Linear two's complement exponent, 0. LSB = 1 °C

Linear two's complement mantissa. The default

OT_FAULT_LIMIT is set by the OTF_DFLT bit in

MFR_SPECIFIC_13.

10:0

OTF_MAN

RW

NVM

7.5.19.2 (51h) OT_WARN_LIMIT

The OT_WARN_LIMIT command sets the over-temperature warning event indicator for unit at the desired

temperature, in degrees Celsius. OT_WARN_LIMIT is a linear format command, and must be accessed through

Read Word/Write Word transactions. OT_WARN_LIMIT is a paged register. In order to access

OT_WARN_LIMIT command for channel A, PAGE must be set to 00h. In order to access OT_WARN_LIMIT

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register for channel B, PAGE must be set to 01h. For simultaneous access of channels A and B, the PAGE

command must be set to FFh.

In response to the OT_WARN_LIMIT being exceeded, the device:

• sets the TEMPERATURE bit in the STATUS_BYTE

• sets the Over-temperature Warning bit in the STATUS_TEMPERATURE register, and

• notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not set)

OT_WARN_LIMIT

15

R

14

R

13

R

12

11

10

9

8

R

RW

OTW_EXP

OTW_MAN

7

6

5

4

3

2

1

0

RW

OTW_MAN

LEGEND: R/W = Read/Write; R = Read only

表7-53. OT_WARN_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

15:11

OTF_EXP

R

00000b

Linear two's complement exponent, 0. LSB = 1 °C

Linear two's complement mantissa. Default = 105 °C

10:0

OTF_MAN

RW

105d

7.5.19.3 (50h) OT_FAULT_RESPONSE

The OT_FAULT_RESPONSE instructs the device on what action to take in response to an output over-

temperature fault. The OT_FAULT_RESPONSE command must be accessed through Read Byte/Write Byte

transactions. The OT_FAULT_RESPONSE command is shared between Channel A and Channel B. All

transactions to this command will affect both channels regardless of the PAGE command.

Upon triggering the over-temperature fault, the device is latched off, and:

• sets the TEMPERATURE bit in the STATUS_BYTE

• sets the OT_FAULT bit in the STATUS_TEMPERATURE register, and

• notifies the host (asserts PMB_ALERT, if the corresponding mask bit in SMBALERT_MASK is not set).

OT_FAULT_RESPONSE

7

6

5

4

3

2

1

0

RW

OTF_RESP

LEGEND: R/W = Read/Write; R = Read only

表7-54. OT_FAULT_RESPONSE Register Field Descriptions

Bit

Field

Type

Reset

Description

80h: Latch-off and do not restart. To clear a shutdown event due to a fault

event, the user must toggle the AVR_EN/BEN pin and/or the ON bit in

OPERATION, per the settings in ON_OFF_CONFIG, or power cycle the

bias power to the V3P3 pin of the controller device.

7:0

OTF_RESP

RW

NVM

C0h: Shutdown and restart when the fault condition is no longer present.

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7.5.20 Dynamic Phase Shedding (DPS)

The dynamic phase shedding (DPS) feature allows the TPSM831D31 to dynamically select the number of

operational phases for each channel, based on the total output current. This increases the total converter

efficiency by reducing unnecessary switching losses when the output current is low enough to be supported by a

fewer number of phases, than are available in hardware. The MFR_SPECIFIC_14 and MFR_SPECIFIC_15

commands may be used to configure dynamic phase shedding behavior and thresholds.

The DPS_EN bit in MFR_SPECIFIC_14 may be used to enable or disable dynamic phase shedding. Un-setting

(writing to 0b) this bit forces each channel to use the maximum number of available phases, regardless of the

output current. DPS is disabled as the factory default.

The phase add/drop thresholds, at which phases are added or dropped are configured based on the peak

efficiency point per phase. For a given switching frequency/duty cycle, the efficiency of an individual power stage

has a "peak" point, at which switching losses become less significant and conduction losses begin to dominate.

For a multiphase converter, the optimum efficiency is achieved when all of the power stages operate as close as

possible to their peak efficiency point. For example, consider a 4-phase design, with power stages that have a

peak efficiency point of 12 A per phase. When the total output current is 25 A, if all four phases were active,

each phase would be supplying 6.25 A, and hence would be operating far away from their peak efficiency point.

With only two phases active, however, each phase supplies 12.5A, meaning that each power stage is operating

close to its peak efficiency point, therefore the total converter efficiency is higher overall.

In order to maintain regulation during severe load transient events, phases may be added immediately whenever

the total peak current reaches phase addition thresholds. To prevent chattering, phases are dropped when the

total average current falls below phase drop thresholds, after a delay of 85 µs typically. Phases are always

added/dropped, in numerical order. For example, phase 3 is added after phase 2, and dropped after phase 4.

The DPS_COURSE_TH bits in MFR_SPECIFIC_15 select the peak efficiency point per phase. Refer to the

power stage datasheet to determine the peak efficiency point per phase.

Phase adding thresholds are configured based on the peak efficiency point per phase. Each phase transition has

a configurable threshold of 6 A to 12 A above the peak efficiency point. For example, the threshold at which the

converter transitions from 2 phases to 3 phases is determined by the DPS_2TO3_FINE_ADD bits in

MFR_SPECIFIC_15. When 8 A is selected, the total peak current which causes the third phase to be added is 2

× I_EFF(PEAK)+ 8 A. See the register descriptions below for more detailed information.

Likewise, phase drop thresholds are configured based on the peak efficiency point per phase. Each phase

transition has a configurable threshold of 2A below A to 4 A above the peak efficiency point. For example, the

threshold at which the converter transitions from 3 phases to 2 phases is determined by the

DPS_3TO2_FINE_DROP bits in MFR_SPECIFIC_14. When 0 A is selected, the total average current which

causes the third phase to be dropped is 2 × I_EFF(PEAK). See the register descriptions below for more detailed

information.

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表7-55. Dynamic Phase Add and Drop

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b);

21

23

25

A

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b);

23

25

27

23

25

27

29

25

27

29

31

27

29

31

33

25

27

29

25

27

29

31

27

29

31

33

29

31

33

35

27

29

31

27

29

31

33

29

31

33

35

31

33

35

37

A

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b);

Dynamic phase

adding threshold, 1 to

2 Phases (peak

current)

V

_RIPPLE≈18 A (estimation)

V_DPSTHA1

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = 2 A; (MFR_SPECIFIC_15<4:3> = 00b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = 4 A; (MFR_SPECIFIC_15<4:3> = 01b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = 6 A; (MFR_SPECIFIC_15<4:3> = 10b);

V

_RIPPLE≈18 A (estimation)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = 8 A; (MFR_SPECIFIC_15<4:3> = 11b);

V

_RIPPLE≈18 A (estimation)

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表7-55. Dynamic Phase Add and Drop (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> =

00b)

4

6

8

10

12

14

10

12

14

16

12

14

16

18

14

16

18

20

A

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> =

01b)

6

8

10

12

8

A

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> =

10b)

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> =

11b)

10

6

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> =

00b)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> =

01b)

8

10

12

14

10

12

14

16

12

14

16

18

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> =

10b)

10

12

8

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> =

11b)

Dynamic phase

shedding threshold, 2

to 1 phase (average

current)

V_DPSTHS1

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> =

00b)

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> =

01b)

10

12

14

10

12

14

16

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> =

10b)

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> =

11b)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = -6 A; (MFR_SPECIFIC_15<14:13> =

00b)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = -4 A; (MFR_SPECIFIC_15<14:13> =

01b)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = -2 A; (MFR_SPECIFIC_15<14:13> =

10b)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = 0 A; (MFR_SPECIFIC_15<14:13> =

11b)

56

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表7-55. Dynamic Phase Add and Drop (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b);

V_RIPPLE= 14 A (estimation)

32.5

35

37.5

A

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b);

V_RIPPLE= 14 A (estimation)

34.5

36.5

38.5

36.5

38.5

40.5

42.5

40.5

42.5

44.5

46.5

44.5

46.5

48.5

50.5

37

39

41

39

41

43

45

43

45

47

49

47

49

51

53

39.5

41.5

43.5

41.5

43.5

45.5

47.5

45.5

47.5

49.5

51.5

49.5

51.5

53.5

55.5

A

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b);

V_RIPPLE= 14 A (estimation)

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> =

11b); V_RIPPLE= 14 A (estimation)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b);

V_RIPPLE= 14 A (estimation)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b);

V_RIPPLE= 14 A (estimation)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b);

V_RIPPLE= 14 A (estimation)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> =

11b); V_RIPPLE= 14 A (estimation)

Dynamic phase

adding threshold, 2 to

3 phases (peak

current)

V_DPSTHA2

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b);

V_RIPPLE= 14 A (estimation)

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b);

V_RIPPLE= 14 A (estimation)

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b);

V_RIPPLE= 14 A (estimation)

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> =

11b); V_RIPPLE= 14 A (estimation)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = 4 A; (MFR_SPECIFIC_15<6:5> = 00b);

V_RIPPLE= 14 A (estimation)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = 6 A; (MFR_SPECIFIC_15<6:5> = 01b);

V_RIPPLE= 14 A (estimation)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = 8 A; (MFR_SPECIFIC_15<6:5> = 10b);

V_RIPPLE= 14 A (estimation)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = 10 A; (MFR_SPECIFIC_15<6:5> = 11b);

V_RIPPLE= 14 A (estimation)

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表7-55. Dynamic Phase Add and Drop (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b)

17.5

20

22.5

24.5

26.5

28.5

26.5

28.5

30.5

32.5

30.5

32.5

34.5

36.5

34.5

36.5

38.5

40.5

A

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b)

19.5

21.5

23.5

21.5

23.5

25.5

27.5

25.5

27.5

29.5

31.5

29.5

31.5

33.5

35.5

22

24

26

24

26

28

30

28

30

32

34

32

34

36

38

A

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b)

Peak Efficiency = 12 A; (MFR_SPECIFIC_15<1:0> =

00b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b)

Peak Efficiency = 14 A; (MFR_SPECIFIC_15<1:0> =

01b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b)

Dynamic phase

shedding threshold, 3

to 2 phases (average

current)

V_DPSTHS2

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b)

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b)

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b)

Peak Efficiency = 16 A; (MFR_SPECIFIC_15<1:0> =

10b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = -4 A; (MFR_SPECIFIC_14<9:8> = 00b)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = -2 A; (MFR_SPECIFIC_14<9:8> = 01b)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = 0 A; (MFR_SPECIFIC_14<9:8> = 10b)

Peak Efficiency = 18 A; (MFR_SPECIFIC_15<1:0> =

11b); Offset = 2 A; (MFR_SPECIFIC_14<9:8> = 11b)

7.5.20.1 (DEh) MFR_SPECIFIC_14

The MFR_SPECIFIC_14 command is used to configure dynamic phase shedding, and compensation ramp

amplitude, and dynamic ramp amplitude during USR, and different power states. The MFR_SPECIFIC_14

command must be accessed through Write Word/Read Word transactions.

MFR_SPECIFIC_14 is a paged register. In order to access MFR_SPECIFIC_14 command for channel A, PAGE

must be set to 00h. In order to access the MFR_SPECIFIC_14 register for channel B, PAGE must be set to 01h.

MFR_SPECIFIC_14

15

RW

n/a

14

RW

n/a

13

RW

n/a

12

RW

n/a

11

RW

n/a

10

RW

n/a

9

8

RW

DPS_3TO2_FINE_DROP

7

6

5

4

3

2

1

0

RW

DYN_RAMP_2 DYN_RAMP_1

PH PH

DPS_EN

DYN_RAMP_USR

RAMP

LEGEND: R/W = Read/Write; R = Read only

58

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表7-56. MFR_SPECIFIC_14 Register Field Descriptions

Bit

Field

Type

Reset

Description

15:10

n/a

RW

NVM

n/a

Dynamic phase drop threshold, fine adjustment, 3 phases to 2

phases. Set as an offset from peak efficiency point per phase in

Amperes. Phases drop when average phase current reaches

the stated threshold. I_EFF(PEAK)refers to the value selected by

DPS_COURSE_TH in MFR_SPECIFIC_15.

9:8

DPS_3TO2_FINE_DROP

RW

NVM

00b: Threshold = 2 × I_EFF(PEAK)–2 A

01b: Threshold = 2 × I_EFF(PEAK)

10b: Threshold = 2 × I_EFF(PEAK)+ 2 A

11b: Threshold = 2 × I_EFF(PEAK)+ 4 A

Enable or Disable Dynamic Phase Shedding

0b: Disable dynamic phase shedding

1b: Enable dynamic phase shedding

7

6:5

4

DPS_EN

RW

NVM

Dynamic ramp amplitude setting during USR operation. Only

applies to USR Level 1.

00b: Equal to the settings in the RAMP bits

01b: 40 mV

DYN_RAMP_USR

DYN_RAMP_2PH

10b: 80 mV

11b: 120 mV

Dynamic ramp amplitude setting during 2 phase operation.

0b: Equal to the settings in the RAMP bits

1b: 120 mV

Dynamic ramp amplitude setting during 1 phase operation.

0b: Equal to the settings in the RAMP bits

1b: 80 mV

3

DYN_RAMP_1PH

RAMP

RW

NVM

2:0

Ramp amplitude settings. See 表7-57.

表7-57. Ramp Amplitude Settings

RAMP (binary)

Ramp Amplitude Setting (mV)

000b

001b

010b

011b

100b

101b

110b

111b

40

80

120

160

200

240

280

320

7.5.20.2 (DFh) MFR_SPECIFIC_15

The MFR_SPECIFIC_15 command is used to configure dynamic phase shedding. The MFR_SPECIFIC_15

command must be accessed through Write Word/Read Word transactions.

MFR_SPECIFIC_15 is a paged register. In order to access MFR_SPECIFIC_15 command for channel A, PAGE

must be set to 00h. In order to access the MFR_SPECIFIC_15 register for channel B, PAGE must be set to 01h.

MFR_SPECIFIC_15

15

RW

14

13

12

RW

n/a

11

RW

n/a

10

RW

n/a

9

8

RW

n/a

RW

n/a

DPS_DCM

DPS_2TO1_FINE_DROP

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MFR_SPECIFIC_15 (continued)

7

6

5

4

3

2

1

0

RW

n/a

RW

DPS_2TO3_FINE_ADD

DPS_1TO2_FINE_ADD

2TO1_PH_EN

DPS_COURSE_TH

LEGEND: R/W = Read/Write; R = Read only

表7-58. MFR_SPECIFIC_15 Register Field Descriptions

Bit

Field

Type

Reset

Description

Enable DCM mode during 1 phase operation, when higher order

phases are dropped due to dynamic phase shedding.

0b: Disable DCM operation during 1 phase operation

1b: Enable DCM operation during 1 phase operation

15

DPS_DCM

RW

NVM

Dynamic phase drop threshold, fine adjustment, 2 phases to

1phase. Set as an offset from peak efficiency point per phase in

Amperes. Phases drop when average phase current reaches

the stated threshold. I_EFF(PEAK)refers to the value selected by

DPS_COURSE_TH below.

14:13

12:7

6:5

DPS_2TO1_FINE_DROP

RW

NVM

00b: Threshold = 1× I_EFF(PEAK)–2 A

01b: Threshold = 1 × I_EFF(PEAK)

10b: Threshold = 1 × I_EFF(PEAK)+ 2 A

11b: Threshold = 1 × I_EFF(PEAK)+ 4 A

n/a

Dynamic phase add threshold, fine adjustment, 2 phases to 3

phases. Set as an offset from peak efficiency point per phase in

Amperes. Phases add when peak phase current reaches the

stated threshold. I_EFF(PEAK)refers to the value selected by

DPS_COURSE_TH below

DPS_2TO3_FINE_ADD

00b: Threshold = 2 × I_EFF(PEAK)+ 6A

01b: Threshold = 2 × I_EFF(PEAK)+ 8 A

10b: Threshold = 2 × I_EFF(PEAK)+ 10 A

11b: Threshold = 2 × I_EFF(PEAK)+ 12 A

Dynamic phase add threshold, fine adjustment, 1 phase to 2

phases. Set as an offset from peak efficiency point per phase in

Amperes. Phases add when peak phase current reaches the

stated threshold. I_EFF(PEAK)refers to the value selected by

DPS_COURSE_TH below

5:4

DPS_1TO2_FINE_ADD

RW

NVM

00b: Threshold = 1 × I_EFF(PEAK)+ 6A

01b: Threshold = 1 × I_EFF(PEAK)+ 8 A

10b: Threshold = 1 × I_EFF(PEAK)+ 10 A

11b: Threshold = 1 × I_EFF(PEAK)+ 12 A

Enable phase dropping from 2 phases to 1 phase operation.

0b: Disable phase shedding to 1 phase

3

2TO1_PH_EN

RW

NVM

1b: Enable phase shedding to 1 phase

Sets the peak efficiency point per phase. This is used to

determine phase add/drop thresholds.

00b: I_EFF(PEAK)= 12 A

2:0

DPS_COURSE_TH

01b: I_EFF(PEAK)= 14 A

10b: I_EFF(PEAK)= 16 A

11b: I_EFF(PEAK)= 18 A

60

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7.5.21 NVM Programming

The USER_DATA_00 - USER_DATA_12 commands are provided to streamline NVM programming. These 6-

byte block commands are mapped internally to all of the user-configurable parameters the TPSM831D31

supports. The MFR_SERIAL command also provides a checksum, to streamline verification of desired

programming values.

The generalized procedure for programming the TPSM831D31 is summarized below.

Configure User-Programmable Parameters

1. First, configure all of the user-accessible parameters via the standard PMBus, and Manufacturer Specific

commands. TI provides the Fusion Digital Power Designer graphical interface software to streamline this

step. The user can also refer to the Technical Reference Manual for a full set of register maps for these

commands.

2. Once the device is configured as desired, issue the STORE_DEFAULT_ALL command to commit these

values to NVM, and update the checksum value. Wait approximately 100 ms after issuing

STORE_DEFAULT_ALL before communicating with the device again.

3. Write PAGE to 00h

4. Read-back and Record the value of IC_DEVICE_ID and IC_DEVICE_REV commands

5. Read-back and Record the value of the USER_DATA_00 through USER_DATA_12 commands

6. Read-back and Record the value of the MFR_SERIAL command

7. Read-back and Record the value of VOUT_MAX

8. Write PAGE to 01h

9. Read-back and Record the value of VOUT_MAX

Program and Verify NVM (repeat for each device)

1. Power the device by supplying +3.3V to the V3P3 pin. Power conversion should be disabled for NVM

programming.

2. Read-back and verify that IC_DEVICE_ID and IC_DEVICE_REV values match those recorded previously.

This ensures that user-parameters being programmed correspond to the same device/revision as previously

configured.

3. Write PAGE to 00h.

4. Write the USER_DATA_00 through USER_DATA_12 commands, with the values recorded previously.

5. Write VOUT_MAX (Page 0) with the value recorded previously.

6. Write PAGE to 01h

7. Write VOUT_MAX (Page 1) with the value recorded previously.

8. Issue STORE_DEFAULT_ALL. Wait appx 100 ms after issuing STORE_DEFAULT_ALL before

communicating with the device again.

9. Read-back the MFR_SERIAL command, and compare the value to that recorded previously. If the new

MFR_SERIAL matches the value recorded previously, NVM programming was successful.

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7.5.22 NVM Security

The MFR_SPECIFIC_42 command can be optionally used to set a password for NVM programming. To prevent

a hacker from simply sending the password command with all possible passwords, the TPSM831D31 goes into

a special extra-secure state when an incorrect password is received. In this state, all passwords are rejected,

even the valid one. The device must be power cycled to clear this state so that another password attempt may

be made. When NVM security is enabled, the TPSM831D31 will not accept writes to any command other than

PAGE and PHASE, which are necessary for reading certain parameters.

Enabling NVM Security

1. Set the NVM password. Write MFR_SPECIFIC_42 to a value other than FFFFh.

2. Issue STORE_DEFAULT_ALL

3. Wait 100ms for the NVM store to complete

4. Power cycle V3P3. NVM Security will be enabled at the next power-up.

Disabling NVM Security

To disable NVM security, use the following procedure:

1. Write the password to MFR_SPECIFIC_42 to disable NVM security. Once the correct password has been

given, NVM security will be disabled, and the device will once again accept write transactions to

configuration registers.

NVM security will be re-enabled at the next power-on, unless MFR_SPECIFIC_42 is set to FFFFh (NVM

Security Disabled), and an NVM store operation (issue STORE_DEFAULT_ALL and wait 100 ms) is performed.

Determining Whether NVM Security is Active

Reads to the MFR_SPECIFIC_42 command returns one of three values:

• 0000h = NVM Security is Disabled

• 0001h = NVM Security is Enabled

• 0002h = MFR_SPECIFIC_42 is locked due to incorrect password entry

7.5.22.1 (FAh) MFR_SPECIFIC_42

MFR_SPECIFIC_42 is used for NVM Security. The MFR_SPECIFIC_42 command must be accessed through

Read Word/Write Word transactions.

MFR_SPECIFIC_42 is a shared register. Write transactions to this register will apply to both channels, and read

transactions to this register returns the same data regardless of the current PAGE.

MFR_SPECIFIC_42

15

14

13

12

11

10

9

8

RW

NVM_SECURITY_KEY

7

6

5

4

3

2

1

0

RW

NVM_SECURITY_KEY

LEGEND: R/W = Read/Write; R = Read only

表7-59. MFR_SPECIFIC_42 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:0

NVM_SECURITY_KEY

RW

NVM

16 bit code for NVM security key.

62

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7.5.23 Black Box Recording

The TPSM831D31 provides a "black box" feature to aid in system-level debugging. According to the PMBus

specification, status bits are latched whenever the condition causing them occurs, regardless of whether or not

other status bits are already set. This, however, makes it difficult for the system designer to understand which

fault condition occurred first, in the case that one fault condition causes others to trigger. The

MFR_SPECIFIC_08 command provides a "snapshot" of the first faults to occur chronologically, for each channel,

which may be stored to NVM, for future debugging. Only the most catastrophic fault conditions are logged, such

as the over-voltage fault, over-current fault, and power stage failure. The black box command may also be reset,

or cleared by writing 00h to the register, and storing to NVM if the NVM value must also be cleared.

Resetting the Black Box Record

Resetting the record allows the user to determine which faults occur first, after the register is cleared. To clear

the record, write 00h to MFR_SPECIFIC_08, and issue STORE_DEFAULT_ALL.

Triggering Black Box Recording

Black box recording is always active, whether or not the TPSM831D31 is converting power. Note however many

of the critical faults summarized in MFR_SPECIFIC_08 are only possible to trigger during power conversion.

Whenever any of the following catastrophic faults occur, the MFR_SPECIFIC_08 register will be updated

according to the register description below, but only if the black box record has been cleared since the last

catastrophic faults occurred. Faults logged include:

• Overvoltage Fault (Device was Converting Power)

• Overvoltage Fault (Device was not Converting Power)

• Input Overcurrent Fault

• Output Overcurrent Fault

• Power Stage Fault

• Input Over-Power Fault

Retrieving the Black Box Record

Reading the MFR_SPECIFIC_08 returns the current value of the Black Box record. If the register reads 00h, no

catastrophic faults have occurred since the record was last cleared. If any value other than 00h is stored in the

register, then de-code the value according to the register description below. In order to read-back the black box

record following a power-down, the STORE_DEFAULT_ALL command must be issued, to store the contents of

the black box record to NVM.

7.5.23.1 (D8h) MFR_SPECIFIC_08

The MFR_SPECIFIC_08 command is used to identify catastrophic faults which occur first, and store this

information to NVM. See the product datasheet for more information. The MFR_SPECIFIC_08 command must

be accessed through Write Byte/Read Byte transactions. MFR_SPECIFIC_08 is a shared register. Transactions

to this register do not require specific PAGE settings. However, note that channels A and B have independent bit

fields within the command.

MFR_SPECIFIC_08

7

R

0

6

R

0

5

4

3

2

1

0

RW

CF_CHA

CF_CHB

LEGEND: R/W = Read/Write; R = Read only

表7-60. MFR_SPECIFIC_08 Register Field Descriptions

Bit

7:6

5:3

2:0

Field

Type

Reset

Description

Not used

CF_CHA

CF_CHB

R

0

Not used and set to 0.

RW

NVM

Catastrophic fault record for channel A.

Catastrophic fault record for channel B.

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Whenever a catastrophic fault occurs, the first event detected will trigger the MFR_SPECIFIC_08 command to

update according to the tables below. This recording happens independently for channel A and channel B. If the

PMBus host issues a STORE_DEFAULT_ALL, this information will be committed to NVM, and may be retrieved

at a later time. In order to clear the record for either channel, the PMBus host must write the corresponding bits

(CF_CHA for channel A, CF_CHB for channel B) to 000b, and issue STORE_DEFAULT_ALL.

Attempts to write any non-zero value to this command will be treated as invalid data - data will be ignored, the

appropriate flags in STATUS_CML, and STATUS_WORD, will be set, and the PMB_ALERT pin will be asserted

to notify the host of the invalid transaction.

表7-61. Catastrophic Fault Recording Interpretation

CF_CHA / CF_CHB (binary)

Interpretation

000b

001b

010b

011b

100b

101b

110b

111b

No fault occurred

OVF occurred, power conversion was disabled

OVF occurred, power conversion was enabled

IIN Overcurrent fault occurred

IOUT Overcurrent fault occurred

Overtemperature fault occurred

Power stage fault occurred

Input overpower warning occurred

7.5.24 Board Identification and Inventory Tracking

The TPSM831D31 provides several bytes of arbitrarily programmable NVM-backed memory to allow for

inventory management and board identification. By default, these values reflect information about the date/

revision of the TPSM831D31 device being used itself. This provides a convenient and easy to use method of

tracking boards, revisions and manufacturing dates. The following commands are provided for this purpose:

• MFR_ID - 16 bits of NVM for end-users to track the power module supplier name

• MFR_MODEL - 16 bits of NVM for tracking the manufacturer model number

• MFR_REVISION - 16 bits of NVM for tracking power module revision code

• MFR_DATE - 16 bits of NVM for tracking power module manufacturing date code

7.5.25 Status Reporting

The TPSM831D31 provides several registers containing status information. The flags in these registers are

latched whenever their corresponding condition occurs, and are not cleared until either the CLEAR_FAULTS

command is issued, or the host writes a value of 1b to that bit location. Register maps for the all of the supported

status registers are shown in the following sections.

7.5.25.1 (78h) STATUS_BYTE

The STATUS_BYTE command returns one byte of information with a summary of the most critical faults, such as

over-voltage, overcurrent, over-temperature, etc.

The STATUS_BYTE command must be accessed through Read Byte transactions. STATUS_BYTE is a paged

register. In order to access STATUS_WORD command for channel A, PAGE must be set to 00h. In order to

access STATUS_WORD register for channel B, PAGE must be set to 01h. If PAGE is set FFh, the device return

value will reflect the status of Channel A.

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图7-4. STATUS_BYTE

7

0

6

R

5

R

4

3

2

R

1

R

0

R

BUSY

OFF

VOUT_OV

IOUT_OC

VIN_UV

TEMP

CML

OTHER

表7-62. STATUS_BYTE Register Field Descriptions

Bit

7

Field

Type

Reset

Description

BUSY

OFF

R

0

Not supported and always set to 0.

6

R

Current

Status

This bit is asserted if the unit is not providing power to the

output, regardless of the reason, including simply not being

enabled.

0: Raw status indicating the IC is providing power to VOUT.

1: Raw status indicating the IC is not providing power to VOUT.

5

4

3

2

1

VOUT_OV

IOUT_OC

VIN_UV

TEMP

R

Current

Status

Output Over-Voltage Fault Condition

0: Latched flag indicating no VOUT OV fault has occurred.

1: Latched flag indicating a VOUT OV fault occurred

Current

Status

Output Over-Current Fault Condition

0: Latched flag indicating no IOUT OC fault has occurred.

1: Latched flag indicating an IOUT OC fault has occurred.

Current

Status

Input Under-Voltage Fault Condition

0: Latched flag indicating VIN is above the UVLO threshold.

1: Latched flag indicating VIN is below the UVLO threshold.

Current

Status

Over-Temperature Fault/Warning

0: Latched flag indicating no OT fault or warning has occurred.

1: Latched flag indicating an OT fault or warning has occurred.

CML

Current

Status

Communications, Memory or Logic Fault

0: Latched flag indicating no communication, memory, or logic

fault has occurred.

1: Latched flag indicating a communication, memory, or logic

fault has occurred.

0

OTHER

R

Current

Status

Other Fault (None of the Above)

This bit is used to flag faults not covered with the other bit faults.

In this case, UVF or OCW faults are examples of other faults not

covered by the bits [7:1] in this register.

0: No fault has occurred

1: A fault or warning not listed in bits [7:1] has occurred.

Per the description in the PMBus 1.3 specification, part II, TPSM831D31 does support clearing of status bits by

writing to STATUS registers. However, the bits in the STATUS_BYTE are summary bits only and reflect the

status of corresponding bits in STATUS_VOUT and STATUS_IOUT. To clear these bits individually, the user

must clear them by writing to the corresponding STATUS_X register. For example: the output overcurrent fault

sets the IOUT_OC bit in STATUS_BYTE, and the IOUT_OC_FLT bit in STATUS_IOUT. Writing a 1 to the

IOUT_OC_FLT bit in STATUS_IOUT clears the fault in both STATUS_BYTE and STATUS_IOUT. Writes to

STATUS_BYTE itself will be treated as invalid transactions.

7.5.25.2 (79h) STATUS_WORD

The STATUS_WORD command returns two bytes of information with a summary of critical faults, such as over-

voltage, overcurrent, and over-temperature.

The STATUS_WORD command must be accessed through Read Word transactions. STATUS_WORD is a

paged register. In order to access STATUS_WORD command for channel A, PAGE must be set to 00h. In order

to access STATUS_WORD register for channel B, PAGE must be set to 01h. If PAGE is set FFh, the device

return value will reflect the status of Channel A.

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图7-5. STATUS_WORD

15

R

14

R

13

R

12

11

10

R

9

R

8

R

VOUT

IOUT

INPUT

MFR

PGOOD

FANS

OTHER

UNKNOWN

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

R

BUSY

OFF

VOUT_OV

IOUT_OC

VIN_UV

TEMP

CML

OTHER

表7-63. STATUS_WORD Register Field Descriptions

Bit

Field

Type

Reset

Description

15

VOUT

R

Current

Status

Output Voltage Fault/Warning. Refer to STATUS_VOUT for

more information.

0: Latched flag indicating no VOUT fault or warning has

occurred.

1: Latched flag indicating a VOUT fault or warning has occurred.

14

13

IOUT

R

Current

Status

Output Current Fault/Warning. Refer to STATUS_IOUT for more

information.

0: Latched flag indicating no IOUT fault or warning has occurred.

1: Latched flag indicating an IOUT fault or warning has occurred.

INPUT

Current

Status

Input Voltage/Current Fault/Warning. Refer to STATUS_INPUT

for more information.

0: Latched flag indicating no VIN or IIN fault or warning has

occurred.

1: Latched flag indicating a VIN or IIN fault or warning has

occurred.

12

11

MFR

R

Current

Status

MFR_SPECIFIC Fault. Refer to STATUS_MFR for more

information.

0: Latched flag indicating no MFR_SPECIFIC fault has occurred.

1: Latched flag indicating a MFR_SPECIFIC fault has occurred.

PGOOD

Current

Status

Power Good Status. Note: Per the PMBus specification, the

PGOOD bit is not latched, always reflecting the current status of

the AVR_RDY/BVR_RDY pin.

0: Raw status indicating AVR_RDY/BVR_RDY pin is at logic

high.

1: Raw status indicating AVR_RDY/BVR_RDY pin is at logic low.

10

9

FANS

R

0

Not supported and always set to 0.

OTHER

8

UNKNOWN

BUSY

7

6

OFF

Current

Status

This bit is asserted if the unit is not providing power to the

output, regardless of the reason, including simply not being

enabled.

0: Raw status indicating the IC is providing power to VOUT.

1: Raw status indicating the IC is not providing power to VOUT.

5

4

3

2

VOUT_OV

IOUT_OC

VIN_UV

TEMP

R

Current

Status

Output Over-Voltage Fault Condition

0: Latched flag indicating no VOUT OV fault has occurred.

1: Latched flag indicating a VOUT OV fault occurred

Current

Status

Output Over-Current Fault Condition

0: Latched flag indicating no IOUT OC fault has occurred.

1: Latched flag indicating an IOUT OC fault has occurred.

Current

Status

Input Under-Voltage Fault Condition

0: Latched flag indicating VIN is above the UVLO threshold.

1: Latched flag indicating VIN is below the UVLO threshold.

Current

Status

Over-Temperature Fault/Warning

0: Latched flag indicating no OT fault or warning has occurred.

1: Latched flag indicating an OT fault or warning has occurred.

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表7-63. STATUS_WORD Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

CML

R

Current

Status

Communications, Memory or Logic Fault

0: Latched flag indicating no communication, memory, or logic

fault has occurred.

1: Latched flag indicating a communication, memory, or logic

fault has occurred.

0

OTHER

R

Current

Status

Other Fault (None of the Above)

This bit is used to flag faults not covered with the other bit faults.

In this case, UVF or OCW faults are examples of other faults not

covered by the bits [7:1] in this register.

0: No fault has occurred

1: A fault or warning not listed in bits [7:1] has occurred.

Per the description in the PMBus 1.3 specification, part II, TPSM831D31 does support clearing of status bits by

writing to STATUS registers. However, the bits in the STATUS_WORD are summary bits only and reflect the

status of corresponding bits in STATUS_VOUT and STATUS_IOUT. To clear these bits individually, the user

must clear them by writing to the corresponding STATUS_X register. For example: the output overcurrent fault

sets the IOUT_OC bit in STATUS_WORD, and the IOUT_OC_FLT bit in STATUS_IOUT. Writing a 1 to the

IOUT_OC_FLT bit in STATUS_IOUT clears the fault in both STATUS_WORD and STATUS_IOUT. Writes to

STATUS_WORD will be treated as invalid transactions.

7.5.25.3 (7Ah) STATUS_VOUT

The STATUS_VOUT command returns one byte of information relating to the status of the converter's output

voltage related faults.

The STATUS_VOUT command must be accessed through Read Byte/Write Byte transactions. STATUS_VOUT

is a paged register. In order to access STATUS_VOUT command for channel A, PAGE must be set to 00h. In

order to access STATUS_VOUT register for channel B, PAGE must be set to 01h. If PAGE is set FFh, the device

return value will reflect the status of Channel A.

图7-6. STATUS_VOUT

7

6

5

4

3

2

0

1

0

RW

0

RW

0

VOUT_OVF

VOUT_OVW

VOUT_UVW

VOUT_UVF

VOUT_MIN_MA

X

TON_MAX

TOFF_MAX

VOUT_TRACK

表7-64. STATUS_VOUT Register Field Descriptions

Bit

Field

VOUT_OVF

Type

Reset

Description

7

RW

Current

Status

Output Over-Voltage Fault

0: Latched flag indicating no VOUT OV fault has occurred.

1: Latched flag indicating a VOUT OV fault has occurred.

6

5

4

VOUT_OVW

VOUT_UVW

VOUT_UVF

R

0

Not supported and always set to 0.

R

RW

Current

Status

Output Under-Voltage Fault

0: Latched flag indicating no VOUT UV fault has occurred.

1: Latched flag indicating a VOUT UV fault has occurred.

3

VOUT_MIN_MAX

RW

Current

Status

Output Voltage Max/Min Exceeded Warning

0: Latched flag indicating no VOUT_MAX/VOUT_MIN warning

has occurred.

1: Latched flag indicating that an attempt has been made to set

the output voltage to a value higher than allowed by the

VOUT_MAX/VOUT_MIN command.

2

1

0

TON_MAX

R

0

Not supported and always set to 0.

TOFF_MAX

VOUT_TRACK

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Per the description in the PMBus 1.3 specification, part II, TPSM831D31 does support clearing of status bits by

writing to STATUS registers. Writing a 1 to any supported bit in this register will attempt to clear it as a fault

condition.

7.5.25.4 (7Bh) STATUS_IOUT

The STATUS_IOUT command returns one byte of information relating to the status of the converter's output

current related faults.

The STATUS_IOUT command must be accessed through Read Byte/Write Byte transactions. STATUS_IOUT is

a paged register. In order to access STATUS_IOUT command for channel A, PAGE must be set to 00h. In order

to access STATUS_IOUT register for channel B, PAGE must be set to 01h. If PAGE is set FFh, the device return

value will reflect the status of Channel A.

图7-7. STATUS_IOUT

7

6

5

4

3

2

1

0

RW

0

RW

0

RW

0

IOUT_OCF

IOUT_OCUVF

IOUT_OCW

IOUT_UCF

CUR_SHAREF

POW_LIMIT

POUT_OPF

POUT_OPW

表7-65. STATUS_IOUT Register Field Descriptions

Bit

Field

IOUT_OCF

Type

Reset

Description

7

RW

Current

Status

Output Over-Current Fault

0: Latched flag indicating no IOUT OC fault has occurred.

1: Latched flag indicating a IOUT OC fault has occurred .

6

5

IOUT_OCUVF

IOUT_OCW

R

0

Not supported and always set to 0.

RW

Current

Status

0: Latched flag indicating no IOUT OC warning has occurred

1: Latched flag indicating a IOUT OC warning has occurred

4

3

IOUT_UCF

R

0

Not supported and always set to 0.

CUR_SHAREF

RW

Current

Status

0: Latched flag indicating no current sharing fault has occurred

1: Latched flag indicating a current sharing fault has occurred

2

1

0

POW_LIMIT

POUT_OPF

POUT_OPW

R

0

Not supported and always set to 0.

Per the description in the PMBus 1.3 specification, part II, TPSM831D31 does support clearing of status bits by

writing to STATUS registers. Writing a 1 to any supported bit in this register will attempt to clear it as a fault

condition.

7.5.25.5 (7Ch) STATUS_INPUT

The STATUS_INPUT command returns one byte of information relating to the status of the converter's input

voltage and current related faults.

The STATUS_INPUT command must be accessed through Read Byte/Write Byte transactions. The

STATUS_INPUT command is shared between Channel A and Channel B. All transactions to this command will

affect both channels regardless of the PAGE command.

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图7-8. STATUS_INPUT Register

7

6

0

5

0

4

3

2

1

0

RW

VIN_OVF

VIN_OVW

VIN_UVW

VIN_UVF

LOW_VIN

IIN_OCF

IIN_OCW

PIN_OPW

表7-66. STATUS_INPUT Register Field Descriptions

Bit

Field

VIN_OVF

Type

Reset

Description

7

R

Current

Status

Input Over-Voltage Fault

0: Latched flag indicating no VIN OV fault has occurred.

1: Latched flag indicating a VIN OV fault has occurred.

6

5

4

VIN_OVW

VIN_UVW

VIN_UVF

R

0

Not supported and always set to 0.

Current

Status

Input Under-Voltage Fault

0: Latched flag indicating no VIN UV fault has occurred.

1: Latched flag indicating a VIN UV fault has occurred.

3

2

1

0

LOW_VIN

IIN_OCF

IIN_OCW

PIN_OPW

R

Current

Status

Unit Off for insufficient input voltage

0: Latched flag indicating no LOW_VIN fault has occurred.

1: Latched flag indicating a LOW_VIN fault has occurred

Current

Status

Input Over-Current Fault

0: Latched flag indicating no IIN OC fault has occurred.

1: Latched flag indicating a IIN OC fault has occurred.

Current

Status

Input Over-Current Warning

0: Latched flag indicating no IIN OC warning has occurred.

1: Latched flag indicating a IIN OC warning has occurred.

Current

Status

Input Over-Power Warning

0: Latched flag indicating no input over-power warning has

occurred.

1: Latched flag indicating a input over-power warning has

occurred.

Per the description in the PMBus 1.3 specification, part II, TPSM831D31 does support clearing of status bits by

writing to STATUS registers. Writing a 1 to any supported bit in this register will attempt to clear it as a fault

condition.

7.5.25.6 (7Dh) STATUS_TEMPERATURE

The STATUS_TEMPERATURE command returns one byte of information relating to the status of the converter's

temperature related faults.

The STATUS_TEMPERATURE command must be accessed through Read Byte/Write Byte transactions.

STATUS_TEMPERATURE is a paged register. In order to access STATUS_TEMPERATURE command for

channel A, PAGE must be set to 00h. In order to access STATUS_TEMPERATURE register for channel B,

PAGE must be set to 01h. If PAGE is set FFh, the device return value will reflect the status of Channel A.

图7-9. STATUS_TEMPERATURE Register

7

6

5

4

3

2

1

0

RW

OTF

RW

OTW

0

UTW

UTF

Reserved

表7-67. STATUS_TEMPERATURE Register Field Descriptions

Bit

Field

Type

Reset

Description

7

OTF

RW

Current

Status

Over-Temperature Fault

0: (Default) A temperature fault has not occurred.

1: A temperature fault has occurred.

6

OTW

RW

Current

Status

Over-Temperature Warning

0: (Default) A temperature warning has not occurred.

1: A temperature warning has occurred.

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表7-67. STATUS_TEMPERATURE Register Field Descriptions (continued)

Bit

5

Field

Type

Reset

Description

UTW

R

0

Not supported and always set to 0.

Always set to 0.

4

UTF

R

0

3-0

Reserved

R

0000

Per the description in the PMBus 1.3 specification, part II, TPSM831D31 does support clearing of status bits by

writing to STATUS registers. Writing a 1 to any supported bit in this register will attempt to clear it as a fault

condition.

7.5.25.7 (7Eh) STATUS_CML

The STATUS_CML command returns one byte with contents regarding communication, logic, or memory

conditions.

The STATUS_CML command must be accessed through Read Byte/Write Byte transactions. The STATUS_CML

command is shared between Channel A and Channel B. All transactions to this command affects both channels

regardless of the PAGE command.

图7-10. STATUS_CML Register

7

6

5

4

3

2

0

1

0

RW

MEM

0

RW

0

IV_CMD

IV_DATA

PEC_FAIL

PRO_FAULT

Reserved

COM_FAIL

CML_OTHER

表7-68. STATUS_CML Register Field Descriptions

Bit

Field

Type

Reset

Description

7

IV_CMD

RW

Current

Status

Invalid or Unsupported Command Received

0: Latched flag indicating no invalid or unsupported command

has been received.

1: Latched flag indicating an invalid or unsupported command

has been received.

6

5

IV_DATA

RW

Current

Status

Invalid or Unsupported Data Received

0: Latched flag indicating no invalid or unsupported data has

been received.

1: Latched flag indicating an invalid or unsupported data has

been received.

PEC_FAIL

Current

Status

Packet Error Check Failed

0: Latched flag indicating no packet error check has failed

1: Latched flag indicating a packet error check has failed

4

3

Reserved

MEM

R

0

Always set to 0.

RW

Current

Status

Memory/NVM Error

0: Latched flag indicating no memory error has occurred

1: Latched flag indicating a memory error has occurred

2

1

Reserved

R

0

Always set to 0.

COM_FAIL

RW

Current

Status

Other Communication Faults

0: Latched flag indicating no communication fault other than the

ones listed in this table has occurred.

1: Latched flag indicating a communication fault other than the

ones listed in this table has occurred.

0

CML_OTHER

R

0

Not supported and always set to 0.

Per the description in the PMBus 1.3 specification, part II, TPSM831D31 does support clearing of status bits by

writing to STATUS registers. Writing a 1 to any bit in this register attempts to clear it as a fault condition.

7.5.25.8 (80h) STATUS_MFR_SPECIFIC

The STATUS_MFR_SPECIFIC command returns one byte containing manufacturer-defined faults or warnings.

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The STATUS_MFR_SPECIFIC command must be accessed through Read Byte/Write Byte transactions.

STATUS_MFR_SPECIFIC is a paged register. In order to access STATUS_MFR_SPECIFIC command for

channel A, PAGE must be set to 00h. In order to access STATUS_MFR_SPECIFIC register for channel B, PAGE

must be set to 01h. If PAGE is set FFh, the device return value reflects the status of Channel A.

图7-11. STATUS_MFR_SPECIFIC Register

7

6

5

4

3

2

1

0

RW

0

RW

FLT_PS

VSNS_OPEN MAX_PH_WAR

N

TSNS_LOW RST_VID (Page

0)

Reserved

PHFLT

表7-69. STATUS_MFR_SPECIFIC Register Field Descriptions

Bit

Field

Type

Reset

Description

7

MFR_FAULT_PS

RW

Current

Status

Power Stage Fault

0b: Latched flag indicating no fault from TI power stage has

occurred.

1b: Latched flag indicating a fault from TI power stage has

occurred.

6

5

VSNS_OPEN

RW

Current

Status

VSNS pin open

0b: Latched flag indicating VSNS pin was not open at power-up.

1b: Latched flag indicating VSNS pin was open at power-up.

MAX_PH_WARN

Current

Status

Maximum Phase Warning

If the selected operational phase number is larger than the

maximum available phase number specified by the hardware,

then MAX_PH_WARN is set, and the operational phase number

is changed to the maximum available phase number.

0b: Latched flag indicating no maximum phase warning has

occurred.

1b: Latched flag indicating a maximum phase warning has

occurred.

4

3

TSNS_LOW

RW

Current

Status

0b: Latched flag indicating that TSEN < 150 mV before soft-

start.

1b: Latched flag indicating that TSEN ≥150 mV before soft-

start.

RST_VID (Page 0)

Current

Status

RST_VID (Page 0 only)

0b: A VID reset operation has NOT occurred

1b: A VID reset operation has occurred

2:1

0

Reserved

PHFLT

R

00b

Always set to 0.

RW

Current

Status

Phase current share fault. The PHFLT bit is set if any phase has

current imbalance warnings occurring repetitively for 7 detection

cycles (~500 µs continuously). Phases with current imbalance

warnings may be read back via MFR_SPECIFIC_03.

0b: No repetitive current share fault has occurred

1b: Repetitive current share fault has occurred

Per the description in the PMBus 1.3 specification, part II, TPSM831D31 supports clearing of status bits by

writing to STATUS registers. Writing a 1 to any supported bit in this register attempts to clear it as a fault

condition.

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8 Application and Implementation

备注

以下应用部分中的信息不属于 TI 元件规格，TI 不担保其准确性和完整性。TI 的客户负责确定元件是否

适合其用途，以及验证和测试其设计实现以确认系统功能。

8.1 Application Information

The TPSM831D31 device has a very simple design procedure. All programmable parameters can be configured

by PMBus and stored in NVM as the new default values to minimize external component count. This design

describes a typical 3-phase, 0.85-V, 120-A application and 1-phase 1.2-V, 40-A application.

8.2 Typical Application

The TPSM831D31 is a highly integrated, dual-output power module that supports PMBus commands. Use the

following design procedure to select key component values and set the appropriate behavioral options through

the PMBus.

图8-1. Typical Dual Output Schematic (Dual Outputs: VOUTA = 0.85V, 120A and VOUTB = 1.2V, 40A)

8.2.1 Design Requirements

表8-1. Typical Application Specifications

VOUTA

VOUTB

Input voltage range

Output voltage

10.8 V –13.2 V

0.85 V

120 A

60 A

1.2 V

40 A

20 A

Output current

Output current step

8.2.2 Detailed Design Procedure

For this design, the default settings inside the module are optimal for the application. The amount of input and

output capacitors have been selected for operation up to full load for each output and for exceptional transient

performance.

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8.2.2.1 Input Capacitors

For optimal performance, TI recommends 500 μF of ceramic capactiance and approximately 1000 μF of high-

quality, polymer-aluminum bulk capacitance. Because the device requires ceramic capacitors to provide high-

frequency noise filtering and ripple reduction, place them directly at the VIN pins of the device. The polymer-

aluminum bulk capacitors supply current during load transients and provide a stable input voltage rail.

This application uses 528 µF (24 × 22 µF, 25 V, 1210 case size) of ceramic capacitance, as well as 940 µF (2 ×

470 µF, 25 V) of polymer-aluminum capacitance. The ceramic capacitors are placed near each VIN pin and its

coresponding GND pin.

8.2.2.2 Output Capacitors

TI recommends 1200 μF of ceramic output capacitance for VOUTA, as well as 5500 µF of additional polymer-

type capacitance. The recommended amount of output capacitance for VOUTB is 400 µF of ceramic

capactiance, as well as 1800 µF of additional polymer-type capacitance. The ceramic capacitance helps to

reduce ripple while the polymer-type supplies current to reduce voltage deviations during a load transient.

This application uses 1200 µF (12 × 100 µF, 6.3 V, 1210 case size) of ceramic capacitance, as well as 7520 µF

(16 × 470 µF, 6.3 V) of polymer-aluminum capacitance.

8.2.2.3 Switching Frequency

The allowable switching frequency range of the TPSM831D31 is 350 kHz to 700 kHz. To balance performance of

efficiency, line and load regulation, as well as transient response, the default switching frequency for both

outputs has been factory set to f_SW(VOUTA) = 400 kHz and f_SW(VOUTB) = 450 kHz. For this application, the

default switching frequencies are unchanged.

8.2.2.4 Set PMBus Address

To communicate with other system controllers with PMBus interfaces, the PMBus address must be set. The

PMBus address is set by the voltage on the ADDR pin and is selected with a resistor from the ADDR pin to

GND. For this application the PMBus address of 105d is set by placing a 10 kΩ resistor between the ADDR pin

and GND. See 表7-5 for other address selections.

8.2.2.5 PMBus GUI Default Values

For this design, 表 8-2 lists the default values that are preset into the PMBus GUI. For information on changing

the default PMBus settings, refer to this NVM Programming application note.

表8-2. PMBus GUI Default Values

VOUTA

VOUTB

AC_gain

AC_LL

1×

0.5×

0.5 mΩ

Compensation

INT_Time

2 µs

10 µs

INTGAIN

2×

Switching Frequency

Protection

FREQUENCY_SWITCH

IOUT_OC_FAULT_LIMIT

OT_FAULT_LIMIT

VIN_OV_FAULT_LIMIT

400 kHz

180 A

450 kHz

60 A

135°C

17 V

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8.2.3 Application Performance Plots

The plots and waveforms below show typical performance of the TPSM831D31.

100

97

94

91

88

85

82

79

76

73

70

100

97

94

91

88

85

82

79

76

73

70

V_OUT

0.85 V

V_OUT

1.2 V

0

10 20 30 40 50 60 70 80 90 100 110 120

Output Current (A)

0

5

10

15

20

25

30

35

40

Output Current (A)

图8-2. VOUTA Efficiency

图8-3. VOUTB Efficiency

16

14

12

10

8

7

6

5

4

3

2

1

0

V_OUT

0.85 V

V_OUT

1.2 V

6

4

2

0

10 20 30 40 50 60 70 80 90 100 110 120

Output Current (A)

0

5

10

15

20

25

30

35

40

Output Current (A)

图8-4. VOUTA Power Dissipation

图8-5. VOUTB Power Dissipation

0.855

0.854

0.853

0.852

0.851

0.85

1.206

1.205

1.204

1.203

1.202

1.201

1.2

0.849

0.848

0.847

0.846

1.199

1.198

1.197

1.196

V_OUT

1.2 V

0.85 V

0

10 20 30 40 50 60 70 80 90 100 110 120

Output Current (A)

0

5

10

15

20

25

30

35

40

Output Current (A)

图8-6. VOUTA Load Regulation

图8-7. VOUTB Load Regulation

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图8-8. VOUTA EN Turn ON

图8-9. VOUTA EN Turn OFF

图8-10. VOUTB EN Turn ON

图8-11. VOUTB EN Turn OFF

VOUTA

30-A load step

VOUTA

60-A load step

10 A/μsec

100 A/μsec

图8-12. Transient Response

图8-13. Transient Response

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VOUTB

20-A load step

100 A/μsec

图8-14. Transient Response

VIN = 12 V

CHA = 0.85 V

CHB = 0.85 V

fsw = 400 kHz

fsw = 450 kHz

IOUT = 120 A

IOUT = 40 A

图8-15. Radiated EMI

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VIN = 12 V

CHA = 1.2 V

CHB = 1.2 V

fsw = 400 kHz

fsw = 450 kHz

IOUT = 120 A

IOUT = 40 A

图8-16. Radiated EMI

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9 Power Supply Recommendations

The TPSM831D31 device is designed to operate from an input voltage supply between 8 V and 14 V. This

supply must be well regulated. These devices are not designed for split-rail operation. Proper bypassing of input

supplies and internal regulators is also critical for noise performance, as is PCB layout and grounding scheme.

10 Layout

10.1 Layout Guidelines

• Use the recommended land pattern, including the via pattern, for the module footprint.

• Place the input bypass capacitors as close as possible to the VIN and GND pins.

• Use large copper areas for power planes (VIN, VOUTA, VOUTB, and GND) to minimize conduction loss and

thermal stress.

• Use multiple vias to connect the power planes to internal layers.

10.2 Layout Examples

图10-1. Top Layer (Top View)

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图10-2. Bottom Layer (Top View)

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11 Device and Documentation Support

11.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.3 Trademarks

PMBus^™, D-CAP+^™, and TI E2E^™are trademarks of Texas Instruments.

Broadcom^®is a registered trademark of Broadcom Limited .

Cavium^®is a registered trademark of Cavium, Inc..

Marvell^®is a registered trademark of Marvell.

NXP^®is a registered trademark of NXP Semiconductors.

Intel^®is a registered trademark of Intel Corporation.

Xilinx^®is a registered trademark of Xilinx Inc..

所有商标均为其各自所有者的财产。

11.4 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI

提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPSM831D31MOA
厂家：	TEXAS INSTRUMENTS
描述：	具有 AVS 和监控功能的 8V-14V 输入、120A + 40A 双输出 PMBus 模块 \| MOA \| 28 \| -40 to 105 监控
文件：	总88页 (文件大小：3009K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPSM831D31MOA [TI]

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