TPSM84209RKHT [TI]

4.5V 至 28V 输入、1.2V 至 6V 输出、2.5A 电源模块 | RKH | 9 | -40 to 85;


型号：	TPSM84209RKHT
厂家：	TEXAS INSTRUMENTS
描述：	4.5V 至 28V 输入、1.2V 至 6V 输出、2.5A 电源模块 \| RKH \| 9 \| -40 to 85 开关电源电路
文件：	总37页 (文件大小：1406K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPSM84209

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

TPSM84209 4.5V 至 28V 输入、1.2V 至 6V 输出、2.5A 电源模块

1 特性

3 说明

•

完整的集成式电源解决方案可实现

小尺寸的薄型设计

TPSM84209 电源模块是一款易于使用的集成式电源，

该模块由一个带屏蔽式电感的 2.5A 直流/直流转换器和

无源元件组成，并且采用薄型 QFN 封装。这套整体电

源解决方案仅使用了四个外部组件，同时仍能够调整关

键参数以满足特定的设计要求。

•

4.5mm × 4mm × 2mm QFN 封装

宽输出电压范围（1.2V 至 6V）

固定开关频率 (750kHz)

高级 Eco-mode™，用于提高轻负载效率

可编程欠压锁定 (UVLO)

TPSM84209 具有较宽的输入电压范围和较小的尺寸封

装，这使得该器件非常适合用于要求输出电流高达

2.5A 的电源轨。

过热热关断保护

过流保护（间断模式）

QFN 封装易于焊接到印刷电路板上，并且具有出色的

功率耗散能力。TPSM84209 极具灵活性且功能丰

富，非常适合为各类器件和系统供电。

安全预偏置输出启动

工作 IC 结温范围：-40°C 至 +125°C

工作环境温度范围：-40°C 至 +85°C

增强的热性能：29.5°C/W

器件信息⁽¹⁾

符合 EN55011 辐射 EMI 标准

- 集成屏蔽电感器

使用 TPSM84209 并借助 WEBENCH^®电源设计器

创建定制设计方案

器件型号

TPSM84209

封装

封装尺寸

QFN (9)

4.50mm × 4.00mm

•

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

2 应用

空白

•

工业和电机控制

自动测试设备

医疗和成像设备

高密度电源系统

简化应用

效率与输出电流间的关系

100

VOUT

VIN

V_IN

V_OUT

R_FBT

TPSM84209

C_OUT

C_IN

GND

R_FBB

V_OUT= 5.0 V

V_IN= 12 V

V_IN= 24 V

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

Eff1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSE31

TPSM84209

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

www.ti.com.cn

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Typical Characteristics (V_IN= 5 V)............................ 7

6.7 Typical Characteristics (V_IN= 12 V).......................... 8

6.8 Typical Characteristics (V_IN= 24 V).......................... 9

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 10

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 20

Application and Implementation ........................ 21

8.1 Application Information............................................ 21

8.2 Typical Application .................................................. 21

Power Supply Recommendations...................... 23

10 Layout................................................................... 24

10.1 Layout Guidelines ................................................. 24

10.2 Layout Examples................................................... 24

10.3 EMI........................................................................ 25

10.4 Package Specifications......................................... 26

11 器件和文档支持 ..................................................... 27

11.1 器件支持 ............................................................... 27

11.2 使用 WEBENCH® 工具创建定制设计方案............ 27

11.3 接收文档更新通知 ................................................. 27

11.4 社区资源................................................................ 27

11.5 商标....................................................................... 27

11.6 静电放电警告......................................................... 27

11.7 术语表 ................................................................... 27

12 机械、封装和可订购信息....................................... 28

12.1 Tape and Reel Information ................................... 32

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (June 2018) to Revision C

Page

•

已更改将“”中的“封装”列从“B3QFN (43)”更改为“QFN (9)”以更正错误.................................................................................... 1

Changed "RVQ Package" to "RKH Package", "43-pin B3QFN" to "9-Pin QFN" ................................................................... 3

Changes from Revision A (April 2018) to Revision B

Page

•

Changed Min Storage temperature to -55°C.......................................................................................................................... 4

Changes from Original (January 2018) to Revision A

Page

•

首次发布生产数据产品说明书 ................................................................................................................................................. 1

TPSM84209

www.ti.com.cn

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

5 Pin Configuration and Functions

RKH Package

9-Pin QFN

Top View

VOUT

VIN

DNC

Pin Functions

(1)

TYPE

DESCRIPTION

NAME

NO.

Do Not Connect. Do not connect these pins to GND or to any other voltage. These pins are

connected to internal circuitry. Each pin must be soldered to an isolated pad.

DNC

6, 7

—

Enable pin. An open drain/collector device can be used to control the EN function. The module is

disabled when this pin is pulled low. This pin can also be connected to an external resistor divider

connected between VIN and GND to adjust the UVLO above the internal default setting. Float this

pin when not used.

Feedback input. To adjust the output voltage connect this pin to the center point of an external

resistor divider connected between VOUT and GND.

Ground pin. This is the return current path for the device. Connect this pin to the input source

return, the load return, and to the ground side of the VIN and VOUT bypass capacitors using power

ground planes on the PCB.

GND

Switch node. These pins are connected to the input side of the internal output inductor. Do not

place any external components on these pins or tie them to a pin of another function.

4, 5

Input voltage. Connect this pin to the input source and connect external bypass capacitors between

this pin and GND, close to the module.

VIN

Output voltage. This pin is connected to the internal output inductor. Connect this pin to the output

load and connect external bypass capacitors between this pin and GND close to the module.

VOUT

(1) G = Ground, I = Input, O = Output

TPSM84209

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–5

MAX

UNIT

VIN

Input voltage

EN, FB

Output voltage

SW (20 ns transient)

VOUT

–0.3

Mechanical shock

Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted

1500

Mechanical vibration

Mil-STD-883D, Method 2007.2, 20 to 2000 Hz

(2)

Operating IC junction temperature, T_J

–40

–55

125

°C

(2)

Operating ambient temperature, T_A

Storage temperature, T_stg

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under the

recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect

device reliability.

(2) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the

internal power IC when the deviceis powered. Operating below the maximum ambient temperature, as shown in the safe operating area

(SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the

module is never exceeded.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2500

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating ambient temperature range (unless otherwise noted)

MIN

MAX

28⁽²⁾

UNIT

Input voltage, V_IN

4.5⁽¹⁾

1.2

Output voltage, V_OUT

EN voltage, V_EN

Output current, I_OUT

2.5⁽³⁾

Operating ambient temperature, T_A

Operating IC junction temperature, T_J

–40

°C

125

(1) The minimum recommended input voltage is 4.5 V or (V_OUT× 1.3), whichever is greater.

(2) The maximum input voltage varies depending on the output voltage (see Operating Range ).

(3) The maximum output current that the TPSM84209 can deliver is a function of input voltage, output voltage, and ambient temperature

(see Output Current Rating ).

TPSM84209

www.ti.com.cn

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

6.4 Thermal Information

TPSM84209

THERMAL METRIC⁽¹⁾

RKH (QFN)

9 PINS

32.7

UNIT

R_θJA

ψ_JT

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-top characterization parameter⁽³⁾

Junction-to-board characterization parameter⁽⁴⁾

°C/W

2.2

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) The junction-to-ambient thermal resistance, R_θJA, applies to devices soldered directly to a 63 mm × 50 mm, 4-layer PCB with 2 oz.

copper and natural convection cooling. Additional airflow reduces R_θJA

(3) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (section 6 and 7). T_J= ψ_JT× Pdis + T_T; where Pdis is the power dissipated in the device and T_Tis

the temperature of the top of the device.

(4) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature, T_J, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). T_J= ψ_JB× Pdis + T_B; where Pdis is the power dissipated in the device and T_Bis

the temperature of the board 1mm from the device.

6.5 Electrical Characteristics

Over –40°C to +85°C ambient temperature, V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 2.5 A, (unless otherwise

noted); C_IN1= 10 µF, 50 V, 1210 ceramic; C_IN2= 100-µF, 35-V, electrolytic; C_OUT= 2 × 47-µF, 16-V, 1210 ceramic.

Minimum and maximum limits are guaranteed through production test or by design. Typical values represent

the expected value for the given test conditions and may or may not be production tested.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT VOLTAGE (V_IN

)

V_IN

Input voltage

Over I_OUTrange

4.5⁽¹⁾

3.8

28⁽²⁾

4.4

V_INincreasing

V_INdecreasing

V_EN= 0 V

4.1

3.6

UVLO

I_SHDN

V_INundervoltage lockout

Shutdown supply current

3.3

3.9

µA

OUTPUT VOLTAGE (V_OUT

)

V_OUT(ADJ)Output voltage adjust

Over I_OUTrange

1.2

V_OUT(Ripple)Output voltage ripple

FEEDBACK

20-MHz bandwidth

Feedback voltage⁽³⁾

T_A= 25°C, I_OUT= 0.2 A

0.581

0.596

0.5%

0.2

0.611

Temperature variation

–40°C ≤ T_J≤ 125°C, I_OUT= 0.2 A

T_A= 25°C, 4.5 V ≤ V_IN≤ 28 V, I_OUT= 0.2 A

Over I_OUTrange, T_A= 25°C

V_FB

Line regulation

Load regulation

0.5

CURRENT

Output current

I_OUT

Natural convection, T_A= 25°C

2.5⁽⁴⁾

Overcurrent threshold

4.8

PERFORMANCE

V_OUT= 5 V

86.5%

82.7%

79.3%

91.7%

89.0%

86.8%

V_IN= 24 V,

V_OUT= 3.3 V

I_OUT= 1 A

V_OUT= 2.5 V

Efficiency

V_OUT= 5 V

V_IN= 12 V,

V_OUT= 3.3 V

I_OUT= 1 A

V_OUT= 2.5 V

Over/undershoot

Recovery Time

µs

25% to 75% load step

1 A/µs slew rate

Transient response

125

(1) The minimum recommended input voltage is 4.5 V or (V_OUT× 1.3), whichever is greater.

(2) The maximum input voltage varies depending on the output voltage (see Operating Range ).

(3) The overall output voltage tolerance will be affected by the tolerance of the external R_FBTand R_FBBresistors.

(4) The maximum output current that the TPSM84209 can deliver is a function of input voltage, output voltage, and ambient temperature

(see Output Current Rating ).

TPSM84209

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

www.ti.com.cn

Electrical Characteristics (continued)

Over –40°C to +85°C ambient temperature, V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 2.5 A, (unless otherwise

noted); C_IN1= 10 µF, 50 V, 1210 ceramic; C_IN2= 100-µF, 35-V, electrolytic; C_OUT= 2 × 47-µF, 16-V, 1210 ceramic.

Minimum and maximum limits are guaranteed through production test or by design. Typical values represent

the expected value for the given test conditions and may or may not be production tested.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SOFT START

T_SS

Internal soft-start time

SWITCHING FREQUENCY

F_SW

Switching frequency

578

1.1

750

923

kHz

ENABLE (EN)

V_EN-RISING

V_EN-FALLIN

Rising

1.21

1.19

0.7

1.28

EN threshold

Falling

EN Input current

V_EN= 1 V

V_EN= 1.5 V

µA

I_EN

EN Hysteresis current

1.55

THERMAL

T_SHDN

Shutdown temperature

Hysteresis

165

°C

Thermal shutdown

CAPACITANCE

Ceramic type

10⁽⁵⁾

µF

C_IN

External input capacitance

Non-ceramic type

Ceramic type

47⁽⁵⁾

min⁽⁶⁾

500⁽⁷⁾

External output

capacitance

C_OUT

Non-ceramic type

(5) A minimum of 10 µF ceramic input capacitance is required for proper operation. An additional 47 µF of bulk capacitance is

recommended for applications with transient load requirements.

(6) The minimum amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection ). A

minimum amount of ceramic capacitance is required. Locate the capacitance close to the device. Adding additional ceramic or non-

ceramic capacitance close to the load improves the response of the regulator to load transients.

(7) The maximum output capacitance of 500 µF can be made up of all ceramic type or a combination of both ceramic and non-ceramic

type.

TPSM84209

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ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

6.6 Typical Characteristics (V_IN= 5 V)

T_A= 25°C, unless otherwise noted.

1.8

1.5

1.2

0.9

0.6

0.3

0.0

100

V_OUT

3.3 V

2.5 V

1.8 V

1.2 V

V_OUT

3.3 V

2.5 V

1.8 V

1.2 V

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

D001

D002

图 1. Efficiency vs Output Current

图 2. Power Dissipation vs Output Current

V_OUT

1.2 V

1.8 V

2.5 V

3.3 V

Airflow

100LFM

Nat Conv

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

D004

D003

V_OUT= 2.5 V

Minimum Required C_OUT

图 4. Safe Operating Area

图 3. Voltage Ripple vs Output Current

Airflow

100LFM

Nat Conv

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

D005

V_OUT= 3.3 V

图 5. Safe Operating Area

TPSM84209

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

www.ti.com.cn

6.7 Typical Characteristics (V_IN= 12 V)

T_A= 25°C, unless otherwise noted.

100

1.8

1.5

1.2

0.9

0.6

0.3

0.0

V_OUT

5.0 V

3.3 V

2.5 V

1.8 V

V_OUT

5.0 V

3.3 V

2.5 V

1.8 V

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

D006

D007

图 6. Efficiency vs Output Current

图 7. Power Dissipation vs Output Current

120

100

V_OUT

1.8 V

2.5 V

3.3 V

5.0 V

Airflow

100LFM

Nat Conv

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

D009

D008

V_OUT= 2.5 V

Minimum Required C_OUT

图 8. Voltage Ripple vs Output Current

图 9. Safe Operating Area

Airflow

100LFM

Nat Conv

200LFM

100LFM

Nat Conv

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

D010

D011

V_OUT= 3.3 V

V_OUT= 5 V

图 10. Safe Operating Area

图 11. Safe Operating Area

TPSM84209

www.ti.com.cn

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

6.8 Typical Characteristics (V_IN= 24 V)

T_A= 25°C, unless otherwise noted.

100

1.8

1.5

1.2

0.9

0.6

0.3

0.0

V_OUT

5.0 V

3.3 V

V_OUT

5.0 V

3.3 V

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

D012

D013

图 12. Efficiency vs Output Current

图 13. Power Dissipation vs Output Current

180

V_OUT

3.3 V

5.0 V

160

140

120

100

Airflow

200LFM

100LFM

Nat Conv

0.0

0.5

1.0

1.5

2.0

2.5

0.5

1.0

1.5

2.0

2.5

Output Current (A)

D015

D014

V_OUT= 3.3 V

C_OUT= 2× 47 µF ceramic

图 15. Safe Operating Area

图 14. Voltage Ripple vs Output Current

Airflow

400LFM

200LFM

100LFM

Nat conv

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

D016

V_OUT= 5 V

图 16. Safe Operating Area

TPSM84209

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPSM84209 is a highly integrated 28-V input, 2.5-A, synchronous step-down power module with PWM,

MOSFETs, inductor, and control circuitry integrated into a low-profile, overmolded, QFN package. This device

enables small designs by integrating all but the input and output capacitors and voltage-setting resistor divider

while keeping the ability to adjust key parameters to meet specific design requirements. The TPSM84209

operates at a 750-kHz fixed switching frequency and features advanced Eco-mode™ pulse-skip operation for

improved light-load efficiency. The TPSM84209 provides an adjustable output-voltage range of 1.2 V to 6 V using

a simple external-resistor divider. The TPSM84209 provides accurate voltage regulation for a variety of loads by

using an internal voltage reference that is 2.5% accurate over temperature. The output-voltage rise time is

controlled by a fixed 5-ms soft start. Input UVLO is internally set at 4.1 V, but can be adjusted upward using a

resistor divider on the EN pin of the module. The EN pin can also be pulled low to put the module in standby

mode to reduce input quiescent current. Thermal shutdown and current limit features protect the device during an

overload condition. A 9-pin, 4-mm × 4.5-mm B3QFN package that includes exposed bottom pads provides a

thermally enhanced solution for space-constrained applications.

7.2 Functional Block Diagram

Shutdown

Logic

VIN

UVLO

VIN

Thermal

Shutdown

OCP

2.2 µH

Power

Stage

and

Control

Logic

VOUT

Comp

VREF

Soft

Start

GND

Oscillator

TPSM84209

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ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

7.3 Feature Description

7.3.1 Adjusting the Output Voltage

A resistor divider connected to the FB pin (pin 1) programs the output voltage of the TPSM84209. The output

voltage adjustment range is from 1.2 V to 6 V. 图 17 shows the feedback resistor connection for setting the

output voltage. The recommended value of R_FBTis 10 kΩ. 表 1 lists the closest standard E96 value for the R_FBB

resistor for a number of common output voltages. For other output voltages, the value of the required R_FFB

resistor can be calculated using 公式 1.

(kꢀ)

R_FBB

(V_OUTœ 0.6)

(1)

VOUT

R_FBT

10 kꢀ

R_FBB

GND

图 17. Setting the Output Voltage

表 1. Standard R_FBBResistor Values

V_OUT(V)

R_FBB(kΩ)

10.0

8.45

7.50

6.65

6.04

5.36

4.99

4.64

4.22

4.02

3.74

3.48

3.32

3.16

3.01

2.87

2.74

2.61

2.49

2.37

2.32

2.21

2.15

2.05

2.00

V_OUT(V)

3.7

3.8

3.9

4.0

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.0

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

6.0

R_FBB(kΩ)

1.96

1.87

1.82

1.74

1.69

1.65

1.62

1.58

1.54

1.50

1.47

1.43

1.40

1.37

1.33

1.30

1.27

1.24

1.22

1.20

1.18

1.15

1.13

1.10

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

TPSM84209

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7.3.2 Input Capacitor Selection

The TPSM84209 requires a ceramic input capacitor with a minimum effective capacitance of 10 μF. Use only

high-quality ceramic type X5R or X7R capacitors with sufficient voltage rating. An additional 47 µF of non-

ceramic capacitance is recommended for applications with transient load requirements. The voltage rating of

input capacitors must be greater than the maximum input voltage. To compensate for the derating of ceramic

capacitors, TI recommends a voltage rating of twice the maximum input voltage. At worst case, when operating

at 50% duty cycle and maximum load, the combined ripple current rating of the input capacitors must be at least

1.25 Arms. 表 2 includes a preferred list of capacitors by vendor.

表 2. Recommended Input Capacitors⁽¹⁾

CAPACITOR CHARACTERISTICS

(2)

(3)

VENDOR

SERIES

PART NUMBER

CAPACITANCE

(µF)

ESR

WORKING VOLTAGE (V)

(mΩ)

TDK

X5R

X7R

C3225X5R1H106K

Murata

GRM32ER71H106K

GRM32ER71J106K

EEHZA1H101P

Murata

Panasonic

100

EEHZA1J560P

(1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details

Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process

requirements for any capacitors identified in this table.

(2) Specified capacitance values

(3) Maximum ESR at 100 kHz, 25°C.

7.3.3 Undervoltage Lockout (UVLO)

The TPSM84209 device has an internal UVLO circuit which prevents the device from operating until the V_IN

voltage exceeds the UVLO rising threshold, (4.1 V (typical)). The device is disabled when the VIN pin voltage

falls below the internal V_INUVLO threshold. The internal V_INUVLO threshold has a hysteresis of 500 mV.

Applications may require a higher UVLO threshold to prevent early turnon, for sequencing requirements or to

prevent input current draw at lower input voltages. An external resistor divider can be added to the EN pin to

adjust the UVLO threshold higher. The external resistor divider can be configured as shown in 图 18. 表 3 lists

standard values for R_UVLO1and R_UVLO2to adjust the UVLO voltage higher.

VIN

R_UVLO1

R_UVLO2

GND

图 18. Adjustable UVLO

表 3. Standard Resistor Values for Adjusting UVLO

V_INUVLO (V)

R_UVLO1(kΩ)

R_UVLO2(kΩ)

4.5

68.1

25.5

68.1

9.53

68.1

6.04

68.1

4.99

68.1

4.42

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7.3.4 Output Capacitor Selection

The minimum amount of required output capacitance for the TPSM84209 varies depending on the output voltage

and whether or not a feed-forward capacitor, C_FF, is used (see Feed-Forward Capacitor for more information on

C_FF). 表 4 lists the minimum output capacitance for several output voltage ranges when not using C_FF. The

required output capacitance must be comprised of all ceramic capacitors or a combination of ceramic and

polymer-type capacitors. The effects of temperature and capacitor voltage rating must be considered when

selecting capacitors to meet the minimum required capacitance.

When adding additional output capacitance, ceramic capacitors or a combination of ceramic and polymer-type

capacitors can be used. The required capacitance above the minimum is determined by actual transient

deviation requirements. See 表 5 for a preferred list of output capacitors by vendor.

表 4. Minimum Required Output Capacitance

V_OUTRANGE (V)

Minimum Required C_OUT

MIN

1.2

1.5

2.5

MAX

< 1.5

< 2.5

< 5

188 µF (4 x 47 µF ceramic)⁽¹⁾

141 µF (3 x 47 µF ceramic)⁽¹⁾

94 µF (2 x 47 µF ceramic)

47 µF (1 x 47 µF ceramic)

(1) The minimum required output capacitance can also be made up of 1 x 47 µF ceramic + 1 x 100 µF polymer-type capacitor.

表 5. Recommended Output Capacitors⁽¹⁾

CAPACITOR CHARACTERISTICS

CAPACITANCE⁽²⁾

(µF)

ESR⁽³⁾

(mΩ)

VENDOR

SERIES

PART NUMBER

WORKING

VOLTAGE (V)

TDK

X5R

C3225X5R1C106K

Murata

TDK

GRM32ER61C106K

C3225X5R1C226M

GRM32ER61C226K

C3225X5R1A476M

GRM32ER61C476K

C3225X5R0J107M

GRM32ER60J107M

GRM32ER61A107M

C1210C107M4PAC7800

6TPE100MI

X5R

Murata

TDK

X5R

Murata

TDK

X5R

6.3

100

220

Murata

Kemet

X5R

Panasonic

POSCAP

6.3

6TPF220M9L

6TPE220ML

(1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details

Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status,

and manufacturing process requirements for any capacitors identified in this table.

(2) Specified capacitance values.

(3) Maximum ESR at 100 kHz, 25°C.

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7.3.5 Feed-Forward Capacitor

The TPSM84209 is internally compensated to be stable over the operating range of the device. However,

depending on the output voltage and amount of output capacitance, an additional feed-forward capacitor, C_FF,

may be added for optimum performance. Adding additional output capacitance above the minimum reduces the

output voltage ripple of the device. However, adding additional output capacitance also reduces the cross-over

frequency of the device, slowing the response to load transients. Adding a feed-forward capacitor when adding

more output capacitance helps to restore cross-over frequency of the device, restoring the transient response.

The external feed-forward capacitor must be placed in parallel with the top resistor divider, R_FBT. The placement

of C_FFis shown in 图 19. 表 6 lists the required C_FFvalues for different amounts of output capacitance. For

output voltages < 2.5 V, it is not recommended to add a C_FFcapacitor.

VOUT

R_FBT

C_FF

10 kꢀ

R_FBB

GND

图 19. Feed-Forward Capacitor

表 6. C_FFValues⁽¹⁾

V_OUTRANGE (V)

Amount of C_OUT

MIN

2.5

3.3

MAX

< 3.3

< 5

47 µF (1 x 47 µF)

Not applicable

C_FF= 100 pF

94 µF (2 x 47 µF)

141 µF (3 x 47 µF)

C_FF= 220 pF

≥ 188 µF (4 x 47 µF)

C_FF= 330 pF

C_FF= 100 pF

C_FF= 330 pF

(1) The C_FFvalues listed in this table apply when R_FBT= 10 kΩ. To calculate the value of C_FFwhen using another R_FBTvalue, multiply the

C_FFvalue listed in the table by 10 kΩ / R_FBT

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7.3.6 Operating Range

The TPSM84209 operates over a wide input voltage and output voltage range; however, not all output voltages

can operate over the entire input voltage range. The maximum and minimum input voltage limits are shown in 图

20. The TPSM84209 can be operated between the Maximum and Minimum V_INlimit lines.

Operating above the Maximum V_INline may cause the device to skip pulses in order to maintain the regulated

output voltage.

Maximum V_IN

Minimum V_IN

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Output Voltage (V)

D017

图 20. Input Voltage vs Output Voltage

7.3.7 Output Current Rating

The maximum output current that the TPSM84209 can deliver is a function of input voltage, output voltage, and

ambient temperature. The TPSM84209 is capable of delivering up to 2.5 A of output current; however refer to 图

21 and 图 22 for maximum current ratings based on operating conditions of the specific application.

V_OUT

6 V

5 V

3.3 V

2.5 V

1.8 V

1.2 V

V_OUT

6 V

5 V

3.3 V

2.5 V

1.8 V

1.2 V

0.0

0.5

1.0

1.5

2.0

2.5

0.0

0.5

1.0

1.5

2.0

2.5

Output Current (A)

D018

D019

图 21. Output Current Derating T_A= 25°C

图 22. Output Current Derating T_A= 85°C

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7.3.8 Enable (EN)

The EN pin provides electrical ON and OFF control of the device. When the EN pin voltage exceeds the

threshold voltage, the device begins operation. If the EN pin voltage is pulled below the threshold voltage, the

regulator stops switching and enters the low-quiescent current state.

The EN pin has an internal pullup-current source, which allows the user to float the EN pin to enable the device.

If an application requires control of the EN pin, use open-drain or open-collector output logic to interface with the

pin.

图 23 shows the typical application of the enable function. Turning Q1 on applies a low voltage to the enable

control pin and disables the output of the supply, shown in 图 24. If Q1 is turned off, the supply executes a soft-

start power-up sequence, as shown in 图 25.

Control

GND

图 23. Typical Enable Control

图 25. Enable Turnon

图 24. Enable Turnoff

7.3.9 Internal Soft Start

The TPSM84209 device uses the internal soft-start function. The internal soft-start time is set to 5 ms typically.

7.3.10 Safe Start-Up Into Prebiased Outputs

The device has been designed to prevent the low-side MOSFET from discharging a prebiased output. During

monotonic prebiased start-up, both high-side and low-side MOSFETs are not allowed to be turned on until the

internal soft-start voltage is higher than FB pin voltage.

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7.3.11 Light Load Efficiency / Eco-Mode

The TPSM84209 device is designed to operate in high-efficiency, pulse-skipping mode under light load

conditions. As the load current on the output is decreased, a point is reached where the energy delivered by a

single switching pulse is more than the load can absorb. This causes the output voltage to rise slightly. This rise

in output voltage is sensed by the feedback loop, and the device responds by skipping one or more switching

cycles until the output voltages falls back to the setpoint. At very light loads or no load, many switching cycles

are skipped. The observed effect during this pulse-skipping mode of operation is an increase in the peak-to-peak

ripple voltage and a decrease in the ripple frequency. The load current where pulse skipping begins is a function

of the input voltage and output voltage. 图 26 is a plot of the pulse-skipping threshold current as a function of

input voltage for a number of popular output voltages.

1.6

V_OUT

1.2 V

1.8 V

2.5 V

3.3 V

5 V

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Input Voltage (V)

SKIP

图 26. Pulse-Skipping Threshold

7.3.12 Voltage Dropout

Voltage dropout is the difference between the input voltage and output voltage that is required to maintain output

voltage regulation while providing the rated output current.

To ensure the TPSM84209 maintains output voltage regulation over the recommended operating range, the

minimum recommended input voltage is 4.5 V or (V_OUT× 1.3), whichever is greater. However, the TPSM84209

does produce an output voltage when operated below the recommended input voltage range. 图 27 shows the

typical dropout voltage curves for 5-V output at T_A= 25°C. (Note: As ambient temperature increases, dropout

voltage and frequency foldback occur at higher input voltage.)

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5.2

4.8

4.6

4.4

4.2

Iout

0.5 A

1.0 A

1.5 A

2.0 A

2.5 A

3.8

3.6

4.2

4.4

4.6

4.8

5.2

5.4

5.6

5.8

Input Voltage (V)

Drop

图 27. Voltage Dropout

7.3.13 Overcurrent Protection

For protection against load faults, the TPSM84209 incorporates output overcurrent protection. Applying a load

that exceeds the overcurrent threshold of the regulator causes the output to shut down. Following shutdown, the

module periodically attempts to recover by initiating a soft-start power-up as shown in 图 28. This is described as

a hiccup mode of operation, where the module continues in a cycle of successive shutdown and power up until

the load fault is removed. During this period, the average current flowing into the fault is significantly reduced

which reduces power dissipation. Once the fault is removed, the module automatically recovers and returns to

normal operation as shown in 图 29.

图 29. Removal of Overcurrent

图 28. Overcurrent Limiting

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7.3.14 Output Overvoltage Protection (OVP)

The TPSM84209 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage

overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an

overvoltage comparator to compare the FB pin voltage and internal thresholds. When the FB pin voltage goes

above 108% × Vref, the high-side MOSFET is forced off. When the FB pin voltage falls below 104% × Vref, the

high-side MOSFET is enabled again.

7.3.15 Thermal Performance

The typical thermal performance of the TPSM84209 is shown in 图 30. The thermal image shows the typical

temperature rise of TPSM84209 is 27.2°C above ambient when operated at V_IN= 12 V, V_OUT= 3.3 V, I_OUT= 2 A,

with no airflow (LFM = 0).

T_A= 25°C

图 30. Thermal Image

7.3.16 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds

165°C (typ). The device reinitiates the power-up sequence when the junction temperature drops below

155°C (typ).

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7.4 Device Functional Modes

7.4.1 Active Mode

When V_INis above the UVLO threshold and the EN pin voltage is above the EN high threshold, the TPSM84209

operates in the active mode. Normal continuous conduction mode (CCM) occurs when inductor peak current is

above 0 A. In CCM, the TPSM84209 operates at a fixed frequency.

7.4.2 Eco-Mode Operation

The TPSM84209 device is designed to operate in high-efficiency, pulse-skipping mode under light load

conditions. Pulse skipping initiates when the high-side FET current is less than 500 mA typically. During pulse

skipping, the low-side FET turns off when the switch current falls to 0 A. The switching node (SW pin) waveform

takes on the characteristics of discontinuous conduction mode (DCM) operation and the apparent switching

frequency decreases. As the output current decreases, the perceived time between switching pulses increases.

7.4.3 Shutdown Mode

The EN pin provides electrical ON and OFF control for the TPSM84209. When the EN pin voltage is below the

EN threshold, the device is in shutdown mode. In shutdown mode the standby current is 2 μA, typically. The

TPSM84209 also employs UVLO protection. If V_INis below the UVLO level, the output of the regulator turns off.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPSM84209 is a synchronous, step-down DC/DC power module. It is used to convert a higher DC voltage to

a lower DC voltage with a maximum output current of 2.5 A. The following design procedure can be used to

select components for the TPSM84209. Alternately, the WEBENCH^®software may be used to generate

complete designs. When generating a design, the WEBENCH software utilizes an iterative design procedure and

accesses comprehensive databases of components. See www.ti.com/webench for more details.

8.2 Typical Application

The TPSM84209 requires only a few external components to convert from a wide input-voltage-supply range to a

wide range of output voltages. 图 31 shows a basic TPSM84209 schematic with only the minimum required

components.

V_IN= 24V

V_OUT= 5 V

VOUT

VIN

TPSM84209

10 kO

10 µF

50 V

47 µF

10 V

47 µF

10 V

1.37 kO

GND

图 31. TPSM84209 Typical Application

8.2.1 Design Requirements

For this design example, use the parameters listed in 表 7 and the following design procedures.

表 7. Design Example Parameters

DESIGN PARAMETER

Input voltage V_IN

VALUE

24 V typical

5 V

Output voltage V_OUT

Output current rating

2 A

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8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the TPSM84209 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (V_IN), output voltage (V_OUT), and output current (I_OUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

•

Run electrical simulations to see important waveforms and circuit performance

Run thermal simulations to understand board thermal performance

Export customized schematic and layout into popular CAD formats

Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage Setpoint

The output voltage of the TPSM84209 device is externally adjustable using a resistor divider (R_FBTand R_FBB

)

between VOUT, FB, and GND. With a fixed value of 10 kΩ for R_FBT, select the value of R_FBBfrom 表 1 or

calculate using 公式 2:

(kꢀ)

R_FBB

(V_OUTœ 0.6)

(2)

For a output voltage of 5 V, the formula yields a value of 1.36 kΩ. Choose the closest available value of 1.37 kΩ

for R_FBB

8.2.2.3 Input Capacitors

For this design, a 10-μF, X7R dielectric ceramic capacitor rated for 50 V is used for the input decoupling

capacitor.

8.2.2.4 Output Capacitors

The minimum required output capacitance for a 5-V output is two 47-μF ceramic capacitors. For this design, two

47-μF, X5R dielectric ceramic capacitors rated for 16 V is used for the output capacitance.

8.2.2.5 Enable Control

The EN pin provides electrical ON/OFF control of the device. If an application requires control of the EN pin, use

open-drain or open-collector output logic to interface with the pin. For this design, a small-signal, low-leakage

MOSFET (BSS138) was used.

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8.2.3 Application Waveforms

V_IN= 24 V

V_OUT= 5 V

I_OUT= 2 A

图 32. Start-Up Waveforms

图 33. Output Ripple and PH Node Waveforms

9 Power Supply Recommendations

The TPSM84209 is designed to operate from an input-voltage-supply range between 4.5 V and 28 V. This input

supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The

resistance of the input supply rail must be low enough that an input current transient does not cause a high

enough drop at the TPSM84209 supply voltage that can cause a false UVLO fault triggering and system reset.

If the input supply is located more than a few inches from the TPSM84209 additional bulk capacitance may be

required in addition to the ceramic bypass capacitors. Typically, a 47-µF or 100-μF electrolytic capacitor is

sufficient.

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10 Layout

The performance of any switching power supply depends as much upon the layout of the PCB as the component

selection. See the following guidelines to design a PCB with the best power conversion performance, thermal

performance, and minimized generation of unwanted EMI.

10.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图 34 and 图 35,

shows a typical PCB layout. Some considerations for an optimized layout are:

•

Use large copper areas for power planes (VIN, VOUT, and GND) to minimize conduction loss and thermal

stress.

•

Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.

Locate additional output capacitors between the ceramic capacitor and the load.

Place the output voltage feedback resistors, R_FBTand R_FBB, as close as possible to their respective pins.

Use multiple vias to connect the power planes to internal layers.

10.2 Layout Examples

图 34. Typical Top-Layer Layout

图 35. Typical GND Layer

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10.3 EMI

The TPSM84209 is compliant with EN55011 radiated emissions. 图 36, 图 37, and 图 38 show typical examples

of radiated emissions plots for the TPSM84209. The graphs include the plots of the antenna in the horizontal and

vertical positions.

10.3.1 EMI Plots

EMI plots were measured using the standard TPSM84209EVM with no input filter.

图 36. Radiated Emissions 12-V Input, 5-V Output, 2.5-A Load (EN55011 Class B)

图 37. Radiated Emissions 24-V Input, 5-V Output, 1-A Load (EN55011 Class B)

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EMI (接下页)

图 38. Radiated Emissions 24-V Input, 5-V Output, 2-A Load (EN55011 Class A)

10.4 Package Specifications

表 8. Package Specifications Table

TPSM84209

VALUE

UNIT

Weight

107

Flammability

Meets UL 94 V-O

MTBF Calculated Reliability

Per Bellcore TR-332, 50% stress, T_A= 40°C, ground benign

123

MHrs

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11 器件和文档支持

11.1 器件支持

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

11.2 使用 WEBENCH® 工具创建定制设计方案

请单击此处，借助 WEBENCH® Power Designer 并使用 TPSM84209 器件创建定制设计方案。

1. 首先输入输入电压 (V_IN)、输出电压 (V_OUT) 和输出电流 (I_OUT) 要求。

2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。

3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。

WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。

在多数情况下，可执行以下操作：

•

运行电气仿真，观察重要波形以及电路性能

运行热性能仿真，了解电路板热性能

将定制原理图和布局方案以常用 CAD 格式导出

打印设计方案的 PDF 报告并与同事共享

有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.5 商标

Eco-mode, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

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12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。

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PACKAGE OUTLINE

RKH0009A

QFN - 2.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

PIN 1 INDEX AREA

4.6

4.4

2.1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2X (0.8)

2X 1.125 0.05

8X (0.3)

SYMM

(0.2) TYP

(0.175) TYP

6X 0.65

2.25 0.05

2X EXPOSED

THERMAL PAD

2X ( 0.25)

PKG

0.000

2X 0.05

0.45

0.35

2X (0.625)

0.1

0.05

C A B

2X 1.05

2X 1.9

0.35

0.25

0.9

0.6

0.4

0.7

0.1

0.05

C A B

2X 0.85

4223793/B 09/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pads must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

TPSM84209

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

www.ti.com.cn

EXAMPLE BOARD LAYOUT

RKH0009A

QFN - 2.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.96)

SYMM

4X (0.7)

(2.23)

4X (0.3)

2X (2.1)

(1.95)

2X (1.9)

2X ( 0.35)

KEEP OUT AREA

3X (0.4)

(1.23)

2X (1.05)

2X (0.625)

(4.6)

(0.23)

3X (1)

8X (0.3)

2X (0.05)

0.000

PKG

(0.275)

(R0.05) TYP

(0.77)

(0.52)

2X (2.25)

(0.925)

(1.33)

(0.65)

(1.575)

(1.77)

(0.375) TYP

0.05 MIN

TYP

SOLDER MASK

OPENING

TYP

METAL UNDER

SOLDER MASK

TYP

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED

SCALE:20X

4223793/B 09/2017

NOTES: (continued)

4. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

www.ti.com

TPSM84209

www.ti.com.cn

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

EXAMPLE STENCIL DESIGN

RKH0009A

QFN - 2.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

METAL UNDER SOLDER MASK

TYP

(R0.05) TYP

4X (0.7)

2X (2.1)

(1.95)

4X (0.3)

2X (1.9)

3X (0.4)

2X (1.05)

3X (1)

SOLDER MASK EDGE

TYP

EXPOSED

METAL

TYP

2X (0.05)

0.000

PKG

2X (0.115)

(0.61)

6X)

(0.65

2X (0.925)

2X (1.735)

8X (0.3)

8X (0.375)

SYMM

6X (0.92)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PADS 3 & 4: 71%

SCALE:25X

4223793/B 09/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

TPSM84209

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

www.ti.com.cn

12.1 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

(mm)

Pin1

Quadrant

Device

Pins

SPQ

QFN-

FCMOD

TPSM84209RKHT

RKH

3000

330.0

12.4

4.3

4.8

2.25

8.0

12.0

TPSM84209

www.ti.com.cn

ZHCSHG7C –JANUARY 2018–REVISED JULY 2018

TAPE AND REEL BOX DIMENSIONS

Width (mm)

Device

Package Type

QFN-FCMOD

Package Drawing Pins

RKH

SPQ

Length (mm) Width (mm)

383.0 353.0

Height (mm)

TPSM84209RKHT

3000

58.0

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

PACKAGE OPTION ADDENDUM

www.ti.com

14-Feb-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPSM84209RKHR

TPSM84209RKHT

ACTIVE QFN-FCMOD

RKH

3000 RoHS & Green

250 RoHS & Green

Level-3-260C-168 HR

-40 to 85

TPSM84209

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

14-Feb-2021

Addendum-Page 2

重要声明和免责声明

TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没

有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可

将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知

识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款

的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

TPSM84209RKHT [TI]

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