TPSM84424 [TI]
采用紧凑型 7.5x7.5mm 封装尺寸的 4.5V 至 17V 输入、0.6V 至 10V 输出、4A 电源模块;型号: | TPSM84424 |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用紧凑型 7.5x7.5mm 封装尺寸的 4.5V 至 17V 输入、0.6V 至 10V 输出、4A 电源模块 电源电路 |
文件: | 总34页 (文件大小:1309K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
TPSM84424 4.5V 至 17V 输入、0.6V 至 10V 输出、4A 电源模块
1 特性
3 说明
1
•
集成电感器电源解决方案
TPSM84424 电源模块是一款易于使用的集成式电源,
它在一个小型 QFM 封装内整合了一个带有功率
MOSFET 的 4A 直流/直流转换器、一个屏蔽式电感器
和多个无源器件。该电源解决方案仅使用了 6 个外部
组件,同时仍能够调整关键参数以满足特定的设计要
求。通过使用 TurboTrans™功能可实现超快速瞬态响
应。TurboTrans 允许对瞬态响应进行优化,以减少输
出电压偏离,并降低所需的输出电容。
•
7.5mm × 7.5mm × 5.3mm QFM 封装
–
所有引脚均分布在封装外围
•
•
•
•
输入电压范围:4.5V 至 17V
宽输出电压范围:0.6V 至 10V
效率高达 96%
可调节固定开关频率
(200kHz 至 1.6MHz)
•
•
•
•
•
•
•
支持与外部时钟同步
7.5mm × 7.5mm × 5.3mm、24 引脚 QFM 封装易于焊
接到印刷电路板上,并且具有出色的功率耗散能力。
TPSM84424 极具灵活性且具有很多 特性, 包括正常
电源、可编程 UVLO、跟踪、预偏置启动以及过流和
过热保护,从而使其成为向各种器件和系统供电的理想
之选。
超快速负载阶跃响应 (TurboTrans™)
电源正常输出
符合 EN55011 B 类辐射发射限制
工作环境温度范围:-40°C 至 +105°C
工作 IC 结温范围:-40°C 至 +150°C
使用 TPSM84424 并借助 WEBENCH® Power
Designer 创建定制设计方案
器件信息(1)
器件型号
TPSM84424
封装
QFM (24)
封装尺寸(标称值)
2 应用
7.50mm × 7.50mm
•
•
•
•
电信和无线基础设施
(1) 如需了解所有可用封装,请参阅产品说明书末尾的可订购产品
附录。
工业自动化测试设备
企业交换和存储 应用
高密度分布式电源系统
空白
空白
空白
空白
简化原理图
瞬态响应
PGOOD
VOUT
VIN
VIN
VOUT
RT/CLK
EN
CIN
TPSM84424
RRT
RFBT
COUT
FB
TT
RTT
AGND
PGND
RFBB
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSEJ2
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics (VIN = 12 V).......................... 8
6.8 Typical Characteristics (VIN = 5 V)............................ 9
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 20
8
9
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application .................................................. 21
Power Supply Recommendations...................... 23
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Examples................................................... 24
10.3 EMI........................................................................ 25
10.4 Package Specifications......................................... 26
11 器件和文档支持 ..................................................... 27
11.1 器件支持 ............................................................... 27
11.2 开发支持................................................................ 27
11.3 接收文档更新通知 ................................................. 27
11.4 社区资源................................................................ 27
11.5 商标....................................................................... 27
11.6 静电放电警告......................................................... 27
11.7 术语表 ................................................................... 27
12 机械、封装和可订购信息....................................... 28
12.1 Tape and Reel Information ................................... 28
7
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Original (February 2018) to Revision A
Page
•
•
•
•
已添加 inductor value to the block diagram ......................................................................................................................... 10
已更改 VOUT Range vs Switching Frequency table .............................................................................................................. 12
已添加 270 µF capacitor to the Allowable Polymer Capacitor table .................................................................................... 15
已添加 EMI section .............................................................................................................................................................. 25
2
Copyright © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
5 Pin Configuration and Functions
MOL Package
24-Pin QFM
Top View
24
23
22
21
1
20
PGND
VOUT
19
18
PGND
PGND
FB
AGND
DNC
2
3
4
5
6
7
17
16
15
14
SW
TT
SW
SS/TR
PGOOD
PGND
PGND
PGND
8
VOUT
13
12
10
11
9
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Analog ground. Zero voltage reference for internal references and logic. These pins should be
connected to one another externally using an analog ground plane on the PCB. Do not connect
this pin to PGND; the connection is made internal to the device.
AGND
3, 9, 23
G
Do Not Connect. Do not connect this pin to AGND, PGND, or to any other voltage. This pin is
connected to internal circuitry.
DNC
4
Enable. Float or pull high to enable the device. Connect a resistor divider to this pin to implement
adjustable undervoltage lockout and hysteresis.
EN
FB
10
2
I
I
Feedback input of the regulator. Connect the output voltage feedback resistor divider to this pin.
Power ground. This is the return current path for the power stage of the device. Connect these
pins to the input source, the load, and to the bypass capacitors associated with VIN and VOUT
using power ground planes on the PCB. Connect pads 12 and 21 to the ground planes using
multiple vias for improved thermal performance.
12, 13, 14,
15, 18, 19,
20, 21
PGND
G
O
Power-good flag. This open drain output asserts low if the output voltage is outside of the PGOOD
thresholds, VIN is lower than its UVLO threshold, EN is low, device is in thermal shutdown or
device is in soft-start. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or other DC voltage no
higher than 6.5 V.
PGOOD
7
Switching frequency setting pin. In RT mode, an external timing resistor adjusts the switching
frequency. In CLK mode, the device synchronizes to an external clock input to this pin.
RT/CLK
SS/TR
24
6
I
I
Soft start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage
soft-start ramp slower than its 1.25-ms default setting. A voltage applied to this pin allows for
tracking and sequencing control.
(1) G = Ground, I = Input, O = Output
Copyright © 2018, Texas Instruments Incorporated
3
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Switch node. Do not place any external components on these pins or tie them to a pin of another
function.
SW
16, 17
O
I
TurboTrans pin. Internal loop compensation network. Connect the required TurboTrans resistor
between this pin and AGND. See TurboTrans (TT) for the value of the resistor. Do not leave this
pin floating.
TT
5
Input voltage. Supplies voltage to the power switches of the converter and all of the internal
circuitry. Connect these pins to the input source and connect external input capacitors between
these pins and PGND, close to the device. Connect these pins to internal VIN layers using multiple
vias for improved thermal performance.
VIN
11, 22
I
Output voltage. These pins are connected to the internal output inductor. Connect these pins to
the output load and connect external output capacitors between these pins and PGND, close to
the device. Connect these pins to internal VOUT layers using multiple vias for improved thermal
performance.
VOUT
1, 8
O
4
Copyright © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
6 Specifications
6.1 Absolute Maximum Ratings
Over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–1
MAX
19
UNIT
V
VIN
Input voltage
EN, PGOOD, SS/TRK, RT/CLK, FB
6.5
V
AGND to PGND
0.3
V
SW
VIN + 1
VIN + 3
VIN
V
Output voltage
SW (< 10-ns transients)
–3
V
VOUT
–0.3
V
Mechanical shock
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
500
G
Mechanical vibration
Mil-STD-883D, Method 2007.2, 20 to 2000 Hz
10
G
(2)
Operating IC junction temperature, TJ
–40
–40
–40
150
°C
°C
°C
(2)
Operating ambient temperature, TA
Storage temperature, Tstg
105
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extendedperiods may affect device reliability.
(2) The ambient temperature is the air temperature of the surroundingenvironment. The junction temperature is the temperature of the
internal power IC when the deviceis powered. Operating below the maximum ambient temperature, as shown in the safe
operatingarea(SOA) curves in the typical characteristics sections, ensures that the maximum junctiontemperature of any component
inside the module is never exceeded.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1250
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted)
MIN
MAX
17
UNIT
V
Input voltage, VIN
4.5(1)
0.6
0
Output voltage, VOUT
10
V
EN voltage, VEN
5.5
5.5
1
V
PGOOD pullup voltage, VPGOOD
PGOOD sink current, IPGOOD
RT/CLK voltage range, VCLK
Output current, IOUT
V
mA
V
0
0
5.5
4
A
Operating ambient temperature, TA
–40
105
°C
(1) For output voltages 0.6 V to < 5.5 V, the recommended minimum VIN is 4.5 V or (VOUT + 1 V), whichever is greater. For output
voltages 5.5 V to < 9 V, the recommended minimum VIN is (VOUT + 2 V). For output voltages 9 V to 10 V, the recommended minimum
VIN is (VOUT + 3 V).
Copyright © 2018, Texas Instruments Incorporated
5
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
6.4 Thermal Information
TPSM84424
MOL (QFN)
24 PINS
22
THERMAL METRIC(1)
UNIT
RθJA
ψJT
Junction-to-ambient thermal resistance(2)
Junction-to-top characterization parameter(3)
Junction-to-board characterization parameter(4)
°C/W
°C/W
°C/W
2.1
ψJB
13.6
(1) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 100 mm × 100 mm, 4-layer PCB with 2 oz.
copper and natural convection cooling. Additional airflow reduces RθJA
.
(3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
6.5 Electrical Characteristics
Over –40°C to +105°C ambient temperature, VIN = 12 V, VOUT = 1.2 V, IOUT = IOUTmax, fsw = 450 kHz (unless otherwise
noted); CIN1 = 2× 10-µF, 25-V, 1210 ceramic; CIN2 = 100-µF, 50-V, electrolytic; COUT = 4× 47-µF, 10-V, 1210 ceramic.
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
4.5(1)
3.7
TYP
MAX UNIT
INPUT VOLTAGE (VIN
)
VIN
Input voltage
Over IOUT range
VIN increasing
VIN decreasing
VEN = 0 V
17
V
V
4.1
3.9
3
4.3
UVLO
ISHDN
VIN undervoltage lockout
Shutdown supply current
V
11
10
µA
OUTPUT VOLTAGE (VOUT
)
VOUT(ADJ) Output voltage adjust
Over IOUT range
0.6
V
VOUT(Ripple) Output voltage ripple
20-MHz bandwidth
16
mV
FEEDBACK
TA = 25°C, IOUT = 0 A
0.596
0.595
0.6
0.6
0.1
0.8
0.604
0.605
V
V
Feedback voltage(2)
–40°C ≤ TJ ≤ 125°C, IOUT = 0 A
Over VIN range, TA = 25°C, IOUT = 0 A
Over IOUT range, TA = 25°C
VFB
Line regulation
mV
mV
Load regulation
CURRENT
Output current
IOUT
Natural convection, TA = 25°C
0
4
A
A
Overcurrent threshold
11
PERFORMANCE
VOUT = 5 V, fSW = 1.2 MHz
VOUT = 3.3 V, fSW = 1.0 MHz
94%
93%
91%
87%
86%
VIN = 12 V,
IOUT = 4 A
ƞ
Efficiency
VOUT = 1.8 V, fSW = 600 kHz
VOUT = 1.2 V, fSW = 450 kHz
VOUT = 1 V, fSW = 400 kHz
25% to 75% load step, 2A/µs slew rate,
RTT = 4.02 kΩ,
COUT = 200-µF ceramic + 220-µF polymer
27
35
mV
mV
Transient response
voltage deviation
25% to 75% load step, 2A/µs slew rate,
RTT = 3.40 kΩ, COUT = 200-µF ceramic
(1) For output voltages 0.6 V to < 5.5 V, the recommended minimum VIN is 4.5 V or (VOUT + 1 V), whichever is greater. For output
voltages 5.5 V to < 9 V, the recommended minimum VIN is (VOUT + 2 V). For output voltages 9 V to 10 V, the recommended minimum
VIN is (VOUT + 3 V).
(2) The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.
6
Copyright © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
Electrical Characteristics (continued)
Over –40°C to +105°C ambient temperature, VIN = 12 V, VOUT = 1.2 V, IOUT = IOUTmax, fsw = 450 kHz (unless otherwise
noted); CIN1 = 2× 10-µF, 25-V, 1210 ceramic; CIN2 = 100-µF, 50-V, electrolytic; COUT = 4× 47-µF, 10-V, 1210 ceramic.
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SOFT START
tSS
Internal soft start time
1.25
5
ms
µA
ISS
Soft start charge current
THERMAL
Shutdown temperature
170
15
°C
°C
TSHDN
Thermal shutdown
Hysteresis
ENABLE (EN)
VEN-H
EN rising threshold
1.2
1.15
1.2
1.26
V
V
VEN-HYS
EN falling threshold
1.1
VEN = 1.1 V
VEN = 1.3 V
µA
µA
IEN
EN pin sourcing current
3.6
POWER GOOD (PGOOD)
VOUT rising (fault)
VOUT falling (good)
108%
106%
91%
89%
0.7
VPGOOD
PGOOD thresholds
VOUT rising (good)
VOUT falling (fault)
Minimum VIN for valid PGOOD VPGOOD < 0.5 V, IPGOOD = 2 mA
1
V
V
PGOOD low voltage
CAPACITANCE
2-mA pullup, VEN = 0 V
0.3
Ceramic type
20(3)
µF
µF
µF
CIN
External input capacitance
External output capacitance
Non-ceramic type
100(3)
COUT
min(4)
1500(5)
(3) A minimum of 20-µF ceramic input capacitance is required for proper operation. An additional 100 µF of bulk capacitance is
recommended for applications with transient load requirements. See the Input Capacitor section for further guidance.
(4) The minimum amount of required output capacitance varies depending on the output voltage (see Standard Component Values Table).
A minimum amount of ceramic output capacitance is required. Locate the capacitance close to the device. Adding additional ceramic or
non-ceramic capacitance close to the load improves the response of the regulator to load transients.
(5) The maximum output capacitance can be made up of all ceramic type or a combination of ceramic and a single non-ceramic type. See
the Low-ESR Output Capacitors Section for requirements of non-ceramic output capacitors.
6.6 Switching Characteristics
Over operating ambient temperature range (unless otherwise noted)
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm, and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SW
tON_MIN
tOFF_MIN
Minimum on-time
Minimum off-time
140
100
ns
ns
FREQUENCY (RT) and SYNCHRONIZATION (EN/SYNC)
Default switching frequency
RT pin = 110 kΩ
400
200
2
450
500
kHz
kHz
V
fSW
Switching frequency range
1600
VCLK-H
VCLK-L
Logic high input voltage
Logic low input voltage
Minimum CLK pulse width
0.8
V
TCLK-MIN
35
ns
Copyright © 2018, Texas Instruments Incorporated
7
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
6.7 Typical Characteristics (VIN = 12 V)
TA = 25°C, unless otherwise noted.
100
95
90
85
80
75
70
2.5
2
VOUT, FSW
9.0 V, 1.3 MHz
7.5 V, 1.3 MHz
5.0 V, 1.3 MHz
3.3 V, 1.0 MHz
2.5 V, 800 kHz
1.8 V, 600 kHz
1.2 V, 400 kHz
1.0 V, 350 kHz
0.8 V, 300 kHz
1.5
1
VOUT, FSW
65
60
55
50
45
40
9.0 V, 1.3 MHz
7.5 V, 1.3 MHz
5.0 V, 1.3 MHz
3.3 V, 1.0 MHz
2.5 V, 800 kHz
1.8 V, 600 kHz
1.2 V, 400 kHz
1.0 V, 350 kHz
0.8 V, 300 kHz
0.5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Output Current (A)
Output Current (A)
D001
D002
图 1. Efficiency vs Output Current
图 2. Power Dissipation vs Output Current
35
30
25
20
15
10
5
115
105
95
VOUT, FSW
9.0 V, 1.3 MHz
7.5 V, 1.3 MHz
5.0 V, 1.3 MHz
3.3 V, 1.0 MHz
2.5 V, 800 kHz
1.8 V, 600 kHz
1.2 V, 400 kHz
1.0 V, 350 kHz
0.8 V, 300 kHz
85
75
65
55
45
Airflow
Nat Conv
35
25
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Output Current (A)
Output Current (A)
D003
D004
COUT = 200 µF ceramic
图 3. Ripple Voltage vs Output Current
VOUT ≤ 3.0 V
图 4. Safe Operating Area
115
105
95
115
105
95
85
75
65
55
45
35
25
85
75
65
55
Airflow
400LFM
200LFM
100LFM
Nat conv
45
Airflow
100LFM
Nat Conv
35
25
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Output Current (A)
Output Current (A)
D005
D006
VOUT = 3.3 V
fSW = 1 MHz
VOUT = 5 V
fSW = 1.2 MHz
图 5. Safe Operating Area
图 6. Safe Operating Area
8
版权 © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
6.8 Typical Characteristics (VIN = 5 V)
TA = 25°C, unless otherwise noted.
100
95
90
85
80
75
70
65
1
0.8
0.6
0.4
0.2
0
VOUT, FSW
3.3 V, 1.0 MHz
2.5 V, 800 kHz
1.8 V, 600 kHz
1.2 V, 450 kHz
1.0 V, 400 kHz
0.8 V, 300 kHz
60
55
50
45
40
VOUT, FSW
3.3 V, 1.0 MHz
2.5 V, 800 kHz
1.8 V, 600 kHz
1.2 V, 450 kHz
1.0 V, 400 kHz
0.8 V, 300 kHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Output Current (A)
Output Current (A)
D007
D008
图 7. Efficiency vs Output Current
图 8. Power Dissipation vs Output Current
35
30
25
20
15
10
5
115
105
95
VOUT, FSW
3.3 V, 1.0 MHz
2.5 V, 800 kHz
1.8 V, 600 kHz
1.2 V, 450 kHz
1.0 V, 400 kHz
0.8 V, 300 kHz
85
75
65
55
45
Airflow
35
Nat Conv
25
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Output Current (A)
Output Current (A)
D009
D010
COUT = 200 µF ceramic
图 9. Ripple Voltage vs Output Current
All VOUT
图 10. Safe Operating Area
版权 © 2018, Texas Instruments Incorporated
9
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPSM84424 is a full-featured 4.5-V to 17-V input, 4-A, synchronous step-down converter with PWM,
MOSFETs, inductor, and control circuitry integrated into a low-profile package. The device integration enables
small designs, while still leaving the ability to adjust key parameters to meet specific design requirements. The
TPSM84424 provides an output voltage range of 0.6 V to 10 V. An external resistor divider is used to adjust the
output voltage to the desired output. The switching frequency is also adjustable by using an external resistor or a
synchronization clock to accommodate various input and output voltage conditions and to optimize efficiency.
The TPSM84424 includes the TurboTrans feature which optimizes the transient response of the converter while
simultaneously reducing the quantity of external output capacitors required to meet a target voltage deviation
specification.
The TPSM84424 has been designed for safe start-up into pre-biased loads. The default start up is when VIN is
typically 4.1 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage
undervoltage lockout (UVLO) with two external resistors. In addition, the internal pullup current of the EN pin
allows the device to operate with the EN pin floating. The EN pin can also be pulled low to put the device in
standby mode to reduce input quiescent current. The device provides a power-good (PGOOD) signal to indicate
when the output voltage is within regulation. Thermal shutdown and current limit features protect the device
during an overload condition. A 24-pin QFN package that includes exposed bottom pads provides a thermally
enhanced solution for space-constrained applications.
7.2 Functional Block Diagram
Shutdown
Logic
PGOOD
EN
PGOOD
Logic
Thermal
Shutdown UVLO
VIN
OCP
FB
VIN
SW
5µA
SS/TR
+
+
10nF
VREF
0.85µH
Comp
Power
Stage
and
VOUT
PGND
TT
DNC
Control
Logic
Oscillator
with PLL
RT/CLK
AGND
TPSM84424
Copyright © 2018, Texas Instruments Incorporated
10
版权 © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
7.3 Feature Description
7.3.1 Adjusting the Output Voltage
A resistor divider connected to the FB pin (pin 2) programs the output voltage of the TPSM84424. The output
voltage adjustment range is from 0.6 V to 10 V. 图 11 shows the feedback resistor connection for setting the
output voltage. The recommended value of RFBT is 10 kΩ. The value for RFBB can be calculated using 公式 1 or
simply selected from the range of values given in 表 1. 表 1 also includes the recommended switching frequency
and minimum required output capacitance for each output voltage.
6
(kꢀ)
RFBB
=
(VOUT œ 0.6)
(1)
VOUT
RFBT
10 kꢀ
FB
RFBB
AGND
图 11. Setting the Output Voltage
表 1. Standard Component Values
Minimum Required COUT(µF)(1)(2)
RECOMMENDED
RRT (kΩ)
VOUT (V)
RFBB (kΩ)
fSW (kHz)
CERAMIC
400
400
300
200
200
200
200
200
200
150
150
150
100
100
100
100
47
POLYMER(3)
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.5
3.3
5.0
6.0
7.5
9.0
10
open
60.4
30.1
20.0
15.0
12.1
10.0
8.66
7.50
6.65
6.04
5.49
4.99
4.64
4.32
3.16
2.21
1.37
1.10
0.866
0.715
0.634
250
250
300
350
400
400
450
500
500
550
550
600
600
650
700
800
1000
1200
1200
1300
1300
1300
200
200
220
220
165
220
143
220
124
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
124
110
97.6
97.6
88.7
88.7
82.5
82.5
75.0
69.8
60.4
48.7
40.2
40.2
36.5
36.5
36.5
47
47
47
22
22
(1) Additional capacitance above the minimum can be ceramic or polymer type.
(2) Load transients with > 2 A/µs slew rates may require additional capacitance, see TurboTrans.
(3) See Low-ESR Output Capacitors for details on polymer capacitors.
版权 © 2018, Texas Instruments Incorporated
11
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
7.3.2 Switching Frequency (RT)
The switching frequency range of the TPSM84424 is 200 kHz to 1.6 MHz. The switching frequency can easily be
set by connecting a resistor (RRT) between the RT pin and AGND. Use 公式 2 to calculate the RRT value for a
desired frequency or simply select from 表 2.
The switching frequency must be selected based on the output voltage setting of the device and the operating
input voltage. See 表 2 for the allowable output voltage range for a given switching frequency.
58650 × fSW (kHz)-1.028 (kꢀ)
RRT
=
(2)
表 2. VOUT Range vs Switching Frequency
VIN = 5 V (±10%)
VOUT RANGE (V)
VIN = 12 V (±5%)
VOUT RANGE (V)
VIN = 15 V (±5%)
VOUT RANGE (V)
SWITCHING
FREQUENCY
min
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.7
0.7
0.9
1
max
0.9
0.9
1.0
1.2
1.8
2.0
2.2
2.5
3.0
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
min
0.6
0.6
0.7
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.8
2.0
2.2
2.3
2.4
2.6
2.8
max
0.8
0.9
1.0
1.2
1.5
1.8
2.0
2.5
2.7
3.0
3.3
3.6
4.0
6.0
9.0
9.0
9.0
9.0
9.0
9.0
min
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.4
1.5
1.6
1.7
1.8
2.0
2.2
2.5
2.7
2.9
3.1
3.3
3.5
max
0.8
0.9
1.0
1.2
1.5
1.8
2.0
2.3
2.5
2.8
3.0
3.3
4.0
4.8
6.0
8.0
10
250 kHz
300 kHz
350 kHz
400 kHz
450 kHz
500 kHz
550 kHz
600 kHz
650 kHz
700 kHz
750 kHz
800 kHz
900 kHz
1.0 MHz
1.1 MHz
1.2 MHz
1.3 MHz
1.4 MHz
1.5 MHz
1.6 MHz
1.1
1.1
1.2
1.3
1.4
10
10
10
7.3.3 Synchronization (CLK)
The TPSM84424 switching frequency can also be synchronized to an external clock from 200 kHz to 1.6 MHz.
Not all VIN, VOUT, and IOUT conditions can be set to all of the frequencies in this range due to on-time or off-time
limitations. See 表 2 for the allowable operating ranges.
An internal Phase Locked Loop (PLL) has been implemented to allow synchronization and to easily switch from
RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the
RT/CLK pin (pin 24) with a duty cycle from 20% to 80%. The clock signal amplitude must transition lower than
0.8 V and higher than 2 V. The start of the switching cycle is synchronized to the falling edge of the RT/CLK pin.
Before the external clock is present the device operates in RT mode and the switching frequency is set by the
RT resistor, RRT. Select RRT to set the frequency close to the external synchronization frequency. When the
external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is pulled above the
RT/CLK high threshold (2 V), the device switches from the RT mode to the CLK mode and the RT/CLK pin
becomes high impedance as the PLL starts to lock onto the frequency of the external clock.
During operation, if the external clock is removed, the internal clock frequency begins to drop. After 10 μs without
receiving a clock pulse, the device returns to RT mode. Output undershoot can occur while the switching
frequency drops and returns to the frequency set by the RT resistor.
12
版权 © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
7.3.4 Output On/Off Enable (EN)
The EN pin provides electrical ON/OFF control of the device. Once the EN pin voltage exceeds the threshold
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters low operating current state. The EN pin has an internal pullup current source allowing
the user to float the EN pin for enabling the device.
If an application requires controlling the EN pin, either drive it directly with a logic input or use an open
drain/collector device to interface with the pin. Applying a low voltage to the enable control (EN) pin disables the
output of the supply, shown in 图 12. When the EN pin voltage exceeds the threshold voltage, the supply
executes a soft-start power-up sequence, as shown in 图 13.
图 12. Enable Turnoff
图 13. Enable Turnon
7.3.5 Input Capacitor Selection
The TPSM84424 requires a minimum input capacitance of 20 µF of ceramic type. Use only high-quality ceramic
type X5R or X7R capacitors with sufficient voltage rating. TI recommends an additional 100 µF of non-ceramic
capacitancefor applications with transient load requirements. The voltage rating of input capacitors must be
greater than the maximum input voltage. To compensate the derating of ceramic capactors, a voltage rating of
twice the maximum input voltage is recommended. At worst case, when operating at 50% duty cycle and
maximum load, the combined ripple current rating of the input capacitors must be at least 2 A(rms). 表 3 includes
a preferred list of capacitors by vendor.
表 3. Recommended Input Capacitors(1)
CAPACITOR CHARACTERISTICS
(2)
(3)
VENDOR
SERIES
PART NUMBER
CAPACITANCE
(µF)
ESR
WORKING VOLTAGE (V)
(mΩ)
TDK
X7R
X7R
ZA
C3225X7R1E106K250AC
GRM32DR71E106KA12L
EEHZA1H101P
25
25
50
50
10
10
2
Murata
2
Panasonic
Panasonic
100
100
28
FC
EEUFC1H101B
162
(1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
(2) Specified capacitance values.
(3) Maximum ESR @ 100 kHz, 25°C.
版权 © 2018, Texas Instruments Incorporated
13
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
7.3.6 Output Capacitor Selection
The minimum required output capacitance of the TPSM84424 is a function of the output voltage and is shown in
表 1. The required capacitance can be comprised of all ceramic capacitors or a combination of ceramic and low-
ESR polymer type capacitors. When adding additional capacitors, low-ESR capacitors like the ones
recommended in Low-ESR Output Capacitors are required. The required capacitance above the minimum is
determined by actual transient deviation requirements. See TurboTrans (TT) for typical transient response values
for several output voltage and capacitance combinations. See 表 4 for recommended output capacitors.
表 4. Recommended Output Capacitors(1)
CAPACITOR CHARACTERISTICS
CAPACITANCE(2)
(µF)
ESR(3)
(mΩ)
VENDOR
SERIES
PART NUMBER
WORKING
VOLTAGE (V)
TDK
X7R
X7R
C3225X7R1C226K
16
16
22
22
2
2
Murata
TDK
GCJ32ER71C226K
C3225X5R1C226M
GRM32ER61C226K
GCM32ER70J476K
GRM32ER71A476K
GRM32ER61C476K
C3225X5R0J107M
GRM32ER60J107M
GRM32ER61A107M
4TPE220MF
X5R
16
22
2
Murata
Murata
Murata
Murata
TDK
X5R
16
22
2
X7R
6.3
10
47
2
X7R
47
2
X5R
16
47
3
X5R
6.3
6.3
10
100
100
100
220
220
330
330
470
470
2
Murata
Murata
Panasonic
Kemet
X5R
2
X5R
2
POSCAP
T520
POSCAP
T520
POSCAP
T520
4.0
6.3
6.3
6.3
2.5
2.5
15
15
10
10
7
T520D227M006ATE015
6TPE330MAA
Panasonic
Kemet
T520D337M006ATE010
2R5TPE470M7
Panasonic
Kemet
T520D477M2R5ATE007
7
(1) Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table.
(2) Specified capacitance values.
(3) Maximum ESR @ 100 kHz, 25°C.
14
版权 © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
7.3.7 TurboTrans (TT)
The TPSM84424 includes the TurboTrans feature which optimizes the transient response of the converter while
simultaneously reducing the quantity of external output capacitors required to meet a target voltage deviation
specification. A TurboTrans resistor, RTT, is required between the TT pin and AGND to properly set the response
of the TPSM84424 based on the amount and type of output capacitors. The value of RTT can be calculated using
公式 3. In order to calculate the RTT value, a TurboTrans constant, KTT, is required. See 表 5 for the KTT value
when using only ceramic output capacitors. See 表 6 for the KTT value when using a combination of ceramic and
polymer output capacitors. Applications operating from input voltages above 14 V, must reduce the calculated
RTT value by 20%. Also, the value of CO used in 公式 3 is the total effective output capacitance, which takes into
account the effects of applied voltage and temperature.
KTT × VOUT × CO(eff)(µF)
(kꢀ)
-2
]
RTT
=
)
[(
50
(3)
表 5. KTT Values (Ceramic Only Output Capacitors)
VOUT (V)
KTT
1 - < 1.2
1.2 - < 1.5
1.5 - < 1.8
1.8 - < 2
2 - < 2.5
2.5 - < 3.3
3.3 - < 7.5
7.5 - 10
1
1.12
1.4
1.5
1.65
1.8
2.0
2.25
表 6. KTT Values (Ceramic + Polymer Output Capacitors)
VOUT (V)
KTT
0.6 - < 0.7
0.7 - < 0.9
0.65
0.9 - < 1
1 - < 2.5
2.5 - < 3.3
3.3 - < 5
5 - < 6
6 - < 7.5
7.5 - 10
0.6
0.7
0.6
0.72
0.9
1.2
1.5
1.8
7.3.7.1 Low-ESR Output Capacitors
When selecting non-ceramic output capacitors, the quality of the capacitor is important to maintain stable
operation and optimize transient performance. The capacitance rating and the ESR rating are important when
selecting these capacitors. Polymer type capacitors with capacitance and ESR in the range shown in 表 7 are
required. Capacitors with lower ESR than the minimum listed in 表 7 can be used, however using capacitors with
an ESR in the range listed will provide optimal transient performance.
If using a combination of ceramic and polymer type of output capacitance, only a single polymer capacitor can
be used. Depending on the output voltage setting, only capacitors that meet the specifications listed in 表 7 can
be used.
表 7. Allowable Polymer Capacitor
ESR (mΩ)
VOUT RANGE
Capacitance (µF)
min
12
9
max
15
12
10
25
15
12
10
220
270
330(1)
0.6 V to < 3.3 V(1)
7
150
15
12
9
220
3.3 V to ≤ 10 V
270
330
7
(1) Applications operating at input voltages > 15 V, output voltages <
3.3V, and temperatures below 0°C, the 330-µF capacitor is not
recommended.
版权 © 2018, Texas Instruments Incorporated
15
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
7.3.7.2 Transient Response
The TPSM84424 transient response is listed in 表 8 for several common output voltages with different capacitor
combinations. The calculated RTT value is included in the table along with the typical voltage deviation for a 1 A
and 2 A load step. All data was taken at the recommended switching frequency for each output voltage.
表 8. Output Voltage Transient Response
VIN = 12 V, CIN1 = 2x 10 µF Ceramic, CIN2 = 100 µF Electrolytic, TA = 25°C
VOLTAGE DEVIATION
VOUT (V)
COUT1 Ceramic
COUT2 BULK
RTT (kΩ)
1 A LOAD STEP
11 mV . (1.4%)
9 mV . (1.1%)
15 mV . (1.5%)
12 mV . (1.2%)
11 mV . (1.1%)
10 mV . (1.0%)
17 mV . (1.4%)
13 mV . (1.1%)
11 mV . (0.9%)
9 mV . (0.8%)
27 mV . (1.6%)
11 mV . (0.6%)
12 mV . (0.7%)
30 mV . (0.9%)
16 mV . (0.5%)
22 mV . (0.7%)
42 mV . (0.9%)
16 mV . (0.3%)
24 mV . (0.5%)
56 mV . (0.8%)
18 mV . (0.3%)
2 A LOAD STEP
22 mV . (2.7%)
18 mV . (2.2%)
30 mV . (3%)
300 µF
400 µF
200 µF
200 µF
400 µF
400 µF
200 µF
200 µF
400 µF
400 µF
100 µF
300 µF
100 µF
100 µF
100 µF
200 µF
100 µF
100 µF
200 µF
100 µF
47 µF
220 µF
3.40
5.36
2.00
3.01
6.04
5.49
3.40
4.02
8.87
6.98
3.40
14.3
4.87
8.66
31.6
19.1
10.0
31.6
22.1
10.5
28.0
0.8(1)
330 µF
-
220 µF
24 mV . (2.4%)
23 mV . (2.3%)
20 mV . (2%)
1(1)
-
220 µF
-
35 mV . (2.9%)
27 mV . (2.2%)
22 mV . (1.8%)
18 mV . (1.5%)
56 mV . (3.1%)
22 mV . (1.2%)
24 mV . (1.3%)
60 mV . (1.8%)
32 mV . (1.0%)
43 mV . (1.3%)
83 mV . (1.7%)
32 mV . (0.6%)
48 mV . (1%)
220 µF
1.2(1)
-
220 µF
-
1.8(1)
3.3(2)
-
220 µF
-
220 µF
-
-
5(2)
220 µF
-
-
112 mV . (1.5%)
36 mV . (0.5%)
7.5(2)
220 µF
(1) Load step slew rate of 2 A/µs
(2) Load step slew rate of 1 A/µs
16
版权 © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
7.3.7.2.1 Transient Waveforms (VIN = 12 V)
VOUT = 0.8 V
COUT = 300 µF ceramic + 220 µF polymer
图 14. VOUT = 0.8 V, 2-A Load Step
VOUT = 0.8 V
COUT = 300 µF ceramic + 330 µF polymer
图 15. VOUT = 0.8 V, 2-A Load Step
VOUT = 1 V
COUT = 400 µF ceramic
图 16. VOUT = 1 V, 2-A Load Step
VOUT = 1 V
COUT = 200 µF ceramic + 220 µF polymer
图 17. VOUT = 1 V, 2-A Load Step
VOUT = 1.2 V
COUT = 200 µF ceramic
图 18. VOUT = 1.2 V, 2-A Load Step
VOUT = 1.2 V
COUT = 200 µF ceramic + 220 µF polymer
图 19. VOUT = 1.2 V, 2-A Load Step
版权 © 2018, Texas Instruments Incorporated
17
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
7.3.8 Undervoltage Lockout (UVLO)
The TPSM84424 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin
voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 4.1 V (typical)
with a typical hysteresis of 200 mV.
Applications may require a higher UVLO threshold to prevent early turnon, for sequencing requirements, or to
prevent input current draw at lower input voltages. An external resistor divider can be added to the EN pin to
adjust the UVLO threshold higher. The external resistor divider can be configured as shown in 图 20. 表 9 lists
standard values for RUVLO1 and RUVLO2 to adjust the UVLO voltage higher.
VIN
RUVLO1
EN
RUVLO2
PGND
图 20. Adjustable UVLO
表 9. Standard Resistor Values for Adjusting UVLO
VIN UVLO (V)
RUVLO1 (kΩ)
4.5
68.1
24.3
385
5
6
7
8
9
10
11
12
68.1
21.5
400
68.1
16.9
430
68.1
14
68.1
12.1
500
68.1
10.5
530
68.1
9.31
565
68.1
8.45
600
68.1
7.50
640
RUVLO2 (kΩ)
Hysteresis (mV)
465
7.3.9 Soft Start (SS/TR)
Leaving SS/TR pin open enables the internal soft-start time interval of approximately 1.25 ms. Adding additional
capacitance between the SS pin and AGND increases the soft-start time. Increasing the soft-start time reduces
inrush current seen by the input source and reduces the current seen by the device when charging the output
capacitors. To avoid the activation of current limit and ensure proper start-up, the SS capacitor may need to be
increased when operating near the maximum output capacitance limit.
See 表 10 for several SS capacitor values and timing interval or use 公式 4 to calculate the value.
0.6V × (CSS + 10nF)
tSS
=
5 µA
(4)
表 10. Soft-Start Capacitor Values and Soft-Start Time
CSS (nF)
SS Time (ms)
open
10
15
22
47
1.25
2.4
3
3.8
6.8
During soft-start, the output voltage increases from its starting voltage and rises into regulation. The device is
allowed to skip pulses as needed whenever the application conditions exceed the minimum on-time of the
device. This behavior is a function of input voltage, output voltage, switching frequency, and load current. During
the initial rise of the output voltage, adding an additional non-ceramic output capacitor in parallel with the
required ceramic capacitance will improve the output voltage ramp-up.
注
When testing soft start performance with an electronic load, the output voltage noise can
be exaggerated due to the control loop of the load. Testing with a pure resistive load is a
better way to quantify the device performance.
18
版权 © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
7.3.10 Sequencing (SS/TR)
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PGOOD
pins. The sequential method is illustrated in 图 21 using two TPSM84424 devices. The PGOOD pin of the first
device is coupled to the EN pin of the second device which enables the second power supply once the primary
supply reaches regulation.
EN
VOUT1
VOUT
PGOOD
EN
VOUT2
VOUT
PGOOD
图 21. Sequencing Schematic
Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2
shown in 图 22 to the output of the power supply that needs to be tracked or to another voltage reference source.
Use 公式 5 and 公式 6 to calculate the values of R1 and R2.
(VOUT2 × 5)
(kꢀ)
R1 =
0.6
(5)
(6)
0.6 × R1
(kꢀ)
R2 =
(VOUT2 œ 0.6)
VOUT1
VOUT
EN
VOUT2
VOUT
SS/TR
EN
R1
R2
图 22. Simultaneous Tracking Schematic
版权 © 2018, Texas Instruments Incorporated
19
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
7.3.11 Power Good (PGOOD)
The PGOOD pin is an open-drain output requiring an external pullup resistor to output a high signal. Once the
output voltage is between 91% and 106% of the setpoint voltage and SS/TR is greater than 0.75 V, the PGOOD
pin pulldown is released and the pin floats. A pullup resistor between the values of 10 kΩ and 100 kΩ to a
voltage source of 6.5 V or less is recommended. The PGOOD pin is pulled low when the output voltage is lower
than 89% or greater than 108% of the setpoint voltage.
7.3.12 Safe Start-up into Pre-Biased Outputs
The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During
monotonic pre-biased start-up, the low-side MOSFET is not allowed to sink current until the SS/TR pin voltage is
higher than the FB pin voltage and the high-side MOSFET begins to switch.
7.3.13 Overcurrent Protection
For protection against load faults, the TPSM84424 is protected from overcurrent conditions by cycle-by-cycle
current limiting. In an extended overcurrent condition the device enters hiccup mode to reduce power dissipation.
In hiccup mode, the module continues in a cycle of successive shutdown and power up until the load fault is
removed. During this period, the average current flowing into the fault is significantly reduced, which reduces
power dissipation. Once the fault is removed, the module automatically recovers and returns to normal operation.
7.3.14 Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
170°C typically. The device reinitiates the power up sequence when the junction temperature drops below 155°C
typically.
7.4 Device Functional Modes
7.4.1 Active Mode
The TPSM84424 is in active mode when VIN is above the UVLO threshold and the EN pin voltage is above the
EN high threshold. The EN pin has an internal current source to enable the output when the EN pin is left
floating. If the EN pin is pulled low the device is put into a low quiescent current state.
7.4.2 Shutdown Mode
The EN pin provides electrical ON and OFF control for the TPSM84424. When the EN pin voltage is below the
EN low threshold, the device is in shutdown mode. In shutdown mode the device is put into a low quiescent
current state. The TPSM84424 also employs undervoltage lockout protection. If VIN is below the UVLO level, the
output of the regulator turns off.
20
版权 © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPSM84424 is a fixed-frequency, synchronous step-down DC-DC power module. It is used to convert a
higher DC voltage to a lower DC voltage with a maximum output current of 4 A. The following design procedure
can be used to select components for the TPSM84424. Alternately, the WEBENCH® software may be used to
generate complete designs. When generating a design, the WEBENCH software utilizes an iterative design
procedure and accesses comprehensive databases of components. See www.ti.com/webench for more details.
8.2 Typical Application
The TPSM84424 requires only a few external components to convert from a wide input voltage supply range to a
wide range of output voltages. 图 23 shows a typical TPSM84424 schematic with only the minimum required
components.
VIN = 12V
VIN
EN
PGOOD
VOUT
VOUT = 1.2 V
10 µF
25 V
10 µF
25 V
TPSM84424
10 kO
10 kO
220 µF
15 mO
100 µF
6.3 V
100 µF
6.3 V
RT/CLK
TT
FB
110 kO
4.12 kO
AGND
PGND
Copyright © 2018, Texas Instruments Incorporated
图 23. TPSM84424 Typical Application
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 11 and follow the design procedures below.
表 11. Design Example Parameters
DESIGN PARAMETER
Input voltage VIN
VALUE
12 V typical
Output voltage VOUT
1.2 V
Output current rating
Key care-abouts
4 A
Small solution size, good transient response
3% voltage deviation, 2-A load step, 1-A/µs slew rate
Transient response requirements
版权 © 2018, Texas Instruments Incorporated
21
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TPSM84424 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of the TPSM84424 device is externally adjustable using a two resistor divider (RFBT and
RFBB). The recommended value of RFBT is 10 kΩ. Select the value of RFBB from 表 1 or calculate using 公式 7:
6
(kꢀ)
RFBB
=
(VOUT œ 0.6)
(7)
To set the output voltage to 1.2 V, the RFBB value is 10 kΩ.
8.2.2.3 Setting the Switching Frequency
To set the switching frequency of the TPSM84424 a resistor (RRT) between the RT/CLK pin and AGND is
required. Select the value of RRT from 表 1 or calculate using 公式 8:
58650 × fSW (kHz)-1.028 (kꢀ)
RRT
=
(8)
The recommended switching frequncy for a 1.2 V output is 450 kHz. To set the switching frequency to 450 kHz,
the RRT value is 110 kΩ.
8.2.2.4 Input Capacitors
For this design, two 10-μF ceramic capacitors rated for 25 V are used for the input decoupling capacitors.
8.2.2.5 Output Capacitors
The minimum required output capacitance for a 1.2-V output is 200 μF of ceramic capacitance, as listed in 表 1.
For this design, two 100-μF ceramic capacitors plus a 220 μF, 15 mΩ polymer capacitor where used to meet the
transient requirement specification.
8.2.2.6 TurboTrans Resistor
A TurboTrans resistor (RTT) is required between the TT pin and AGND. The value of RTT can be calulated using
公式 9. When calculating the RTT value, the total effective output capacitance which takes into account the
effects of applied voltage and temperature.
KTT × VOUT × CO(eff)(µF)
(kꢀ)
-2
]
RTT
=
)
[(
50
(9)
The calulated value for RTT for this application is 4.12 kΩ.
22
版权 © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
8.2.2.7 Application Waveforms
图 25. Transient Response Waveforms
图 24. Output Ripple and SW Waveforms
9 Power Supply Recommendations
The TPSM84424 is designed to operate from an input voltage supply range between 4.5 V and 17 V. This input
supply must be well regulated and able to withstand maximum input current and maintain a stable voltage. The
resistance of the input supply rail must be low enough that an input current transient does not cause a high
enough drop at the TPSM84424 supply voltage that can cause a false UVLO fault triggering and system reset.
If the input supply is located more than a few inches from the TPSM84424 additional bulk capacitance may be
required in addition to the ceramic bypass capacitors. Typically, a 47-µF or 100-μF electrolytic capacitor will
suffice.
版权 © 2018, Texas Instruments Incorporated
23
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
10 Layout
The performance of any switching power supply depends as much upon the layout of the PCB as the component
selection. The following guidelines will help users design a PCB with the best power conversion performance,
thermal performance, and minimized generation of unwanted EMI.
10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. 图 26 thru 图 29,
shows a typical PCB layout. Some considerations for an optimized layout are:
•
Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal
stress.
•
•
•
•
•
Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
Locate additional output capacitors between the ceramic capacitor and the load.
Keep AGND and PGND separate from one another. The connection is made internal to the device.
Place RFBB, RRT, and CSS as close as possible to their respective pins.
Use multiple vias to connect the power planes (VIN, VOUT, and PGND) to internal layers.
10.2 Layout Examples
图 26. Typical Top-Layer Layout
图 27. Typical Layer-2 Layout
图 29. Typical Bottom-Layer Layout (Bottom View)
图 28. Typical Layer-3 Layout
24
版权 © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
10.3 EMI
The TPSM84424 is compliant with EN55011 Class B radiated emissions. 图 30 and 图 31 show typical examples
of radiated emissions plots for the TPSM84424. The graphs include the plots of the antenna in the horizontal and
vertical positions.
10.3.1 EMI Plots
EMI plots were measured using the standard TPSM84424EVM with no input filter.
图 30. Radiated Emissions 12-V Input, 1.2-V Output, 4-A Load (EN55011 Class B)
图 31. Radiated Emissions 12-V Input, 5-V Output, 4-A Load (EN55011 Class B)
版权 © 2018, Texas Instruments Incorporated
25
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
10.4 Package Specifications
TPSM84424
VALUE
UNIT
Weight
0.90
grams
Flammability
Meets UL 94 V-O
MTBF Calculated Reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
73.5
MHrs
26
版权 © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息,不能构成与此类产品或服务或保修的适用性有关的认可,不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.2 开发支持
11.2.1 使用 WEBENCH® 工具创建定制设计
请单击此处,借助 WEBENCH® Power Designer 并使用 TPSM84424 器件创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数,如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下,可执行以下操作:
•
•
•
•
运行电气仿真,观察重要波形以及电路性能
运行热性能仿真,了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息,请访问 www.ti.com.cn/WEBENCH。
11.3 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
TurboTrans, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
版权 © 2018, Texas Instruments Incorporated
27
TPSM84424
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本,请查阅左侧的导航栏。
12.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
TPSM84424MOLR
QFM
MOL
24
500
330.0
16.0
7.8
7.8
5.81
12.0
16.0
Q2
28
版权 © 2018, Texas Instruments Incorporated
TPSM84424
www.ti.com.cn
ZHCSHN0A –FEBRUARY 2018–REVISED APRIL 2018
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
QFM
Package Drawing Pins
MOL 24
SPQ
Length (mm) Width (mm)
383.0 353.0
Height (mm)
TPSM84424MOLR
500
58.0
版权 © 2018, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
22-May-2019
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TPSM84424MOLR
ACTIVE
QFM
MOL
24
500
RoHS Exempt
& Green
NIAU
Level-3-260C-168 HR
-40 to 105
TPSM84424
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
MOL0024A
QFM - 5.4 mm max height
S
C
A
L
E
1
.
5
0
0
QUAD FLAT MODULE
7.6
7.4
A
B
PIN 1
INDEX AREA
7.6
7.4
5.4 MAX
C
SEATING PLANE
0.08 C
6.4
PKG
1.4
1.2
4X
13
(0.05) TYP
2X 0.15
12
8
3.4
4X
3.2
4X
2.05
2X
5.9
SYMM
2X
3.25
6.4
0.45
0.25
16X
0.1
C A B
0.05
ALL PADS
12X 0.65
20
1
PIN 1 ID
(OPTIONAL)
1.6
1.4
24
22
4X
1.1
0.9
20X
2X 1.425
2X 1.6
4223723/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
MOL0024A
QFM - 5.4 mm max height
QUAD FLAT MODULE
4X (1.3)
Cu KEEP OUT AREA
(1.8 X 5.3)
4X (1.2)
24
21
1
20
4X (1.7)
4X (3.05)
4X (3.5)
4X (2)
4X (1.3)
16X
(0.35)
0.000
SYMM
12X (0.65)
16X (1.2)
4X (1.15)
4X (2.15)
6X (2.7)
8
4X (3.15)
6X (3.4)
4X (3.3)
13
(
0.2) VIA
TYP
9
11
(R0.05) TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:12X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK DETAIL
4223723/A 05/2017
NOTES: (continued)
4. This package is designed to be soldered to the thermal pads on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
MOL0024A
QFM - 5.4 mm max height
QUAD FLAT MODULE
16X (3.3)
4X (1.6)
2X (1.425)
4X (0.15)
4X (1.1)
(R0.05)
TYP
24
21
1
20
12X (1.6)
8X (3.05)
16X (0.35)
4X
(1.25)
SYMM
16X (0.65)
4X (3.3)
16X (1.2)
EXPOSED
METAL
TYP
8
13
9
11
PKG
8X (1.2)
SOLDER MASK EDGE
TYP
METAL UNDER
SOLDER MASK
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1, 8, 13 & 20: 86%
PADS 11, 12, 21 & 22: 84%
SCALE:15X
4223723/A 05/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资
源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、
验证并测试您的应用;(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更,恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2019 德州仪器半导体技术(上海)有限公司
相关型号:
©2020 ICPDF网 联系我们和版权申明