TXS02326A_技术文档

TXS02326A

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SCES830 –MAY 2012

DUAL-SUPPLY 2:1 SIM CARD MULTIPLEXER/TRANSLATOR

WITH AUTOMATIC DETECTION AND SLOT DEDICATED DUAL LDO

Check for Samples: TXS02326A

1

FEATURES

RGE PACKAGE

(TOP VIEW)

•

Level Translator

VDDIO Range of 1.7-V to 3.3-V

Low-Dropout (LDO) Regulator

–

•

–

50-mA LDO Regulator With Enable

1.8-V or 2.95-V Selectable Output Voltage

2.3-V to 5.5-V Input Voltage Range

24 23 22 21 20 19

1

2

3

4

5

6

18

IRQ

RSTX

SDN

SIMI/O

SIMCLK

SIMRST

NC

SIM1CLK

SIM1I/O

17

16

15

14

13

Exposed

Thermal Pad

Very Low Dropout: 100 mV (Max) at 50 mA

BSI

SIM2CLK

SIM2I/O

•

Control and Communication Through I²C

Interface With Baseband Processor

7

8 9 10 11 12

ESD Protection Exceeds JESD 22

–

2500-V Human-Body Model (A114-B)

6000-V Human-Body Model (A114-B) on

VSIM1, SIM1CLK, SIM1I/O, SIM1RST, VSIM2,

SIM2CLK, SIM2I/O, SIM2RST

Note: The Exposed Thermal Pad must be

connect to Ground.

–

1000-V Charged-Device Model (C101)

•

Package

24-Pin QFN (4 mm x 4 mm)

–

DESCRIPTION/ORDERING INFORMATION

The TXS02326A is a complete dual-supply standby Smart Identity Module (SIM) card solution for interfacing

wireless baseband processors with two individual SIM subscriber cards to store data for mobile handset

applications. It is a custom device which is used to extend a single SIM/UICC interface to support two

SIMs/UICCs.

The device complies with ISO/IEC Smart-Card Interface requirements as well as GSM and 3G mobile standards.

It includes a high-speed level translator capable of supporting Class-B (2.95-V) and Class-C (1.8-V) interfaces;

two low-dropout (LDO) voltage regulators with output voltages that are selectable between 2.95-V Class-B and

1.8-V Class-C interfaces; an integrated "fast-mode" 400 kb/s "slave" I²C control register interface, for

configuration purposes; and a 32-kHz clock input, for internal timing generation. The TXS02326A also includes a

shutdown input and a comparator input that detects battery pack removal to safely power-down the two SIM

cards. The shutdown input and comparator input are equipped with two programmable debounce counter (i.e.

BSI input and SDN input) circuits realized by an 8 bit counter.

The voltage-level translator has two supply voltage pins. VDDIO sets the reference for the baseband interface

and can be operated from 1.7-V to 3.3-V. VSIM1 and VSIM2 are programmed to either 1.8-V or 2.95-V, each

supplied by an independent internal LDO regulator. The integrated LDO accepts input battery voltages from 2.3-

V to 5.5-V and outputs up to 50 mA to the B-side circuitry and external Class-B or Class-C SIM card.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

YJ326A

–40°C to 85°C

QFN – RGE (Pin 1, Quadrant 1) Tape and reel

TXS02326AMRGER

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TXS02326A

SCES830 –MAY 2012

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

VBAT

3-V or 1.8-V

SIM Card

I²C

Control

Logic

SCK

VSIM1

SDA

LDO

V

GND

VPP

I/O

CC

SIM1RST

SIM1CLK

Reset

CLK

NC

SIMRST

SIMCLK

NC

Translator

SIM1I/O

SIMI/O

VDDIO

Baseband

V

CC

3-V or 1.8-V

SIM Card

RSTX

IRQ

VSIM2

LDO

V

GND

VPP

I/O

CC

SIM2RST

SIM2CLK

Reset

CLK

NC

CLK

BSI

OE

NC

Translator

SIM2I/O

GND

TXS02326A

SDN

Figure 1. Interfacing With SIM Card

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SCES830 –MAY 2012

TERMINAL FUNCTIONS

POWER

DOMAIN

NAME

TYPE⁽¹⁾

DESCRIPTION

1

IRQ

RSTX

SDN

I/O

I

VDDIO

VSIM2

VBAT

Interrupt to baseband. This signal is used to set the I2C address.

Active-low reset input from baseband

2

3

I

Power down SIM2; for example, from switch

4

BSI

I

Analog signal from battery. This input accepts input voltages up to 3 V.

5

SIM2CLK

SIM2I/O

SIM2RST

VSIM2

VBAT

O

I/O

O

P

SIM2 clock

6

SIM2 data

7

SIM2 reset

8

1.8 V/2.95 V supply voltage to SIM2

Battery power supply

Ground

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

GND

G

O

I/O

O

VSIM1

SIM1RST

SIM1I/O

SIM1CLK

NC

VSIM1

1.8 V/2.95 V supply voltage to SIM1

SIM1 reset

SIM1 data

SIM1 clock

No connect

SIMRST

SIMCLK

SIMI/O

OE

I

VDDIO

UICC/SIM reset from baseband

UICC/SIM clock

I/O

I

UICC/SIM data

UICC/SIM data direction from baseband

GND

G

P

I

VDDIO

CLK

VDDIO

1.8-V power supply for device operation and I/O buffers toward baseband

32-kHz clock

I²C clock

I²C data

SCK

I

SDA

I/O

(1) G = Ground, I = Input, O = Output, P = Power

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Table 1. Register Overview

REGISTER BITS

COMMAND

BYTE

READ

OR

WRITE

POWER-UP

DEFAULT

REGISTER

B7

B6

B5

B4

B3

B2

B1

B0

(HEX)

Device

hardware

revision

0

1

0

1

0

00h

01h

04h

R

0001 0010

0000 0000

information

Software

revision

information

0

Battery

Removal Battery

Interrupt

Status

SDN

Interrupt

Status

SIM2 Interface

Status

SIM1 Interface

Status

SDN

Status

Register

Status

SIM2

SIM1

LDO

Enable/

Disable

SIM

SIM1

Voltage

Select

SIM2 Interface

Status

LDO

SIM1 Interface

Status

Interface

Control

Register

Voltage

Enable/

Select

08h

0Ah

R/W

0000 0000

0000 0100

Disable

BSI Input

Debounce

Counter

BSI Debounce Counter Value

SDN Input

Debounce

Counter

SDN Debounce Counter Value

Reserved / Not Supported

Clock Control (Reserved)

0Bh

0Ch

0Dh

R/W

0000 0100

0000 0000

Reserved

Clock

Source

Select

External

Clock

Control

Battery

Removal

Interrupt Direction Control

Enable/

Disable

SDN

Detection

SDN

Level

SDN

BSI

Level

OE

Device

Control

Register

Interrupt Detection

0Eh

10h-14h

15h

R/W

0000 0000

xxxx xxxx

0000 0000

Behavior Detection Enable/ Behavior Detection

control Select Disable Control Select

Control

Select

Device-

specific

testing

SDN

Pull-

down

Enable/

Disable

SDN

Pull-up

Enable/

Disable

General

purpose

Reserved

4

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Table 2. Device Hardware Revision Register (00h)

Device HW Driver

Bits(s)

Type (R/W)

Description

Register

This register contains the manufacturer and device ID⁽¹⁾(value to be

specified by the manufacturer)

HW identification

7:0

R

(1) The manufacturer ID part of this data shall remain unchanged when the HW revision ID is updated. The manufacturer ID shall uniquely

identify the manufacturer. The manufacturer ID is encoded on the MSB nibble.

Table 3. Device Software Revision Register (01h)

Device SW Driver

Bits(s)

Type (R/W)

Description

Register

This register contains information about the SW driver required for this

device. This information shall only be updated when changes to the

device requires SW modifications. Initial register value is 00h

SW Driver Version

7:0

R

Table 4. Status Register (04h)

Status Register

Bits(s)

Type (R/W)

Description

SDN signal state captured at the input pin

'0' SDN signal at GND

SDN Status

0

R

'1' SDN signal at VDDIO level

SDN interrupt status

SDN Interrupt

1

2

3

R

'0' No interrupt

'1' Interrupt occurred, (the read operation will automatically clear this bit)

'0' Battery present

'1' Battery not present, i.e. debounce counter expired

Battery Status

Battery removal interrupt status

'0' No interrupt

Battery Removal Interrupt

'1' Interrupt occurred, (the read operation will automatically clear this bit)

Status of SIM1 interface

'00' Powered down with pull-downs activated

'01' Isolated with pull-downs deactivated

'10' Powered with pull downs activated

'11' Active with pull downs deactivated

SIM1 Interface Status [1:0]

SIM2 Interface Status [1:0]

5:4⁽¹⁾

R

Status of SIM2 interface

'00' Powered down with pull-downs activated

'01' Isolated with pull-downs deactivated

'10' Powered with pull downs activated

'11' Active with pull downs deactivated

7:6⁽¹⁾

(1) The content of bits 5:4 and 7:6 reflects the value written to the state bits in the SIM Interface control register 3:2 and 7:6 respectively

and the setting of the regulator bits in the SIM interface control register 0 and 4 respectively.

Table 5. State and Status Bit Mapping

SIM Interface Control Register

(08h)

SIM1 interface state bits 3:2

SIM2 interface state bits 7:6

SIM Interface Control Register

(08h)

SIM1 regulator control bit 0

SIM2 regulator control bit 4

SIM Status Register (04h)

SIM1 status bits 5:4

SIM2 status bits 7:6

Comment

'00' Powered down state with pull-

downs activated

'0' Regulator is off, regulator output is '00' Powered down with pulldowns

pulled down activated

'00' Powered down state with pull-

downs activated

'1' Regulator is powered on, regulator '10' Powered with totem pole pull-

output pull-down is released downs

The interface can

only be in isolated

state when the

'01' Isolated state with pulldowns

deactivated

'0' Regulator is off, regulator output is '00' Powered down with pulldowns

pulled down activated

interface is powered

'01' Isolated state with pulldowns

deactivated

'1' Regulator is powered on, regulator '01' Isolated with pull-downs

output pull-down is released deactivated

This combination

'0' Regulator is off, regulator output is '00' Powered down with pulldowns

shall not be used. If

used the status bit

coding is as specified

'10' Not allowed

pulled down

activated

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Table 5. State and Status Bit Mapping (continued)

SIM Interface Control Register

(08h)

SIM1 interface state bits 3:2

SIM2 interface state bits 7:6

SIM Interface Control Register

SIM Status Register (04h)

(08h)

SIM1 status bits 5:4

Comment

SIM1 regulator control bit 0

SIM2 status bits 7:6

SIM2 regulator control bit 4

This combination

'1' Regulator is powered on, regulator '10' Powered with pull downs

shall not be used. If

used the status bit

coding is as specified

'10' Not allowed

output pull-down is released

activated

The interface can

only be active if it is

powered

'11' Active state with pull-downs

deactivated

'0' Regulator is off, regulator output is '00' Powered down with pulldowns

pulled down activated

'11' Active state with pull-downs

deactivated

'1' Regulator is powered on, regulator '11' Active with pull-downs

output pull-down is released deactivated

Table 6. SIM Interface Control Register (08h)⁽¹⁾⁽²⁾

Status

Register

Type

(R/W)

Bit(s)

Description

SIM1

Regulator

Control

'0' Regulator is off, regulator output is pulled down

'1' Regulator is powered on, regulator output pull-down is released

0

R/W

SIM1

Regulator

Voltage

Selection

'0' 1.8 V

'1' 2.95 V

1

Status of SIM1 interface

'00' state is dependent on bit 0:

If bit 0 = '0', then powered down state with pull-downs activated

If bit 0 = '1', then isolated state with pull-downs deactivated

Pull down resistor active

SIM1

Interface

State [1:0]

Totem pole pull down

3:2

R/W

Output latched at previous state driven

by totem pole output

'01' Isolated state with pull-downs deactivated

'10' Not allowed

Not allowed

'11' Active state with pull-downs deactivated

Outputs follow the inputs

SIM2

Regulator

Control

'0' Regulator is off, regulator output is pulled down

'1' Regulator is powered on, regulator output pull-down is released

4

5

R/W

SIM2

Regulator

Voltage

Selection

'0' 1.8 V

'1' 2.95 V

Status of SIM2 interface

'00' State is dependent on bit 4:

If bit 4 = '0', then powered down state with pull-downs activated

If bit 4 = '1', then isolated state with pull-downs deactivated

Pull down resistor active

Totem pole pull down

SIM2

Interface

State [1:0]

7:6

R/W

Output latched at previous state driven

by totem pole output

'01' Isolated state with pull-downs deactivated

'10' Not allowed

Not allowed

'11' Active state with pull-downs deactivated

Outputs follow the inputs

(1) Reset value: 00h

(2) The state '10', on bits 3:2 and 7:6, is not prevented by HW but shall never be set by SW. State '10' means that the interface is powered

with the pull-downs active, this state correspond to state '00' with the regulator being switched on. Setting the state to '10' does not have

any impact on the corresponding regulator bit setting. The regulator control bits do not impact the state bits in this register. The regulator

control bits however do impact the status bits in the status register.

6

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Table 7. Battery Presence Detection Debounce Counter (0Ah)⁽¹⁾⁽²⁾

BSI Debounce Counter

Bits(s)

Type (R/W)

Description

Debounce Counter Value

[7:0]

This register contains the BSI input debounce counter value. The value

00h means that the counter is not used, i.e. no debounce.

7:0

R/W

(1) Reset value: 04h

(2) Updating the register causes the counter to restart with the new value if the counter is counting when the register is updated. The new

value shall take affect no later than one clock cycle (32 KHz) after the register has been updated.

Table 8. SDN Input Debounce Counter (0Bh)⁽¹⁾⁽²⁾

SDN Debounce Counter

Bits(s)

Type (R/W)

Description

Debounce Counter Value

[7:0]

This register contains the SDN input debounce counter value. The value

00h means that the counter is not used, i.e. no debounce.

7:0

R/W

(1) Reset value: 04h

(2) Updating the register causes the counter to restart with the new value if the counter is counting when the register is updated. The new

value shall take affect no later than one clock cycle (32 KHz) after the register has been updated.

Table 9. External Clock Control (0Dh)⁽¹⁾

Clock Control Register

Bits(s)

Type (R/W)

Description

Clock Control

6:0

R/W

Reserved

'0' Internal clock source used

'1' External clock source CLK (supplied on pin 22 used)

Clock Source Select

(1) Reset value: 00h

7

R/W

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Table 10. Device Control Register (0Eh)⁽¹⁾

Clock Control Register

Bits(s)

Type (R/W)

Description

‘0’ OE is not used to control the data direction on the selected SIM I/O

and the base band I/O

OE Control

0

R/W

‘1’ OE controls the data direction, see below

‘0’ OE input = ‘0’ data direction Base band -> SIM

OE input = ‘1’ data direction SIM -> base band

‘1’ OE input = ‘0’ data direction SIM -> base band

OE input = ‘1’ data direction Base band -> SIM

OE Direction Control

1

R/W

‘0’ Battery removal interrupt disabled

Battery Removal Interrupt

BSI Level Detection

2

3

R/W

‘1’ Battery removal detected causes interrupt on IRQ (interrupt sets b3 in

the status register)

BSI detection level

‘0’ 1.2V

‘1’ 1.65V

BSI detection behavior

‘0’ Battery not present causes automatic power down of both SIM

interfaces

‘1’ Battery not present doesn’t cause automatic power down

BSI Detection Control

4

5

R/W

‘0’ SDN detection interrupt disabled

‘1’ SDN detected causes interrupt on IRQ (interrupt sets b1 in the status

register)

SDN Detection Interrupt

SDN input active level

‘0’ SDN is active low

SDN Detection Level

6

7

R/W

i.e. automatic shutdown occurs when debounced SDN is low.

‘1’ SDN is active high

i.e. automatic shutdown occurs when debounced SDN is high

Disable automatic power down upon SDN detection

‘0’ SDN detection causes automatic power down of SIM2 interface

‘1’ SDN detection doesn’t cause automatic power down of SIM2 interface

SDN Detection Control

(1) Reset value: 00h

Table 11. General Purpose Register (15h)⁽¹⁾

Function

Bit(s)

Type (R/W)

Description

'0' SDN input pull-up enabled

'1' SDN input pull-up disabled

SDN pull-up control

0

R/W

'0' SDN pull-down disabled

'1' SDN pull-down enabled

SDN pull-down control

RFU

1

R/W

7:2

(1) The RFU bits shall allow for the write operation to complete but shall read as '0'. The SW should write '0' into these locations, reset

value.

8

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BASIC DEVICE OPERATION

The TXS02326A is controlled through a standard I²C interface reference to VDDIO. It is connected between the

two SIM card slots and the SIM/UICC interface of the baseband. The device uses VBAT and VDDI/O as supply

voltages. The supply voltage for each SIM card is generated by an on-chip low drop out regulator. The interface

between the baseband and the TXS02326A is reference to VDDIO while the interface between the TXS02326A

and the SIM card is referenced to the LDO output of either VSIM1 or VSIM2 depending on which slot is being

selected. The VDDIO on the baseband side normally does not exceed 1.8V, thus voltage level shifting is needed

to support a 3V SIM/UICC interface (Class B).

The TXS02326A has two basic states, the reset and operation state. The baseband utilizes information in the

status registers to determine how to manipulate the control registers to properly switch between two SIM cards.

These fundamental sequences are outlined below and are to help the user to successfully incorporate this device

into the system.

DEVICE ADDRESS

The address of the device is shown below:

Slave Address

IRQ

0

1

0

R/W

Address Reference

IRQ@ Reset

R/W

0 (W)

1 (R)

0 (W)

1 (R)

Slave Address

0

1

120 (decimal), 78(h)

121 (decimal), 79(h)

122 (decimal), 7A(h)

123 (decimal), 7B(h)

RESET STATE

In the reset state the device settings are brought back to their default values and any SIM card that has been

active is deactivated. After reset, neither of the UICC/SIM interfaces is selected. The active pull-downs at the

UICC/SIM interface are automatically activated. To ensure the system powers up in an operational state, device

uses an internal 32 KHz clock for internal timing generation. After power up, the system has the option to

continue to utilize the internal clock or select an external clock source. This clock source is selectable by the

Clock Source Select I²C register bit.

•

Power up the TXS02326A by asserting VBAT to enter the operation state

I²C Interface becomes active with the VDD_I/O supply

RESET summary:

•

Any pending interrupts are cleared

I²C registers are in the default state

BSI and SDN counter value in the registers are set to four clock cycles or “0000 0100”

Both on chip regulators are set to 1.8V and disabled

All SIM1 and SIM2 signals are pulled to GND

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SETTING UP THE SIM INTERFACE

The TXS02326A supports both Class C (1.8V) or Class B (2.95V) SIM cards. In order to support these cards

types, the interface on the SIM side needs to be properly setup. After power up, the system should default to

SIM1 card. The following sequence outlines a rudimentary sequence of preparing the SIM1 card interface:

•

Configure the SIM1 regulator to 1.8V by asserting B1 = 0 in the SIM Interface Control Register (08h). The

system by default should start in 1.8V mode.

•

Configure the OE signal by asserting B0 = 0 in the Device Control Register (0Eh). The default value

essentially disables the OE pin and the device is configured as an auto direction translator.

•

The baseband SIM interface is set to a LOW state.

Disable the SIM1 interface by asserting B2 = 0 and B3 = 0 in the SIM Interface Control Register.

Disable the SIM2 interface by asserting B6 = 0 and B7 = 0 in the SIM Interface Control Register.

VSIM1 voltage regulator should now be activated by asserting B0 = 1 in the SIM Interface Control Register.

Enable the SIM1 interface by asserting B2 = 1 and B3 = 1 in the SIM Interface Control Register.

The SIM1 interface (VSIM1, SIM1CLK, SIM1I/O) is now active. The TXS02326A relies on the baseband to

perform the power up sequencing of the SIM card. If there is lack of communication between the baseband

and the SIM card, the SIM1 interface must be powered-down and then powered up again through the

regulator by configuring it to 2.95V by asserting B1 = 1 in the SIM Interface Control Register.

SWITCHING BETWEEN SIM CARDS

The following sequence outlines a rudimentary sequence of switching between the SIM1 card and SIM2 card:

•

Put the SIM1 card interface into “clock stop” mode then assert B2 = 1 and B3 = 0 in the SIM Interface Control

Register (08h). This will latch the state of the SIM1 interface (SIM1CLK, SIM1I/O, SIM1RST).

•

There can be two scenarios when switching to SIM2 card:

–

SIM2 may be in the power off mode, B6 = 0 and B7 = 0 in the Status Register (04h). If SIM2 is in power

off mode, the SIM/UICC interface will need to be set to the power off state. In this case the baseband will

most likely need to go through a power up sequence iteration

–

SIM2 may already be in the “clock stop” mode, B6 = 1 and B7 = 0 in the Status Register (04h). If SIM2 is

in “clock stop” mode, the interface between the baseband and the device is set to the clock stop mode

levels that correspond to the SIM2 card interface.

•

After determining whether the SIM2 card is either in power off mode or clock stop mode, the SIM2 card

interface is then activated by asserting B6 = 1 and B7 = 1 in the SIM Interface Control Register (08h) and the

negotiation between the baseband and card can continue.

Switching from SIM2 to SIM1 done in the same manner.

AUTOMATIC SHUTDOWN

Both SIM card interfaces can be configured to automatically shut down upon disconnecting the battery. The

shutdown threshold BSI_Thresholdis configured in B3 of the Device Control Register (0Eh). Two threshold levels are

available for this configuration. When the BSI input level exceeds the BSI_Thresholdlevel that caused this power-

down, both SIM card interfaces will automatically be shut down. If the battery removal interrupt is enabled

through B2 of the Device Control Register, then an interrupt will be issued to the baseband on IRQ. This case

may happen if the user decides to remove the battery.

There are two scenarios for shutting down each SIM: SIMx is “active”, or in “clock stop” mode. In clock stop

mode, when the debounce timer expires, the SIMx signals all go low immediately, then the regulator is disabled

one 32KHz cycle later. If SIMx is active, the signals go low and the regulator is disabled in a particular sequence

to be described in the next section.

The SIM2 interface can also be configured to automatically shut down via the SDN pin.

10

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BSI / SDN DEBOUNCE AND AUTOMATIC SHUTDOWN SEQUENCE TIMING

There are two debounce counters: one each for the BSI and SDN inputs. For each counter, when the device is

reset or the related input is “false”, the counter is loaded with the value in the associated Debounce Counter

register and the debounced signal (i.e. BSI_DEB or SDN_DEB) is subsequently set to a “false” state. When the

related input becomes “true”, the counter begins counting down on subsequent CLK rising-edges. (CLK is either

the internal or external 32 kHz clock as selected by Clock Source Select)

If the input changes state during the count, the counter is again loaded with the register value. The debounce

counter propagates the input signal to the output when the counter expires.

For BSI and BSI_DEB, the “true” state is high. For SDN and SDN_DEB, the “true” state is the state stored in the

SDN Detection Level register. Once either count reaches zero, the debounced signal switches to the “true” state

on the next CLK rising edge. Writing a new value to the SDN detection level register such that SDN is now in the

TRUE state will force the debounce counter to zero, but will not generate an interrupt nor initiate a shutdown

sequence.

If BSI_DEB goes high and Battery Removal Interrupt (bit 2 of the Device Control Register) is 1, an interrupt is

generated and appears on IRQ. Also, if BSI_DEB goes high and BSI Detection Control (bit 4 of the Device

Control Register) is 0, the Automatic Shutdown sequence begins for both SIM’s.

If SDN_DEB goes “true” and SDN Detection Interrupt (bit 5 of the Device Control Register) is 1, an interrupt is

generated and appears on IRQ. Also, if SDN_DEB goes “true” and SDN Detection Control (bit 7 of the Device

Control Register) is 0, the Automatic Shutdown sequence begins for SIM2 only, leaving SIM1 unaffected.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

CLK

DEB CNT

BSI

4

3

2

4

3

2

1

4

0

BSI_DEB

IRQ

SIMCLK

SIM1 RST

SIM1 CLK

SIM1 I/O

SIM1 VCC

SIM2 RST

SIM2 CLK

SIM2 I/O

SIM2 VCC

Active Data

Latched RST

Latched Clock

Latched Data

Figure 2. BSI Debounce Timing – SIM1 Active and SIM2 Isolated

Notes:

BSI debounce count value set to 4

SIM1 Active, SIM2 powered but Isolated

BSI Detection Control set to 0

Battery Removal Interrupt set to 1

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Once BSI is high for four cycles, BSI_DEB goes high causing automatic shutdown sequence on both SIMs.

Since SIM1 is active with SIMCLK running, it follows the staged shutdown sequence. Since SIM2 is powered up

but inactive, it follows the instant shutdown sequence.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

CLK

DEB CNT

BSI

4

3

2

4

3

2

1

4

0

BSI_DEB

IRQ

SIMCLK

SIM1 RST

SIM1 CLK

SIM1 I/O

SIM1 VCC

SIM2 RST

SIM2 CLK

SIM2 I/O

SIM2 VCC

Clock stopped

Active Data

Latched RST

Latched Clock

Latched Data

Figure 3. BSI Debounce Timing – SIM1 Clock Stop and SIM2 Isolated

Notes:

BSI debounce counter set to 4

SIM1 Active in Clock Stop Mode

SIM2 powered but Isolated

BSI Detection Control set to 0

Battery Removal Interrupt set to 1

Once BSI is high for four cycles, BSI_DEB goes high causing automatic shutdown sequence on both SIMs.

Since SIM1 is active with SIMCLK stopped, it follows the instant shutdown sequence. Since SIM2 is powered up

but inactive, it follows the instant shutdown sequence.

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

CLK

DEB CNT

BSI

4

3

2

4

3

2

1

4

0

BSI_DEB

IRQ

SIMCLK

SIM1 RST

SIM1 CLK

SIM1 I/O

SIM1 VCC

SIM2 RST

SIM2 CLK

SIM2 I/O

SIM2 VCC

Latched RST

Latched Clock

Latched Data

Active Data

Figure 4. BSI Debounce Timing – SIM1 Isolated, SIM2 Active

Notes:

BSI debounce counter set to 4

SIM2 Active

SIM1 powered but Isolated

BSI Detection Control set to 0

Battery Removal Interrupt set to 1

Once BSI is high for four cycles, BSI_DEB goes high causing automatic shutdown sequence on both SIMs.

Since SIM2 is active with SIMCLK running, it follows the staged shutdown sequence. Since SIM1 is powered up

but inactive, it follows the instant shutdown sequence.

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

CLK

4

3

2

1

7

6

5

4

3

2

1

4

DEB CNT

Wt. 0Ah

BSI

0

BSI_DEB

IRQ

SIMCLK

SIM1 RST

SIM1 CLK

SIM1 I/O

SIM1 VCC

SIM2 RST

SIM2 CLK

SIM2 I/O

SIM2 VCC

Active Data

Latched RST

Latched Clock

Latched Data

Figure 5. BSI Debounce Timing – Debounce Count Value Write During Debounce

Notes:

BSI debounce count value set to 4, but written to 7 during debounce

SIM1 Active

SIM2 powered but Isolated

BSI Detection Control set to 0

Battery Removal Interrupt set to

BSI_DEB goes high causing automatic shutdown sequence on both SIM’s. Since SIM1 follows the staged

shutdown sequence. SIM2 follows the instant shutdown sequence. BSI returning low does not interrupt shutdown

sequence.

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

CLK

DEB CNT

SDN

4

3

2

4

3

2

1

4

0

SDN_DEB

IRQ

SIMCLK

SIM1 RST

SIM1 CLK

SIM1 I/O

SIM1 VCC

SIM2 RST

SIM2 CLK

SIM2 I/O

SIM2 VCC

Active Data

Latched RST

Latched Clock

Latched Data

Figure 6. SDN Debounce Timing – SDN Detection Level High

Notes:

SDN debounce count value set to 4

SIM1 Active

SIM2 powered but Isolated

SDN Detection Control set to 0

SDN Detection level set to 1

SDN Detection Interrupt set to 1

Once SDN is high for four cycles, SDN_DEB goes high causing automatic shutdown sequence on SIM2. SIM1 is

unaffected. Since SIM2 is powered up but inactive, it follows the instant shutdown sequence.

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

CLK

4

3

2

4

3

2

1

4

DEB CNT

SDN

0

SDN_DEB

IRQ

SIMCLK

SIM1 RST

SIM1 CLK

SIM1 I/O

SIM1 VCC

SIM2 RST

SIM2 CLK

SIM2 I/O

SIM2 VCC

Active Data

Latched RST

Latched Clock

Latched Data

Figure 7. SDN Debounce Timing – SDN Detection Level Low

Notes:

SDN debounce count value set to 4

SIM1 Active

SIM2 powered but Isolated

SDN Detection Control set to 0

SDN Detection level set to 0

SDN Detection Interrupt set to 1

Once SDN is low for four cycles, SDN_DEB goes low causing automatic shutdown sequence on SIM2. SIM1 is

unaffected. Since SIM2 is powered up but inactive, it follows the instant shutdown sequence.

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

CLK

DEB CNT

SDN

4

3

2

4

3

2

1

4

0

SDN_DEB

IRQ

SIMCLK

SIM1 RST

SIM1 CLK

SIM1 I/O

SIM1 VCC

SIM2 RST

SIM2 CLK

SIM2 I/O

SIM2 VCC

Latched RST

Latched Clock

Latched Data

Active Data

Figure 8. SDN Debounce Timing – SIM1 Isolated and SIM 2 Active

Notes:

SDN debounce count value set to 4

SIM1 powered but Isolated

SIM2 Active

SDN Detection Control set to 0

SDN Detection level set to 1

SDN Detection Interrupt set to 1

SDN_DEB goes high causing automatic shutdown sequence on SIM2. Since SIM2 is active with SIMCLK

running, it follows the staged shutdown sequence, SIM1 is unaffected.

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Level Translator⁽¹⁾

MIN

MAX UNIT

VDDI

Supply voltage range

O

–0.3

4.0

V

VDDIO-port

VSIMx-port

Control inputs

VDDIO-port

VSIMx-port

VDDIO-port

VSIMx-port

V_I< 0

–0.5

4.6

V_I

Input voltage range

V

4.6

V_O

Voltage range applied to any output in the high-impedance or power-off state

Voltage range applied to any output in the high or low state

V

4.6

I_IK

I_OK

I_O

Input clamp current

–50

±50

±100

150

2.5

mA

°C

Output clamp current

V_O< 0

Continuous output current

Continuous current through V_CCAor GND

Storage temperature range

Human-Body Model (HBM)

T_stg

–65

All pins

kV

Baseband Side I/O:

SIM1CLK, SIM1I/O,

SIM1RST, SIM2CLK,

SIM2I/O, SIM2RST

Human-Body Model (HBM-

HV)

ESD rating

6

Kv

V

Charge-Device Model (CDM)

1000

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

LDO⁽¹⁾

MIN

–0.3

–55

MAX UNIT

V_IN

Input voltage range

6

V

V_OUTOutput voltage range

6

T_J

Junction temperature range

Storage temperature range

150

°C

T_stg

LDO Output:

VSIM1, VSIM2

Human-Body Model (HBM-HV)

Charged-Device Model (CDM)

6

kV

V

ESD rating

1000

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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THERMAL IMPEDANCE RATINGS

UNIT

θ_JA

Package thermal impedance⁽¹⁾

RGE package

45

°C/W

(1) The package thermal impedance is calculated in accordance with JESD 51-7.

RECOMMENDED OPERATING CONDITIONS⁽¹⁾

Level Translator

Description

MIN

MAX

3.3

UNIT

V

VDDIO

V_IH

Supply voltage

1.7

High-level input voltage

Applies to pins: RESET, SDN,

SCL, SDA, IRQ, OE, 32kHz,

SIM_RST, SIM_CLK, SIM_I/O

VDDIO × 0.7

0

1.9

V

V_IL

Low-level input voltage

VDDIO × 0.3

V

Δt/Δv

Input transition rise or fall rate

Operating free-air temperature

5

ns/V

°C

T_A

–40

85

(1) All unused data inputs of the device must be held at V_CCIor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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ELECTRICAL CHARACTERISTICS

Level Translator

over recommended operating free-air temperature range (unless otherwise noted)

TYP⁽

PARAMETER

TEST CONDITIONS

VDDIO

VSIM1

VSIM2

MIN

MAX

UNIT

1)

SIM1_RST

SIM1_CLK

VSIM1 × 0.8

I_OH= –100 µA

Push-Pull

I_OH= –10 µA

Open-Drain

SIM1_I/O

VSIM1 × 0.8

I_OH= –100 µA

Push-Pull

SIM2_RST

SIM2_CLK

VSIM2 × 0.8

I_OH= –100 µA

Push-Pull

1.8 V / 2.95 1.8 V / 2.95

1.7 V to

3.3 V

V

V_OH

V

(Supplied

by LDO)

(Supplied by

LDO)

I_OH= –10 µA

Open-Drain

SIM2_I/O

SIM_I/O

VSIM2 × 0.8

VDDIO × 0.8

I_OH= –100 µA

Push-Pull

I_OH= –10 µA

Open-Drain

I_OH= –100 µA

Push-Pull

I_OL= 1 mA

Push-Pull

SIM1_RST

SIM1_CLK

VSIM1 × 0.2

I_OL= 1 mA

Push-Pull

I_OL= 1 mA

Open-Drain

SIM1_I/O

0.3

I_OL= 1 mA

Push-Pull

I_OL= 1 mA

Push-Pull

1.8 V / 2.95 1.8 V / 2.95

SIM2_RST

SIM2_CLK

VSIM2 × 0.2

1.7 V to

3.3 V

V

V_OL

V

(Supplied

by LDO)

(Supplied by

LDO)

I_OL= 1 mA

Push-Pull

I_OL= 1 mA

Open-Drain

SIM2_I/O

SIM_I/O

0.3

I_OL= 1 mA

Push-Pull

I_OL= 1 mA

Open-Drain

I_OL= 1 mA

Push-Pull

1.8 V / 2.95 1.8 V / 2.95

Control

inputs

1.7 V to

3.3 V

V

I_I

V_I= OE

±1

±5

µA

(Supplied

by LDO)

(Supplied by

LDO)

1.8 V / 2.95 1.8 V / 2.95

V_I= V_CCI

I_O= 0

1.7 V to

3.3 V

V

I_{CC I/O}

(Supplied

by LDO)

(Supplied by

LDO)

SIM_I/O

port

7

4

C_io

C_i

pF

SIMx port

Control

inputs

V_I= VDDIO or GND

3

Clock input

(1) All typical values are at T_A= 25°C.

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ELECTRICAL CHARACTERISTICS

LDO (Control Input Logic = High)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2.3

TYP⁽¹⁾

MAX

5.5

UNIT

VBAT

V_OUT

V_DO

Input voltage

V

Class-B Mode

Class-C Mode

I_OUT= 50 mA

I_OUT= 0 mA

I_OUT= 50 mA

R_L= 0 Ω

2.85

1.7

2.95

1.8

3.05

1.9

Output voltage

V

Dropout voltage

Ground-pin current

100

35

mV

µA

I_GND

150

400

I_OUT(SC)

C_OUT

Short-circuit current

Output Capacitor

mA

µF

1

VBAT = 3.25 V,

VSIMx = 1.8 V or 3 V,

C_OUT= 1 µF, I_OUT= 50 mA

f = 1 kHz

50

40

PSRR

Power-supply rejection ratio

dB

f = 10 kHz

VSIMx = 1.8 V or 3 V, I_OUT= 10 mA,

C_OUT= 1 µF

T_STR

T_J

Start-up time

50

85

µS

°C

Operating junction

temperature

–40

(1) All typical values are at T_A= 25°C.

GENERAL ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Current Consumption in RESET

Mode

VBAT = 2.3 to 4.8V, VDDIO = 1.8 V

or 0 V

1

I_SHUTDOWN

µA

BSI detection level “1”

BSI detection level “0”

1.6

1.1

1.7

1.3

BSI_ThresholdComparator Threshold

V

Hyst

Internal hysteresis of comparator

±50

32

mV

KHz

kΩ

CLK_Int

R_SIMPU

Internal System Clock

SIM I/O pull-up

–20%

18

+20%

22.6

9

20

Class B

Class C

6

7.5

4.5

R_SIMxPU

R_SIMPD

SIMx I/O pull-up

kΩ

3.8

5.2

Active pull-downs are connected to

the VSIM1/2 regulator output to the

SIM1/2 CLK, SIM1/2 RST, SIM1/2

I/O when the respective regulator is

disabled

SIMx I/O pull-down

2

kΩ

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SWITCHING CHARACTERISTICS

VSIMx = 1.8 V or 2.95 V Supplied by Internal LDO, VBAT = 2.3V to 5.5V

over recommended operating free-air temperature range (unless otherwise noted)

VDDIO = 1.7 V to 3.3 V

TEST

CONDITIONS

PARAMETER

UNIT

MIN

MAX

320

8.6

4.3

9.3

16

6.5

4.5

9.5

245

10

18

8

SIMx_I/O

Open Drain

ns

MHz

ns

Push Pull

Open Drain

Push Pull

Open Drain

Push Pull

Open Drain

Push Pull

Open Drain

Push Pull

Open Drain

Push Pull

Open Drain

Push Pull

Open Drain

Push Pull

t_rA

Baseband side to SIM side

SIMx_RST

SIMx_CLK

SIMx_I/O

t_fA

Baseband side to SIM side

SIMx_RST

SIMx_CLK

SIM_I/O

t_rB

SIM side to Baseband side

SIM_I/O

t_fB

SIM side to Baseband side

SIM_I/O

f_max

SIMx_CLK

5

SIM_CLK to SIMx_CLK

SIM_RST to SIMx_RST

SIM_IO to SIMx_IO

SIMx_IO to SIMIO

SIM_CLK to SIMx_CLK

SIM_RST to SIMx_RST

SIM_IO to SIMx_IO

SIMx_IO to SIM_IO

8.9

8

18

10

10.5

10

7

t_PLH

23

8

t_PHL

23

10

22

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OPERATING CHARACTERISTICS

T_A= 25°C, V_SIMx= 1.8 V for Class C, V_SIMx= 2.95 V for Class B

TEST

CONDITIONS

PARAMETER

TYP

UNIT

Class B

Class C

C_L= 0,

f = 5 MHz,

t_r= t_f= 1 ns

11

(1)

C_pd

pF

9.5

(1) Power dissipation capacitance per transceiver

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APPLICATION INFORMATION

The LDO’s included on the TXS02326A achieve ultra-wide bandwidth and high loop gain, resulting in extremely

high PSRR at very low headroom (V_BAT– V_SIM1/2). The TXS02326A provides fixed regulation at 1.8V or 2.95V.

Low noise, enable through I²C control, and low ground pin current make it ideal for portable applications. The

device offers sub-bandgap output voltages, current limit, thermal protection, and is fully specified from –40°C to

+85°C.

VSIM1

VDDIO

VBAT

TXS02326A

1μF

VSIM2

GND

1μF

0.1μF

Figure 9. Typical Application circuit for TXS02326A

Input and Output Capacitor Requirements

It is good analog design practice to connect a 1.0 μF low equivalent series resistance (ESR) capacitor across the

input supply (VBAT) near the regulator. Also, a 0.1uF is required for the logic core supply (VDDIO).

This capacitor will counteract reactive input sources and improve transient response, noise rejection, and ripple

rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if

the device is located several inches from the power source. The LDO’s are designed to be stable with standard

ceramic capacitors of values 1.0 μF or larger. X5R- and X7R-type capacitors are best because they have

minimal variation in value and ESR over temperature. Maximum ESR should be < 1.0 Ω.

Output Noise

In most LDO’s, the bandgap is the dominant noise source. To improve ac performance such as PSRR, output

noise, and transient response, it is recommended that the board be designed with separate ground planes for V_IN

and V_OUT, with each ground plane connected only at the GND pin of the device. In addition, the ground

connection for the bypass capacitor should connect directly to the GND pin of the device.

Internal Current Limit

The TXS02326A internal current limit helps protect the regulator during fault conditions. During current limit, the

output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the

device should not be operated in a current limit state for extended periods of time.

The PMOS pass element in the TXS02326A has a built-in body diode that conducts current when the voltage at

V_SIM1/2exceeds the voltage at V_BAT. This current is not limited, so if extended reverse voltage operation is

anticipated, external limiting may be appropriate.

Dropout Voltage

The TXS02326A uses a PMOS pass transistor to achieve low dropout. When (V_BAT– V_SIM1/2) is less than the

dropout voltage (V_DO), the PMOS pass device is in its linear region of operation and the input-to-output

resistance is the R_DS(ON)of the PMOS pass element. V_DOwill approximately scale with output current because

the PMOS device behaves like a resistor in dropout.

Startup

The TXS02326A uses a quick-start circuit which allows the combination of very low output noise and fast start-up

times. Note that for fastest startup, V_BATTshould be applied first, and then enabled by asserting the I²C register.

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Transient Response

As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but

increases duration of the transient response.

Minimum Load

The TXS02326A is stable and well-behaved with no output load. Traditional PMOS LDO regulators suffer from

lower loop gain at very light output loads. The TXS02326A employs an innovative low-current mode circuit to

increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation

performance down to zero output current.

THERMAL INFORMATION

Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing

the device to cool. When the junction temperature cools to approximately +140°C the output circuitry is again

enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection

circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage

because of overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate

heat sink. For reliable operation, junction temperature should be limited to +85°C maximum. To estimate the

margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal

protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should

trigger at least +35°C above the maximum expected ambient condition of your particular application. This

configuration produces a worst-case junction temperature of +85°C at the highest expected ambient temperature

and worst-case load.

The internal protection circuitry of the TXS02326A has been designed to protect against overload conditions. It

was not intended to replace proper heat sinking. Continuously running the TXS02326A into thermal shutdown will

degrade device reliability.

TYPICAL CHARACTERISTICS

110

100

90

80

70

60

50

40

30

20

10

0

-90

-80

-70

-60

-50

-40

-30

-20

1.8 V Vsim

85°C Vsim

2.95 V Vsim

-40°C Vsim

25°C Vsim

-10

0

100

1000

10000

100000

1000000

0

5

10 15 20 25 30 35 40 45 50

- Output Current - mA

f - Frequency - Hz

I

OUT

Figure 10. PSRR

Figure 11. Dropout Voltage vs Output Current

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TYPICAL CHARACTERISTICS (continued)

1

0.8

0.6

0.4

0.2

0

I

= 50 mA

O

-0.2

-0.4

-100 mA, Vsim

-0.6

-40°C Vsim

-0.2

-0.4

-0.6

-0.8

-1

85°C Vsim

-0.8

-1

-1.2

-1.4

-50 mA, Vsim

-1.4

-1.6

25°C Vsim

-1.6

-1.8

-2

-2.2

-2.4

-1.8

-2

0

5

10 15 20 25 30 35 40 45 50

- Output Current - mA

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80

- Temperature - °C

I

OUT

T

A

Figure 12. Output Voltage vs Temperature, Class-B/C

Figure 13. Load Regulation, Iout = 50 mA, Class-C

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

I = 50 mA

O

-40°C Vsim

-0.2

-0.4

-0.6

-40°C Vsim

25°C Vsim

-0.8

-1.2

-1.4

-1.6

-1.8

-2

85°C Vsim

-1

-1.2

85°C Vsim

-1.4

-1.6

I

= 50 mA

-1.8

-2

-2.2

-2.4

O

0

5

10 15 20 25 30 35 40 45 50

- Output Current - mA

2.7

3.1

3.5

3.9

V

4.3

- V

4.7

5.1

5.5

I

BAT

OUT

Figure 14. Load Regulation, Iout = 50 mA, Class-B

Figure 15. Line Regulation, Iout = 50 mA, Class-C

26

Submit Documentation Feedback

Product Folder Link(s): TXS02326A

TXS02326A

www.ti.com

SCES830 –MAY 2012

TYPICAL CHARACTERISTICS (continued)

330

0

-0.2

-0.4

-0.6

-0.8

-1

I

= 50 mA

O

300

-40°C Vsim

25°C Vsim

270

240

210

180

150

120

90

-40°C Vsim

25°C Vsim

85°C Vsim

-1.2

-1.4

-1.6

-1.8

-2

60

30

-2.2

-2.4

0

2.7

3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

3.5

3.1

3.9

V

4.3

- V

4.7

5.1

5.5

V

- V

BAT

Figure 16. Line Regulation, Iout = 50 mA, Class-B

Figure 17. Current Limit vs Input Voltage, Class-B/C

150

-50 mA, Vsim

120

90

60

30

-100 mA, Vsim

0

-40 -30 -20 -10

0

10 20 30 40 50 60 70 80

- ºC

T

A

Figure 18. Ground Current vs Temperature, Class-C

Submit Documentation Feedback

27

Product Folder Link(s): TXS02326A

PACKAGE MATERIALS INFORMATION

www.ti.com

5-May-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TXS02326AMRGER

VQFN

RGE

24

3000

330.0

12.4

4.25

1.15

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-May-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VQFN RGE 24

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 29.0

TXS02326AMRGER

3000

Pack Materials-Page 2

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型号：	TXS02326A
厂家：	TEXAS INSTRUMENTS
描述：	DUAL-SUPPLY 2:1 SIM CARD MULTIPLEXER/TRANSLATOR 双电源2 ： 1 SIM卡多路复用器/转换器转换器复用器
文件：	总34页 (文件大小：845K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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