UCC20225AQNPLTQ1 [TI]
具有单 PWM 输入、5V UVLO 且采用 LGA 封装的汽车类 2.5kVrms、4A/6A 双通道隔离式栅极驱动器 | NPL | 13 | -40 to 125;
| 型号： | UCC20225AQNPLTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有单 PWM 输入、5V UVLO 且采用 LGA 封装的汽车类 2.5kVrms、4A/6A 双通道隔离式栅极驱动器 | NPL | 13 | -40 to 125 栅极驱动 接口集成电路 驱动器 |
| 文件： | 总47页 (文件大小：2096K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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UCC20225-Q1, UCC20225A-Q1
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
适用于汽车 48V 系统、采用 LGA 封装且具有单输入的 UCC20225-Q1、
UCC20225A-Q1 隔离式双通道栅极驱动器
1 特性
3 说明
1
•
具有符合 AEC-Q100 标准的下列特性：
是UCC20225-Q1 系列是一款单输入、双输出隔离式栅
极驱动器，具有 4A 峰值拉电流和 6A 峰值灌电流，并
且采用 5mm x 5mm LGA-13 封装。该器件旨在以一流
的传播延迟和脉宽失真度驱动功率晶体管，频率最高可
达 5MHz。
–
–
–
器件温度 1 级
器件 HBM ESD 分类等级 H2
器件 CDM ESD 分类等级 C6
•
•
•
•
•
单 PWM 输入，双输出
可通过电阻器编程的死区时间
4A 峰值拉电流、6A 峰值灌电流输出
CMTI 大于 100V/ns
输入侧通过一个 2.5kVRMS 隔离栅与两个输出驱动器隔
离，共模瞬态抗扰度 (CMTI) 的最小值为 100V/ns。两
个输出侧驱动器之间的内部功能隔离支持高达 700VDC
的工作电压。
开关参数：
–
–
–
19ns 典型传播延迟
5ns 最大延迟匹配
6ns 最大脉宽失真
UCC20225-Q1 系列通过 DT 引脚上的电阻器支持可编
程死区时间。DIS 引脚在设为高电平时可同时关断两个
输出，在接地时允许器件正常运行。
•
•
•
•
•
•
3V 至 18V 输入 VCCI 范围
VDD 高达 25V，带 5V 和 8V UVLO 选项
抑制短于 5ns 的输入瞬变
该器件接受的 VDD 电源电压高达 25V。凭借 3V 至
18V 的宽 VCCI 范围，该驱动器非常适合连接模拟和
数字控制器。所有电源电压引脚都具有欠压锁定
(UVLO) 保护功能。
TTL 和 CMOS 兼容输入
节省空间的 5mm x 5mm LGA-13 封装
安全相关认证：
凭借上述所有高级 功能，UCC20225-Q1 系列可在各
种汽车 应用中实现高功率密度、高效率和稳健性。
–
–
–
符合 VDE V 0884-11:2017 标准的 3535VPK 隔
离
符合 UL 1577 标准且持续时长为 1 分钟的
2500VRMS 隔离
器件信息(1)
器件型号
UCC20225A-Q1
UCC20225-Q1
封装
UVLO
5V
符合 GB4943.1-2011 的 CQC 认证
LGA (13) 5 × 5 mm
LGA (13) 5 × 5 mm
8V
2 应用
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
•
•
汽车外部音频放大器
汽车 48V 系统
功能方框图
VDD
VCC
RBOOT
HV DC-Link
VCC
RIN
VDDA
PWM
NC
13
12
11
PWM
2
3
4
1
5
6
7
RON
CBOOT
OUTA
VSSA
CIN
CIN
RGS
VCCI
GND
DIS
mC
CVCC
SW
Functional
Isolation
VDD
Analog
or
Digital
Disable
RDIS
VDDB
10
9
CDT
≥2.2nF
CDIS
DT
RON
OUTB
VSSB
CVDD
RGS
VCCI
RDT
8
VSS
Copyright © 2019, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLUSDC2
UCC20225-Q1, UCC20225A-Q1
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
目录
7.6 CMTI Testing........................................................... 17
Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 22
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application .................................................. 24
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Power Ratings........................................................... 5
6.6 Insulation Specifications............................................ 6
6.7 Safety-Related Certifications..................................... 7
6.8 Safety Limiting Values .............................................. 7
6.9 Electrical Characteristics........................................... 8
6.10 Switching Characteristics........................................ 9
6.11 Thermal Derating Curves...................................... 10
6.12 Typical Characteristics.......................................... 11
Parameter Measurement Information ................ 15
7.1 Propagation Delay and Pulse Width Distortion....... 15
7.2 Rising and Falling Time ......................................... 15
7.3 PWM Input and Disable Response Time................ 15
7.4 Programable Dead Time ........................................ 16
7.5 Power-up UVLO Delay to OUTPUT........................ 16
8
9
10 Power Supply Recommendations ..................... 35
11 Layout................................................................... 36
11.1 Layout Guidelines ................................................. 36
11.2 Layout Example .................................................... 37
12 器件和文档支持 ..................................................... 39
12.1 相关链接................................................................ 39
12.2 文档支持 ............................................................... 39
12.3 认证....................................................................... 39
12.4 接收文档更新通知 ................................................. 39
12.5 社区资源................................................................ 39
12.6 商标....................................................................... 39
12.7 静电放电警告......................................................... 39
12.8 Glossary................................................................ 39
13 机械、封装和可订购信息....................................... 39
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (June 2019) to Revision C
Page
•
已更改 将 UCC20225A-Q1 的销售状态从“预告信息”更改为“初始发行版” .............................................................................. 1
Changes from Revision A (April 2019) to Revision B
Page
•
已添加 向数据表添加了 UCC20225A-Q1 器件 ....................................................................................................................... 1
Changes from Original (November 2018) to Revision A
Page
•
已更改 将销售状态从“预告信息”更改为“初始发行版”。........................................................................................................... 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
UCC20225-Q1, UCC20225A-Q1
www.ti.com.cn
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
5 Pin Configuration and Functions
NPL Package
13-Pin LGA
Top View
GND
PWM
NC
1
2
3
4
5
6
7
13
VDDA
OUTA
VSSA
12
11
VCCI
DISABLE
DT
10
9
VDDB
OUTB
VSSB
VCCI
8
Not to scale
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
NO.
Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled
low internally if left open. It is recommended to tie this pin to ground if not used to achieve
better noise immunity. Bypass using a ≈1nF low ESR/ESL capacitor close to DIS pin when
connecting to a micro controller with distance.
DISABLE
5
I
Programmable dead time function.
Tying DT to VCCI disables the DT function with dead time ≈ 0ns. Placing a resistor (RDT
between DT and GND adjusts dead time according to: DT (in ns) = 10 x RDT (in kΩ). It is
recommended to parallel a ceramic capacitor, 2.2nF or above, close to DT pin to achieve
)
DT
6
I
better noise immunity when using RDT
.
GND
NC
1
3
G
–
Primary-side ground reference. All signals in the primary side are referenced to this ground.
No internal connection.
Output of driver A. Connect to the gate of the A channel FET or IGBT. Output A is in phase
with PWM input with a propagation delay
OUTA
OUTB
PWM
VCCI
VCCI
VDDA
VDDB
12
9
O
O
I
Output of driver B. Connect to the gate of the B channel FET or IGBT. Output B is always
complementary to output A with a programmed dead time.
PWM input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if
left open.
2
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor
located as close to the device as possible.
4
P
P
P
P
This pin is internally shorted to pin 4. Preference should be given to bypassing pin-4 to pin-1
instead of pin-7 to pin-1.
7
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL
capacitor located as close to the device as possible.
13
10
Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL
capacitor located as close to the device as possible.
VSSA
VSSB
11
8
G
G
Ground for secondary-side driver A. Ground reference for secondary side A channel.
Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1) P =Power, G= Ground, I= Input, O= Output
Copyright © 2018–2019, Texas Instruments Incorporated
3
UCC20225-Q1, UCC20225A-Q1
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
20
UNIT
V
Input bias pin supply voltage
Driver bias supply
VCCI to GND
VDDA-VSSA, VDDB-VSSB
30
V
VVDDA+0.3,
VVDDB+0.3
OUTA to VSSA, OUTB to VSSB
–0.3
–2
V
V
Output signal voltage
OUTA to VSSA, OUTB to VSSB,
Transient for 200 ns
VVDDA+0.3,
VVDDB+0.3
PWM, DIS, DT to GND
PWM Transient for 50ns
VSSA-VSSB, VSSB-VSSA
–0.3
–5
VVCCI+0.3
VVCCI+0.3
700
V
V
Input signal voltage
Channel to channel voltage
V
(2)
Junction temperature, TJ
–40
–65
150
°C
°C
Storage temperature, Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) To maintain the recommended operating conditions for TJ, see the Thermal Information.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
3
MAX
UNIT
VCCI
VCCI Input supply voltage
Driver output bias supply
18
25
V
UCC20225A-Q1
UCC20225-Q1
6.5
9.2
–40
–40
VDDA,
VDDB
V
25
TA
TJ
Ambient Temperature
Junction Temperature
125
130
°C
°C
4
Copyright © 2018–2019, Texas Instruments Incorporated
UCC20225-Q1, UCC20225A-Q1
www.ti.com.cn
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
6.4 Thermal Information
UCC20225A-Q1,
UCC20225-Q1
THERMAL METRIC(1)
UNIT
LGA (13)(2)
98.0
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
48.8
78.9
26.2
76.8
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Standard JESD51-9 Area Array SMT Test Board (2s2p) in still air, with 12-mil dia. 1-oz copper vias connecting VSSA and VSSB to the
plane immediately below (three vias for VSSA, three vias for VSSB).
6.5 Power Ratings
VALUE
UNIT
PD
Power dissipation by UCC20225A-Q1, UCC20225-
Q1
0.95
VCCI = 18 V, VDDA/B = 12 V, PWM = 3.3 V,
2.7 MHz 50% duty cycle square wave 1-nF
load
PDI
Power dissipation by primary side of UCC20225A-
Q1, UCC20225-Q1
0.05
0.45
W
PDA, PDB
Power dissipation by each driver side of
UCC20225A-Q1, UCC20225-Q1
Copyright © 2018–2019, Texas Instruments Incorporated
5
UCC20225-Q1, UCC20225A-Q1
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
6.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
VALUE
3.5
UNIT
mm
CLR
CPG
External clearance(1)(2)
External creepage(1)
Shortest pin-to-pin distance through air
Shortest pin-to-pin distance across the package surface
3.5
mm
Distance through the
insulation
DTI
CTI
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
>21
µm
V
Comparative tracking index
Material group
> 600
I
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
I-III
I-II
Overvoltage category per
IEC 60664-1
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01(3)
Maximum repetitive peak
isolation voltage
VIORM
AC voltage (bipolar)
792
VPK
AC voltage (sine wave); time dependent dielectric breakdown
(TDDB) test; (See 图 1)
560
792
VRMS
VDC
VPK
Maximum working isolation
voltage
VIOWM
DC Voltage
Maximum transient isolation VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t
VIOTM
VIOSM
3535
voltage
= 1 s (100% production)
Maximum surge isolation
voltage(4)
Test method per IEC 62368-1, 1.2/50 μs waveform, VTEST =
1.3 × VIOSM (qualification)
3500
<5
VPK
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM, tm = 10s
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM, tm = 10s
<5
qpd
Apparent charge(5)
pC
Method b1; At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM; tini = 1 s;
<5
Vpd(m) = 1.5 × VIORM , tm = 1s
Barrier capacitance, input to
output(6)
CIO
RIO
VIO = 0.4 sin (2πft), f =1 MHz
1.2
pF
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Isolation resistance, input to
output
VIO = 500 V at 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS =150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO = 3000 VRMS, t = 60 sec. (qualification),
VTEST = 1.2 × VISO = 3000VRMS, t = 1 sec (100% production)
VISO
Withstand isolation voltage
2500
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) Package dimension tolerance ± 0.05mm.
(3) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
(4) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-pin device.
6
Copyright © 2018–2019, Texas Instruments Incorporated
UCC20225-Q1, UCC20225A-Q1
www.ti.com.cn
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
6.7 Safety-Related Certifications
VDE
UL
CQC
Recognized under UL 1577
Component Recognition Program 2011
Certified according to GB 4943.1-
Certified according to DIN V VDE V 0884-11:2017-01
Basic Insulation,
Altitude ≤ 5000 m,
Tropical Climate 320-VRMS
maximum working voltage
Basic Insulation Maximum Transient Overvoltage, 3535 VPK
;
Maximum Repetitive Peak Voltage, 792 VPK
;
Single protection, 2500 VRMS
Certification Number: E181974
Maximum Surge Isolation Voltage, 2719 VPK
Certification Number:
CQC18001186974
Certification Number: 40016131
6.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
SIDE
MIN
TYP
MAX
UNIT
R
θJA = 98.0ºC/W, VDDA/B = 12 V, TA
=
=
DRIVER A,
DRIVER B
25°C, TJ = 150°C
50
mA
Safety output supply
current(1)
See 图 2
IS
RθJA = 98.0ºC/W, VDDA/B = 25 V, TA
DRIVER A,
DRIVER B
24
mA
25°C, TJ = 150°C
INPUT
DRIVER A
DRIVER B
TOTAL
0.05
0.60
0.60
1.25
150
R
θJA = 98.0ºC/W, TA = 25°C, TJ = 150°C
PS
TS
Safety supply power(1)
Safety temperature(1)
W
See 图 3
°C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
Copyright © 2018–2019, Texas Instruments Incorporated
7
UCC20225-Q1, UCC20225A-Q1
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
6.9 Electrical Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
SUPPLY CURRENTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVCCI
VCCI quiescent current
DISABLE = VCCI
1.5
1.0
2.0
1.8
mA
mA
IVDDA
IVDDB
,
VDDA and VDDB quiescent current DISABLE = VCCI
(f = 500 kHz) current per channel,
COUT = 100 pF
IVCCI
VCCI operating current
2.5
2.5
mA
mA
IVDDA
IVDDB
,
(f = 500 kHz) current per channel,
COUT = 100 pF
VDDA and VDDB operating current
VCCI SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS
VVCCI_ON
VVCCI_OFF
VVCCI_HYS
Rising threshold VCCI_ON
Falling threshold VCCI_OFF
Threshold hysteresis
2.55
2.35
2.7
2.5
0.2
2.85
2.65
V
V
V
UCC20225A-Q1 VDD SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS
VVDDA_ON,
VVDDB_ON
Rising threshold VDDA_ON,
VDDB_ON
5.7
5.4
6.0
5.7
0.3
6.3
6
VVDDA_OFF,
VVDDB_OFF
Falling threshold VDDA_OFF,
VDDB_OFF
V
V
VVDDA_HYS,
VVDDB_HYS
Threshold hysteresis
UCC20225-Q1 VDD SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS
VVDDA_ON,
VVDDB_ON
Rising threshold VDDA_ON,
VDDB_ON
8.3
7.8
8.7
8.2
0.5
9.2
8.7
VVDDA_OFF,
VVDDB_OFF
Falling threshold VDDA_OFF,
VDDB_OFF
VVDDA_HYS,
VVDDB_HYS
Threshold hysteresis
PWM AND DISABLE
VPWMH, VDISH Input high voltage
VPWML, VDISL Input low voltage
1.6
0.8
1.8
1
2
V
V
1.2
VPWM_HYS
VDIS_HYS
,
Input hysteresis
0.8
V
V
Negative transient, ref to GND, 50
ns pulse
Not production tested, bench test
only
VPWM
–5
OUTPUT
IOA+, IOB+
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
Peak output source current
Peak output sink current
4
6
A
A
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
IOA-, IOB-
IOUT = –10 mA, TA = 25°C, ROHA
,
ROHB do not represent drive pull-
up performance. See tRISE in
Switching Characteristics and
Output Stage for details.
ROHA, ROHB
Output resistance at high state
5
Ω
ROLA, ROLB
VOHA, VOHB
Output resistance at low state
Output voltage at high state
IOUT = 10 mA, TA = 25°C
0.55
Ω
VVDDA, VVDDB = 12 V, IOUT = –10
mA, TA = 25°C
11.95
V
VVDDA, VVDDB = 12 V, IOUT = 10
mA, TA = 25°C
VOLA, VOLB
Output voltage at low state
5.5
mV
DEADTIME AND OVERLAP PROGRAMMING
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Electrical Characteristics (continued)
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Pull DT pin to VCCI
MIN
TYP
MAX
UNIT
0
ns
DT pin is left open, min spec
characterized only, tested for
outliers
Dead time
8
15
ns
ns
RDT = 20 kΩ
160
200
240
6.10 Switching Characteristics
VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tRISE
Output rise time, 20% to 80%
measured points
6
16
ns
COUT = 1.8 nF
tFALL
tPWmin
tPDHL
tPDLH
Output fall time, 90% to 10%
measured points
7
12
20
30
30
ns
ns
ns
ns
COUT = 1.8 nF
Minimum pulse width
Output off for less than minimum,
COUT = 0 pF
Propagation delay from INx to OUTx
falling edges
14
14
19
19
Propagation delay from INx to OUTx
rising edges
tPWD
tDM
Pulse width distortion |tPDLH – tPDHL
|
6
5
ns
ns
Propagation delays matching
between VOUTA, VOUTB
High-level common-mode transient
immunity
|CMH|
|CML|
100
100
PWM is tied to GND or VCCI;
VCM=1200V; (See CMTI Testing)
V/ns
Low-level common-mode transient
immunity
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6.11 Thermal Derating Curves
1.E+10
Safety Margin Zone: 672 VRMS, 26 Years
Operating Zone: 560 VRMS, 20 Years
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
1.E+2
1.E+1
1.E+0
20%
0
500
1000
1500
2000
2500
3000
3500
Stress Voltage (VRMS
)
图 1. Isolation Capacitor Life Time Projection
60
50
40
30
20
10
0
1500
VDD = 12V
VDD = 25V
1250
1000
750
500
250
0
0
50
100
Ambient Temperature (°C)
150
200
0
50
100
Ambient Temperature (°C)
150
200
D002
D003
图 2. Thermal Derating Curve for Safety-Related Limiting
图 3. Thermal Derating Curve for Safety-Related Limiting
Current
(Current in Each Channel with Both Channels Running
Simultaneously)
Power
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6.12 Typical Characteristics
VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.
20
16
12
8
50
40
30
20
10
0
4
VDD=12v
VDD=25v
VDD= 12V
VDD= 25V
0
0
800
1600
2400 3200
Frequency (kHz)
4000
4800
5600
0
500
1000
1500
Frequency (kHz)
2000
2500
3000
D001
D001
图 4. Per Channel Current Consumption vs. Frequency (No
图 5. Per Channel Current Consumption (IVDDA/B) vs.
Load, VDD = 12 V or 25 V)
Frequency (1-nF Load, VDD = 12 V or 25 V)
6
5
4
3
2
1
0
30
24
18
12
6
50kHz
250kHz
500kHz
1MHz
VDD= 12V
VDD= 25V
0
10
25
40
55
Frequency (kHz)
70
85 100
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (èC)
D001
D001
图 6. Per Channel Current Consumption (IVDDA/B) vs.
图 7. Per Channel (IVDDA/B) Supply Current Vs. Temperature
Frequency (10-nF Load, VDD = 12 V or 25 V)
(No Load, Different Switching Frequencies)
2
1.6
1.2
0.8
0.4
0
2
1.8
1.6
1.4
1.2
VDD= 12V
VDD= 25V
VCCI= 3.3V
VCCI= 5V
1
-40
-40
-20
0
20
40
60
80
100 120 140
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D001
D001
图 8. Per Channel (IVDDA/B) Quiescent Supply Current vs
图 9. IVCCI Quiescent Supply Current vs Temperature (No
Temperature (No Load, Input Low, No Switching)
Load, DIS is High, No Switching)
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Typical Characteristics (接下页)
VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.
25
20
15
10
5
10
8
6
Output Pull-Up
Output Pull-Down
4
2
tRISE
tFALL
0
0
0
2
4
6
8
10
-40
-20
0
20
40
60
80
100 120 140
Load (nF)
Temperature (èC)
D001
D001
图 10. Rising and Falling Times vs. Load (VDD = 12 V)
图 11. Output Resistance vs. Temperature
28
20
19
18
17
16
15
24
20
16
12
8
Rising Edge (tPDLH
Falling Edge (tPDHL
)
)
Rising Edge (tPDLH)
Falling Edge (tPDHL
)
-40
-20
0
20
40
60
80
100 120 140
3
6
9
12
15 18
Temperature (èC)
VCCI (V)
D001
D001
图 12. Propagation Delay vs. Temperature
图 13. Propagation Delay vs. VCCI
5
3
5
2.5
0
1
-1
-3
-5
-2.5
Rising Edge
Falling Edge
-5
-40
-20
0
20
40
60
80
100 120 140
10
13
16
19
22
25
Temperature (èC)
VDDA/B (V)
D001
D001
图 14. Pulse Width Distortion vs. Temperature
图 15. Propagation Delay Matching (tDM) vs. VDD
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Typical Characteristics (接下页)
VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.
350
330
310
290
270
250
5
2.5
0
-2.5
Rising Edge
Falling Edge
-5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D001
D001
图 16. Propagation Delay Matching (tDM) vs. Temperature
图 17. UCC20225A-Q1 VDD 5-V UVLO Hysteresis vs.
Temperature
550
530
510
490
470
450
6.5
6
5.5
VVDD_ON
VVDD_OFF
5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D001
D001
图 18. UCC20225A-Q1 VDD 5-V UVLO Threshold vs.
图 19. UCC20225-Q1 VDD 8-V UVLO Hysteresis vs.
Temperature
Temperature
900
860
820
780
740
700
10
9
8
7
6
VCC=3.3V
VCC=5V
VCC=12V
VVDDA_ON
VVDDA_OFF
5
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D001
D001
图 20. UCC20225-Q1 VDD 8-V UVLO Threshold vs.
图 21. PWM/DIS Hysteresis vs. Temperature
Temperature
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Typical Characteristics (接下页)
VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.
1.2
1.14
1.08
1.02
0.96
0.9
2
1.92
1.84
1.76
1.68
1.6
VCC=3.3V
VCC= 5V
VCC=12V
VCC=3.3V
VCC= 5V
VCC=12V
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D001
D001
图 22. PWM/DIS Low Threshold
图 23. PWM/DIS High Threshold
1500
1200
900
600
300
0
5
-6
RDT= 20kW
RDT= 100kW
-17
-28
-39
-50
RDT= 20kW
RDT = 100kW
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D001
D001
图 24. Dead Time vs. Temperature (with RDT = 20 kΩ and 100
kΩ)
图 25. Dead Time Matching vs. Temperature (with RDT = 20
kΩ and 100 kΩ)
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7 Parameter Measurement Information
7.1 Propagation Delay and Pulse Width Distortion
图 26 shows how to calculate pulse width distortion (tPWD) and delay matching (tDM) from the propagation delays
of channels A and B. These parameters can be measured by disabling the dead time function by shorting the DT
Pin to VCC.
PWM
tDM-F = | tPDHLA Å tPDHLB
tDM-R = | tPDLHA Å tPDLHB
|
|
OUTA
90%
tPDLHA
tPWD = | tPDLHA/B Å tPDHLA/B
|
tPDHLA
10%
90%
tPDLHB
tPDHLB
OUTB
图 26. Propagation Delay Matching and Pulse Width Distortion
7.2 Rising and Falling Time
图 27 shows the criteria for measuring rising (tRISE) and falling (tFALL) times. For more information on how short
rising and falling times are achieved see Output Stage.
90%
80%
tRISE
tFALL
20%
10%
图 27. Rising and Falling Time Criteria
7.3 PWM Input and Disable Response Time
图 28 shows the response time of the disable function. For more information, see Disable Pin.
PWM
DIS High
Response Time
DIS
DIS Low
Response Time
OUTA
90%
10%
10%
图 28. Disable Pin Timing
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7.4 Programable Dead Time
Tying it to GND through an appropriate resistor (RDT) sets a dead-time interval. For more details on dead time,
refer to Programmable Dead Time (DT) Pin.
PWM
90%
OUTA
10%
tPDHL
90%
10%
OUTB
Dead Time
(with RDT1
Dead Time
(with RDT2
tPDHL
)
)
图 29. Dead-Time Switching Parameters
7.5 Power-up UVLO Delay to OUTPUT
Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising edge
to output and it is defined as tVCCI+ to OUT for VCCI UVLO (typically 40-µs) and tVDD+ to OUT for VDD UVLO (typically
50-µs). It is recommended to consider proper margin before launching PWM signal after the driver's VCCI and
VDD bias supply is ready. 图 30 and 图 31 show the power-up UVLO delay timing diagram for VCCI and VDD.
If PWM are active before VCCI or VDD have crossed above their respective on thresholds, the output will not
update until tVCCI+ to OUT or tVDD+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when
either VCCI or VDD receive a voltage less than their respective off thresholds, there is <1µs delay, depending on
the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to
ensure safe operation during VCCI or VDD brownouts.
VCCI,
INx
VCCI,
INx
VVCCI_ON
VVCCI_OFF
VDDx
OUTx
VDDx
OUTx
tVCCI+ to OUT
tVDD+ to OUT
VVDD_ON
VVDD_OFF
图 30. VCCI Power-up UVLO Delay
图 31. VDDA/B Power-up UVLO Delay
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7.6 CMTI Testing
图 32 is a simplified diagram of the CMTI testing configuration.
VCC
VDD
VDDA
PWM
2
13
OUTA
OUTA
VSSA
12
11
VCC
VCCI
4
GND
Functional
Isolation
1
5
6
7
DIS
DT
VDDB
10
9
OUTB
OUTB
VSSB
VCCI
8
GND
VSS
Common Mode Surge
Generator
Copyright © 2017, Texas Instruments Incorporated
图 32. Simplified CMTI Testing Setup
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8 Detailed Description
8.1 Overview
There are several instances where controllers are not capable of delivering sufficient current to drive the gates of
power transistors. This is especially the case with digital controllers, since the input signal from the digital
controller is often a 3.3-V logic signal capable of only delivering a few mA. In order to switch power transistors
rapidly and reduce switching power losses, high-current gate drivers are often placed between the output of
control devices and the gates of power transistors.
The UCC20225A-Q1 and UCC20225-Q1, are flexible dual gate drivers which can be configured to fit a variety of
power supply and motor drive topologies, as well as drive several types of transistors, including SiC MOSFETs.
UCC20225-Q1 family has many features that allow it to integrate well with control circuitry and protect the gates
it drives such as: resistor-programmable dead time (DT) control, a DISABLE pin, and under voltage lock out
(UVLO) for both input and output voltages. The UCC20225 also holds its OUTA low when the PWM is left open
or when the PWM pulse is not wide enough. The driver input PWM is CMOS and TTL compatible for interfacing
to digital and analog power controllers alike. Importantly, Channel A is in phase with PWM input and Channel B
is always complimentary with Channel A with programmed dead time.
8.2 Functional Block Diagram
PWM
PWM
2
13 VDDA
200 kW
VCCI
Driver
MOD
DEMOD
12 OUTA
11 VSSA
UVLO
VCCI 4,7
UVLO
GND
DT
1
6
5
Deadtime
Control
Functional Isolation
DIS
10 VDDB
200 kW
Driver
MOD
DEMOD
UVLO
9
8
OUTB
VSSB
PWM
NC
3
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8.3 Feature Description
8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
The UCC20225 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks
between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than VVDD_ON at device
start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected outputs low, regardless
of the status of the input pin (PWM).
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an
active clamp circuit that limits the voltage rise on the driver outputs (illustrated in 图 33 ). In this condition, the
upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through RCLAMP
.
In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device,
typically around 1.5V, when no bias power is available. The clamp sinking current is limited only by the per-
channel safety supply power, the ambient temperature, and the 6A peak sink current rating.
VDD
RHI_Z
Output
Control
OUT
RCLAMP
RCLAMP is activated
during UVLO
VSS
图 33. Simplified Representation of Active Pull Down Feature
The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is
ground noise from the power supply. This also allows the device to accept small drops in bias voltage, which
occurs when the device starts switching and operating current consumption increases suddenly.
The input side of the UCC20225-Q1 family also has an internal under voltage lock out (UVLO) protection feature.
The device isn't active unless the voltage at VCCI exceeds VVCCI_ON. A signal will cease to be delivered when
VCCI receives a voltage less than VVCCI_OFF. As with the UVLO for VDD, there is hystersis (VVCCI_HYS) to ensure
stable operation.
If PWM is active before VCCI or VDD have crossed above their respective on thresholds, the output will not
update until 50µs (typical) after VCCI or VDD crossing its UVLO rising threshold. However, when either VCCI or
VDD receive a voltage less than their respective UVLO off thresholds, there is <1µs delay, depending on the
voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to
ensure safe operation during VCCI or VDD brownouts.
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Feature Description (接下页)
The UCC20225-Q1 family can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.
表 1. UCC20225-Q1 family VCCI UVLO Feature Logic
CONDITION
INPUT
OUTPUTS
PWM
OUTA
OUTB
VCCI-GND < VVCCI_ON during device start up
VCCI-GND < VVCCI_ON during device start up
VCCI-GND < VVCCI_OFF after device start up
VCCI-GND < VVCCI_OFF after device start up
H
L
L
L
L
L
L
L
L
L
H
L
表 2. UCC20225-Q1 family VDD UVLO Feature Logic
CONDITION
INPUT
OUTPUTS
PWM
OUTA
OUTB
VDD-VSS < VVDD_ON during device start up
VDD-VSS < VVDD_ON during device start up
VDD-VSS < VVDD_OFF after device start up
VDD-VSS < VVDD_OFF after device start up
H
L
L
L
L
L
L
L
L
L
H
L
8.3.2 Input and Output Logic Table
Assume VCCI, VDDA, VDDB are powered up. See VDD, VCCI, and Under Voltage Lock Out (UVLO) for more information on
UVLO operation modes.
表 3. INPUT/OUTPUT Logic Table(1)
INPUT
PWM
OUTPUTS
OUTA
DISABLE(2)
NOTE
OUTB
L or Left
Open
L or Left Open
L
H
Output transitions occur after the dead time expires. See Programmable
Dead Time (DT) Pin
H
X
L or Left Open
H
H
L
L
L
-
(1) "X" means L, H or left open.
(2) DIS pin disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low internally if left open. It is
recommended to tie this pin to ground if not used to achieve better noise immunity. Bypass using a ≈1nF low ESR/ESL capacitor close
to DIS pin when connecting to a µC with distance.
8.3.3 Input Stage
The input pins (PWM and DIS) of the UCC20225-Q1 family are based on a TTL and CMOS compatible input-
threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive with logic-
level control signals (such as those from 3.3-V micro-controllers), since UCC20225-Q1 family has a typical high
threshold (VPWMH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see 图 22,图 23).
A wide hysteresis (VPWM_HYS) of 0.8 V makes for good noise immunity and stable operation. If any of the inputs
are ever left open, internal pull-down resistors force the pin low. These resistors are typically 200 kΩ (See
Functional Block Diagram). However, it is still recommended to ground an input if it is not being used for
improved noise immunity.
Since the input side of UCC20225-Q1 family is isolated from the output drivers, the input signal amplitude can be
larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility
when integrating with control signal sources, and allows the user to choose the most efficient VDD for any gate.
That said, the amplitude of any signal applied to PWM must never be at a voltage higher than VCCI.
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8.3.4 Output Stage
The UCC20225-Q1 family’s output stages features a pull-up structure which delivers the highest peak-source
current when it is most needed, during the Miller plateau region of the power-switch turn on transition (when the
power switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-
channel MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel
MOSFET is to provide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by
briefly turning on the N-channel MOSFET during a narrow instant when the output is changing states from low to
high. The on-resistance of this N-channel MOSFET (RNMOS) is approximately 1.47-Ω when activated.
The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device
only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on only
for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the
UCC20225-Q1 family pull-up stage during this brief turn-on phase is much lower than what is represented by the
ROH parameter, yielding a faster turn-on. The turn-on phase output resistance is the parallel combination
ROH||RNMOS
.
The pull-down structure in UCC20225-Q1 family is simply composed of an N-channel MOSFET. The ROL
parameter, which is also a DC measurement, is representative of the impedance of the pull-down state in the
device. Both outputs of the UCC20225-Q1 family are capable of delivering 4-A peak source and 6-A peak sink
current pulses. The output voltage swings between VDD and VSS provides rail-to-rail operation, thanks to the
MOS-out stage which delivers very low drop-out.
VDD
ROH
Shoot-
RNMOS
Input
Signal
Through
Prevention
Circuitry
OUT
VSS
ROL
Pull Up
图 34. Output Stage
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8.3.5 Diode Structure in UCC20225-Q1 family
图 35 illustrates the multiple diodes involved in the ESD protection components of the UCC20225-Q1 family. This
provides a pictorial representation of the absolute maximum rating for the device.
VCCI
4,7
VDDA
13
30 V
12 OUTA
11 VSSA
20 V 20 V
PWM
2
DIS
DT
5
6
10 VDDB
30 V
9
OUTB
1
8
GND
VSSB
图 35. ESD Structure
8.4 Device Functional Modes
8.4.1 Disable Pin
Setting the DISABLE pin high shuts down both outputs simultaneously. Grounding (or left open) the DISABLE pin
allows UCC20225-Q1 family to operate normally. The DISABLE response time is in the range of 20ns and quite
responsive, which is as fast as propagation delay. The DISABLE pin is only functional (and necessary) when
VCCI stays above the UVLO threshold. It is recommended to tie this pin to ground if the DISABLE pin is not used
to achieve better noise immunity.
8.4.2 Programmable Dead Time (DT) Pin
UCC20225-Q1 family allows the user to adjust dead time (DT) in the following ways:
8.4.2.1 Tying the DT Pin to VCC
If DT pin is tied to VCC, dead time function between OUTA and OUTB is disabled and the dead time between
the two output channels is around 0ns.
22
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Device Functional Modes (接下页)
8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
If the DT pin is left open, the dead time duration (tDT) is set to <15-ns. It is not recommended to leave DT pin
open for noisy environment. One can program tDT by placing a resistor, RDT, between the DT pin and GND. The
appropriate RDT value can be determined from 公式 1, where RDT is in kΩ and tDT in ns:
tDT » 10´ RDT
(1)
The steady state voltage at DT pin is around 0.8V, and the DT pin current will be less than 10uA when RDT=100-
kΩ. Since the DT pin current is used internally to set the dead time, and this current decreases as RDT increases,
it is recommended to parallel a ceramic capacitor, 2.2-nF or above, close to DT pin to achieve better noise
immunity and better dead time matching between two channels, especially when the dead time is larger than
300-ns.
The input signal’s falling edge activates the programmed dead time for the output. An output signal's dead time is
always set to the driver’s programmed dead time. The driver dead time logic is illustrated in 图 36:
PWM
DT
OUTA
OUTB
图 36. Input and Output Logic Relationship with Dead Time
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCC20225-Q1 family effectively combines both isolation and buffer-drive functions. The flexible, universal
capability of the UCC20225-Q1 family (with up to 18-V VCCI and 25-V VDDA/VDDB) allows the device to be
used as a low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or SiC MOSFETs.
With integrated components, advanced protection features (UVLO, dead time, and disable) and optimized
switching performance, the UCC20225-Q1 family enables designers to build smaller, more robust designs for
enterprise, telecom, automotive, and industrial applications with a faster time to market.
9.2 Typical Application
The circuit in 图 37 shows a reference design with UCC20225-Q1 driving a typical half-bridge configuration which
could be used in several popular power converter topologies such as synchronous buck, synchronous boost,
half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.
VDD
VCC
RBOOT
HV DC-Link
VCC
RIN
VDDA
PWM
NC
13
12
11
PWM
2
3
4
1
5
6
7
RON
CBOOT
OUTA
VSSA
CIN
CIN
RGS
VCCI
GND
DIS
mC
CVCC
SW
Functional
Isolation
VDD
Analog
or
Digital
Disable
RDIS
VDDB
10
9
CDT
≥2.2nF
CDIS
DT
RON
OUTB
VSSB
CVDD
RGS
VCCI
RDT
8
VSS
Copyright © 2019, Texas Instruments Incorporated
图 37. Typical Application Schematic
24
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Typical Application (接下页)
9.2.1 Design Requirements
表 4 lists reference design parameters for the example application: UCC20225-Q1 family driving 700-V
MOSFETs in a high side-low side configuration.
表 4. UCC20225-Q1 family Design Requirements
PARAMETER
Power transistor
VCC
VALUE
UNITS
IPB65R150CFD
-
V
5.0
12
VDD
V
Input signal amplitude
Switching frequency (fs)
DC link voltage
3.3
200
400
V
kHz
V
9.2.2 Detailed Design Procedure
9.2.2.1 Designing PWM Input Filter
It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)
the signal at the output. However, a small input RIN-CIN filter can be used to filter out the ringing introduced by
non-ideal layout or long PCB traces.
Such a filter should use an RIN in the range of 0-Ω to 100-Ω and a CIN between 10-pF and 100-pF. In the
example, an RIN = 51-Ω and a CIN = 33-pF are selected, with a corner frequency of approximately 100-MHz.
When selecting these components, it is important to pay attention to the trade-off between good noise immunity
and propagation delay.
9.2.2.2 Select External Bootstrap Diode and its Series Resistor
The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side
transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation
in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.
Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver
circuit.
When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes
or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the loss
introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage is 800
VDC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good margin.
Therefore, a 600-V ultrafast diode, MURA160T3G, is chosen in this example.
A bootstrap resistor, RBOOT, is used to reduce the inrush current in DBOOT and limit the ramp up slew rate of
voltage of VDDA-VSSA during each switching cycle, especially when the VSSA(SW) pin has an excessive
negative transient voltage. The recommended value for RBOOT is between 1 Ω and 20 Ω depending on the diode
used. In the example, a current limiting resistor of 2.7 Ω is selected to limit the inrush current of bootstrap diode.
The estimated worst case peak current through DBoot is,
VDD - VBDF
12 V -1.5 V
2.7 W
IDBoot (PK)
=
=
» 4 A
RBoot
where
•
VBDF is the estimated bootstrap diode forward voltage drop at 4 A.
(2)
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9.2.2.3 Gate Driver Output Resistor
The external gate driver resistors, RON/ROFF, are used to:
1. Limit ringing caused by parasitic inductances/capacitances.
2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.
3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.
4. Reduce electromagnetic interference (EMI).
As mentioned in Output Stage, the UCC20225-Q1 family has a pull-up structure with a P-channel MOSFET and
an additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the
peak source current can be predicted with:
æ
ö
÷
÷
ø
VDD - VBDF
IOA + = min 4A,
ç
ç
è
RNMOS ROH + RON + RGFET _Int
(3)
æ
ö
÷
÷
ø
VDD
IOB + = min 4A,
ç
ç
è
RNMOS ROH + RON + RGFET _Int
where
•
•
•
RON: External turn-on resistance.
RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the
calculated value based on the gate drive loop resistance.
(4)
In this example:
VDD - VBDF
RNMOS ROH + RON + RGFET _Int 1.47 W 5 W + 2.2 W +1.5W
VDD
OH + RON + RGFET _Int 1.47 W 5 W + 2.2 W + 1.5 W
12 V -1.3 V
IOA +
=
=
» 2.2 A
» 2.5 A
(5)
(6)
12 V
IOB +
=
=
RNMOS
R
Therefore, the high-side and low-side peak source current is 2.2 A and 2.5 A respectively. Similarly, the peak
sink current can be calculated with:
æ
ö
÷
÷
ø
VDD - VBDF - VGDF
IOA - = min 6A,
ç
ç
è
ROL + ROFF RON + RGFET _Int
(7)
æ
ö
÷
÷
ø
VDD - VGDF
IOB - = min 6A,
ç
ç
è
ROL + ROFF RON + RGFET _Int
where
•
•
ROFF: External turn-off resistance.
VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is an
MSS1P4.
•
IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated
value based on the gate drive loop resistance.
(8)
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In this example,
VDD - VBDF - VGDF
12 V - 0.8 V - 0.75 V
0.55 W + 0 W + 1.5 W
IOA -
=
=
» 5.1 A
ROL + ROFF RON + RGFET _Int
(9)
VDD - VGDF
12 V - 0.75 V
IOB -
=
=
ROL + ROFF RON + RGFET _Int 0.55 W + 0 W + 1.5 W
» 5.5 A
(10)
Therefore, the high-side and low-side peak sink current is 5.1 A and 5.5 A respectively.
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and
undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other
hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the power
transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the
parasitic ringing period.
9.2.2.4 Estimate Gate Driver Power Loss
The total loss, PG, in the gate driver subsystem includes the power losses of the UCC20225-Q1 family (PGD) and
the power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not
included in PG and not discussed in this section.
PGD is the key power loss which determines the thermal safety-related limits of the UCC20225-Q1 family, and it
can be estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as
driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the
bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and
ambient temperature. 图 4 shows the per output channel current consumption vs. operating frequency with no
load. In this example, VVCCI = 5 V and VVDD = 12 V. The current on each power supply, with PWM switching from
0 V to 3.3 V at 200 kHz is measured to be IVCCI = 2 mA, and IVDDA = IVDDB = 1.5 mA. Therefore, the PGDQ can be
calculated with
PGDQ = VVCCI ´ IVCCI + VVDDA ´ IVDDA + VVDDB ´ IVDDB » 46 mW
(11)
The second component is switching operation loss, PGDO, with a given load capacitance which the driver charges
and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW, can be
estimated with
PGSW = 2 ´ VDD ´ QG ´ fSW
where
•
QG is the gate charge of the power transistor.
(12)
If a split rail is used to turn on and turn off, then VDD is the total difference between the positive rail to the
negative rail.
So, for this example application:
PGSW = 2 ´ 12 V ´ 100 nC ´ 200 kHz = 480 mW
(13)
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QG represents the total gate charge of the power transistor switching 400 V at 14 A, and is subject to change
with different testing conditions. The UCC20225-Q1 family's gate driver loss on the output stage, PGDO, is part of
PGSW. PGDO will be equal to PGSW if the external gate driver resistances and power transistor internal resistances
are 0 Ω, and all the gate driver loss is dissipated inside the UCC20225-Q1 family. If there are external turn-on
and turn-off resistance, the total loss will be distributed between the gate driver pull-up/down resistances,
external gate resistances, and power transistor internal resistances. Importantly, the pull-up/down resistance is a
linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however, it will be non-linear if
the source/sink current is saturated. Therefore, PGDO is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
æ
ç
ç
è
ö
÷
÷
ø
ROH RNMOS
PGSW
2
ROL
PGDO
=
+
ROH RNMOS + RON + RGFET _Int ROL + ROFF RON + RGFET _Int
(14)
In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC20225-Q1
family's gate driver loss can be estimated with:
æ
ö
5 W 1.47 W
480 mW
2
0.55 W
PGDO
=
+
» 120 mW
ç
÷
ç
÷
5 W 1.47 W + 2.2 W + 1.5 W 0.55 W + 0 W + 1.5 W
è
ø
(15)
Case 2 - Nonlinear Pull-Up/Down Resistor:
TR _ Sys
TF _ Sys
é
ù
ú
ê
PGDO = 2 ´ fSW ´ 4 A ´
V
- VOUT (t) dt + 6 A ´
VOUT (t) dt
A/B
(
)
DD
ò
A/B
ò
ê
ú
0
0
ê
ú
û
ë
where
•
VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off period. In cases where the
output is saturated for some time, this can be simplified as a constant current source (4 A at turn-on and 6 A at
turn-off) charging/discharging a load capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and
TF_Sys can be easily predicted.
(16)
For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO
will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull-
down based on the above discussion.
Total gate driver loss dissipated in the gate driver UCC20225-Q1 family, PGD, is:
PGD = PGDQ + PGDO = 46 mW + 120 mW = 166 mW
(17)
which is equal to 127 mW in the design example.
9.2.2.5 Estimating Junction Temperature
The junction temperature (TJ) of the UCC20225-Q1 family can be estimated with:
TJ = TC + YJT ´ PGD
where
•
TC is the UCC20225-Q1 family case-top temperature measured with a thermocouple or some other instrument,
and
•
ΨJT is the Junction-to-top characterization parameter from the Thermal Information table.
(18)
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with
metal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately
estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy
leaving through the top of the IC will be similar in both the testing environment and the application environment.
As long as the recommended layout guidelines are observed, junction temperature estimates can be made
accurately to within a few degrees Celsius. For more information, see the Semiconductor and IC Package
Thermal Metrics application report.
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9.2.2.6 Selecting VCCI, VDDA/B Capacitor
Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is
recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with
sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC
will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500
nF when a DC bias of 15 VDC is applied.
9.2.2.6.1 Selecting a VCCI Capacitor
A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total
current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for this
application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or
electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.
9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for
gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with
IVDD @ 200 kHz (No Load)
fSW
1.5 mA
QTotal = QG
+
= 100 nC +
= 107.5 nC
200 kHz
where
•
•
QG: Gate charge of the power transistor.
IVDD: The channel self-current consumption with no load at 200kHz.
(19)
(20)
Therefore, the absolute minimum CBoot requirement is:
QTotal
107.5 nC
CBoot
=
=
» 0.22 mF
DVDDA
0.5 V
where
•
ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.
In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by
the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.
Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the
VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.
CBoot = 1mF
(21)
To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with
a low capacitance value, in this example a 100 nF, in parallel with CBoot to optimize the transient performance.
注
Too large CBOOT can be detrimental. CBOOT may not be charged within the first few cycles
and VBOOT could stay below UVLO. As a result, the high-side FET will not follow input
signal commands for several cycles. Also during initial CBOOT charging cycles, the
bootstrap diode has highest reverse recovery current and losses.
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9.2.2.6.3 Select a VDDB Capacitor
Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as CVDD in 图
37) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current for
VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 0.22-µF MLCC are chosen for CVDD. If the
bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor, with
a value over 10 µF, should be used in parallel with CVDD
.
9.2.2.7 Dead Time Setting Guidelines
For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor
is important for preventing shoot-through during dynamic switching.
The UCC20225-Q1 family dead time specification in the electrical table is defined as the time interval from 90%
of one channel’s falling edge to 10% of the other channel’s rising edge (see 图 29). This definition ensures that
the dead time setting is independent of the load condition, and guarantees linearity through manufacture testing.
However, this dead time setting may not reflect the dead time in the power converter system, since the dead time
setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as well as
the input capacitance of the load transistor.
Here is a suggestion on how to select an appropriate dead time for UCC20225-Q1 family:
DTSetting = DTReq + TF _ Sys + TR _ Sys - TD(on)
where
•
•
DTsetting: UCC20225-Q1 family dead time setting in ns, DTSetting = 10 × RDT(in kΩ).
DTReq: System required dead time between the real VGS signal of the top and bottom switch with enough
margin, or ZVS requirement.
•
•
•
TF_Sys: In-system gate turn-off falling time at worst case of load, voltage/current conditions.
TR_Sys: In-system gate turn-on rising time at worst case of load, voltage/current conditions.
TD(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold.
(22)
In the example, DTSetting is set to 250-ns.
It should be noted that the UCC20225-Q1 family's dead time setting is decided by the DT pin configuration (See
Programmable Dead Time (DT) Pin), and it cannot automatically fine-tune the dead time based on system
conditions. It is recommended to parallel a ceramic capacitor, 2.2-nF or above, close to DT pin to achieve better
noise immunity and dead time matching.
30
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9.2.2.8 Application Circuits with Output Stage Negative Bias
When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and
TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on
and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below
the threshold. Below are a few examples of implementing negative gate drive bias.
图 38 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the
isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power
supply, VA, is equal to 25 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 25 V – 5.1 V ≈ 20 V.
The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for
a half-bridge configuration, and there will be steady state power consumption from RZ.
HV DC-Link
VDDA
ROFF
13
1
CA1
+
VA
œ
CIN
RZ
25 V
RON
OUTA
VSSA
12
11
2
3
4
5
6
7
CA2
VZ = 5.1 V
SW
Functional
Isolation
VDDB
10
9
OUTB
VSSB
Copyright © 2017, Texas Instruments Incorporated
8
图 38. Negative Bias with Zener Diode on Iso-Bias Power Supply Output
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图 39 shows another example which uses two supplies (or single-input-double-output power supply). Power
supply VA+ determines the positive drive output voltage and VA– determines the negative turn-off voltage. The
configuration for channel B is the same as channel A. This solution requires more power supplies than the first
example, however, it provides more flexibility when setting the positive and negative rail voltages.
HV DC-Link
VDDA
OUTA
ROFF
RON
13
12
1
2
3
4
5
6
7
CA1
+
VA+
œ
CIN
CA2
+
VA-
œ
VSSA
11
Functional
Isolation
SW
VDDB
10
9
OUTB
VSSB
Copyright © 2017, Texas Instruments Incorporated
8
图 39. Negative Bias with Two Iso-Bias Power Supplies
32
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The last example, shown in 图 40, is a single power supply configuration and generates negative bias through a
Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and the
bootstrap power supply can be used for the high side drive. This design requires the least cost and design effort
among the three solutions. However, this solution has limitations:
1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which
means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a fixed
duty cycle (~50%) such as variable frequency resonant converters or phase shift converters favor this
solution.
2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,
which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel)
diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%
duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in
the other two example circuits.
VDD
RBOOT
HV DC-Link
VDDA
CZ
VZ
ROFF
RON
13
12
11
1
2
3
4
5
6
7
OUTA
VSSA
CIN
CBOOT
RGS
SW
Functional
Isolation
VDD
VDDB
CZ
VZ
ROFF
RON
10
9
OUTB
VSSB
CVDD
RGS
8
VSS
Copyright © 2017, Texas Instruments Incorporated
图 40. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path
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9.2.3 Application Curves
图 41 and 图 42 shows the bench test waveforms for the design example shown in 图 37 under these conditions:
VCC = 5 V, VDD = 12 V, fSW = 200 kHz, VDC-Link = 400 V.
Channel 1 (Indigo): UCC20225-Q1 family's PWM pin signal.
Channel 2 (Cyan): Gate-source signal on the high side power transistor.
Channel 3 (Magenta): Gate-source signal on the low side power transistor.
In 图 41, PWM is sent a 3.3 V, 20% duty-cycle signal. The gate drive signals on the power transistor have a 250-
ns dead time, shown in the measurement section of 图 41. The dead time matching is 10-ns with the 250-ns
dead time setting. Note that with high voltage present, lower bandwidth differential probes are required, which
limits the achievable accuracy of the measurement.
图 42 shows a zoomed-in version of the waveform of 图 41, with measurements for propagation delay and
rising/falling time. Importantly, the output waveform is measured between the power transistors’ gate and source
pins, and is not measured directly from the driver OUTA and OUTB pins. Due to the split on and off resistors
(RON, ROFF), different sink and source currents, and the Miller plateau, different rising (60, 120 ns) and falling
time (25 ns) are observed in 图 42.
图 41. Bench Test Waveform for PWM and OUTA/B
图 42. Zoomed-In bench-test waveform
34
版权 © 2018–2019, Texas Instruments Incorporated
UCC20225-Q1, UCC20225A-Q1
www.ti.com.cn
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
10 Power Supply Recommendations
The recommended input supply voltage (VCCI) for UCC20225-Q1 family is between 3-V and 18-V. The
recommended output bias supply voltage (VDDA/VDDB) range is 6.5-V to 25-V for UCC20225A-Q1 and 9.2-V to
25-V for UCC20225-Q1. The lower end of this bias supply range is governed by the internal under voltage
lockout (UVLO) protection feature of each device. VDD and VCCI should not fall below their respective UVLO
thresholds for normal operation, or else gate driver outputs can become clamped low for >50µs by the UVLO
protection feature (for more information on UVLO see VDD, VCCI, and Under Voltage Lock Out (UVLO)). The
upper end of the VDDA/VDDB range depends on the maximum gate voltage of the power device being driven by
UCC20225-Q1 family, and should not exceed the recommended maximum VDDA/VDDB of 25-V.
A local bypass capacitor should be placed between the VDD and VSS pins, with a value of between 220 nF and
10 µF for device biasing. It is further suggested that an additional 100-nF capacitor be placed in parallel with the
device biasing capacitor for high frequency filtering. Both capacitors should be positioned as close to the device
as possible. Low ESR, ceramic surface mount capacitors are recommended.
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of
current drawn by the logic circuitry within the input side of UCC20225-Q1 family, this bypass capacitor has a
minimum recommended value of 100 nF.
版权 © 2018–2019, Texas Instruments Incorporated
35
UCC20225-Q1, UCC20225A-Q1
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
One must pay close attention to PCB layout in order to achieve optimum performance for the UCC20225-Q1
family. Below are some key points.
Component Placement:
•
Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins
and between the VDD and VSS pins to support high peak currents when turning on the external power
transistor.
•
•
•
To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the
source of the top transistor and the source of the bottom transistor must be minimized.
It is recommended to place the dead time setting resistor, RDT, and its bypassing capacitor close to DT pin of
UCC20225-Q1 family.
It is recommended to bypass using a ≈1nF low ESR/ESL capacitor, CDIS, close to DIS pin when connecting to
a µC with distance.
•
•
Grounding Considerations:
It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal
physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the
transistors. The gate driver must be placed as close as possible to the transistors.
•
Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-
referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is
recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This
recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and
area on the circuit board is important for ensuring reliable operation.
High-Voltage Considerations:
•
To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB
traces or copper below the driver device. PCB cutting or scoring beneath the IC are not recommended, since
this can severely exacerbate board warping and twisting issues.
•
For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could
operate with a DC-link voltage up to 700 VDC, one should try to increase the creepage distance of the PCB
layout between the high and low-side PCB traces.
Thermal Considerations:
•
A large amount of power may be dissipated by the UCC20225-Q1 family if the driving voltage is high, the load
is heavy, or the switching frequency is high (Refer to Estimate Gate Driver Power Loss for more details).
Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal
impedance (θJB).
•
•
Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority
on maximizing the connection to VSSA and VSSB (see 图 44 and 图 45). However, high voltage PCB
considerations mentioned above must be maintained.
If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and
VSSB pins to internal ground or power planes through multiple vias of adequate size. These vias should be
located close to the IC pins to maximize thermal conductivity. However, keep in mind that there shouldn’t be
any traces/coppers from different high voltage planes overlapping.
36
版权 © 2018–2019, Texas Instruments Incorporated
UCC20225-Q1, UCC20225A-Q1
www.ti.com.cn
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
11.2 Layout Example
图 43 shows a 2-layer PCB layout example with the signals and key components labeled.
图 43. Layout Example
图 44 and 图 45 shows top and bottom layer traces and copper.
注
There are no PCB traces or copper between the primary and secondary side, which
ensures isolation performance.
版权 © 2018–2019, Texas Instruments Incorporated
37
UCC20225-Q1, UCC20225A-Q1
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
www.ti.com.cn
Layout Example (接下页)
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the
creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node
VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.
图 44. Top Layer Traces and Copper
图 45. Bottom Layer Traces and Copper
图 46 and 图 47 are 3D layout pictures with top view and bottom views.
注
The location of the PCB cutout between the primary side and secondary sides, which
ensures isolation performance.
图 46. 3-D PCB Top View
图 47. 3-D PCB Bottom View
38
版权 © 2018–2019, Texas Instruments Incorporated
UCC20225-Q1, UCC20225A-Q1
www.ti.com.cn
ZHCSJ23C –NOVEMBER 2018–REVISED SEPTEMBER 2019
12 器件和文档支持
12.1 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 5. 相关链接
器件
产品文件夹
单击此处
单击此处
立即订购
单击此处
单击此处
技术文档
单击此处
单击此处
工具与软件
单击此处
单击此处
支持和社区
单击此处
单击此处
UCC20225-Q1
UCC20225A-Q1
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
•
隔离相关术语
12.3 认证
UL 在线认证目录，“FPPT2.E181974 非光学隔离器件 - 组件”，证书编号：20170718-E181974，
VDE Pruf- und Zertifizierungsinstitut 认证，工厂监督合格证书
CQC 在线认证目录，“GB4943.1-2011 数字隔离器证书”，证书编号：CQC18001186974
12.4 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.5 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.6 商标
E2E is a trademark of Texas Instruments.
12.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018–2019, Texas Instruments Incorporated
39
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC20225AQNPLRQ1
UCC20225AQNPLTQ1
UCC20225QNPLRQ1
UCC20225QNPLTQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VLGA
VLGA
VLGA
VLGA
NPL
NPL
NPL
NPL
13
13
13
13
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
UC20225AQ
NIAU
NIAU
NIAU
UC20225AQ
UCC20225Q
UCC20225Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Aug-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC20225AQNPLRQ1
UCC20225QNPLRQ1
VLGA
VLGA
NPL
NPL
13
13
3000
3000
330.0
330.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Aug-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC20225AQNPLRQ1
UCC20225QNPLRQ1
VLGA
VLGA
NPL
NPL
13
13
3000
3000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
NPL0013A
VLGA - 1 max height
S
C
A
L
E
2
.
5
0
0
LAND GRID ARRAY
5.1
4.9
A
B
PIN 1 INDEX
AREA
5.1
4.9
C
(0.7)
1 MAX
SEATING PLANE
0.08 C
4.15
2.075
(0.1) TYP
7
8
2X
3.9
SYMM
1
13
12X 0.65
0.35
13X
0.25
0.15
0.08
SYMM
PIN 1 ID
NOTE 3
C A B
C
0.7
0.6
13X
0.15
C B A
4222800/B 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Pin 1 indicator is electrically connected to pin 1.
www.ti.com
EXAMPLE BOARD LAYOUT
NPL0013A
VLGA - 1 max height
LAND GRID ARRAY
13X (0.65)
SYMM
1
13
13X (0.3)
SYMM
10X (0.65)
8
7
(R0.05) TYP
(4.15)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PACKAGE SOLDER PADS
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4222800/B 04/2017
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
NPL0013A
VLGA - 1 max height
LAND GRID ARRAY
SYMM
13X (0.65)
1
13
13X (0.3)
SYMM
10X (0.65)
8
7
(R0.05)
(4.15)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4222800/B 04/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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