UCC21220ADR [TI]
适用于 MOSFET 和 GaNFET 的具有禁用引脚和 5V UVLO 的 3.0kVrms 4A/6A 双通道隔离式栅极驱动器 | D | 16 | -40 to 125;型号: | UCC21220ADR |
厂家: | TEXAS INSTRUMENTS |
描述: | 适用于 MOSFET 和 GaNFET 的具有禁用引脚和 5V UVLO 的 3.0kVrms 4A/6A 双通道隔离式栅极驱动器 | D | 16 | -40 to 125 栅极驱动 驱动器 |
文件: | 总45页 (文件大小:1384K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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UCC21220, UCC21220A
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
具有高噪声抗扰度的 UCC21220、UCC21220A 4A/6A 双通道基本隔离式
和功能隔离式栅极驱动器
1 特性
•
工业运输和机器人
1
•
•
•
•
支持基本隔离和功能隔离
3 说明
CMTI 大于 100V/ns
UCC21220 和 UCC21220A 器件是具有 4A 峰值拉电
流和 6A 峰值灌电流的基本隔离式和功能隔离式双通道
栅极驱动器。它们设计用于在 PFC、隔离式直流/直流
和同步整流应用中驱动功率 MOSFET 和 GaNFET ,
借助超过 100V/ns 的共模瞬态抗扰度 (CMTI),可实现
快速开关性能和稳健的接地反弹保护。
4A 峰值拉电流、6A 峰值灌电流输出
开关参数:
–
–
–
40ns 最大传播延迟
5ns 最大延迟匹配
5.5ns 最大脉宽失真中,将最大脉宽失真 从
“5ns”更改为“5.5ns”
–
35µs 最大 VDD 上电延迟
这些器件可以配置为两个低侧驱动器、两个高侧驱动器
或半桥驱动器。可以将两个输出并联,以形成单个驱动
器,由于具有一流的延迟匹配性能,因此可以在重负载
条件下使驱动强度加倍。
•
高达 18V 的 VDD 输出驱动电源
5V 和 8V VDD UVLO 选项
–
•
•
•
•
•
工作温度范围 (TA) –40°C 至 125°C
窄体 SOIC-16 (D) 封装
抑制短于 5ns 的输入脉冲
TTL 和 CMOS 兼容输入
安全相关认证:
保护 功能 包括:DIS 引脚在设置为高电平时可同时关
断两个输出;INA/B 引脚可抑制短于 5ns 的输入瞬
态;输入和输出可以承受 –2V 的尖峰达 200ns,所有
电源都具有欠压锁定 (UVLO) 功能,有源下拉保护功能
可以在断电或悬空时将输出钳制在 2.1V 以下。
–
–
–
符合 DIN V VDE V 0884-11:2017-01 和 DIN
EN 61010-1 标准的 4242VPK 隔离(计划)
凭借这些 功能,这些器件可实现高效率、高功率密度
和稳健性,适用于多种电源 应用。
符合 UL 1577 标准且持续时长为 1 分钟的
3000VRMS 隔离
符合 GB4943.1-2011 标准的 CQC 认证(计
划)
器件信息(1)
器件型号
UCC21220
UCC21220A
封装
UVLO
8V
SOIC (16)
SOIC (16)
2 应用
5V
•
•
•
•
服务器电源
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
光伏逆变器、光伏电源优化器
电信砖型转换器
无线基础设施
典型应用
VDD
VCC
RBOOT
HV DC-Link
VCC
VDDA
INA
INB
ROFF
RON
16
15
14
PWM-A
RIN
1
2
3
4
5
OUTA
VSSA
CIN
PWM-B
RGS
CBOOT
VCCI
GND
DIS
CIN
mC
CVCC
SW
Functional
Isolation
VDD
DIS
I/O
VDDB
ROFF
RON
11
10
9
RDIS
CDIS
OUTB
VSSB
RGS
VCCI
CVDD
8
VSS
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLUSCK0
UCC21220, UCC21220A
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
www.ti.com.cn
目录
8.5 Power-up UVLO Delay to OUTPUT........................ 17
8.6 CMTI Testing........................................................... 18
Detailed Description ............................................ 19
9.1 Overview ................................................................. 19
9.2 Functional Block Diagram ....................................... 19
9.3 Feature Description................................................. 20
9.4 Device Functional Modes........................................ 23
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information.................................................. 7
7.5 Power Ratings........................................................... 7
7.6 Insulation Specifications............................................ 8
7.7 Safety-Related Certifications..................................... 9
7.8 Safety-Limiting Values .............................................. 9
7.9 Electrical Characteristics......................................... 10
7.10 Switching Characteristics...................................... 11
7.11 Thermal Derating Curves...................................... 11
7.12 Typical Characteristics.......................................... 12
Parameter Measurement Information ................ 16
8.1 Minimum Pulses...................................................... 16
8.2 Propagation Delay and Pulse Width Distortion....... 16
8.3 Rising and Falling Time ......................................... 16
8.4 Input and Disable Response Time.......................... 17
9
10 Application and Implementation........................ 24
10.1 Application Information.......................................... 24
10.2 Typical Application ................................................ 24
11 Power Supply Recommendations ..................... 34
12 Layout................................................................... 35
12.1 Layout Guidelines ................................................. 35
12.2 Layout Example .................................................... 36
13 器件和文档支持 ..................................................... 38
13.1 文档支持 ............................................................... 38
13.2 相关链接................................................................ 38
13.3 接收文档更新通知 ................................................. 38
13.4 社区资源................................................................ 38
13.5 商标....................................................................... 38
13.6 静电放电警告......................................................... 38
13.7 Glossary................................................................ 38
14 机械、封装和可订购信息....................................... 38
8
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision D (December 2018) to Revision E
Page
•
•
•
•
•
已更改 特性、 应用和 说明列表 部分 .................................................................................................................................... 1
已更改 将“功能方框图”更改为“典型应用” ............................................................................................................................... 1
Added UL certificate number ................................................................................................................................................. 9
Added maximum VCCI Power-up Delay Time: UVLO Rise to OUTA, OUTB...................................................................... 11
Added maximum VDDA, VDDB Power-up Delay Time: UVLO Rise to OUTA, OUTB ....................................................... 11
Changes from Revision C (August 2018) to Revision D
Page
•
已更改 将 UCC21220A 的销售状态从“产品预览”更改成了“初始发行版”。 ............................................................................. 1
Changes from Revision B (May 2018) to Revision C
Page
•
已添加 5V VDD UVLO threshold and hysteresis graph in Typical Characteristics section.................................................. 12
Changes from Revision A (December 2017) to Revision B
Page
•
•
已添加 添加了 UCC21220A 预告信息器件。.......................................................................................................................... 1
Changed DTI from 16µm to 17µm in Insulation Specifications table .................................................................................... 8
2
版权 © 2017–2019, Texas Instruments Incorporated
UCC21220, UCC21220A
www.ti.com.cn
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
Changes from Original (November 2017) to Revision A
Page
•
•
•
•
•
•
已更改 在特性 部分................................................................................................................................................................. 1
已更改 将数据表状态从预告信息 更改为产品数据 .................................................................................................................. 1
Clarified descriptions in Pin Functions table........................................................................................................................... 5
Separated figure titles and condition statements in Typical Characteristics section............................................................ 12
已添加 typical timing specifications to Power-up UVLO Delay to OUTPUT section ............................................................ 17
已添加 guideline to Layout Guidelines section..................................................................................................................... 35
Copyright © 2017–2019, Texas Instruments Incorporated
3
UCC21220, UCC21220A
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
www.ti.com.cn
5 Device Comparison Table
RECOMMENDED
VDD SUPPLY MIN.
DEVICE OPTIONS
UVLO
PACKAGE
UCC21220D
8-V
5-V
9.2-V
6.0-V
Narrow Body SOIC-16
Narrow Body SOIC-16
UCC21220AD
4
Copyright © 2017–2019, Texas Instruments Incorporated
UCC21220, UCC21220A
www.ti.com.cn
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
6 Pin Configuration and Functions
D Package
16-Pin SOIC
Top View
INA
INB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDA
OUTA
VSSA
NC
VCCI
GND
DIS
NC
NC
VDDB
OUTB
VSSB
NC
VCCI
Not to scale
Pin Functions
PIN
I/O(1)
DESCRIPTION
Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low
internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise
immunity. Bypass using a ≈ 1-nF low ESR/ESL capacitor close to DIS pin when connecting to a µC with
distance.
DIS
5
I
GND
INA
4
1
P
I
Primary-side ground reference. All signals in the primary side are referenced to this ground.
Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is pulled low
internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise
immunity.
Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is pulled low
internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise
immunity.
INB
NC
2
I
6
7
No internal connection.
12
13
15
10
OUTA
OUTB
O
O
Output of driver A. Connect to the gate of the A channel FET or IGBT.
Output of driver B. Connect to the gate of the B channel FET or IGBT.
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close
to the device as possible.
VCCI
VCCI
VDDA
3
8
P
P
P
This pin is internally shorted to pin 3.
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located
as close to the device as possible.
16
Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located
as close to the device as possible.
VDDB
11
P
VSSA
VSSB
14
9
P
P
Ground for secondary-side driver A. Ground reference for secondary side A channel.
Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1) P = power, G = ground, I = input, O = output
Copyright © 2017–2019, Texas Instruments Incorporated
5
UCC21220, UCC21220A
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
MAX
6
UNIT
V
Input bias pin supply voltage
Driver bias supply
VCCI to GND
VDDA-VSSA, VDDB-VSSB
20
V
VVDDA+0.5,
VVDDB+0.5
OUTA to VSSA, OUTB to VSSB
–0.5
–2
V
V
Output signal voltage
Input signal voltage
OUTA to VSSA, OUTB to VSSB, Transient for 200
ns(2)
VVDDA+0.5,
VVDDB+0.5
INA, INB, DIS to GND
INA, INB Transient to GND for 200ns(2)
–0.5
–2
VVCCI+0.5
VVCCI+0.5
150
V
V
(3)
Junction temperature, TJ
–40
–65
°C
°C
Storage temperature, Tstg
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Values are verified by characterization and are not production tested.
(3) To maintain the recommended operating conditions for TJ, see the Thermal Information.
7.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
V
VCCI
VCCI Input supply voltage
Driver output bias supply
3
UCC21220 – 8V UVLO Version
UCC21220A – 5V UVLO Version
9.2
6.0
–40
–40
18
V
VDDA,
VDDB
18
V
TJ
Junction Temperature
Ambient Temperature
130
125
°C
°C
TA
6
Copyright © 2017–2019, Texas Instruments Incorporated
UCC21220, UCC21220A
www.ti.com.cn
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
7.4 Thermal Information
UCC21220,
UCC21220A
THERMAL METRIC(1)
UNIT
D (SOIC)
16 PINS
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
68.5
30.5
22.8
17.1
22.5
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Power Ratings
VALUE
1825
15
UNIT
mW
mW
mW
PD
Power dissipation
VCCI = 5.5 V, VDDA/B = 12 V, INA/B = 3.3
V, 5.4 MHz 50% duty cycle square wave 1.0-
nF load
PDI
Power dissipation by transmitter side
Power dissipation by each driver side
PDA, PDB
905
Copyright © 2017–2019, Texas Instruments Incorporated
7
UCC21220, UCC21220A
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
www.ti.com.cn
7.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
Shortest pin-to-pin distance through air
VALUE
> 4
UNIT
mm
CLR
CPG
External clearance(1)
External creepage(1)
Shortest pin-to-pin distance across the package surface
> 4
mm
Distance through the
insulation
DTI
CTI
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
>17
µm
V
Comparative tracking index
Material group
> 600
I
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
I-IV
I-III
I-II
Overvoltage category per
IEC 60664-1
DIN V VDE V 0884-11:2017-01(2)
Maximum repetitive peak
VIORM
AC voltage (bipolar)
990
VPK
isolation voltage
AC voltage (sine wave); time dependent dielectric breakdown
(TDDB) test;
700
990
VRMS
VDC
VPK
Maximum working isolation
voltage
VIOWM
DC Voltage
Maximum transient isolation VTEST = VIOTM, t = 60 s (qualification);
VIOTM
VIOSM
4242
voltage
VTEST = 1.2 × VIOTM, t = 1 s (100% production)
Maximum surge isolation
voltage(3)
Test method per IEC 62368-1, 1.2/50 μs waveform,
VTEST = 1.3 × VIOSM = 7800 VPK (qualification)
6000
<5
VPK
Method a, After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
<5
qpd
Apparent charge(4)
pC
Method b1; At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM; tini = 1 s;
<5
Vpd(m) = 1.5 × VIORM , tm = 1 s
Barrier capacitance, input to
output(5)
CIO
RIO
VIO = 0.4 sin (2πft), f =1 MHz
0.5
pF
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Isolation resistance, input to
output(5)
VIO = 500 V at 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS =150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO = 3000 VRMS, t = 60 s. (qualification),
VTEST = 1.2 × VISO = 3600 VRMS, t = 1 s (100% production)
VISO
Withstand isolation voltage
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
8
Copyright © 2017–2019, Texas Instruments Incorporated
UCC21220, UCC21220A
www.ti.com.cn
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
7.7 Safety-Related Certifications
VDE
UL
CQC
Certified according to DIN V VDE V 0884-
11:2017-01 and DIN EN 61010-1 (VDE
0411-1):2011-07
Recognized under UL 1577 Component
Recognition Program
Certified according to GB 4943.1-2011
Basic Insulation Maximum Transient
Overvoltage, 4242 VPK
Maximum Repetitive Peak Voltage, 990
VPK
Maximum Surge Isolation Voltage, 6000
VPK
;
Basic insulation, Altitude ≤ 5000 m, Tropical
Climate, 660 VRMS maximum working voltage
Single protection, 3000 VRMS
Certificate Number: E181974
;
Planned for certification
Planned for certification
7.8 Safety-Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
SIDE
MIN
TYP
MAX
UNIT
R
θJA = 68.5ºC/W, VVDDA/B = 12 V, TJ =
Safety output supply
current
DRIVER A,
DRIVER B
IS
150°C, TA = 25°C
See 图 1
75
mA
INPUT
DRIVER A
DRIVER B
TOTAL
15
905
R
θJA = 68.5ºC/W, VVCCI = 5.5 V, TJ =
PS
TS
Safety supply power
Safety temperature(1)
150°C, TA = 25°C
See 图 2
mW
°C
905
1825
150
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
Copyright © 2017–2019, Texas Instruments Incorporated
9
UCC21220, UCC21220A
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
www.ti.com.cn
7.9 Electrical Characteristics
VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1uF capacitor from VDDA/B to VSSA/B, VVDDA = VVDDB = 12
V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, unless otherwise noted(1)(2)
.
PARAMETER
SUPPLY CURRENTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVCCI
VCCI quiescent current
VINA = 0 V, VINB = 0 V
1.5
1.0
2.5
2.0
1.8
mA
mA
mA
VDDA and VDDB quiescent
current
IVDDA, IVDDB
IVCCI
VINA = 0 V, VINB = 0 V
VCCI operating current
(f = 500 kHz) current per channel
(f = 500 kHz) current per channel,
COUT = 100 pF,
VVDDA, VVDDB = 12 V
VDDA and VDDB operating
current
IVDDA, IVDDB
2.5
mA
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCCI_ON
VVCCI_OFF
VVCCI_HYS
UVLO Rising threshold
UVLO Falling threshold
UVLO Threshold hysteresis
2.55
2.35
2.7
2.5
0.2
2.85
2.65
V
V
V
UCC21220A VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS (5-V UVLO Version)
VVDDA_ON
VVDDB_ON
,
UVLO Rising threshold
UVLO Falling threshold
UVLO Threshold hysteresis
5.0
4.7
5.5
5.2
0.3
5.9
5.6
V
V
V
VVDDA_OFF
VVDDB_OFF
,
VVDDA_HYS
VVDDB_HYS
,
UCC21220 VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS (8-V UVLO Version)
VVDDA_ON
VVDDB_ON
,
UVLO Rising threshold
UVLO Falling threshold
UVLO Threshold hysteresis
8
8.5
8
9
V
V
V
VVDDA_OFF
VVDDB_OFF
,
7.5
8.5
VVDDA_HYS
VVDDB_HYS
,
0.5
INA, INB AND DISABLE
VINAH, VINBH
VDISH
,
Input high threshold voltage
Input low threshold voltage
1.6
0.8
1.8
1
2
V
V
VINAL, VINBL
VDISL
,
1.25
VINA_HYS
VINB_HYS
VDIS_HYS
,
,
Input threshold hysteresis
0.8
V
OUTPUT
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
IOA+, IOB+
Peak output source current
Peak output sink current
4
6
A
A
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
IOA-, IOB-
IOUT = –10 mA, ROHA, ROHB do not
represent drive pull-up
ROHA, ROHB
Output resistance at high state
performance. See tRISE in
5
Ω
Switching Characteristics and
Output Stage for more details.
ROLA, ROLB
VOHA, VOHB
VOLA, VOLB
Output resistance at low state
Output voltage at high state
Output voltage at low state
IOUT = 10 mA
0.55
11.95
5.5
Ω
V
VVDD = 12 V, IOUT = –10 mA
VVDD = 12 V, IOUT = 10 mA
mV
Driver output (VOUTA, VOUTB
active pull down
)
VVDDA and VVDDB unpowered,
IOUTA, IOUTB = 200 mA
VOAPDA, VOAPDB
1.75
2.1
V
(1) Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless
otherwise noted).
(2) Parameters that has only typical values, are not production tested and guaranteed by design.
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7.10 Switching Characteristics
VVCCI = 3.3 V or 5.5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, load capacitance COUT = 0 pF, TJ = –40°C to +125°C, unless otherwise noted(1)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tRISE
Output rise time, see 图 28
CVDD = 10 µF, COUT = 1.8 nF,
VVDDA, VVDDB = 12 V, f = 1 kHz
5
16
ns
tFALL
tPWmin
Output fall time, see 图 28
CVDD = 10 µF, COUT = 1.8 nF ,
VVDDA, VVDDB = 12 V, f = 1 kHz
6
12
20
ns
ns
Minimum input pulse width that
passes to output,
see 图 25 and 图 26
10
Output does not change the state if
input signal less than tPWmin
tPDHL
tPDLH
tPWD
tDM
Propagation delay at falling edge,
see 图 27
INx high threshold, VINH, to 10% of
the output
28
28
40
40
5.5
5
ns
ns
ns
ns
Propagation delay at rising edge,
see 图 27
INx low threshold, VINL, to 90% of
the output
Pulse width distortion in each
channel, see 图 27
|tPDLHA – tPDHLA|, |tPDLHB– tPDHLB
|
Propagation delays matching,
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|,
see 图 27
f = 1 MHz
tVCCI+ to
OUT
VCCI Power-up Delay Time: UVLO
Rise to OUTA, OUTB,
See 图 30
40
22
59
35
INA or INB tied to VCCI
INA or INB tied to VCCI
µs
tVDD+ to
OUT
VDDA, VDDB Power-up Delay Time:
UVLO Rise to OUTA, OUTB
See 图 31
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM=1000 V;
High-level common-mode transient
immunity (See CMTI Testing)
|CMH|
|CML|
100
100
V/ns
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM=1000 V;
Low-level common-mode transient
immunity (See CMTI Testing)
(1) Parameters that has only typical values, are not production tested and guaranteed by design.
7.11 Thermal Derating Curves
100
80
60
40
20
0
2000
1600
1200
800
400
0
IVDDA/B for VDD=12V
IVDDA/B for VDD=18V
0
50
100
Ambient Temperature (°C)
150
200
0
50
100
Ambient Temperature (°C)
150
200
D001
D001
Current in Each Channel with Both Channels Running
Simultaneously
图 2. Thermal Derating Curve for Limiting Power Per VDE
图 1. Thermal Derating Curve for Limiting Current Per VDE
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7.12 Typical Characteristics
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, TA = 25°C, CL=0pF unless otherwise noted.
2.68
2.64
2.6
1.6
1.5
1.4
1.3
1.2
VCCI = 3.3V
VCCI = 5.0V
2.56
2.52
2.48
2.44
2.4
VCCI = 3.3V, fS=50kHz
VCCI = 3.3V, fS=1.0MHz
VCCI = 5.0V, fS=50kHz
VCCI = 5.0V, fS=1.0MHz
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D001
D001
No Load
INA = INB = GND
图 3. VCCI Quiescent Current
图 4. VCCI Operating Current - IVCCI
2.6
2.58
2.56
2.54
2.52
2.5
1.6
1.4
1.2
1
VCCI = 3.3V
VCCI = 5.0V
VDD = 12V
VDD = 18V
0.8
0
100 200 300 400 500 600 700 800 900 1000
Frequency (kHz)
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D001
D001
No Load
INA = INB = GND
图 5. VCCI Operating Current vs. Frequency
图 6. VDD Per Channel Quiescent Current (IVDDA, IVDDB)
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
3
2.8
2.6
2.4
2.2
2
VDD = 12V, fS=50kHz
VDD = 12V, fS=1.0MHz
VDD = 15V, fS=50kHz
VDD = 15V, fS=1.0MHz
1.8
1.6
1.4
1.2
1
VDD = 12V
VDD = 15V
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
0
100 200 300 400 500 600 700 800 900 1000
Frequency (kHz)
D001
D001
No Load
No Load
INA and INB both switching
图 7. VDD Per Channel Operating Current - IVDDA/B
)
图 8. Per Channel Operating Current (IVDDA/B) vs. Frequency
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Typical Characteristics (接下页)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, TA = 25°C, CL=0pF unless otherwise noted.
212
208
204
200
196
192
188
2.9
2.8
2.7
2.6
2.5
2.4
VVCCI_ON
VVCCI_OFF
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D001
D001
图 9. VCCI UVLO Threshold Voltage
图 10. VCCI UVLO Threshold Hysteresis Voltage
540
530
520
510
500
9
8.7
8.4
8.1
7.8
7.5
VVDD_ON
VVDD_OFF
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D001
D001
图 11. 8V VDD UVLO Threshold Voltage
图 12. 8V VDD UVLO Threshold Hysteresis
6
5.8
5.6
5.4
5.2
5
360
350
340
330
320
VVDD_ON
VVDD_OFF
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
UDV0L0O1
UDV0L0O1
图 13. 5V VDD UVLO Threshold Voltage
图 14. 5V VDD UVLO Threshold Hysteresis
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Typical Characteristics (接下页)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, TA = 25°C, CL=0pF unless otherwise noted.
875
850
825
800
775
750
2.5
IN/DIS High
IN/DIS Low
2
1.5
1
0.5
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D001
D001
图 15. INA/INB/DIS High and Low Threshold Voltage
图 16. INA/INB/DIS High and Low Threshold Hysteresis
10
8
37.5
OUTPUT Pull-Up
OUTPUT Pull-Down
Rising Edge (tPDLH
Falling Edge (tPDHL
)
)
35
32.5
30
6
27.5
25
4
2
22.5
0
20
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D001
D001
图 17. OUT Pullup and Pulldown Resistance
图 18. Propagation Delay, Rising and Falling Edge
3
2
3
2
Rising Edge
Falling Edge
1
1
0
0
-1
-2
-3
-1
-2
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D001
D001
tPDLH – tPDHL
图 19. Propagation Delay Matching, Rising and Falling Edge
图 20. Pulse Width Distortion
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Typical Characteristics (接下页)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, TA = 25°C, CL=0pF unless otherwise noted.
10
60
56
52
48
44
40
36
32
Rising
Falling
DIS Low to High
DIS High to Low
8
6
4
2
0
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D001
D001
CL = 1.8 nF
图 21. Rise Time and Fall Time
图 22. DISABLE Response Time
2.5
2
10
9
VDD Open
VDD = 0V
8
1.5
1
7
6
0.5
5
0
4
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
D001
D001
图 23. OUTPUT Active Pulldown Voltage
图 24. Minimum Pulse that Changes Output
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8 Parameter Measurement Information
8.1 Minimum Pulses
A typical 5-ns deglitch filter removes small input pulses introduced by ground bounce or switching transients. To
change the output stage on OUTA or OUTB, one has to assert longer pulses than tPW(min), typically 10 ns, to
guarantee an output state change. see 图 25 and 图 26 for detailed information of the operation of deglitch filter.
INx
VINH
VINL
VINL
VINH
INx
tPWM < tPWmin
tPWM < tPWmin
OUTx
OUTx
图 25. Deglitch Filter – Turn ON
图 26. Deglitch Filter – Turn OFF
8.2 Propagation Delay and Pulse Width Distortion
图 27 shows how one calculates pulse width distortion (tPWD) and delay matching (tDM) from the propagation
delays of channels A and B. It can be measured by ensuring that both inputs are in phase.
INA/B
tPDHLA
tPDLHA
tDM
OUTA
tPDLHB
tPDHLB
tPWDB = |tPDLHB t tPDHLB|
OUTB
图 27. Delay Matching and Pulse Width Distortion
8.3 Rising and Falling Time
图 28 shows the criteria for measuring rising (tRISE) and falling (tFALL) times. For more information on how short
rising and falling times are achieved see Output Stage
90%
80%
tRISE
tFALL
20%
10%
图 28. Rising and Falling Time Criteria
16
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8.4 Input and Disable Response Time
图 29 shows the response time of the disable function. For more information, see Disable Pin .
INA/B
VINL
VINH
VDISH
VDISL
DIS High
Response Time
DIS
DIS Low
Response Time
OUTA
tPDLH
90%
90%
tPDHL
10%
10%
10%
图 29. Disable Pin Timing
8.5 Power-up UVLO Delay to OUTPUT
Before the driver is ready to deliver a proper output state, there is a power-up delay from the UVLO rising edge
to output and it is defined as tVCCI+ to OUT for VCCI UVLO, which is 40 µs typically, and tVDD+ to OUT for VDD UVLO,
which is 22 µs typically. It is recommended to consider proper margin before launching PWM signal after the
driver VCCI and VDD bias supply is ready. 图 30 and 图 31 show the power-up UVLO delay timing diagram for
VCCI and VDD.
If INA or INB are active before VCCI or VDD have crossed above their respective on thresholds, the output will
not update until tVCCI+ to OUT or tVDD+ to OUT after VCCI or VDD crossing its UVLO rising threshold. However, when
either VCCI or VDD receive a voltage less than their respective off thresholds, there is <1µs delay, depending on
the voltage slew rate on the supply pins, before the outputs are held low. This asymmetric delay is designed to
ensure safe operation during VCCI or VDD brownouts.
VCCI,
INx
VCCI,
INx
VVCCI_ON
VVCCI_OFF
VDDx
OUTx
VDDx
OUTx
tVCCI+ to OUT
tVDD+ to OUT
VVDD_ON
VVDD_OFF
图 30. VCCI Power-up UVLO Delay
图 31. VDDA/B Power-up UVLO Delay
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8.6 CMTI Testing
图 32 is a simplified diagram of the CMTI testing configuration.
VCC
VDD
VDDA
OUTA
VSSA
INA
1
16
15
14
OUTA
INB
2
VCC
VCCI
3
GND
4
Functional
Isolation
DIS
5
VDDB
11
10
9
OUTB
OUTB
VSSB
GND
VCCI
8
VSS
Common Mode Surge
Generator
Copyright © 2017, Texas Instruments Incorporated
图 32. Simplified CMTI Testing Setup
18
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9 Detailed Description
9.1 Overview
In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are
often placed between the output of control devices and the gates of power transistors. There are several
instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.
This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V
logic signal capable of only delivering a few mA.
The UCC21220, UCC21220A are flexible dual gate drivers which can be configured to fit a variety of power
supply and motor drive topologies, as well as drive several types of transistors. UCC21220 and UCC21220A
have many features that allow it to integrate well with control circuitry and protect the gates it drives such as:
disable pin, and under voltage lock out (UVLO) for both input and output voltages. The UCC21220, UCC21220A
also hold its outputs low when the inputs are left open or when the input pulse is not wide enough. The driver
inputs are CMOS and TTL compatible for interfacing with digital and analog power controllers alike. Each
channel is controlled by its respective input pins (INA and INB), allowing full and independent control of each of
the outputs.
9.2 Functional Block Diagram
INA
1
16 VDDA
200 kW
Driver
MOD
DEMOD
Deglitch
Filter
VCCI
15 OUTA
14 VSSA
UVLO
VCCI 3,8
UVLO
GND
4
13 NC
12 NC
Functional Isolation
DIS
5
11 VDDB
Driver
50 kW
MOD
DEMOD
Deglitch
Filter
10 OUTB
UVLO
INB
2
9
VSSB
200 kW
NC
NC
7
6
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9.3 Feature Description
9.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
The UCC21220 and UCC21220A have an internal under voltage lock out (UVLO) protection feature on the
supply circuit blocks between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than
VVDD_ON at device start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the effected output
low, regardless of the status of the input pins (INA and INB).
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an
active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in 图 33). In this condition, the
upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through RCLAMP
.
In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device,
typically around 1.5V, when no bias power is available.
VDD
RHI_Z
Output
Control
OUT
RCLAMP
RCLAMP is activated
during UVLO
VSS
图 33. Simplified Representation of Active Pull Down Feature
The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is
ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is
bound to happen when the device starts switching and operating current consumption increases suddenly.
The input side of the UCC21220 and UCC21220A also have an internal under voltage lock out (UVLO) protection
feature. The device isn't active unless the voltage, VCCI, is going to exceed VVCCI_ON on start up. And a signal
will cease to be delivered when that pin receives a voltage less than VVCCI_OFF. And, just like the UVLO for VDD,
there is hystersis (VVCCI_HYS) to ensure stable operation.
表 1. VCCI UVLO Feature Logic
CONDITION
INPUTS
OUTPUTS
INA
H
L
INB
L
OUTA
OUTB
VCCI-GND < VVCCI_ON during device start up
VCCI-GND < VVCCI_ON during device start up
VCCI-GND < VVCCI_ON during device start up
VCCI-GND < VVCCI_ON during device start up
VCCI-GND < VVCCI_OFF after device start up
VCCI-GND < VVCCI_OFF after device start up
VCCI-GND < VVCCI_OFF after device start up
VCCI-GND < VVCCI_OFF after device start up
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
L
H
H
L
H
L
20
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表 2. VDD UVLO Feature Logic
CONDITION
INPUTS
OUTPUTS
INA
H
L
INB
OUTA
OUTB
VDD-VSS < VVDD_ON during device start up
VDD-VSS < VVDD_ON during device start up
VDD-VSS < VVDD_ON during device start up
VDD-VSS < VVDD_ON during device start up
VDD-VSS < VVDD_OFF after device start up
VDD-VSS < VVDD_OFF after device start up
VDD-VSS < VVDD_OFF after device start up
VDD-VSS < VVDD_OFF after device start up
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
L
H
L
9.3.2 Input and Output Logic Table
Assume VCCI, VDDA, VDDB are powered up (see VDD, VCCI, and Under Voltage Lock Out (UVLO) for more information on
UVLO operation modes), 表 3 shows the operation with INA, INB and DIS and the corresponding output state.
表 3. INPUT/OUTPUT Logic Table(1)
INPUTS
OUTPUTS
DIS
NOTE
INA
L
INB
L
OUTA
OUTB
L or Left Open
L or Left Open
L or Left Open
L or Left Open
L
L
L
H
L
Disables both driver outputs if asserted high, enables if set low or left
open. This pin is pulled low internally if left open. It is recommended to tie
this pin to ground if not used to achieve better noise immunity. Bypass
using a ≈1nF low ESR/ESL capacitor close to DIS pin when connecting to
a µC with distance.
L
H
H
L
H
H
H
H
H
It is recommended to tie INA/INB to ground if not used to achieve better
noise immunity.
Left Open Left Open L or Left Open
L
L
L
L
X
X
H
-
(1) "X" means L, H or left open.
9.3.3 Input Stage
The input pins (INA, INB, and DIS) of UCC21220 and UCC21220A are based on a TTL and CMOS compatible
input-threshold logic that is totally isolated from the VDD supply voltage. The input pins are easy to drive with
logic-level control signals (such as those from 3.3-V micro-controllers), since the UCC21220 and UCC21220A
have a typical high threshold (VINAH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature
(see 图 12 and 图 16). A wide hysterisis (VINA_HYS) of 0.8 V makes for good noise immunity and stable operation.
If any of the inputs are ever left open, internal pull-down resistors force the pin low. These resistors are typically
200 kΩ for INA/B and 50 kΩ for DIS (See Functional Block Diagram). However, it is still recommended to ground
an input if it is not being used.
Since the input side of UCC21220 or UCC21220A are isolated from the output drivers, the input signal amplitude
can be larger or smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater
flexibility when integrating with control signal sources, and allows the user to choose the most efficient VDD for
their MOSFET/IGBT gate. That said, the amplitude of any signal applied to INA or INB must never be at a
voltage higher than VCCI.
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9.3.4 Output Stage
The UCC21220 and UCC21220A output stages feature a pull-up structure which delivers the highest peak-
source current when it is most needed, during the Miller plateau region of the power-switch turn on transition
(when the power switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features
a P-channel MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel
MOSFET is to provide a boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly
turning on the N-channel MOSFET during a narrow instant when the output is changing states from low to high.
The on-resistance of this N-channel MOSFET (RNMOS) is approximately 1.47 Ω when activated.
The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device
only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on only
for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the
UCC21220 and UCC21220A pull-up stage during this brief turn-on phase is much lower than what is represented
by the ROH parameter.
The pull-down structure of the UCC21220 and UCC21220A are composed of an N-channel MOSFET. The ROL
parameter, which is also a DC measurement, is representative of the impedance of the pull-down state in the
device. Both outputs of the UCC21220 and UCC21220A are capable of delivering 4-A peak source and 6-A peak
sink current pulses. The output voltage swings between VDD and VSS provides rail-to-rail operation, thanks to
the MOS-out stage which delivers very low drop-out.
VDD
ROH
Shoot-
RNMOS
Input
Signal
Through
Prevention
Circuitry
OUT
VSS
ROL
Pull Up
图 34. Output Stage
22
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9.3.5 Diode Structure in UCC21220 and UCC21220A
图 35 illustrates the multiple diodes involved in the ESD protection components. This provides a pictorial
representation of the absolute maximum rating for the device.
VCCI
3,8
VDDA
16
20 V
15 OUTA
14 VSSA
6 V
6 V
INA
INB
DIS
1
2
5
11 VDDB
10 OUTB
20 V
4
9
GND
VSSB
图 35. ESD Structure
9.4 Device Functional Modes
9.4.1 Disable Pin
Setting the DIS pin high shuts down both outputs simultaneously. Pull the DIS pin low (or left open) allows
UCC21220 and UCC21220A to operate normally. The DIS pin is quite responsive, as far as propagation delay
and other switching parameters are concerned (See 图 22). The DIS pin is only functional (and necessary) when
VCCI stays above the UVLO threshold. It is recommended to tie this pin to GND if the DIS pin is not used to
achieve better noise immunity.
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The UCC21220 and UCC21220A effectively combine both isolation and buffer-drive functions. The flexible,
universal capability of the UCC21220 (with up to 5.5-V VCCI and 18-V VDDA/VDDB) allows the device to be
used as a low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or GaN transistor.
With integrated components, advanced protection features (UVLO and disable) and optimized switching
performance; the UCC21220 and UCC21220A enable designers to build smaller, more robust designs for
enterprise, telecom, automotive, and industrial applications with a faster time to market.
10.2 Typical Application
The circuit in 图 36 shows a reference design with UCC21220 or UCC21220A driving a typical half-bridge
configuration which could be used in several popular power converter topologies such as synchronous buck,
synchronous boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.
VDD
VCC
RBOOT
HV DC-Link
VCC
VDDA
INA
INB
ROFF
RON
16
15
14
PWM-A
1
2
3
4
5
RIN
OUTA
VSSA
CIN
PWM-B
RGS
CBOOT
VCCI
GND
DIS
CIN
mC
CVCC
SW
Functional
Isolation
VDD
DIS
VDDB
I/O
ROFF
RON
11
10
9
RDIS
CDIS
OUTB
VSSB
RGS
VCCI
CVDD
8
VSS
Copyright © 2017, Texas Instruments Incorporated
图 36. Typical Application Schematic
24
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Typical Application (接下页)
10.2.1 Design Requirements
表 4 lists reference design parameters for the example application: UCC21220 or UCC21220A driving 650-V
MOSFETs in a high side-low side configuration.
表 4. UCC21220 and UCC21220A Design Requirements
PARAMETER
Power transistor
VCC
VALUE
UNITS
IPP65R150CFD
-
V
5.0
12
VDD
V
Input signal amplitude
Switching frequency (fs)
DC link voltage
3.3
100
400
V
kHz
V
10.2.2 Detailed Design Procedure
10.2.2.1 Designing INA/INB Input Filter
It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)
the signal at the output. However, a small input RIN-CIN filter can be used to filter out the ringing introduced by
non-ideal layout or long PCB traces.
Such a filter should use an RIN in the range of 0 Ω to100 Ω and a CIN between 10 pF and 100 pF. In the
example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz.
When selecting these components, it is important to pay attention to the trade-off between good noise immunity
and propagation delay.
10.2.2.2 Select External Bootstrap Diode and its Series Resistor
The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side
transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation
in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.
Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver
circuit.
When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes
or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the loss
introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage is 400
VDC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good margin.
Therefore, a 600-V ultrafast diode, MURA160T3G, is chosen in this example.
A bootstrap resistor, RBOOT, is used to reduce the inrush current in DBOOT and limit the ramp up slew rate of
voltage of VDDA-VSSA during each switching cycle, especially when the VSSA(SW) pin has an excessive
negative transient voltage. The recommended value for RBOOT is between 1 Ω and 20 Ω depending on the diode
used. In the example, a current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode.
The estimated worst case peak current through DBoot is,
VDD - VBDF
RBoot
12V -1.5V
2.7W
IDBoot pk
=
=
ö 4A
(
)
where
•
VBDF is the estimated bootstrap diode forward voltage drop around 4 A.
(1)
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10.2.2.3 Gate Driver Output Resistor
The external gate driver resistors, RON/ROFF, are used to:
1. Limit ringing caused by parasitic inductances/capacitances.
2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.
3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.
4. Reduce electromagnetic interference (EMI).
As mentioned in Output Stage, the UCC21220 and UCC21220A have a pull-up structure with a P-channel
MOSFET and an additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A.
Therefore, the peak source current can be predicted with:
≈
’
VDD - VBDF
RNMOS ||ROH + RON + RGFET _Int
IOA+ = min 4A,
∆
÷
÷
◊
∆
«
(2)
≈
’
VDD
IOB+ = min 4A,
∆
÷
÷
◊
∆
«
RNMOS ||ROH + RON + RGFET _Int
where
•
•
•
RON: External turn-on resistance.
RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the
calculated value based on the gate drive loop resistance.
(3)
In this example:
VDD - VBDF
RNMOS ||ROH + RON + RGFET _Int 1.47W || 5W + 2.2W +1.5W
12V - 0.8V
IOA+
=
=
ö 2.3A
ö 2.5A
(4)
(5)
VDD
RNMOS ||ROH + RON + RGFET _Int 1.47W || 5W + 2.2W +1.5W
12V
IOB+
=
=
Therefore, the high-side and low-side peak source current is 2.3 A and 2.5 A respectively. Similarly, the peak
sink current can be calculated with:
≈
’
VDD - VBDF - VGDF
ROL +ROFF ||RON +RGFET _Int
IOA- = min 6A,
∆
÷
÷
◊
∆
«
(6)
≈
’
VDD - VGDF
ROL + ROFF ||RON + RGFET _Int
IOB- = min 6A,
∆
÷
÷
◊
∆
«
where
•
•
ROFF: External turn-off resistance, ROFF=0 in this example;
VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is an
MSS1P4.
•
IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated
value based on the gate drive loop resistance.
(7)
26
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In this example,
VDD - VBDF - VGDF
ROL +ROFF ||RON +RGFET _Int
12V - 0.8V -0.85V
0.55W + 0W +1.5W
IOA-
=
=
ö 5.0A
(8)
(9)
VDD - VGDF
12V - 0.85V
IOB-
=
=
ö 5.4A
ROL + ROFF ||RON + RGFET _Int 0.55W + 0W +1.5W
Therefore, the high-side and low-side peak sink current is 5.0 A and 5.4A respectively.
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and
undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other
hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the power
transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the
parasitic ringing period.
10.2.2.4 Estimating Gate Driver Power Loss
The total loss, PG, in the gate driver subsystem includes the power losses of the UCC21220 and UCC21220A
(PGD) and the power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode
loss is not included in PG and not discussed in this section.
PGD is the key power loss which determines the thermal safety-related limits of the UCC21220 and UCC21220A,
and it can be estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as
driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the
bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and
ambient temperature. 图 5 and 图 8shows the operating current consumption vs. operating frequency with no
load. In this example, VVCCI = 5 V and VVDD = 12 V. The current on each power supply, with INA/INB switching
from 0 V to 3.3 V at 100 kHz is measured to be IVCCI ≈ 2.5 mA, and IVDDA = IVDDB ≈ 1.5 mA. Therefore, the PGDQ
can be calculated with
PGDQ = VVCCI ìIVCCI + VVDDA ìIDDA + VVDDB ìIDDB = 50mW
(10)
The second component is switching operation loss, PGDO, with a given load capacitance which the driver charges
and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW, can be
estimated with
PGSW = 2ì VDD ìQG ì fSW
where
•
QG is the gate charge of the power transistor.
(11)
If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail
to the negative rail.
So, for this example application:
PGSW = 2ì12V ì100nCì100kHz = 240mW
(12)
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QG represents the total gate charge of the power transistor switching 480 V at 14 A provided by the datasheet,
and is subject to change with different testing conditions. The UCC21220 and UCC21220A gate driver loss on
the output stage, PGDO, is part of PGSW. PGDO will be equal to PGSW if the external gate driver resistances are
zero, and all the gate driver loss is dissipated inside the UCC21220 and UCC21220A. If there are external turn-
on and turn-off resistances, the total loss will be distributed between the gate driver pull-up/down resistances and
external gate resistances. Importantly, the pull-up/down resistance is a linear and fixed resistance if the
source/sink current is not saturated to 4 A/6 A, however, it will be non-linear if the source/sink current is
saturated. Therefore, PGDO is different in these two scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
≈
’
PGSW
2
ROH ||RNMOS
ROL
PGDO
=
ì
+
∆
∆
«
÷
÷
◊
ROH ||RNMOS +RON +RGFET _Int ROL +ROFF ||RON + RGFET _Int
(13)
In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC21220
and UCC21220A gate driver loss can be estimated with:
≈
∆
«
’
÷
◊
240mW
2
5W ||1.47W
0.55W
PGDO
=
ì
+
ö 60mW
5W ||1.47W + 2.2W +1.5W 0.55W + 0W +1.5W
(14)
Case 2 - Nonlinear Pull-Up/Down Resistor:
TR _ Sys
TF _ Sys
»
ÿ
Ÿ
…
PGDO = 2ì fSW ì 4A ì
VDD - VOUTA/B
t
( )
dt + 6A ì
VOUTA/B t dt
( )
(
)
—
—
…
Ÿ
0
0
…
Ÿ
⁄
where
•
VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be
simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load
capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.
(15)
For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO
will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull-
down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC21220
and UCC21220A, PGD, is:
PGD = PGDQ + PGDO
(16)
which is equal to 127 mW in the design example.
10.2.2.5 Estimating Junction Temperature
The junction temperature (TJ) of the UCC21220 and UCC21220A can be estimated with:
TJ = TC + YJT ìPGD
where
•
TC is the UCC21220 and UCC21220A case-top temperature measured with a thermocouple or some other
instrument, ψJT is the junction-to-top characterization parameter from the Thermal Information table.
Importantly, ψJT is developed based on JEDEC standard PCB board and it is subject to change when the PCB
board layout is different. For more information, please visit application report - semiconductor and IC package
thermal metrics.
(17)
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with
metal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately
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estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy
leaving through the top of the IC will be similar in both the testing environment and the application environment.
As long as the recommended layout guidelines are observed, junction temperature estimates can be made
accurately to within a few degrees Celsius. For more information, see the Layout Guidelines and Semiconductor
and IC Package Thermal Metrics application report.
10.2.2.6 Selecting VCCI, VDDA/B Capacitor
Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is
recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with
sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC
will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500
nF when a DC bias of 15 VDC is applied.
10.2.2.6.1 Selecting a VCCI Capacitor
A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total
current consumption, which is only a few mA. Therefore, a 25-V MLCC with over 100 nF is recommended for this
application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or
electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.
10.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for
gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with
IVDD @100kHz No Load
(
fSW
)
= 100nC +
1.5mA
QTotal = QG +
= 115nC
100kHz
where
•
•
•
QG: Gate charge of the power transistor.
IVDD: The channel self-current consumption with no load at 100kHz.
(18)
(19)
Therefore, the absolute minimum CBoot requirement is:
QTotal
115nC
0.5V
CBoot
=
=
= 230nF
DVVDDA
where
•
ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.
In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by
the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.
Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the
VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.
CBoot=1ꢀF
(20)
To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with
a low capacitance value, in this example a 100 nF, in parallel with CBoot to optimize the transient performance.
注
Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and
VBOOT could stay below UVLO. As a result, the high-side FET does not follow input signal
command. Also during initial CBOOT charging cycles, the bootstrap diode has highest
reverse recovery current and losses.
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10.2.2.6.3 Select a VDDB Capacitor
Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as CVDD in 图
36) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current for
VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for CVDD. If the
bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor with
a value over 10 µF, should be used in parallel with CVDD
.
10.2.2.7 Application Circuits with Output Stage Negative Bias
When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and
TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on
and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below
the threshold. Below are a few examples of implementing negative gate drive bias.
图 37 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the
isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power
supply, VA, is equal to 17 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 17 V – 5.1 V ≈ 12 V.
The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for
a half-bridge configuration, and there will be steady state power consumption from RZ.
HV DC-Link
VDDA
ROFF
16
1
CA1
+
VA
œ
CIN
RZ
RON
OUTA
VSSA
15
14
2
3
4
5
CA2
VZ
SW
Functional
Isolation
VDDB
11
10
9
OUTB
VSSB
Copyright © 2017, Texas Instruments Incorporated
8
图 37. Negative Bias with Zener Diode on Iso-Bias Power Supply Output
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图 38 shows another example which uses two supplies (or single-input-double-output power supply). Power
supply VA+ determines the positive drive output voltage and VA– determines the negative turn-off voltage. The
configuration for channel B is the same as channel A. This solution requires more power supplies than the first
example, however, it provides more flexibility when setting the positive and negative rail voltages.
HV DC-Link
VDDA
OUTA
ROFF
RON
16
15
1
2
3
4
5
CA1
+
VA+
œ
CIN
CA2
+
VA-
œ
VSSA
SW
14
Functional
Isolation
VDDB
11
10
9
OUTB
VSSB
Copyright © 2017, Texas Instruments Incorporated
8
图 38. Negative Bias with Two Iso-Bias Power Supplies
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The last example, shown in 图 39, is a single power supply configuration and generates negative bias through a
Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and the
bootstrap power supply can be used for the high side drive. This design requires the least cost and design effort
among the three solutions. However, this solution has limitations:
1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which
means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a fixed
duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors which favor this
solution.
2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,
which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel)
diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%
duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in
the other two example circuits.
VDD
RBOOT
HV DC-Link
VDDA
CZ
VZ
ROFF
RON
16
15
14
1
2
3
4
5
OUTA
VSSA
CIN
CBOOT
RGS
SW
Functional
Isolation
VDD
VDDB
CZ
VZ
ROFF
RON
11
10
9
OUTB
VSSB
CVDD
RGS
8
VSS
Copyright © 2017, Texas Instruments Incorporated
图 39. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path
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10.2.3 Application Curves
图 40 and 图 41 shows the bench test waveforms for the design example shown in 图 36 under these conditions:
VCC = 5.0 V, VDD = 12 V, fSW = 100 kHz, VDC-Link = 400 V.
Channel 1 (Yellow): INA pin signal.
Channel 2 (Blue): INB pin signal.
Channel 3 (Pink): Gate-source signal on the high side power transistor.
Channel 4 (Green): Gate-source signal on the low side power transistor.
In 图 40, INA and INB are sent complimentary 3.3-V, 20%/80% duty-cycle signals with 200ns deadtime. The gate
drive signals on the power transistor have a 200-ns dead time with 400V high voltage on the DC-Link, shown in
the measurement section of 图 40. Note that with high voltage present, lower bandwidth differential probes are
required, which limits the achievable accuracy of the measurement.
图 41 shows a zoomed-in version of the waveform of 图 40, with measurements for propagation delay and
deadtime. Importantly, the output waveform is measured between the power transistors’ gate and source pins,
and is not measured directly from the driver's OUTA and OUTB pins.
图 40. Bench Test Waveform for INA/B and OUTA/B
图 41. Zoomed-In bench-test waveform
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11 Power Supply Recommendations
The recommended input supply voltage (VCCI) for UCC21220 and UCC21220A is between 3 V and 5.5 V. The
output bias supply voltage (VDDA/VDDB) range from 9.2V to 18V. The lower end of this bias supply range is
governed by the internal under voltage lockout (UVLO) protection feature of each device. One mustn’t let VDD or
VCCI fall below their respective UVLO thresholds (For more information on UVLO see VDD, VCCI, and Under
Voltage Lock Out (UVLO)). The upper end of the VDDA/VDDB range depends on the maximum gate voltage of
the power device being driven by UCC21220 and UCC21220A. The UCC21220 and UCC21220A have a
recommended maximum VDDA/VDDB of 18 V.
A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned
as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further
suggested that one place two such capacitors: one with a value of ≈10-µF for device biasing, and an additional
≤100-nF capacitor in parallel for high frequency filtering..
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of
current drawn by the logic circuitry within the input side of UCC21220 and UCC21220A, this bypass capacitor
has a minimum recommended value of 100 nF.
34
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12 Layout
12.1 Layout Guidelines
Consider these PCB layout guidelines for in order to achieve optimum performance for the UCC21220 and
UCC21220A.
12.1.1 Component Placement Considerations
•
Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins
and between the VDD and VSS pins to support high peak currents when turning on the external power
transistor.
•
•
To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the
source of the top transistor and the source of the bottom transistor must be minimized.
It is recommended to bypass using a ≥1-nF low ESR/ESL capacitor, CDIS, close to DIS pin when connecting
to a μC with distance
12.1.2 Grounding Considerations
•
It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal
physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the
transistors. The gate driver must be placed as close as possible to the transistors.
•
Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-
referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is
recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This
recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and
area on the circuit board is important for ensuring reliable operation.
12.1.3 High-Voltage Considerations
•
To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB
traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination
that may compromise the UCC21220 and UCC21220A isolation performance.
•
For half-bridge, or high-side/low-side configurations, one should try to increase the clearance distance of the
PCB layout between the high and low-side PCB traces.
12.1.4 Thermal Considerations
•
A large amount of power may be dissipated by the UCC21220 and UCC21220A if the driving voltage is high,
the load is heavy, or the switching frequency is high (Refer to Estimating Gate Driver Power Loss for more
details). Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction to
board thermal impedance (θJB).
•
•
Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority
on maximizing the connection to VSSA and VSSB (See 图 43 and 图 44). However, high voltage PCB
considerations mentioned above must be maintained.
If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and
VSSB pins to internal ground or power planes through multiple vias of adequate size. Ensure that no traces
or coppers from different high-voltage planes overlap.
版权 © 2017–2019, Texas Instruments Incorporated
35
UCC21220, UCC21220A
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
www.ti.com.cn
12.2 Layout Example
图 42 shows a 2-layer PCB layout example with the signals and key components labeled.
Input Filters
(Top Layer)
PCB Cutout
Bootstrap Caps
(Bot. Layer)
Bootstrap Diode
(Bot. Layer)
PWM Input
(Top Layer)
To High Side
Transistor
VCCI Caps.
(Top Layer)
GND plane
(Bot. Layer)
To Low Side
Transistor
VDD Caps.
(Bot. Layer)
图 42. Layout Example
图 43 and 图 44 shows top and bottom layer traces and copper.
注
There are no PCB traces or copper between the primary and secondary side, which
ensures isolation performance.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the
creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node
VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.
图 43. Top Layer Traces and Copper
图 44. Bottom Layer Traces and Copper
36
版权 © 2017–2019, Texas Instruments Incorporated
UCC21220, UCC21220A
www.ti.com.cn
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
Layout Example (接下页)
图 45 and 图 46 are 3D layout pictures with top view and bottom views.
注
The location of the PCB cutout between the primary side and secondary sides, which
ensures isolation performance.
图 46. 3-D PCB Bottom View
图 45. 3-D PCB Top View
版权 © 2017–2019, Texas Instruments Incorporated
37
UCC21220, UCC21220A
ZHCSH68E –NOVEMBER 2017–REVISED MAY 2019
www.ti.com.cn
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档
请参阅如下相关文档:
•
隔离相关术语
13.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件,以及申请样片或购买产品的快速链
接。
表 5. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
UCC21220
UCC21220A
13.3 接收文档更新通知
要接收文档更新通知,请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产品
信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.5 商标
E2E is a trademark of Texas Instruments.
13.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
13.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
38
版权 © 2017–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC21220AD
UCC21220ADR
UCC21220D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
16
16
16
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
21220A
2500 RoHS & Green
40 RoHS & Green
2500 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
21220A
21220
21220
UCC21220DR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC21220ADR
UCC21220ADR
UCC21220DR
UCC21220DR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
16
16
16
16
2500
2500
2500
2500
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
6.5
6.5
6.5
6.5
10.3
10.3
10.3
10.3
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UCC21220ADR
UCC21220ADR
UCC21220DR
UCC21220DR
SOIC
SOIC
SOIC
SOIC
D
D
D
D
16
16
16
16
2500
2500
2500
2500
356.0
350.0
350.0
356.0
356.0
350.0
350.0
356.0
35.0
43.0
43.0
35.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-May-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
UCC21220AD
UCC21220AD
UCC21220D
UCC21220D
D
D
D
D
SOIC
SOIC
SOIC
SOIC
16
16
16
16
40
40
40
40
505.46
506.6
6.76
8
3810
3940
3810
3940
4
4.32
4
505.46
506.6
6.76
8
4.32
Pack Materials-Page 3
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Copyright © 2023,德州仪器 (TI) 公司
相关型号:
UCC21220D
适用于 MOSFET 和 GaNFET 的具有禁用引脚和 8V UVLO 的 3.0kVrms 4A/6A 双通道隔离式栅极驱动器 | D | 16 | -40 to 125
TI
UCC21220DR
适用于 MOSFET 和 GaNFET 的具有禁用引脚和 8V UVLO 的 3.0kVrms 4A/6A 双通道隔离式栅极驱动器 | D | 16 | -40 to 125
TI
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