UCC20520_技术文档

UCC20520

ZHCSFN1A –NOVEMBER 2016 –REVISED JANUARY 2022

具有单输入的UCC205204A/6A、5.7 kV_RMS隔离式双通道栅极驱动器

1 特性

3 说明

• 单输入、双输出

• 工作温度范围：–40 至125° C

• 开关参数：

UCC20520 是一款隔离式单输入、双通道栅极驱动

器，其峰值拉电流为4A，峰值灌电流为6A。该器件设

计用于驱动高达 5MHz 的功率 MOSFET、IGBT 和

SiC MOSFET，具有一流的传播延迟和脉宽失真度。

– 19ns 典型传播延迟

– 10ns 最小脉冲宽度

– 5ns 最大延迟匹配

– 6ns 最大脉宽失真

输入侧通过 5.7kV_RMS增强型隔离层与两个输出驱动器

隔离，具有最少100V/ns 的共模瞬态抗扰度 (CMTI) 。

两个次级侧驱动器之间的内部功能隔离，支持的工作电

压高达1500 V_DC。

• 共模瞬态抗扰度(CMTI) 大于100V/ns

• 浪涌抗扰度高达12.8kV

• 隔离栅寿命大于40 年

• 4A 峰值拉电流、6A 峰值灌电流输出

• TTL 和CMOS 兼容输入

• 3V 至18V 输入VCCI 范围，可与数字控制器和模

拟控制器连接

• 高达25V 的VDD 输出驱动电源

• 可编程死区时间

• 抑制短于5ns 的输入脉冲和噪声瞬态

• 快速禁用电源定序

该驱动器可用于具有可编程死区时间 (DT) 的半桥驱动

器。禁用引脚在设为高电平时可同时关断两个输出，并

在开路或接地时允许正常运行。作为一种故障安全措

施，初级侧逻辑故障强制两个输出均为低电平。

此器件接受高达 25V 的VDD 电源电压。3V 到18V 的

宽输入电压 VCCI 范围使得该驱动器适用于与模拟和数

字控制器连接。所有电源电压引脚都具有欠压锁定

(UVLO) 保护功能。

凭借所有这些高级特性，UCC20520 能够在各种各样

的电源应用中实现高效率、高电源密度和稳健性。

• 业界通用的宽体SOIC-16 (DW) 封装

• 安全相关及监管批准：

– 符合DIN V VDE V 0884-11:2017-01 标准的

8000V_PK隔离

– 符合UL 1577 标准且长达1 分钟的5700V_RMS

隔离

器件信息

封装⁽¹⁾

封装尺寸（标称值）

零件编号

UCC20520

DW SOIC (16)

10.30mm × 7.50mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

– 获得CSA 认证，符合IEC 60950-1、IEC

62368-1、IEC 61010-1 和IEC 60601-1 终端设

备标准

VCCI 3,8

16 VDDA

– 获得CQC 认证，符合GB4943.1-2011 标准

Driver

DEMOD UVLO

MOD

15 OUTA

14 VSSA

PWM

DIS

1

5

2 应用

• 隔离式交流/直流电源转换器

• 服务器、电信、IT 和工业基础设施

• 电机驱动和直流/交流光伏逆变器

• LED 照明

Disable,

UVLO

and

13 NC

12 NC

NC 2,7

Functional Isolation

Deadtime

DT

6

11 VDDB

10 OUTB

• 感应加热

• 不间断电源(UPS)

Driver

MOD

DEMOD UVLO

• HEV 和BEV 电池充电器

GND

4

9

VSSB

功能框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSCN0

UCC20520

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ZHCSFN1A –NOVEMBER 2016 –REVISED JANUARY 2022

Table of Contents

7.3 PWM Input and Disable Response Time.................. 15

7.4 Programable Dead Time...........................................16

7.5 CMTI Testing.............................................................16

8 Detailed Description......................................................17

8.1 Overview...................................................................17

8.2 Functional Block Diagram.........................................17

8.3 Feature Description...................................................18

8.4 Device Functional Modes..........................................21

9 Application and Implementation..................................23

9.1 Application Information............................................. 23

9.2 Typical Application.................................................... 23

10 Layout...........................................................................35

10.1 Layout Guidelines................................................... 35

10.2 Layout Example...................................................... 36

11 Device and Documentation Support..........................38

11.1 Documentation Support.......................................... 38

11.2 接收文档更新通知................................................... 38

11.3 支持资源..................................................................38

11.4 Trademarks............................................................. 38

11.5 Electrostatic Discharge Caution..............................38

11.6 术语表..................................................................... 38

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Power Ratings.............................................................5

6.6 Insulation Specifications............................................. 6

6.7 Safety-Related Certifications...................................... 7

6.8 Safety-Limiting Values................................................ 7

6.9 Electrical Characteristics.............................................8

6.10 Switching Characteristics..........................................9

6.11 Insulation Characteristics Curves............................10

6.12 Typical Characteristics............................................ 11

7 Parameter Measurement Information..........................15

7.1 Propagation Delay and Pulse Width Distortion.........15

7.2 Rising and Falling Time.............................................15

4 Revision History

Changes from Revision * (November 2016) to Revision A (January 2022)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 将特性中的最大脉宽失真值从“5ns”更改为“6ns”....................................................................................... 1

• Changed maximum pulse width distortion specification in 节6.10 from "5 ns" to "6 ns"....................................9

• Updated bench test waveform colors for better readability only. No data or measurment changes. ...............33

2

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5 Pin Configuration and Functions

PWM

NC

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VDDA

OUTA

VSSA

NC

VCCI

GND

DISABLE

DT

NC

VDDB

OUTB

VSSB

NC

VCCI

Not to scale

图5-1. DW Package, 16-Pin SOIC (Top View)

表5-1. Pin Functions

TYPE1

DESCRIPTION

NAME

NO.

Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled

low internally if left open. It is recommended to tie this pin to ground if not used to achieve

better noise immunity.

DISABLE

5

I

Programmable dead time function.

Tying DT to VCCI disables the DT function with dead time ≅ 0 ns. Leaving DT open sets the

dead time to <15 ns. Placing a 500-Ωto 500-kΩresistor (R_DT) between DT and GND

DT

6

adjusts dead time according to: DT (in ns) = 10 × R_DT(in kΩ). It is recommended to parallel

a ceramic capacitor, ≥2.2-nF, with R_DTto achieve better noise immunity.

GND

NC

4

2

P

Primary-side ground reference. All signals in the primary side are referenced to this ground.

No connection.

–

NC

7

NC

12

13

NC

Output of driver A. Connect to the gate of the A channel FET or IGBT. Output A is in phase

with PWM input with a propagation delay

OUTA

OUTB

PWM

15

10

1

O

I

Output of driver B. Connect to the gate of the B channel FET or IGBT. Output B is always

complementary to output A with a programmed dead time.

PWM input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if

left open.

Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor

located as close to the device as possible.

VCCI

VDDA

3

8

P

Primary-side supply voltage. This pin is internally shorted to pin 3.

Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL

capacitor located as close to the device as possible.

16

Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL

capacitor located as close to the device as possible.

VDDB

11

P

VSSA

VSSB

14

9

P

Ground for secondary-side driver A. Ground reference for secondary side A channel.

Ground for secondary-side driver B. Ground reference for secondary side B channel.

1. I = input, O = output, I/O = input or output, FB = feedback, G = ground, P = power

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

20

UNIT

V

VCCI to GND

VDDA-VSSA, VDDB-VSSB

30

V

V_VDDA+0.3,

V_VDDB+0.3

OUTA to VSSA, OUTB to VSSB

V

–0.3

–2

V_VDDA+0.3,

V_VDDB+0.3

OUTA to VSSA, OUTB to VSSB, Transient for 200 ns

PWM, DIS, DT to GND

PWM Transient for 50 ns

VSSA-VSSB, VSSB-VSSA

V_VCCI+0.3

1500

V

–0.3

–5

V

(2)

Junction temperature, T_J

150

°C

–40

–65

Storage temperature, T_stg

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) To maintain the recommended operating conditions for T_J, see the 节6.4.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VCCI

VCCI Input supply voltage

Driver output bias supply

3

18

V

VDDA,

VDDB

9.2

25

V

T_A

T_J

Ambient Temperature

Junction Temperature

125

130

°C

–40

4

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6.4 Thermal Information

UCC20520

UNIT

DW-16 (SOIC)

THERMAL METRIC⁽¹⁾

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

78.1

11.1

48.4

12.5

48.4

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Power Ratings

VALUE

1.05

UNIT

W

P_D

Power dissipation by UCC20520DW

P_DI

Power dissipation by primary side of

UCC20520DW

VCCI = 18 V, VDDA/B = 12 V, PWM = 3.3 V,

3 MHz 50% duty cycle square wave 1-nF

load

0.05

W

P_DA, P_DB

Power dissipation by secondary driver side of

UCC20520DW

0.5

W

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6.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

VALUE

UNIT

CLR

CPG

External clearance⁽¹⁾

Shortest terminal to terminal distance through air

> 8

mm

Shortest terminal to terminal distance across the package

surface

External creepage⁽¹⁾

> 8

mm

DTI

CTI

Distance through insulation

Comparative tracking index

Material group

Distance through internal isolation (internal clearance)

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

>21

> 600

I

µm

V

I-IV

I-III

Rated mains voltage ≤600 V_RMS

Overvoltage category per

IEC 60664-1

Rated mains voltage ≤1000 V_RMS

DIN V VDE 0884-10 (VDE V 0884-10): 2006-2012⁽²⁾

Maximum repetitive peak

isolation voltage

V_IORM

AC voltage (bipolar)

2121

V_PK

1500

2121

V_RMS

V_DC

Maximum isolation working

voltage

Time dependent dielectric breakdown (TDDB) test, (See 图

6-1)

V_IOWM

V_TEST= V_IOTM

t = 60 sec (qualification)

t = 1 sec (100% production)

Maximum transient isolation

voltage

V_IOTM

8000

<5

V_PK

Maximum surge isolation

voltage⁽³⁾

Test method per IEC 60065, 1.2/50 µs waveform, V_TEST= 1.6

× V_IOSM= 12800 V_PK(qualification)

V_IOSM

V_PK

Method a, After Input/Output safety test subgroup 2/3. V_ini

V_IOTM, t_ini= 60s;

=

V_pd(m)= 1.2 X V_IORM= 2545 V_PK, t_m= 10s

Method a, After environmental tests subgroup 1. V_ini= V_IOTM

,

t_ini= 60s;

<5

q_pd

Apparent charge⁽⁴⁾

pC

V_pd(m)= 1.6 X V_IORM= 3394 V_PK, t_m= 10s

Method b1; At routine test (100% production) and

preconditioning (type test)

<5

V_ini= V_IOTM; t_ini= 1s;

V_pd(m)= 1.875 * V_IORM= 3977 V_PK, t_m= 1s

Barrier capacitance, input to

output⁽⁵⁾

C_IO

R_IO

1.2

pF

V_IO= 0.4 sin (2πft), f =1 MHz

V_IO= 500 V at T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

Isolation resistance, input to

output

V_IO= 500 V at 100°C ≤T_A≤125°C

V_IO= 500 V at T_S=150°C

Ω

Pollution degree

Climatic category

2

40/125/21

UL 1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 sec. (qualification),

V_TEST= 1.2 × V_ISO= 6840V_RMS, t = 1 sec (100% production)

V_ISO

Withstand isolation voltage

5700

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the

isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in

certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these

specifications.

(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings

shall be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device.

6

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6.7 Safety-Related Certifications

VDE

CSA

UL

CQC

Certified according to DIN VDE V

0884-10 (VDE V

Approved under CSA Component

Acceptance Notice 5A, IEC

60950-1 and IEC 60601-1

Certified according to UL 1577

component recognition program GB 4943.1-2011

Certified according to

0884-10):2006-12 and DIN EN

60950-1 (VDE 0805 Teil

1):2011-01

Reinforced insulation maximum

transient isolation voltage,

Reinforced insulation,

Altitude ≤5000 m,

Tropical climate, 400 V_RMS

maximum working voltage

8000 V_PK

maximum repetitive peak

isolation voltage,

;

Reinforced insulation per CSA

60950-1-07+A1+A2 and IEC

60950-1 2nd Ed.

Single protection,

5700 V_RMS

2121 V_PK

;

maximum surge isolation voltage,

8000 V_PK

Certification number:

40040142

File number:

E181974

Certification number:

CQC16001155011

Agency qualification planned

6.8 Safety-Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of

the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat

the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

SIDE

MIN

TYP

MAX

UNIT

R

_θJA= 78.1°C/W, VDDA/B = 12 V, T_A=

DRIVER A,

DRIVER B

25°C, T_J= 150°C

64

mA

Safety output supply

current

See 图6-2

I_S

R

_θJA= 78.1°C/W, VDDA/B = 25 V, T_A=

DRIVER A,

DRIVER B

31

mA

25°C, T_J= 150°C

INPUT

DRIVER A

DRIVER B

TOTAL

50

775

R

_θJA= 78.1°C/W, T_A= 25°C, T_J= 150°C

P_S

T_S

Safety supply power

Safety temperature

mW

°C

See 图6-3

775

1600

150

The maximum safety temperature is the maximum junction temperature specified for the device. The power

dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines

the junction temperature. The assumed junction-to-air thermal resistance in the 节 6.4 table is that of a device

installed on a High-K test board for leaded surface mount packages. The power is the recommended maximum

input voltage times the current. The junction temperature is then the ambient temperature plus the power times

the junction-to-air thermal resistance.

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6.9 Electrical Characteristics

V_VCCI= 3.3 V or V_VCCI= 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V, 1-µF capacitor from VDDA and

VDDB to VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENTS

I_VCCI

VCCI quiescent current

DISABLE = VCCI

1.5

1.0

2.0

1.8

mA

I_VDDA

I_VDDB

,

VDDA and VDDB quiescent current

DISABLE = VCCI

(f = 500 kHz) current per channel,

C_OUT= 100 pF

I_VCCI

VCCI operating current

2.5

mA

I_VDDA

I_VDDB

(f = 500 kHz) current per channel,

C_OUT= 100 pF

VDDA and VDDB operating current

VCCI SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS

V_{VCCI_ON}

V_{VCCI_OFF}

V_{VCCI_HYS}

Rising threshold VCCI_ON

Falling threshold VCCI_OFF

Threshold hysteresis

2.55

2.35

2.7

2.5

0.2

2.85

2.65

V

VDDA/VDDB SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS

V_{VDDA_ON,}

Rising threshold VDDA_ON, VDDB_ON

V_{VDDB_ON}

8

8.5

8

9

V

V_{VDDA_OFF,}

Falling threshold VDDA_OFF, VDDB_OFF

V_{VDDB_OFF}

7.5

8.5

V_{VDDA_HYS,}

Threshold hysteresis

V_{VDDB_HYS}

0.5

PWM AND DISABLE

V_PWMH

V_DISH

,

Input high voltage

1.6

0.8

1.8

1

2

V

V_PWML, V_DISLInput low voltage

1.2

V_{PWM_HYS}

V_{DIS_HYS}

,

Input hysteresis

0.8

Negative transient, ref to GND, 50 ns

pulse

Not production tested, bench test

only

V_PWM

V

–5

8

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V_VCCI= 3.3 V or V_VCCI= 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V, 1-µF capacitor from VDDA and

VDDB to VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

C_VDD= 10 µF, C_LOAD= 0.18 µF, f

= 1 kHz, bench measurement

I_OA+, I_OB+

Peak output source current

Peak output sink current

4

6

A

C_VDD= 10 µF, C_LOAD= 0.18 µF, f

= 1 kHz, bench measurement

I_OA-, I_OB-

I_OUT= –10 mA, T_A= 25°C,

R_OHA, R_OHBdo not represent

drive pull-up performance. See

t_RISEin 节6.10 and 节8.3.4 for

details.

R_OHA, R_OHBOutput resistance at high state

5

Ω

R_OLA, R_OLBOutput resistance at low state

V_OHA, V_OHBOutput voltage at high state

I_OUT= 10 mA, T_A= 25°C

0.55

Ω

V_VDDA, V_VDDB= 12 V, I_OUT= –10

mA, T_A= 25°C

11.95

V

V_VDDA, V_VDDB= 12 V, I_OUT= 10

mA, T_A= 25°C

V_OLA, V_OLB

Output voltage at low state

5.5

mV

DEADTIME AND OVERLAP PROGRAMMING

Pull DT pin to VCCI

0

8

ns

DT pin is left open, min spec

characterized only, tested for

outliers

15

Dead time

160

200

240

R_DT= 20 kΩ

6.10 Switching Characteristics

V_VCCI= 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, T_A= –40°C to +125°C, (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_RISE

Output rise time, 20% to 80%

measured points

6

16

ns

C_OUT= 1.8 nF

t_FALL

Output fall time, 90% to 10%

measured points

7

12

20

30

ns

C_OUT= 1.8 nF

t_PWmin

t_PDHL

t_PDLH

Minimum pulse width

Output off for less than minimum,

C_OUT= 0 pF

Propagation delay from INx to OUTx

falling edges

19

Propagation delay from INx to OUTx

rising edges

t_PWD

t_DM

6

5

ns

Pulse width distortion |t_PDLH–t_PDHL

|

Propagation delays matching

between VOUTA, VOUTB

f = 100 kHz

Static common-mode transient

immunity (See 节7.5)

Slew rate of GND versus VSSA and

VSSB, PWM is tied to GND or VCCI

CMTI

100

V/ns

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6.11 Insulation Characteristics Curves

1.E+11

1.E+10

Safety Margin Zone: 1800 V_RMS, 254 Years

Operating Zone: 1500 V_RMS, 135 Years

TDDB Line (<1 PPM Fail Rate)

87.5%

1.E+9

1.E+8

1.E+7

1.E+6

1.E+5

1.E+4

1.E+3

1.E+2

1.E+1

20%

500 1500 2500 3500 4500 5500 6500 7500 8500 9500

Stress Voltage (V_RMS

)

图6-1. Reinforced Isolation Capacitor Life Time Projection

80

70

60

50

40

30

20

10

0

1800

I_VDDA/Bfor VDD=12V

I_VDDA/Bfor VDD=25V

1500

1200

900

600

300

0

50

100

Ambient Temperature (èC)

150

200

0

50

100

Ambient Temperature (èC)

150

200

D001

图6-3. Thermal Derating Curve for Safety-Related

图6-2. Thermal Derating Curve for Safety-Related

Limiting Current (Current in Each Channel with

Both Channels Running Simultaneously)

Limiting Power

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6.12 Typical Characteristics

VDDA = VDDB= 12 V, VCCI = 3.3 V, T_A= 25°C, No load unless otherwise noted.

20

16

12

8

50

40

30

20

10

0

4

VDD=12v

VDD=25v

VDD= 12V

VDD= 25V

0

800

1600

2400 3200

Frequency (kHz)

4000

4800

5600

0

500

1000

1500

Frequency (kHz)

2000

2500

3000

D001

No load

C_LOAD= 1 nF

图6-4. Per Channel Current Consumption vs.

图6-5. Per Channel Current Consumption (I_VDDA/B)

Frequency

vs. Frequency

30

24

18

12

6

50kHz

250kHz

500kHz

1MHz

5

4

3

2

1

0

VDD= 12V

VDD= 25V

0

10

25

40

55

Frequency (kHz)

70

85 100

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (èC)

D001

C_LOAD= 10 nF

No load

图6-6. Per Channel Current Consumption (I_VDDA/B

)

图6-7. Per Channel (I_VDDA/B) Supply Current Vs.

vs. Frequency

Temperature

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2

1.6

1.2

0.8

0.4

2

1.8

1.6

1.4

1.2

1

VDD= 12V

VDD= 25V

VCCI= 3.3V

VCCI= 5V

0

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

D001

Temperature (èC)

D001

No load

Input low

No switching

No load

DIS is high

No switching

图6-8. Per Channel (I_VDDA/B) Quiescent Supply

图6-9. I_VCCIQuiescent Supply Current vs

Current vs Temperature

Temperature

25

20

15

10

5

10

8

6

Output Pull-Up

Output Pull-Down

4

2

t_RISE

t_FALL

0

2

4

6

8

10

-40

-20

0

20

40

60

80

100 120 140

Load (nF)

Temperature (èC)

D001

VDD = 12 V

图6-11. Output Resistance vs. Temperature

图6-10. Rising and Falling Times vs. Load

28

20

19

18

17

16

24

20

16

12

Rising Edge (t_PDLH

Falling Edge (t_PDHL

)

Rising Edge (t_PDLH)

Falling Edge (t_PDHL

)

8

15

-40

-20

0

20

40

60

80

100 120 140

3

6

9

12

15 18

Temperature (èC)

VCCI (V)

D001

图6-12. Propagation Delay vs. Temperature

图6-13. Propagation Delay vs. VCCI

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5

2.5

0

3

1

-1

-3

-5

-2.5

Rising Edge

Falling Edge

-5

10

13

16

19

22

25

-40

-20

0

20

40

60

80

100 120 140

VDDA/B (V)

Temperature (èC)

D001

图6-15. Propagation Delay Matching (t_DM) vs. VDD

图6-14. Pulse Width Distortion vs. Temperature

5

550

530

510

490

470

450

2.5

0

-2.5

Rising Edge

Falling Edge

-5

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

图6-16. Propagation Delay Matching (t_DM) vs.

图6-17. VDD UVLO Hysteresis vs. Temperature

Temperature

10

9

900

860

820

780

8

7

740

6

VCC=3.3V

VCC=5V

VCC=12V

V_{VDDA_ON}

V_{VDDA_OFF}

700

-40

5

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

图6-19. PWM/DIS Hysteresis vs. Temperature

图6-18. VDD UVLO Threshold vs. Temperature

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1.2

1.14

1.08

1.02

0.96

2

1.92

1.84

1.76

1.68

1.6

VCC=3.3V

VCC= 5V

VCC=12V

VCC=3.3V

VCC= 5V

VCC=12V

0.9

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

图6-20. PWM/DIS Low Threshold

图6-21. PWM/DIS High Threshold

1500

1200

900

600

300

0

5

-6

R_DT= 20kW

R_DT= 100kW

-17

-28

-39

-50

R_DT= 20kW

R_DT= 100kW

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

D001

Temperature (èC)

D001

图6-22. Dead Time vs. Temperature

图6-23. Dead Time Matching vs. Temperature

18

14

10

6

2

-2

-6

1 nF Load

10 nF Load

0

100

200

300

400

Time (ns)

500

600

700

800

D001

图6-24. Typical Output Voltage

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7 Parameter Measurement Information

7.1 Propagation Delay and Pulse Width Distortion

图 7-1 shows how one calculates pulse width distortion (t_PWD) and delay matching (t_DM) from the propagation

delays of channels A and B. It can be measured by disabling the dead time function by shorting the DT Pin to

VCC.

PWM

t_DM-F= | t_PDHLAÅ t_PDHLB

t_DM-R= | t_PDLHAÅ t_PDLHB

|

OUTA

90%

t_PDLHA

t_PWD= | t_PDLHA/BÅ t_PDHLA/B

|

t_PDHLA

10%

90%

t_PDLHB

t_PDHLB

OUTB

图7-1. Propagation Delay Matching and Pulse Width Distortion

7.2 Rising and Falling Time

图 7-2 shows the criteria for measuring rising (t_RISE) and falling (t_FALL) times. For more information on how short

rising and falling times are achieved see 节8.3.4

90%

80%

t_RISE

t_FALL

20%

10%

图7-2. Rising and Falling Time Criteria

7.3 PWM Input and Disable Response Time

图7-3 shows the response time of the disable function. For more information, see 节8.4.1 .

PWM

DIS High

Response Time

DIS

DIS Low

Response Time

OUTA

90%

10%

图7-3. Disable Pin Timing

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7.4 Programable Dead Time

Leaving the DT pin open or tying it to GND through an appropriate resistor (R_DT) sets a dead-time interval. For

more details on dead time, refer to 节8.4.2 .

PWM

90%

OUTA

10%

tPDHL

90%

10%

OUTB

Dead Time

(with DT1

tPDHL

Dead Time

(with R^DT2)

R

)

图7-4. Dead-Time Switching Parameters

7.5 CMTI Testing

图7-5 is a simplified diagram of the CMTI testing configuration.

VCC

VDD

VDDA

OUTA

VSSA

PWM

1

16

15

14

OUTA

VCC

VCCI

3

GND

Functional

4

Isolation

DIS

5

VDDB

11

10

9

OUTB

VSSB

6

8

DT

VCCI

GND

VSS

Common Mode Surge

Generator

图7-5. Simplified CMTI Testing Setup

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8 Detailed Description

8.1 Overview

In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are

often placed between the output of control devices and the gates of power transistors. There are several

instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.

This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V

logic signal capable of only delivering a few mA.

The UCC20520 is a flexible dual gate driver which can be configured to fit a variety of power supply and motor

drive topologies, as well as drive several types of transistors, including SiC MOSFETs. UCC20520 has many

features that allow it to integrate well with control circuitry and protect the gates it drives such as: resistor-

programmable dead time (DT) control, a DISABLE pin, and under voltage lock out (UVLO) for both input and

output voltages. The UCC20520 also holds its OUTA low when the PWM is left open or when the PWM pulse is

not wide enough. The driver input PWM is CMOS and TTL compatible for interfacing to digital and analog power

controllers alike. Importantly, Channel A is in phase with PWM input and Channel B is always complimentary

with Channel A with programmed deadtime.

8.2 Functional Block Diagram

PWM

1

16 VDDA

200 kW

Driver

MOD

DEMOD

VCCI

15 OUTA

14 VSSA

UVLO

VCCI 3,8

UVLO

GND

DT

4

6

5

13 NC

12 NC

Deadtime

Control

Functional Isolation

DIS

11 VDDB

200 kW

Driver

MOD

DEMOD

UVLO

10 OUTB

PWM

9

VSSB

NC 2,7

Copyright

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8.3 Feature Description

8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)

The UCC20520 has an internal under voltage lock out (UVLO) protection feature on the supply circuit blocks

between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than V_{VDD_ON}at device

start-up or lower than V_{VDD_OFF}after start-up, the VDD UVLO feature holds the effected outputs low, regardless

of the status of the input pin (PWM).

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an

active clamp circuit that limits the voltage rise on the driver outputs (Illustrated in 图 8-1 ). In this condition, the

upper PMOS is resistively held off by R_Hi-Zwhile the lower NMOS gate is tied to the driver output through

R_CLAMP. In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS

device, typically less than 1.5V, when no bias power is available.

VDD

R_{HI_Z}

Output

Control

OUT

R_CLAMP

R_CLAMPis activated

during UVLO

VSS

图8-1. Simplified Representation of Active Pull Down Feature

The VDD UVLO protection has a hysteresis feature (V_{VDD_HYS}). This hysteresis prevents chatter when there is

ground noise from the power supply. Also this allows the device to accept small drops in bias voltage, which is

bound to happen when the device starts switching and operating current consumption increases suddenly.

The input side of the UCC20520 also has an internal under voltage lock out (UVLO) protection feature. The

device isn't active unless the voltage, VCCI, is going to exceed V_{VCCI_ON}on start up. And a signal will cease to

be delivered when that pin receives a voltage less than V_{VCCI_OFF}. And, just like the UVLO for VDD, there is

hystersis (V_{VCCI_HYS}) to ensure stable operation.

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All versions of the UCC20520 can withstand an absolute maximum of 30 V for VDD, and 20 V for VCCI.

表8-1. UCC20520 VCCI UVLO Feature Logic

CONDITION

INPUT

OUTPUTS

PWM

OUTA

OUTB

VCCI-GND < V_{VCCI_ON}during device start up

VCCI-GND < V_{VCCI_OFF}after device start up

H

L

H

L

表8-2. UCC20520 VDD UVLO Feature Logic

CONDITION

INPUT

OUTPUTS

PWM

OUTA

OUTB

VDD-VSS < V_{VDD_ON}during device start up

VDD-VSS < V_{VDD_OFF}after device start up

H

L

H

L

8.3.2 Input and Output Logic Table

表8-3. INPUT/OUTPUT Logic Table⁽¹⁾

Assume VCCI, VDDA, VDDB are powered up. See 节8.3.1 for more information on UVLO operation modes.

INPUT

OUTPUTS

DISABLE

NOTE

PWM

OUTA

OUTB

L or Left

Open

L or Left Open

L

H

Output transitions occur after the dead time expires. See 节8.4.2

H

X

L or Left Open

H

L

-

(1) "X" means L, H or left open.

8.3.3 Input Stage

The input pins (PWM and DIS) of UCC20520 are based on a TTL and CMOS compatible input-threshold logic

that is totally isolated from the VDD supply voltage. The input pins are easy to drive with logic-level control

signals (Such as those from 3.3-V micro-controllers), since UCC20520 has a typical high threshold (V_PWMH) of

1.8 V and a typical low threshold of 1 V, which vary little with temperature (see 图 6-20,图 6-21). A wide

hysteresis (V_{PWM_HYS}) of 0.8 V makes for good noise immunity and stable operation. If any of the inputs are ever

left open, internal pull-down resistors force the pin low. These resistors are typically 200 kΩ (See 节 8.2).

However, it is still recommended to ground an input if it is not being used.

Since the input side of UCC20520 is isolated from the output drivers, the input signal amplitude can be larger or

smaller than VDD, provided that it doesn’t exceed the recommended limit. This allows greater flexibility when

integrating with control signal sources, and allows the user to choose the most efficient VDD for their chosen

gate. That said, the amplitude of any signal applied to PWM must never be at a voltage higher than VCCI.

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8.3.4 Output Stage

The UCC20520’s output stages features a pull-up structure which delivers the highest peak-source current

when it is most needed, during the Miller plateau region of the power-switch turn on transition (when the power

switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel

MOSFET and an additional Pull-Up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to

provide a brief boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning

on the N-channel MOSFET during a narrow instant when the output is changing states from low to high. The on-

resistance of this N-channel MOSFET (R_NMOS) is approximately 1.47 Ωwhen activated.

The R_OHparameter is a DC measurement and it is representative of the on-resistance of the P-channel device

only. This is because the Pull-Up N-channel device is held in the off state in DC condition and is turned on only

for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the

UCC20520 pull-up stage during this brief turn-on phase is much lower than what is represented by the R_OH

parameter. Therefore, the value of R_OHbelies the fast nature of the UCC20520's turn-on time.

The pull-down structure in UCC20520 is simply composed of an N-channel MOSFET. The R_OLparameter, which

is also a DC measurement, is representative of the impedance of the pull-down state in the device. Both outputs

of the UCC20520 are capable of delivering 4-A peak source and 6-A peak sink current pulses. The output

voltage swings between VDD and VSS provides rail-to-rail operation, thanks to the MOS-out stage which

delivers very low drop-out.

VDD

R_OH

Shoot-

R_NMOS

Input

Signal

Through

Prevention

Circuitry

OUT

VSS

R_OL

Pull Up

图8-2. Output Stage

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8.3.5 Diode Structure in UCC20520

图8-3 illustrates the multiple diodes involved in the ESD protection components of the UCC20520. This provides

a pictorial representation of the absolute maximum rating for the device.

VCCI

3,8

VDDA

16

30 V

15 OUTA

14 VSSA

20 V 20 V

PWM

1

DIS

DT

5

6

11 VDDB

10 OUTB

30 V

4

9

GND

VSSB

图8-3. ESD Structure

8.4 Device Functional Modes

8.4.1 Disable Pin

Setting the DISABLE pin high shuts down both outputs simultaneously. Grounding (or left open) the DISABLE

pin allows UCC20520 to operate normally. The DISABLE response time is in the range of 20ns and quite

responsive, which is as fast as propagation delay. The DISABLE pin is only functional (and necessary) when

VCCI stays above the UVLO threshold. It is recommended to tie this pin to ground if the DISABLE pin is not

used to achieve better noise immunity.

8.4.2 Programmable Dead Time (DT) Pin

UCC20520 allows the user to adjust dead time (DT) in the following ways:

8.4.2.1 Tying the DT Pin to VCC

If DT pin is tied to VCC, dead time function between OUTA and OUTB is disabled and the deadtime between the

two output channels is around 0ns.

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8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins

If the DT pin is left open, the dead time duration (t_DT) is set to <15 ns. One can program t_DTby placing a resistor,

_DT, between the DT pin and GND. The appropriate R_DTvalue can be determined from 方程式 1, where R_DTis

R

in kΩ and t_DTin ns:

8.4.2.3

t_DT» 10 ´ R_DT

(1)

The steady state voltage at DT pin is around 0.8V, and the DT pin current will be less than 10uA when

_DT=100kΩ. Therefore, It is recommended to parallel a ceramic capacitor, 2.2nF or above, with R_DTto achieve

R

better noise immunity and better deadtime matching between two channels, especially when the dead time is

larger than 300ns. The major consideration is that the current through the R_DTis used to set the dead time, and

this current decreases as R_DTincreases.

PWM input signal’s falling edge activates the programmed dead time for the other signal. The output signals’

dead time is always set to the driver’s programmed dead time. Various driver dead time logic operating

conditions are illustrated and explained in 图8-4:

PWM

DT

OUTA

OUTB

图8-4. Input and Output Logic Relationship with Dead Time

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The UCC20520 effectively combines both isolation and buffer-drive functions. The flexible, universal capability of

the UCC20520 (with up to 18-V VCCI and 25-V VDDA/VDDB) allows the device to be used as a low-side, high-

side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or SiC MOSFETs. With integrated

components, advanced protection features (UVLO, dead time, and disable) and optimized switching

performance; the UCC20520 enables designers to build smaller, more robust designs for enterprise, telecom,

automotive, and industrial applications with a faster time to market.

9.2 Typical Application

图 9-1 shows a reference design with UCC20520 driving a typical half-bridge configuration which can be used in

several popular power converter topologies such as synchronous buck, synchronous boost, half-bridge/full

bridge isolated topologies, and three-phase motor drive applications.

VDD

VCC

R_BOOT

HV DC-Link

VCC

R_IN

VDDA

R_OFF

R_ON

C_BOOT

16

15

14

PWM

1

2

3

4

5

6

8

PWM

OUTA

VSSA

C_IN

R_GS

VCCI

GND

DIS

mC

C_VCC

SW

Functional

Isolation

VDD

Analog

or

Digital

Disable

VDDB

R_OFF

R_ON

11

10

9

≥2.2nF

DT

OUTB

VSSB

R_DIS

C_VDD

R_GS

VCCI

R_DT

VSS

图9-1. Typical Application

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9.2.1 Design Requirements

表 9-1 lists reference design parameters for the example application: UCC20520 driving 1200-V SiC-MOSFETs

in a high side-low side configuration.

表9-1. UCC20520 Design Requirements

PARAMETER

Power transistor

VCC

VALUE

UNITS

C2M0080120D

-

V

5.0

20

VDD

V

Input signal amplitude

Switching frequency (f_s)

DC link voltage

V

0 ↔ 3.3

100

kHz

V

800

9.2.2 Detailed Design Procedure

9.2.2.1 Designing PWM Input Filter

It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)

the signal at the output. However, a small input R_IN-C_INfilter can be used to filter out the ringing introduced by

non-ideal layout or long PCB traces.

Such a filter should use an R_INin the range of 0 Ω to100 Ω and a C_INbetween 10 pF and 100 pF. In the

example, an R_IN= 51 Ωand a C_IN= 33 pF are selected, with a corner frequency of approximately 100 MHz.

When selecting these components, it is important to pay attention to the trade-off between good noise immunity

and propagation delay.

9.2.2.2 Select External Bootstrap Diode and its Series Resistor

The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side

transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation

in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.

Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver

circuit.

When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes

or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the

loss introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage

is 800 V_DC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good

margin. Therefore, a 1200-V SiC diode, C4D02120E, is chosen in this example.

A bootstrap resistor, R_BOOT, is used to reduce the inrush current in D_BOOTand limit the ramp up slew rate of

voltage of VDDA-VSSA during each switching cycle, especially when the VSSA(SW) pin has an excessive

negative transient voltage. The recommended value for R_BOOTis between 1 Ω and 20 Ω depending on the

diode used. In the example, a current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap

diode. The estimated worst case peak current through D_Bootis,

V_DD- V_BDF

R_Boot

20V - 2.5V

2.2W

I_{DBoot pk}

=

ö 8A

(

)

(2)

where

• V_BDFis the estimated bootstrap diode forward voltage drop at 8 A.

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9.2.2.3 Gate Driver Output Resistor

The external gate driver resistors, R_ON/R_OFF, are used to:

1. Limit ringing caused by parasitic inductances/capacitances.

2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.

3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.

4. Reduce electromagnetic interference (EMI).

As mentioned in 节 8.3.4, the UCC20520 has a pull-up structure with a P-channel MOSFET and an additional

pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak source

current can be predicted with:

≈

∆

«

’

V_DD- V_BDF

R_NMOS||R_OH+R_ON+R_{GFET _Int}

I_OA+= min 4A,

∆

÷

◊

(3)

(4)

≈

∆

«

’

V_DD

I_OB+= min 4A,

∆

÷

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}

◊

where

• R_ON: External turn-on resistance.

• R_{GFET_INT}: Power transistor internal gate resistance, found in the power transistor datasheet.

• I_O+= Peak source current –The minimum value between 4 A, the gate driver peak source current, and the

calculated value based on the gate drive loop resistance.

In this example:

V_DD- V_BDF

20V - 0.8V

I_OA+

=

ö 2.4A

ö 2.5A

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}1.47W || 5W + 2.2W + 4.6W

(5)

(6)

V_DD

20V

I_OB+

=

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}1.47W || 5W + 2.2W + 4.6W

Therefore, the high-side and low-side peak source current is 2.4 A and 2.5 A respectively. Similarly, the peak

sink current can be calculated with:

≈

∆

«

’

V_DD- V_BDF- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET_Int}

I_OA-= min 6A,

∆

÷

◊

(7)

(8)

≈

∆

«

’

V_DD- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET _Int}

I_OB-= min 6A,

∆

÷

◊

where

• R_OFF: External turn-off resistance;

• V_GDF: The anti-parallel diode forward voltage drop which is in series with R_OFF. The diode in this example is

an MSS1P4.

• I_O-: Peak sink current –the minimum value between 6 A, the gate driver peak sink current, and the

calculated value based on the gate drive loop resistance.

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In this example,

V_DD- V_BDF- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET _Int}

20V - 0.8V - 0.75V

0.55W + 0W + 4.6W

I_OA-

=

ö 3.6A

(9)

V_DD- V_GDF

20V-0.75V

I_OB-=

=

ö 3.7A

R_OL+ R_OFF||R_ON+ R_{GFET _Int}0.55W + 0W + 4.6W

(10)

Therefore, the high-side and low-side peak sink current is 3.6 A and 3.7 A respectively.

Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic

inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and

undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other

hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (C_ISS) of the

power transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close

to the parasitic ringing period.

9.2.2.4 Estimate Gate Driver Power Loss

The total loss, P_G, in the gate driver subsystem includes the power losses of the UCC20520 (P_GD) and the

power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not

included in P_Gand not discussed in this section.

P_GDis the key power loss which determines the thermal safety-related limits of the UCC20520, and it can be

estimated by calculating losses from several components.

The first component is the static power loss, P_GDQ, which includes quiescent power loss on the driver as well as

driver self-power consumption when operating with a certain switching frequency. P_GDQis measured on the

bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and

ambient temperature. 图 6-4 shows the per output channel current consumption vs. operating frequency with no

load. In this example, V_VCCI= 5 V and V_VDD= 20 V. The current on each power supply, with PWM switching from

0 V to 3.3 V at 100 kHz is measured to be I_VCCI= 2.5 mA, and I_VDDA= I_VDDB= 1.5 mA. Therefore, the P_GDQcan

be calculated with

P

= V_VCCIìI_VCCI+ V_VDDAìI_DDA+ V_VDDBìI_DDBö 72mW

GDQ

(11)

The second component is switching operation loss, P_GDO, with a given load capacitance which the driver

charges and discharges the load during each switching cycle. Total dynamic loss due to load switching, P_GSW

can be estimated with

,

P_GSW= 2 ì V_DDì Q_Gì f_SW

(12)

where

• Q_Gis the gate charge of the power transistor.

If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail

to the negative rail.

So, for this example application:

P_GSW= 2 ì 20V ì 60nC ì100kHz = 240mW

(13)

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Q_Grepresents the total gate charge of the power transistor switching 800 V at 20 A, and is subject to change

with different testing conditions. The UCC20520 gate driver loss on the output stage, P_GDO, is part of P_GSW

.

P_GDOwill be equal to P_GSWif the external gate driver resistances are zero, and all the gate driver loss is

dissipated inside the UCC20520. If there are external turn-on and turn-off resistance, the total loss will be

distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly, the pull-

up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A, however,

it will be non-linear if the source/sink current is saturated. Therefore, P_GDOis different in these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

≈

’

R_OH||R_NMOS

R_OL

P_GDO= P_GSW

ì

+

∆

÷

R_OH||R_NMOS+ R_ON+ R_{GFET _Int}R_OL+ R_OFF||R_ON+ R_{GFET _Int}

«

◊

(14)

In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the UCC20520

gate driver loss can be estimated with:

≈

5W ||1.47W

0.55W

’

P_GDO= 240mW ì

+

ö 60mW

∆

«

÷

◊

5W ||1.47W + 2.2W + 4.6W 0.55W + 0W + 4.6W

(15)

Case 2 - Nonlinear Pull-Up/Down Resistor:

T_{R _ Sys}

T_{F_ Sys}

»

ÿ

P_GDO= 2 ì f_SWì 4A ì

V - V

t dt + 6A ì

( )

V_OUTA/Bt dt

( )

…

Ÿ

(

)

DD

OUTA/B

—

…

Ÿ

⁄

0

(16)

where

• V_OUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be

simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load

capacitor. Then, the V_OUTA/B(t) waveform will be linear and the T_{R_Sys}and T_{F_Sys}can be easily predicted.

For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the P_GDO

will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull-

down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC20520,

P_GD, is:

P_GD= P + P

GDQ

GDO

(17)

which is equal to 127 mW in the design example.

9.2.2.5 Estimating Junction Temperature

The junction temperature (T_J) of the UCC20520 can be estimated with:

T_J= T_C+ R_qJCìP_GD

(18)

where

• T_Cis the UCC20520 case-top temperature measured with a thermocouple or some other instrument, R_θJCis

the Junction-to-case-top thermal resistance from the 节6.4 table. Importantly, R_θJA, the junction to ambient

thermal impedance provided in the Thermal Information table, is developed based on JEDEC standard PCB

board and it is subject to change when the PCB board layout is different.

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9.2.2.6 Selecting VCCI, VDDA/B Capacitor

Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is

recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with

sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC

will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500

nF when a DC bias of 15 V_DCis applied.

9.2.2.6.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total

current consumption, which is only a few mA. Therefore, a 50-V MLCC with over 100 nF is recommended for this

application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or

electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.

9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor

A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for

gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.

The total charge needed per switching cycle can be estimated with

I_VDD@100kHz No Load

(

f_SW

)

1.5mA

Q_Total= Q_G+

= 60nC +

= 75nC

100kHz

(19)

where

• Q_G: Gate charge of the power transistor.

• I_VDD: The channel self-current consumption with no load at 100kHz.

Therefore, the absolute minimum C_Bootrequirement is:

Q_Total

75nC

C_Boot

=

= 150nF

DV_VDDA0.5V

(20)

where

• ΔV_VDDAis the voltage ripple at VDDA, which is 0.5 V in this example.

In practice, the value of C_Bootis greater than the calculated value. This allows for the capacitance shift caused by

the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.

Therefore, it is recommended to include a safety-related margin in the C_Bootvalue and place it as close to the

VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.

C_Boot= 1ꢀF

(21)

To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with

a low capacitance value, in this example a 100 nF, in parallel with C_Bootto optimize the transient performance.

备注

Too large C_BOOTis not good. C_BOOTmay not be charged within the first few cycles and V_BOOTcould

stay below UVLO. As a result, the high-side FET does not follow input signal command. Also during

initial C_BOOTcharging cycles, the bootstrap diode has highest reverse recovery current and losses.

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9.2.2.6.3 Select a VDDB Capacitor

Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as C_VDDin 图

9-1) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current for

VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for C_VDD. If the

bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor,

with a value over 10 µF, should be used in parallel with C_VDD

.

9.2.2.7 Dead Time Setting Guidelines

For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor

is important for preventing shoot-through during dynamic switching.

The UCC20520 dead time specification in the electrical table is defined as the time interval from 90% of one

channel’s falling edge to 10% of the other channel’s rising edge (see 图 7-4). This definition ensures that the

dead time setting is independent of the load condition, and guarantees linearity through manufacture testing.

However, this dead time setting may not reflect the dead time in the power converter system, since the dead

time setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as

well as the input capacitance of the load transistor.

Here is a suggestion on how to select an appropriate dead time for UCC20520:

DT_Setting= DT_Req+ T_{F_Sys}+ T_{R_Sys}- T_{D on}

(

)

(22)

where

• DT_setting: UCC20520 dead time setting in ns, DT_Setting= 10 × RDT(in kΩ).

• DT_Req: System required dead time between the real V_GSsignal of the top and bottom switch with enough

margin, or ZVS requirement.

• T_{F_Sys}: In-system gate turn-off falling time at worst case of load, voltage/current conditions.

• T_{R_Sys}: In-system gate turn-on rising time at worst case of load, voltage/current conditions.

• T_D(on): Turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold.

In the example, DT_Settingis set to 250 ns.

It should be noted that the UCC20520 dead time setting is decided by the DT pin configuration (See 节 8.4.2),

and it cannot automatically fine-tune the dead time based on system conditions, i.e. zero voltage switching

conditions. It is recommended to parallel a ceramic capacitor, 2.2nF or above, with R_DTto achieve better noise

immunity and deadtime matching.

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9.2.2.8 Application Circuits with Output Stage Negative Bias

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and

TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during

high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on

and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below

the threshold. Below are a few examples of implementing negative gate drive bias.

图 9-2 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the

isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power

supply, V_A, is equal to 25 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 25 V -–5.1 V ≈20 V.

The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for

a half-bridge configuration, and there will be steady state power consumption from R_Z.

9.2.2.9

HV DC-Link

VDDA

R_OFF

16

1

C_A1

+

V_A

œ

C_IN

R_Z

25 V

R_ON

OUTA

VSSA

15

14

2

3

4

5

6

8

C_A2

V_Z= 5.1 V

SW

Functional

Isolation

VDDB

11

10

9

OUTB

VSSB

图9-2. Negative Bias with Zener Diode on Iso-Bias Power Supply Output

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图 9-3 shows another example which uses two supplies (or single-input-double-output power supply). Power

supply V_A+determines the positive drive output voltage and V_A–determines the negative turn-off voltage. The

configuration for channel B is the same as channel A. This solution requires more power supplies than the first

example, however, it provides more flexibility when setting the positive and negative rail voltages.

HV DC-Link

VDDA

OUTA

R_OFF

R_ON

16

15

1

2

3

4

5

6

8

C_A1

+

V_A+

œ

C_IN

C_A2

+

V_A-

œ

VSSA

14

Functional

Isolation

SW

VDDB

11

10

9

OUTB

VSSB

图9-3. Negative Bias with Two Iso-Bias Power Supplies

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The last example, shown in 图9-4, is a single power supply configuration and generates negative bias through a

Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and the

bootstrap power supply can be used for the high side drive. This design requires the least cost and design effort

among the three solutions. However, this solution has limitations:

1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which

means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a fixed

duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors which favor this

solution.

2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,

which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel)

diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%

duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in

the other two example circuits.

VDD

R_BOOT

HV DC-Link

VDDA

C_Z

V_Z

R_OFF

R_ON

16

15

14

1

2

3

4

5

6

8

OUTA

VSSA

C_IN

C_BOOT

R_GS

SW

Functional

Isolation

VDD

VDDB

C_Z

V_Z

R_OFF

R_ON

11

10

9

OUTB

VSSB

C_VDD

R_GS

VSS

图9-4. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path

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9.2.3 Application Curves

图 9-5 and 图 9-6 shows the bench test waveforms for the design example shown in 图 9-1 under these

conditions: VCC = 5 V, VDD = 20 V, f_SW= 100 kHz, V_DC-Link= 0 V.

Channel 1 (Blue): UCC20520 PWM pin signal.

Channel 2 (Red): Gate-source signal on the high side power transistor.

Channel 3 (Green): Gate-source signal on the low side power transistor.

In 图 9-5, PWM is sent with 50% duty-cycle signals. The gate drive signals on the power transistor have a 250-

ns dead time, shown in the measurement section of 图9-5.

图 9-6 shows a zoomed-in version of the waveform of 图 9-5, with measurements for propagation delay and

rising/falling time. Cursors are also used to measure dead time. Importantly, the output waveform is measured

between the power transistors’ gate and source pins, and is not measured directly from the driver OUTA and

OUTB pins. Due to the split on and off resistors (R_ON,R_OFF) and different sink and source currents, different

rising (16 ns) and falling time (9 ns) are observed in 图9-6.

图9-5. Bench Test Waveform for PWM and OUTA/B

图9-6. Zoomed-In bench-test waveform

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Power Supply Recommendations

The recommended input supply voltage (VCCI) for UCC20520 is between 3-V and 18-V. The recommended

output bias supply voltage (VDDA/VDDB) range is between 9.2-V to 25-V. The lower end of this bias supply

range is governed by the internal under voltage lockout (UVLO) protection feature of each device. One mustn’t

let VDD or VCCI fall below their respective UVLO thresholds (For more information on UVLO see 节 8.3.1). The

upper end of the VDDA/VDDB range depends on the maximum gate voltage of the power device being driven by

UCC20520.

A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned

as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further

suggested that one place two such capacitors: one with a value of between 220 nF and 10 µF for device biasing,

and an additional 100-nF capacitor in parallel for high frequency filtering.

Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of

current drawn by the logic circuitry within the input side of UCC20520, this bypass capacitor has a minimum

recommended value of 100 nF.

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10 Layout

10.1 Layout Guidelines

To achieve optimum performance for the UCC20520, pay close attention to PCB layout in order.

Component Placement:

• Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins

and between the VDD and VSS pins to support high peak currents when turning on the external power

transistor.

• To avoid large negative transients on the switch node VSSA (HS) pin, the parasitic inductances between the

source of the top transistor and the source of the bottom transistor must be minimized.

• It is recommended to place the dead time setting resistor, R_DT, and its bypassing capacitor close to DT pin of

UCC20520.

Grounding Considerations:

• It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal

physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the

transistors. The gate driver must be placed as close as possible to the transistors.

• Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-

referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is

recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This

recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and

area on the circuit board is important for ensuring reliable operation.

High-Voltage Considerations:

• To ensure isolation performance between the primary and secondary side, one should avoid placing any PCB

traces or copper below the driver device. A PCB cutout is recommended in order to prevent contamination

that may compromise the UCC20520’s isolation performance.

• For half-bridge, or high-side/low-side configurations, where the channel A and channel B drivers could

operate with a DC-link voltage up to 1500 V_DC, one should try to increase the creepage distance of the PCB

layout between the high and low-side PCB traces.

Thermal Considerations:

• A large amount of power may be dissipated by the UCC20520 if the driving voltage is high, the load is heavy,

or the switching frequency is high (Refer to 节9.2.2.4 for more details). Proper PCB layout can help dissipate

heat from the device to the PCB and minimize junction to board thermal impedance (θ_JB).

• Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended (See 图10-2

and 图10-3). However, high voltage PCB considerations mentioned above must be maintained.

• If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and

VSSB pins to internal ground or power planes through multiple vias of adequate size. However, keep in mind

that there shouldn’t be any traces/coppers from different high voltage planes overlapping.

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10.2 Layout Example

图10-1 shows a 2-layer PCB layout example with the signals and key components labeled.

图10-1. Layout Example

图10-2 and 图10-3 shows top and bottom layer traces and copper.

备注

There are no PCB traces or copper between the primary and secondary side, which ensures isolation

performance.

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PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the

creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node

VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.

图10-2. Top Layer Traces and Copper

图10-3. Bottom Layer Traces and Copper

图10-4 and 图10-5 are 3D layout pictures with top view and bottom views.

备注

The location of the PCB cutout between the primary side and secondary sides, which ensures

isolation performance.

图10-4. 3-D PCB Top View

图10-5. 3-D PCB Bottom View

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

• Isolation Glossary

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.3.1 Certifications

UL Online Certifications Directory, "FPPT2.E181974 Nonoptical Isolating Devices - Component" Certificate

Number: 20160516-E181974, (SLUQ001)

VDE Online Certifications Directory, "Certificate of Conformity with Factory Surveillance" Certificate Number:

40040142

CQC Online Certifications Directory, "GB4943.1-2011, Digital Isolator Certificate" Certificate Number:

CQC16001155011

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

38

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Product Folder Links: UCC20520

GENERIC PACKAGE VIEW

DW 16

7.5 x 10.3, 1.27 mm pitch

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224780/A

www.ti.com

PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height

S

C

A

L

E

1

.

5

0

SOIC

C

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

14X 1.27

16

1

2X

10.5

10.1

NOTE 3

8.89

8

9

0.51

0.31

16X

7.6

7.4

B

2.65 MAX

0.25

C A

B

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

www.ti.com

EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (2)

1

16X (1.65)

SEE

DETAILS

SEE

DETAILS

1

16

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

9

8

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (1.65)

16X (2)

1

16

16X (0.6)

SYMM

14X (1.27)

8

9

8

9

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	UCC20520
厂家：	TEXAS INSTRUMENTS
描述：	具有双输入、8V UVLO 且采用 LGA 封装的 5.7kVrms、4A/6A 双通道隔离式栅极驱动器栅极驱动驱动器
文件：	总45页 (文件大小：2849K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC20520 [TI]

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