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UCC21222-Q1

ZHCSHQ7 –FEBRUARY 2018

UCC21222-Q1 汽车 4A、6A、3.0kV_RMS隔离式双通道栅极驱动器

（具有死区时间）

1 特性

3 说明

1

•

具有符合 AEC Q100 标准的下列特性：

UCC21222-Q1 器件是具有可编程死区时间和宽温度范

围的隔离式双通道栅极驱动器。该器件在极端温度条件

下表现出一致的性能和稳定性。该器件采用 4A 峰值拉

电流和 6A 峰值灌电流来驱动功率 MOSFET、IGBT 和

GaN 晶体管。

–

器件温度 1 级

器件人体放电模式 (HBM) 静电放电 (ESD) 分类

等级 H2

–

器件 CDM ESD 分类等级 C6

•

结温范围为 –40°C 至 150°C

UCC21222-Q1 器件可配置为两个低侧驱动器、两个高

侧驱动器或一个半桥驱动器。该器件的 5ns 延迟匹配

性能允许并联两个输出，能够在重负载条件下将驱动强

度提高一倍，而无内部击穿风险。

可通过电阻器编程的死区时间

通用：双路低侧、双路高侧或半桥驱动器

4A 峰值拉电流、6A 峰值灌电流输出

3V 至 5.5V 输入 VCCI 范围

输入侧通过一个 3.0kV_RMS隔离栅与两个输出驱动器隔

离，共模瞬态抗扰度 (CMTI) 的最小值为 100V/ns。

高达 18V 的 VDD 输出驱动电源

–

8V VDD UVLO

•

开关参数：

可通过电阻器编程的死区时间可让您调整系统限制的死

区时间，从而提高效率并防止输出重叠。其他保护特

性包括：当 DIS 设置为高电平时，通过禁用功能同时

关闭两路输出；集成的抗尖峰滤波器可抑制短于 5ns

的输入瞬变；以及在输入和输出引脚上对高达 -2V 的

尖峰进行 200ns 的负电压处理。所有电源都有 UVLO

保护。

–

28ns 典型传播延迟

10ns 最小脉冲宽度

5ns 最大延迟匹配度

5.5ns 最大脉宽失真

•

TTL 和 CMOS 兼容输入

集成抗尖峰滤波器

I/O 承受 –2V 电压的时间达 200ns

共模瞬态抗扰度 (CMTI) 大于 100V/ns

隔离栅寿命大于 40 年

器件信息⁽¹⁾

器件型号

封装

封装尺寸（标称值）

UCC21222-Q1

SOIC (16)

9.9mm × 3.91mm

浪涌抗扰度高达 7800V_PK

窄体 SOIC-16 (D) 封装

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

安全相关认证（计划）：

功能方框图

–

符合 DIN V VDE V 0884-11:2017-01 和 DIN

EN 61010-1 标准的 4242V_PK隔离

VCCI 3,8

16 VDDA

符合 UL 1577 标准且长达 1 分钟的 3000V_RMS

隔离

Driver

DEMOD UVLO

MOD

15 OUTA

14 VSSA

INA

DIS

DT

1

5

6

7

获得 CSA 认证，符合 IEC 60950-1、IEC

62368-1 和 IEC 61010-1 终端设备标准

Input

Logic,

Disable,

UVLO,

Dead

通过 GB4943.1-2011 CQC 认证

13 NC

12 NC

Functional Isolation

2 应用

Time

NC

11 VDDB

10 OUTB

•

HEV 和 EV 电池充电器

Driver

INB

2

4

MOD

DEMOD UVLO

交流/直流和直流/直流电源中的隔离转换器

电机驱动器和逆变器

GND

9

VSSB

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLUSDA5

UCC21222-Q1

ZHCSHQ7 –FEBRUARY 2018

www.ti.com.cn

7.6 Power-up UVLO Delay to OUTPUT........................ 17

7.7 CMTI Testing........................................................... 18

Detailed Description ............................................ 19

8.1 Overview ................................................................. 19

8.2 Functional Block Diagram ....................................... 19

8.3 Feature Description................................................. 20

8.4 Device Functional Modes........................................ 23

Application and Implementation ........................ 25

9.1 Application Information............................................ 25

9.2 Typical Application .................................................. 25

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Power Ratings........................................................... 5

6.6 Insulation Specifications............................................ 6

6.7 Safety-Related Certifications..................................... 7

6.8 Safety-Limiting Values .............................................. 7

6.9 Electrical Characteristics........................................... 8

6.10 Switching Characteristics........................................ 9

6.11 Thermal Derating Curves...................................... 10

6.12 Typical Characteristics.......................................... 11

Parameter Measurement Information ................ 15

7.1 Minimum Pulses...................................................... 15

7.2 Propagation Delay and Pulse Width Distortion....... 15

7.3 Rising and Falling Time ......................................... 15

7.4 Input and Disable Response Time.......................... 16

7.5 Programmable Dead Time...................................... 16

8

9

10 Power Supply Recommendations ..................... 35

11 Layout................................................................... 36

11.1 Layout Guidelines ................................................. 36

11.2 Layout Example .................................................... 37

12 器件和文档支持 ..................................................... 39

12.1 文档支持 ............................................................... 39

12.2 相关链接................................................................ 39

12.3 接收文档更新通知 ................................................. 39

12.4 社区资源................................................................ 39

12.5 商标....................................................................... 39

12.6 静电放电警告......................................................... 39

12.7 Glossary................................................................ 39

13 机械、封装和可订购信息....................................... 39

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2018 年2 月

*

初始发行版。

2

UCC21222-Q1

www.ti.com.cn

ZHCSHQ7 –FEBRUARY 2018

5 Pin Configuration and Functions

D Package

16-Pin SOIC

Top View

Pin Functions

(1)

I/O

Description

NAME

NO.

Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low

internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise

immunity. Bypass using a ≈ 1-nF low ESR/ESL capacitor close to DIS pin when connecting to a µC with

distance.

DIS

5

I

Programmable dead time function.

Tying DT to VCCI or leaving DT open allows the outputs to overlap. Placing a resistor (R_DT) between DT

and GND adjusts dead time according to the equation: DT (in ns) = 10 × R_DT(in kΩ). TI recommends

bypassing this pin with a ceramic capacitor, 2.2 nF or greater, to achieve better noise immunity. Place

this capacitor and R_DTclose to the DT pin.

DT

6

GND

INA

4

1

P

I

Primary-side ground reference. All signals in the primary side are referenced to this ground.

Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is pulled low

internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise

immunity.

Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is pulled low

internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise

immunity.

INB

NC

2

I

7

12

13

15

10

-

No internal connection.

OUTA

OUTB

O

Output of driver A. Connect to the gate of the A channel FET or IGBT.

Output of driver B. Connect to the gate of the B channel FET or IGBT.

Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close

to the device as possible.

VCCI

VDDA

3

8

P

This pin is internally shorted to pin 3.

Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located

as close to the device as possible.

16

Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located

as close to the device as possible.

VDDB

11

P

VSSA

VSSB

14

9

P

Ground for secondary-side driver A. Ground reference for secondary side A channel.

Ground for secondary-side driver B. Ground reference for secondary side B channel.

(1) P = power, I = input, O = output

3

UCC21222-Q1

ZHCSHQ7 –FEBRUARY 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

MAX

6

UNIT

V

Input bias pin supply voltage

Driver bias supply

VCCI to GND

VDDA-VSSA, VDDB-VSSB

20

V

V_VDDA+0.5,

V_VDDB+0.5

OUTA to VSSA, OUTB to VSSB

–0.5

–2

V

Output signal voltage

Input signal voltage

OUTA to VSSA, OUTB to VSSB, Transient for 200

ns⁽²⁾

V_VDDA+0.5,

V_VDDB+0.5

INA, INB, DIS to GND

INA, INB Transient to GND for 200ns⁽²⁾

–0.5

–2

V_VCCI+0.5

150

V

(3)

Junction temperature, T_J

–40

–65

°C

Storage temperature, T_stg

150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Values are verified by characterization and are not production tested.

(3) To maintain the recommended operating conditions for T_J, see the Thermal Information.

6.2 ESD Ratings

VALUE

±4000

±1500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

UNIT

VCCI

VCCI Input supply voltage

Driver output bias supply

3

5.5

V

VDDA,

VDDB

9.2

18

V

T_J

Junction Temperature

Ambient Temperature

–40

150

125

°C

T_A

4

UCC21222-Q1

www.ti.com.cn

ZHCSHQ7 –FEBRUARY 2018

6.4 Thermal Information

UCC21222-Q1

THERMAL METRIC⁽¹⁾

D (SOIC)

16 PINS

68.5

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

30.5

22.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

17.1

ψ_JB

22.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Power Ratings

VALUE

1825

15

UNIT

mW

P_D

Power dissipation

VCCI = 5.5 V, VDDA/B = 12 V, INA/B = 3.3

V, 5.4 MHz 50% duty cycle square wave 1.0-

nF load

P_DI

Power dissipation by transmitter side

Power dissipation by each driver side

P_DA, P_DB

905

5

UCC21222-Q1

ZHCSHQ7 –FEBRUARY 2018

www.ti.com.cn

6.6 Insulation Specifications

PARAMETER

TEST CONDITIONS

Shortest pin-to-pin distance through air

VALUE

> 4

UNIT

mm

CLR

CPG

External clearance⁽¹⁾

External creepage⁽¹⁾

Shortest pin-to-pin distance across the package surface

> 4

mm

Distance through the

insulation

DTI

CTI

Minimum internal gap (internal clearance)

DIN EN 60112 (VDE 0303-11); IEC 60112

>17

µm

V

Comparative tracking index

Material group

> 600

I

Rated mains voltage ≤ 150 V_RMS

Rated mains voltage ≤ 300 V_RMS

Rated mains voltage ≤ 600 V_RMS

I-IV

I-III

I-II

Overvoltage category per

IEC 60664-1

DIN V VDE V 0884-11:2017-01⁽²⁾

Maximum repetitive peak

V_IORM

AC voltage (bipolar)

990

V_PK

isolation voltage

AC voltage (sine wave); time dependent dielectric breakdown

(TDDB) test;

700

990

V_RMS

V_DC

V_PK

Maximum working isolation

voltage

V_IOWM

DC Voltage

Maximum transient isolation V_TEST= V_IOTM, t = 60 s (qualification); V_TEST= 1.2 × V_IOTM, t

V_IOTM

V_IOSM

4242

voltage

= 1 s (100% production)

Maximum surge isolation

voltage⁽³⁾

Test method per IEC 62368-1, 1.2/50 μs waveform, V_TEST=

1.3 × V_IOSM= 7800 V_PK(qualification)

6000

<5

V_PK

Method a, After Input/Output safety test subgroup 2/3,

V_ini= V_IOTM, t_ini= 60s;

V_pd(m)= 1.2 × V_IORM, t_m= 10s

Method a, After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60s;

V_pd(m)= 1.2 × V_IORM, t_m= 10s

<5

q_pd

Apparent charge⁽⁴⁾

pC

Method b1; At routine test (100% production) and

preconditioning (type test)

V_ini= 1.2 × V_IOTM; t_ini= 1 s;

<5

V_pd(m)= 1.5 × V_IORM, t_m= 1s

Barrier capacitance, input to

output⁽⁵⁾

C_IO

R_IO

V_IO= 0.4 sin (2πft), f =1 MHz

0.5

pF

V_IO= 500 V at T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

Isolation resistance, input to

output

V_IO= 500 V at 100°C ≤ T_A≤ 125°C

V_IO= 500 V at T_S=150°C

Ω

Pollution degree

Climatic category

2

40/125/21

UL 1577

V_TEST= V_ISO= 3000 V_RMS, t = 60 sec. (qualification),

V_TEST= 1.2 × V_ISO= 3600V_RMS, t = 1 sec (100% production)

V_ISO

Withstand isolation voltage

3000

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall

be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-pin device.

6

UCC21222-Q1

www.ti.com.cn

ZHCSHQ7 –FEBRUARY 2018

6.7 Safety-Related Certifications

VDE

CSA

UL

CQC

Plan to certify according to

DIN V VDE V 0884-11:2017- Plan to certify according to IEC 60950-

01 and DIN EN 61010-1

(VDE 0411-1):2011-07

Plan to be recognized under

UL 1577 Component

Recognition Program

Plan to certify according to GB

4943.1-2011

1, IEC 62368-1 and IEC 61010-1

6.8 Safety-Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER

TEST CONDITIONS

SIDE

MIN

TYP

MAX

UNIT

θ_JA= 68.5ºC/W, V_VDDA/B= 12 V, T_J=

150°C, T_A= 25°C

See

Safety output supply

current

DRIVER A,

DRIVER B

I_S

75

mA

INPUT

DRIVER A

DRIVER B

TOTAL

15

905

θ_JA= 68.5ºC/W, V_VCCI= 5.5 V, T_J= 150°C,

T_A= 25°C

See

P_S

T_S

Safety supply power

Safety temperature⁽¹⁾

mW

°C

905

1825

150

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand P_Sshould not be

exceeded. These limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the Thermal Information table is that of a device installed on a high-K test board for

leaded surface-mount packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum allowed junction temperature.

P_S= I_S× V_I, where V_Iis the maximum input voltage.

7

UCC21222-Q1

ZHCSHQ7 –FEBRUARY 2018

www.ti.com.cn

6.9 Electrical Characteristics

V_VCCI= 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1-µF capacitor from VDDA/B to VSSA/B, V_VDDA= V_VDDB= 12

V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, C_L= 0 pF, T_J= –40°C to +150°C unless

otherwise noted⁽¹⁾⁽²⁾

.

PARAMETER

SUPPLY CURRENTS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_VCCI

VCCI quiescent current

V_INA= 0 V, V_INB= 0 V

1.5

1.0

2.5

2.0

1.8

mA

VDDA and VDDB quiescent

current

I_VDDA, I_VDDB

I_VCCI

V_INA= 0 V, V_INB= 0 V

VCCI operating current

(f = 500 kHz) current per channel

(f = 500 kHz) current per channel,

C_OUT= 100 pF,

V_VDDA, V_VDDB= 12 V

VDDA and VDDB operating

current

I_VDDA, I_VDDB

2.5

mA

VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS

V_{VCCI_ON}

V_{VCCI_OFF}

V_{VCCI_HYS}

UVLO Rising threshold

UVLO Falling threshold

UVLO Threshold hysteresis

2.55

2.35

2.7

2.5

0.2

2.85

2.65

V

VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS

V_{VDDA_ON}

V_{VDDB_ON}

,

UVLO Rising threshold

UVLO Falling threshold

UVLO Threshold hysteresis

8

8.5

8

9

V

V_{VDDA_OFF}

V_{VDDB_OFF}

,

7.5

8.5

V_{VDDA_HYS}

V_{VDDB_HYS}

,

0.5

INA, INB AND DISABLE

V_INAH, V_INBH

V_DISH

,

Input high threshold voltage

Input low threshold voltage

1.6

0.8

1.8

1

2

V

V_INAL, V_INBL

V_DISL

,

1.25

V_{INA_HYS}

V_{INB_HYS}

V_{DIS_HYS}

,

Input threshold hysteresis

0.8

V

OUTPUT

C_VDD= 10 µF, C_LOAD= 0.18 µF, f

= 1 kHz, bench measurement

I_OA+, I_OB+

Peak output source current

Peak output sink current

4

6

A

C_VDD= 10 µF, C_LOAD= 0.18 µF, f

= 1 kHz, bench measurement

I_OA-, I_OB-

I_OUT= –10 mA, R_OHA, R_OHBdo not

represent drive pull-up

R_OHA, R_OHB

Output resistance at high state

performance. See t_RISEin

Switching Characteristics and

Output Stage for details.

5

Ω

R_OLA, R_OLB

V_OHA, V_OHB

Output resistance at low state

Output voltage at high state

I_OUT= 10 mA

0.55

Ω

V_VDDA, V_VDDB= 12 V, I_OUT= –10

mA

11.95

V

V_VDDA, V_VDDB= 12 V, I_OUT= 10

mA

V_OLA, V_OLB

Output voltage at low state

5.5

mV

V

Driver output (V_OUTA, V_OUTB

active pull down

)

V_VDDAand V_VDDBunpowered,

I_OUTA, I_OUTB= 200 mA

V_OAPDA, V_OAPDB

1.75

2.1

(1) Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless

otherwise noted).

(2) Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for

purposes of TI's product warranty.

8

UCC21222-Q1

www.ti.com.cn

ZHCSHQ7 –FEBRUARY 2018

Electrical Characteristics (continued)

V_VCCI= 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1-µF capacitor from VDDA/B to VSSA/B, V_VDDA= V_VDDB= 12

V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, C_L= 0 pF, T_J= –40°C to +150°C unless

otherwise noted⁽¹⁾⁽²⁾

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DEAD TIME AND OVERLAP PROGRAMMING

DT pin open or pull DT pin to

VCCI

Overlap determined by INA, INB

-

R_DT= 10 kΩ

R_DT= 20 kΩ

R_DT= 50 kΩ

R_DT= 10 kΩ

R_DT= 20 kΩ

R_DT= 50 kΩ

80

100

200

500

0

120

240

600

10

Dead time, DT

160

ns

400

-

Dead time matching, |DT_AB-DT_BA

|

0

20

ns

0

65

6.10 Switching Characteristics

V_VCCI= 3.3 V or 5.5 V, 0.1-µF capacitor from VCCI to GND, V_VDDA= V_VDDB= 12 V, 1-µF capacitor from VDDA and VDDB to

VSSA and VSSB, load capacitance C_OUT= 0 pF, T_J= –40°C to +150°C unless otherwise noted⁽¹⁾

.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t_RISE

Output rise time, see 图 28

C_VDD= 10 µF, C_OUT= 1.8 nF,

V_VDDA, V_VDDB= 12 V, f = 1 kHz

5

16

ns

t_FALL

t_PWmin

Output fall time, see 图 28

C_VDD= 10 µF, C_OUT= 1.8 nF ,

V_VDDA, V_VDDB= 12 V, f = 1 kHz

6

12

20

ns

Minimum input pulse width that

passes to output,

see 图 25 and 图 26

10

Output does not change the state if

input signal less than t_PWmin

t_PDHL

t_PDLH

t_PWD

t_DM

Propagation delay at falling edge,

see 图 27

INx high threshold, V_INH, to 10% of

the output

28

40

5.5

5

ns

Propagation delay at rising edge,

see 图 27

INx low threshold, V_INL, to 90% of

the output

Pulse width distortion in each

channel, see 图 27

|t_PDLHA– t_PDHLA|, |t_PDLHB– t_PDHLB

|

Propagation delays matching,

|t_PDLHA– t_PDLHB|, |t_PDHLA– t_PDHLB|,

see 图 27

f = 250kHz

t_{VCCI+ to}

OUT

VCCI Power-up Delay Time: UVLO

Rise to OUTA, OUTB,

See 图 31

40

22

INA or INB tied to VCCI

µs

t_{VDD+ to}

OUT

VDDA, VDDB Power-up Delay Time:

UVLO Rise to OUTA, OUTB

See 图 32

Slew rate of GND vs. VSSA/B, INA

and INB both are tied to GND or

VCCI; V_CM=1000 V;

High-level common-mode transient

immunity (See CMTI Testing)

|CM_H|

|CM_L|

100

V/ns

Slew rate of GND vs. VSSA/B, INA

and INB both are tied to GND or

VCCI; V_CM=1000 V;

Low-level common-mode transient

immunity (See CMTI Testing)

(1) Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for

purposes of TI's product warranty.

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6.11 Thermal Derating Curves

100

2000

1600

1200

800

400

0

I_VDDA/Bfor VDD = 12V

I_VDDA/Bfor VDD = 18V

80

60

40

20

0

50

100

150

200

0

50

100

150

200

Ambient Temperature (èC)

D002

D003

Current in Each Channel with Both Channels Running

Simultaneously

图 2. Thermal Derating Curve for Limiting Power Per VDE

图 1. Thermal Derating Curve for Limiting Current Per VDE

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6.12 Typical Characteristics

VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, T_A= 25°C, C_L= 0 pF unless otherwise noted.

1.5

1.45

1.4

2.7

2.65

2.6

VCCI = 3.3V

VCCI = 5.0V

1.35

1.3

2.55

2.5

VCCI = 3.3V, f_S=50kHz

VCCI = 3.3V, f_S=1.0MHz

VCCI = 5.0V, f_S=50kHz

VCCI = 5.0V, f_S=1.0MHz

1.25

2.45

1.2

2.4

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Temperature (èC)

Junction Temperature (èC)

D004

D005

No Load

INA = INB = GND

图 3. VCCI Quiescent Current

图 4. VCCI Operating Current - I_VCCI

2.6

2.58

2.56

2.54

2.52

2.5

1.6

1.4

1.2

1

VCCI = 3.3V

VCCI = 5.0V

VDD = 12V

VDD = 18V

0.8

0

100 200 300 400 500 600 700 800 900 1000

-40 -20

0

20

40

60

80 100 120 140 160

Frequency (kHz)

Junction Temperature (èC)

D006

D007

No Load

INA = INB = GND

图 5. VCCI Operating Current vs. Frequency

图 6. VDD Per Channel Quiescent Current (I_VDDA, I_VDDB)

3

2.7

2.4

2.1

1.8

1.5

1.2

0.9

3

2.8

2.6

2.4

2.2

2

VDD = 12V, f_S=50kHz

VDD = 12V, f_S=1.0MHz

VDD = 15V, f_S=50kHz

VDD = 15V, f_S=1.0MHz

1.8

1.6

1.4

1.2

1

VDD = 12V

VDD = 15V

-40 -20

0

20

40

60

80 100 120 140 160

0

100 200 300 400 500 600 700 800 900 1000

Junction Temperature (èC)

Frequency (kHz)

D008

D009

No Load

INA and INB both switching

图 7. VDD Per Channel Operating Current - I_VDDA/B

图 8. Per Channel Operating Current (I_VDDA/B) vs. Frequency

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Typical Characteristics (接下页)

VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, T_A= 25°C, C_L= 0 pF unless otherwise noted.

212

208

204

200

196

192

188

2.9

2.8

2.7

2.6

2.5

2.4

V_{VCCI_ON}

V_{VCCI_OFF}

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (èC)

D010

D011

图 9. VCCI UVLO Threshold Voltage

图 10. VCCI UVLO Threshold Hysteresis Voltage

540

530

520

510

500

9

8.7

8.4

8.1

7.8

7.5

V_{VDD_ON}

V_{VDD_OFF}

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (èC)

D012

D013

图 11. VDD UVLO Threshold Voltage

图 12. VDD UVLO Threshold Hysteresis Voltage

875

850

825

800

775

750

2.5

2

IN/DIS High

IN/DIS Low

1.5

1

0.5

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (èC)

D014

D015

图 13. INA/INB/DIS High and Low Threshold Voltage

图 14. INA/INB/DIS High and Low Threshold Hysteresis

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Typical Characteristics (接下页)

VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, T_A= 25°C, C_L= 0 pF unless otherwise noted.

10

37.5

OUTA/OUTB Pull-Up

Rising Edge (t_PDLH

)

OUTA/OUTB Pull-Down

Falling Edge (t_PDHL

)

35

8

32.5

30

6

27.5

25

4

2

22.5

20

0

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (èC)

D016

D017

图 15. OUT Pullup and Pulldown Resistance

图 16. Propagation Delay, Rising and Falling Edge

3

2

3

2

Rising Edge

Falling Edge

1

0

-1

-2

-3

-1

-2

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (èC)

D018

D019

t_PDLH– t_PDHL

图 17. Propagation Delay Matching, Rising and Falling Edge

图 18. Pulse Width Distortion

10

60

56

52

48

44

40

36

32

Rising

Falling

DIS Low to High

DIS High to Low

8

6

4

2

0

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (èC)

D020

D021

C_L= 1.8 nF

图 19. Rise Time and Fall Time

图 20. DISABLE Response Time

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Typical Characteristics (接下页)

VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, T_A= 25°C, C_L= 0 pF unless otherwise noted.

10

2.5

VDD Open

VDD Tied to VSS

9

2

8

1.5

1

7

6

0.5

5

0

4

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (èC)

D022

D023

图 21. OUTPUT Active Pulldown Voltage

图 22. Minimum Pulse that Changes Output

700

600

500

400

300

200

100

0

6

5

R_DT= 10kW

R_DT= 20kW

R_DT= 50kW

R_DT= 10kW

R_DT= 20kW

R_DT= 50kW

4

3

2

1

0

-1

-2

-40 -20

0

20

40

60

80 100 120 140 160

-40 -20

0

20

40

60

80 100 120 140 160

Junction Temperature (°C)

D024

D025

图 23. Dead Time Temperature Drift

图 24. Dead Time Matching

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7 Parameter Measurement Information

7.1 Minimum Pulses

A typical 5-ns deglitch filter removes small input pulses introduced by ground bounce or switching transients. An

input pulse with duration longer than t_PWmin, typically 10 ns, must be asserted on INA or INB to guarantee an

output state change at OUTA or OUTB. See 图 25 and 图 26 for detailed information of the operation of deglitch

filter.

INx

V_INH

V_INL

V_INH

INx

t_PWM< t_PWmin

OUTx

图 25. Deglitch Filter – Turn ON

图 26. Deglitch Filter – Turn OFF

7.2 Propagation Delay and Pulse Width Distortion

图 27 shows calculation of pulse width distortion (t_PWD) and delay matching (t_DM) from the propagation delays of

channels A and B. To measure delay matching, both inputs must be in phase, and the DT pin must be shorted to

VCCI to enable output overlap.

INA/B

tPDHLA

tPDLHA

tDM

OUTA

OUTB

tPDLHB

tPDHLB

tPWDB = |tPDLHB t tPDHLB|

图 27. Delay Matching and Pulse Width Distortion

7.3 Rising and Falling Time

图 28 shows the criteria for measuring rising (t_RISE) and falling (t_FALL) times. For more information on how short

rising and falling times are achieved see Output Stage.

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Rising and Falling Time (接下页)

90%

t_FALL

80%

t_RISE

20%

10%

图 28. Rising and Falling Time Criteria

7.4 Input and Disable Response Time

图 29 shows the response time of the disable function. For more information, see Disable Pin.

INx

DIS High

Response Time

DIS

DIS Low

Response Time

OUTx

t_PDLH

90%

t_PDHL

10%

图 29. Disable Pin Timing

7.5 Programmable Dead Time

Tying DT to VCCI or leaving DT open allows the outputs to overlap. Placing a resistor (R_DT) between DT and

GND adjusts dead time according to the equation: DT (in ns) = 10 × R_DT(in kΩ). TI recommends bypassing this

pin with a ceramic capacitor, 2.2 nF or greater, to achieve better noise immunity. Place this capacitor and R_DT

close to the DT pin.. For more details on dead time, refer to Programmable Dead Time (DT) Pin.

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Programmable Dead Time (接下页)

INA

INB

90%

10%

OUTA

tPDHL

tPDLH

90%

10%

OUTB

tPDHL

Dead Time

(Determined by Input signals if

longer than DT set by RDT

(Set by RDT

)

图 30. Dead Time Switching Parameters

7.6 Power-up UVLO Delay to OUTPUT

Whenever the supply voltage VCCI crosses from below the falling threshold V_{VCCI_OFF}to above the rising

threshold V_{VCCI_ON}, and whenever the supply voltage VDDx crosses from below the falling threshold V_{VDDx_OFF}to

above the rising threshold V_{VDDx_ON}, there is a delay before the outputs begin responding to the inputs. For VCCI

UVLO this delay is defined as t_{VCCI+ to OUT}, and is typically 40 µs. For VDDx UVLO this delay is defined as t_{VDD+ to}

_OUT, and is typically 22 µs. TI recommends allowing some margin before driving input signals, to ensure the

driver VCCI and VDD bias supplies are fully activated. 图 31 and 图 32 show the power-up UVLO delay timing

diagram for VCCI and VDD.

Whenever the supply voltage VCCI crosses below the falling threshold V_{VCCI_OFF}, or VDDx crosses below the

falling threshold V_{VDDx_OFF}, the outputs stop responding to the inputs and are held low within 1 µs. This

asymmetric delay is designed to ensure safe operation during VCCI or VDDx brownouts.

VCCI,

INx

VCCI,

INx

V_{VCCI_ON}

V_{VCCI_OFF}

VDDx

t_{VCCI+ to OUT}

t_{VDD+ to OUT}

V_{VDD_ON}

V_{VDD_OFF}

OUTx

图 31. VCCI Power-up UVLO Delay

图 32. VDDA/B Power-up UVLO Delay

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7.7 CMTI Testing

图 33 is a simplified diagram of the CMTI testing configuration.

VCC

VDD

VDDA

OUTA

VSSA

INA

1

16

15

14

OUTA

INB

2

VCC

VCCI

3

GND

4

Functional

Isolation

DIS

5

VDDB

11

10

9

OUTB

DT

6

OUTB

VSSB

GND

VCCI

8

VSS

Common Mode Surge

Generator

图 33. Simplified CMTI Testing Setup

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8 Detailed Description

8.1 Overview

In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are

often placed between the output of control devices and the gates of power transistors. There are several

instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.

This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V

logic signal capable of only delivering a few mA.

The UCC21222-Q1 is a flexible dual gate driver which can be configured to fit a variety of power supply and

motor drive topologies, as well as drive several types of transistors. The UCC21222-Q1 has many features that

allow it to integrate well with control circuitry and protect the gates it drives such as: resistor-programmable dead

time (DT) control, disable pin, and under voltage lock out (UVLO) for both input and output supplies. The

UCC21222-Q1 also holds its outputs low when the inputs are left open or when the input pulse duration is too

short. The driver inputs are CMOS and TTL compatible for interfacing with digital and analog power controllers

alike. Each channel is controlled by its respective input pins (INA and INB), allowing full and independent control

of each of the outputs.

8.2 Functional Block Diagram

INA

1

16 VDDA

200 kW

VCCI

Driver

MOD

DEMOD

Deglitch

Filter

15 OUTA

14 VSSA

UVLO

VCCI 3,8

UVLO

GND

DT

4

6

13 NC

12 NC

Dead Time

Control

Functional Isolation

DIS

5

11 VDDB

Driver

50 kW

MOD

DEMOD

Deglitch

Filter

10 OUTB

UVLO

INB

NC

2

7

9

VSSB

200 kW

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8.3 Feature Description

8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)

The UCC21222-Q1 has an internal under voltage lock out (UVLO) protection feature on each supply voltage

between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than V_{VDD_ON}at device

start-up or lower than V_{VDD_OFF}after start-up, the VDD UVLO feature holds the channel output low, regardless of

the status of the input pins.

When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an

active clamp circuit that limits the voltage rise on the driver outputs (illustrated in 图 34). In this condition, the

upper PMOS is resistively held off by R_Hi-Zwhile the lower NMOS gate is tied to the driver output through R_CLAMP

.

In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device,

typically around 1.5V, regardless of whether bias power is available.

VDD

R_{HI_Z}

Output

Control

OUT

R_CLAMP

R_CLAMPis activated

during UVLO

VSS

图 34. Simplified Representation of Active Pull Down Feature

The VDD UVLO protection has a hysteresis feature (V_{VDD_HYS}). This hysteresis prevents chatter when there is

ground noise from the power supply. This also allows the device to accept small drops in bias voltage, which

commonly occurs when the device starts switching and operating current consumption increases suddenly.

The inputs of the UCC21222-Q1 also have an internal under voltage lock out (UVLO) protection feature. The

inputs cannot affect the outputs unless the supply voltage VCCI exceeds V_{VCCI_ON}on start-up. The outputs are

held low and cannot respond to inputs when the supply voltage VCCI drops below V_{VCCI_OFF}after start-up. Like

the UVLO for VDD, there is hystersis (V_{VCCI_HYS}) to ensure stable operation.

表 1. VCCI UVLO Feature Logic

CONDITION

INPUTS

OUTPUTS

INA

H

L

INB

L

OUTA

OUTB

VCCI-GND < V_{VCCI_ON}during device start up

VCCI-GND < V_{VCCI_OFF}after device start up

L

H

L

H

L

H

L

H

L

H

L

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表 2. VDD UVLO Feature Logic

CONDITION

INPUTS

OUTPUTS

INA

H

L

INB

OUTA

OUTB

VDD-VSS < V_{VDD_ON}during device start up

VDD-VSS < V_{VDD_OFF}after device start up

L

H

L

H

L

H

L

H

L

H

L

8.3.2 Input and Output Logic Table

Assume VCCI, VDDA, VDDB are powered up (see VDD, VCCI, and Under Voltage Lock Out (UVLO) for more information on

UVLO operation modes). 表 3 shows the operation with INA, INB and DIS and the corresponding output state.

表 3. INPUT/OUTPUT Logic Table⁽¹⁾

INPUTS

OUTPUTS

DIS

NOTE

INA

L

INB

L

OUTA

OUTB

L or Left Open

L

H

L

H

If the dead time function is used, output transitions occur after the dead

time expires. See .

H

L

H

L

H

L

H

DT is programmed with R_DT

.

H

L

H

L

DT pin is left open or pulled to VCCI.

Left Open Left Open L or Left Open

X

H

L

(1) "X" means L, H or left open. TI recommends connecting any unused inputs (INA, INB, DIS) to GND for improved noise immunity.

8.3.3 Input Stage

The input pins (INA, INB, and DIS) of the UCC21222-Q1 are based on a TTL and CMOS compatible input-

threshold logic that is totally isolated from the VDD supply voltage of the output channels. The input pins are

easy to drive with logic-level control signals (such as those from 3.3-V microcontrollers), since the UCC21222-Q1

has a typical high threshold (V_INAH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature

(see 图 11 and 图 13). A wide hysterisis (V_{INA_HYS}) of 0.8 V makes for good noise immunity and stable operation.

If any of the inputs are ever left open, internal pull-down resistors force the pin low. These resistors are typically

200 kΩ for INA/B and 50 kΩ for DIS (see Functional Block Diagram). TI recommends grounding any unused

inputs.

The amplitude of any signal applied to the inputs must never be at a voltage higher than VCCI.

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8.3.4 Output Stage

The UCC21222-Q1 output stage features a pull-up structure which delivers the highest peak-source current

when it is most needed: during the Miller plateau region of the power-switch turn on transition (when the power

switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel

MOSFET and an additional pull-up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to

provide a boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning on the

N-channel MOSFET during a narrow instant when the output is changing states from low to high. The on-

resistance of this N-channel MOSFET (R_NMOS) is approximately 1.47 Ω when activated.

The R_OHparameter is a DC measurement and it is representative of the on-resistance of the P-channel device

only. This is because the pull-up N-channel device is held in the off state in DC condition and is turned on only

for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the

UCC21222-Q1 pull-up stage during this brief turn-on phase is much lower than what is represented by the R_OH

parameter.

The pull-down structure of the UCC21222-Q1 is composed of an N-channel MOSFET. The R_OLparameter, which

is also a DC measurement, is representative of the impedance of the pull-down state in the device. Both outputs

of the UCC21222-Q1 are capable of delivering 4-A peak source and 6-A peak sink current pulses. The output

voltage swings between VDD and VSS for rail-to-rail operation.

VDD

R_OH

Shoot-

R_NMOS

Input

Signal

Through

Prevention

Circuitry

OUT

VSS

R_OL

Pull Up

图 35. Output Stage

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8.3.5 Diode Structure in the UCC21222-Q1

图 36 illustrates the multiple diodes involved in the ESD protection components. This provides a pictorial

representation of the absolute maximum rating for the device.

VCCI

3,8

VDDA

16

20 V

15 OUTA

14 VSSA

6 V 6 V

INA

INB

DIS

DT

1

2

5

6

11 VDDB

10 OUTB

20 V

4

9

GND

VSSB

图 36. ESD Structure

8.4 Device Functional Modes

8.4.1 Disable Pin

When the DIS pin is set high, both outputs are shut down simultaneously. When the DIS pin is set low or left

open, the UCC21222-Q1 operates normally. The DIS circuit logic structure is nearly identical compared to INA or

INB, and the propagation delay is similar (see 图 20). The DIS pin is only functional (and necessary) when VCCI

stays above the UVLO threshold. It is recommended to tie this pin to GND if the DIS pin is not used to achieve

better noise immunity.

8.4.2 Programmable Dead Time (DT) Pin

The UCC21222-Q1 allows the user to adjust dead time (DT) in the following ways:

8.4.2.1 DT Pin Tied to VCCI or DT Pin Left Open

Outputs completely match inputs, so no minimum dead time is asserted. This allows the outputs to overlap.

8.4.2.2 Connecting a Programming Resistor between DT and GND Pins

Program t_DTby placing a resistor, R_DT, between the DT pin and GND. The appropriate R_DTvalue can be

determined from:

t_DTö 10ìR_DT

where

•

t_DTis the programmed dead time, in nanoseconds.

R_DTis the value of resistance between DT pin and GND, in kilo-ohms.

(1)

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Device Functional Modes (接下页)

The steady state voltage at the DT pin is about 0.8 V. R_DTprograms a small current at this pin, which sets the

dead time. As the value of R_DTincreases, the current sourced by the DT pin decreases. The DT pin current will

be less than 10 µA when R_DT= 100 kΩ. For larger values of R_DT, TI recommends placing R_DTand a ceramic

capacitor, 2.2 nF or greater, as close to the DT pin as possible to achieve greater noise immunity and better

dead time matching between both channels.

The falling edge of an input signal initiates the programmed dead time for the other signal. The programmed

dead time is the minimum enforced duration in which both outputs are held low by the driver. The outputs may

also be held low for a duration greater than the programmed dead time, if the INA and INB signals include a

dead time duration greater than the programmed minimum. If both inputs are high simultaneously, both outputs

will immediately be set low. This feature is used to prevent shoot-through in half-bridge applications, and it does

not affect the programmed dead time setting for normal operation. Various driver dead time logic operating

conditions are illustrated and explained in 图 37.

INA

INB

DT

OUTA

OUTB

A

B

C

D

E

F

图 37. Input and Output Logic Relationship with Input Signals

Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead

time to OUTA. OUTA is allowed to go high after the programmed dead time.

Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed

dead time to OUTB. OUTB is allowed to go high after the programmed dead time.

Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead

time for OUTA. In this case, the input signal dead time is longer than the programmed dead time. When INA

goes high after the duration of the input signal dead time, it immediately sets OUTA high.

Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead

time to OUTB. In this case, the input signal dead time is longer than the programmed dead time. When INB goes

high after the duration of the input signal dead time, it immediately sets OUTB high.

Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, OUTB is immediately pulled

low. After some time OUTB goes low and assigns the programmed dead time to OUTA. OUTB is already low.

After the programmed dead time, OUTA is allowed to go high.

Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, OUTA is immediately pulled

low. After some time OUTA goes low and assigns the programmed dead time to OUTB. OUTA is already low.

After the programmed dead time, OUTB is allowed to go high.

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9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The UCC21222-Q1 effectively combines both isolation and buffer-drive functions. The flexible, universal

capability of the UCC21222-Q1 (with up to 5.5-V VCCI and 18-V VDDA/VDDB) allows the device to be used as a

low-side, high-side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or GaN transistor. With

integrated components, advanced protection features (UVLO, dead time, and disable) and optimized switching

performance, the UCC21222-Q1 enables designers to build smaller, more robust designs for enterprise, telecom,

automotive, and industrial applications with a faster time to market.

9.2 Typical Application

The circuit in 图 38 shows a reference design with the UCC21222-Q1 driving a typical half-bridge configuration

which could be used in several popular power converter topologies such as synchronous buck, synchronous

boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.

VCC

VDD

R_BOOT

HV DC-Link

C_IN

VCC

VDDA

INA

INB

R_OFF

R_ON

16

15

14

PWM-A

1

2

3

4

5

6

8

R_IN

OUTA

VSSA

PWM-B

R_GS

C_IN

C_BOOT

VCCI

GND

mC

C_VCC

SW

Functional

Isolation

VDD

DIS

DT

DIS

VDDB

I/O

R_OFF

R_ON

11

10

9

R_DIS

C_DIS

OUTB

VSSB

R_DT

C_DT

R_GS

VCCI

C_BOOT

图 38. Typical Application Schematic

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Typical Application (接下页)

9.2.1 Design Requirements

表 4 lists reference design parameters for the example application: UCC21222-Q1 driving 650-V MOSFETs in a

high side-low side configuration.

表 4. UCC21222-Q1 Design Requirements

PARAMETER

Power transistor

VCC

VALUE

UNITS

650-V, 150-mΩ R_{DS_ON}with 12-V V_GS

-

V

5.0

12

VDD

V

Input signal amplitude

Switching frequency (f_s)

Dead Time

3.3

100

200

400

V

kHz

ns

V

DC link voltage

9.2.2 Detailed Design Procedure

9.2.2.1 Designing INA/INB Input Filter

It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)

the signal at the output. However, a small input R_IN-C_INfilter can be used to filter out the ringing introduced by

non-ideal layout or long PCB traces.

Such a filter should use an R_INin the range of 0 Ω to 100 Ω and a C_INbetween 10 pF and 100 pF. In the

example, an R_IN= 51 Ω and a C_IN= 33 pF are selected, with a corner frequency of approximately 100 MHz.

When selecting these components, it is important to pay attention to the trade-off between good noise immunity

and propagation delay.

9.2.2.2 Select Dead Time Resistor and Capacitor

From 公式 1, a 20-kΩ resistor is selected to set the dead time to 200 ns. A 2.2-nF capacitor is placed in parallel

close to the DT pin to improve noise immunity.

9.2.2.3 Select External Bootstrap Diode and its Series Resistor

The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side

transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation

in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.

Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver

circuit.

When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes

or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the loss

introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage is 400

V_DC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good margin.

Therefore, a 600-V ultrafast diode, MURA160T3G, is chosen in this example.

A bootstrap resistor, R_BOOT, is used to reduce the inrush current in D_BOOTand limit the ramp up slew rate of

voltage of VDDA-VSSA during each switching cycle, especially when the VSSA(SW) pin has an excessive

negative transient voltage. The recommended value for R_BOOTis between 1 Ω and 20 Ω depending on the diode

used. In the example, a current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode.

The estimated worst case peak current through D_Bootis,

V_DD- V_BDF

12V -1.5V

2.7W

I_{DBoot pk}

=

ö 4A

(

)

R_Boot

where

•

V_BDFis the estimated bootstrap diode forward voltage drop around 4 A.

(2)

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9.2.2.4 Gate Driver Output Resistor

The external gate driver resistors, R_ON/R_OFF, are used to:

1. Limit ringing caused by parasitic inductances/capacitances.

2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.

3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.

4. Reduce electromagnetic interference (EMI).

As mentioned in Output Stage, the UCC21222-Q1 has a pull-up structure with a P-channel MOSFET and an

additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak

source current can be predicted with:

≈

’

V_DD- V_BDF

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}

I_OA+= min 4A,

∆

÷

◊

∆

«

(3)

≈

’

V_DD

I_OB+= min 4A,

∆

÷

◊

∆

«

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}

where

•

R_ON: External turn-on resistance.

R_{GFET_INT}: Power transistor internal gate resistance, found in the power transistor datasheet.

I_O+= Peak source current – The minimum value between 4 A, the gate driver peak source current, and the

calculated value based on the gate drive loop resistance.

(4)

In this example:

V_DD- V_BDF

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}1.47W || 5W + 2.2W +1.5W

12V - 0.8V

I_OA+

=

ö 2.3A

ö 2.5A

(5)

(6)

V_DD

R_NMOS||R_OH+ R_ON+ R_{GFET _Int}1.47W || 5W + 2.2W +1.5W

12V

I_OB+

=

Therefore, the high-side and low-side peak source current is 2.3 A and 2.5 A respectively. Similarly, the peak

sink current can be calculated with:

≈

’

V_DD- V_BDF- V_GDF

R_OL+R_OFF||R_ON+R_{GFET _Int}

I_OA-= min 6A,

∆

÷

◊

∆

«

(7)

≈

’

V_DD- V_GDF

R_OL+ R_OFF||R_ON+ R_{GFET _Int}

I_OB-= min 6A,

∆

÷

◊

∆

«

where

•

R_OFF: External turn-off resistance, R_OFF=0 in this example;

V_GDF: The anti-parallel diode forward voltage drop which is in series with R_OFF. The diode in this example is an

MSS1P4.

•

I_O-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated

value based on the gate drive loop resistance.

(8)

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In this example,

V_DD- V_BDF- V_GDF

R_OL+R_OFF||R_ON+R_{GFET _Int}

12V - 0.8V -0.85V

0.55W + 0W +1.5W

I_OA-

=

ö 5.0A

(9)

V_DD- V_GDF

12V - 0.85V

I_OB-

=

ö 5.4A

R_OL+ R_OFF||R_ON+ R_{GFET _Int}0.55W + 0W +1.5W

(10)

Therefore, the high-side and low-side peak sink current is 5.0 A and 5.4A respectively.

Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic

inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and

undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other

hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (C_ISS) of the power

transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the

parasitic ringing period.

9.2.2.5 Estimating Gate Driver Power Loss

The total loss, P_G, in the gate driver subsystem includes the power losses of the UCC21222-Q1 (P_GD) and the

power losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not

included in P_Gand not discussed in this section.

P_GDis the key power loss which determines the thermal safety-related limits of the UCC21222-Q1, and it can be

estimated by calculating losses from several components.

The first component is the static power loss, P_GDQ, which includes quiescent power loss on the driver as well as

driver self-power consumption when operating with a certain switching frequency. P_GDQis measured on the

bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and

ambient temperature. 图 5 and 图 8 show the operating current consumption vs. operating frequency with no

load. In this example, V_VCCI= 5 V and V_VDD= 12 V. The current on each power supply, with INA/INB switching

from 0 V to 3.3 V at 100 kHz is measured to be I_VCCI≈ 2.5 mA, and I_VDDA= I_VDDB≈ 1.5 mA. Therefore, the P_GDQ

can be calculated with

P_GDQ= V_VCCIìI_VCCI+ V_VDDAìI_DDA+ V_VDDBìI_DDB= 50mW

(11)

The second component is switching operation loss, P_GDO, with a given load capacitance which the driver charges

and discharges the load during each switching cycle. Total dynamic loss due to load switching, P_GSW, can be

estimated with

P_GSW= 2ì V_DDìQ_Gì f_SW

where

•

Q_Gis the gate charge of the power transistor.

(12)

If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail

to the negative rail.

So, for this example application:

P_GSW= 2ì12V ì100nCì100kHz = 240mW

(13)

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Q_Grepresents the total gate charge of the power transistor switching 480 V at 14 A provided by the datasheet,

and is subject to change with different testing conditions. The UCC21222-Q1 gate driver loss on the output

stage, P_GDO, is part of P_GSW. P_GDOwill be equal to P_GSWif the external gate driver resistances are zero, and all

the gate driver loss is dissipated inside the UCC21222-Q1. If there are external turn-on and turn-off resistances,

the total loss will be distributed between the gate driver pull-up/down resistances and external gate resistances.

Importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated

to 4 A/6 A, however, it will be non-linear if the source/sink current is saturated. Therefore, P_GDOis different in

these two scenarios.

Case 1 - Linear Pull-Up/Down Resistor:

≈

’

P_GSW

2

R_OH||R_NMOS

R_OL

P_GDO

=

ì

+

∆

«

÷

◊

R_OH||R_NMOS+R_ON+R_{GFET _Int}R_OL+R_OFF||R_ON+ R_{GFET _Int}

(14)

In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the the

UCC21222-Q1 gate driver loss can be estimated with:

≈

∆

«

’

÷

◊

240mW

2

5W ||1.47W

0.55W

P_GDO

=

ì

+

ö 60mW

5W ||1.47W + 2.2W +1.5W 0.55W + 0W +1.5W

(15)

Case 2 - Nonlinear Pull-Up/Down Resistor:

T_{R _ Sys}

T_{F _ Sys}

»

ÿ

Ÿ

…

P_GDO= 2ì f_SWì 4A ì

V_DD- V_OUTA/B

t

( )

dt + 6A ì

V_OUTA/Bt dt

( )

(

)

—

…

Ÿ

0

…

Ÿ

⁄

where

•

V_OUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be

simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load

capacitor. Then, the V_OUTA/B(t) waveform will be linear and the T_{R_Sys}and T_{F_Sys}can be easily predicted.

(16)

For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the P_GDO

will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull-

down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC21222-

Q1 P_GD, is:

P_GD= P_GDQ+ P_GDO

(17)

which is equal to 127 mW in the design example.

9.2.2.6 Estimating Junction Temperature

The junction temperature of the UCC21222-Q1 can be estimated with:

T_J= T_C+ Y_JTìP_GD

where

•

T_Jis the junction temperature.

T_Cis the UCC21222-Q1 case-top temperature measured with a thermocouple or some other instrument.

ψ_JTis the junction-to-top characterization parameter from the Thermal Information table.

(18)

Using the junction-to-top characterization parameter (Ψ_JT) instead of the junction-to-case thermal resistance

(R_ΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal

energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the

total energy is released through the top of the case (where thermocouple measurements are usually conducted).

R_ΘJCcan only be used effectively when most of the thermal energy is released through the case, such as with

metal packages or when a heatsink is applied to an IC package. In all other cases, use of R_ΘJCwill inaccurately

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estimate the true junction temperature. Ψ_JTis experimentally derived by assuming that the amount of energy

leaving through the top of the IC will be similar in both the testing environment and the application environment.

As long as the recommended layout guidelines are observed, junction temperature estimates can be made

accurately to within a few degrees Celsius. For more information, see the Layout Guidelines and Semiconductor

and IC Package Thermal Metrics application report.

9.2.2.7 Selecting VCCI, VDDA/B Capacitor

Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is

recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with

sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC

will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500

nF when a DC bias of 15 V_DCis applied.

9.2.2.7.1 Selecting a VCCI Capacitor

A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total

current consumption, which is only a few mA. Therefore, a 25-V MLCC with over 100 nF is recommended for this

application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or

electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.

9.2.2.7.2 Selecting a VDDA (Bootstrap) Capacitor

A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for

gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.

The total charge needed per switching cycle can be estimated with

I_VDD@100kHz No Load

(

)

= 100nC +

1.5mA

Q_Total= Q_G+

= 115nC

f_SW

100kHz

where

•

Q_G: Gate charge of the power transistor.

I_VDD: The channel self-current consumption with no load at 100kHz.

(19)

(20)

Therefore, the absolute minimum C_Bootrequirement is:

Q_Total

115nC

0.5V

C_Boot

=

= 230nF

DV_VDDA

where

•

ΔV_VDDAis the voltage ripple at VDDA, which is 0.5 V in this example.

In practice, the value of C_Bootis greater than the calculated value. This allows for the capacitance shift caused by

the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.

Therefore, it is recommended to include a safety-related margin in the C_Bootvalue and place it as close to the

VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.

C_Boot=1ꢀF

(21)

To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with

a low capacitance value, in this example a 100 nF, in parallel with C_Bootto optimize the transient performance.

注

Too large C_BOOTis not good. C_BOOTmay not be charged within the first few cycles and

V_BOOTcould stay below UVLO. As a result, the high-side FET does not follow input signal

command. Also during initial C_BOOTcharging cycles, the bootstrap diode has highest

reverse recovery current and losses.

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9.2.2.7.3 Select a VDDB Capacitor

Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as C_VDDin 图

38) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current for

VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for C_VDD. If the

bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor with

a value over 10 µF, should be used in parallel with C_VDD

.

9.2.2.8 Application Circuits with Output Stage Negative Bias

When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and

TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during

high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on

and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below

the threshold. Below are a few examples of implementing negative gate drive bias.

图 39 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the

isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power

supply, V_A, is equal to 17 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 17 V – 5.1 V ≈ 12 V.

The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for

a half-bridge configuration, and there will be steady state power consumption from R_Z.

HV DC-Link

VDDA

R_OFF

16

1

C_A1

+

V_A

œ

C_IN

R_Z

R_ON

OUTA

VSSA

15

14

2

3

4

5

6

8

C_A2

V_Z

SW

Functional

Isolation

VDDB

11

10

9

OUTB

VSSB

图 39. Negative Bias with Zener Diode on Iso-Bias Power Supply Output

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图 40 shows another example which uses two supplies (or single-input-double-output power supply). Power

supply V_A+determines the positive drive output voltage and V_A–determines the negative turn-off voltage. The

configuration for channel B is the same as channel A. This solution requires more power supplies than the first

example, however, it provides more flexibility when setting the positive and negative rail voltages.

HV DC-Link

VDDA

OUTA

R_OFF

R_ON

16

15

1

2

3

4

5

6

8

C_A1

+

V_A+

œ

C_IN

C_A2

+

V_A-

œ

VSSA

SW

14

Functional

Isolation

VDDB

11

10

9

OUTB

VSSB

图 40. Negative Bias with Two Iso-Bias Power Supplies

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The last example, shown in 图 41, is a single power supply configuration and generates negative bias through a

Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and the

bootstrap power supply can be used for the high side drive. This design requires the least cost and design effort

among the three solutions. However, this solution has limitations:

1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which

means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a fixed

duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors which favor this

solution.

2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,

which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel)

diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%

duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in

the other two example circuits.

VDD

R_BOOT

HV DC-Link

VDDA

C_Z

V_Z

R_OFF

R_ON

16

15

14

1

2

3

4

5

6

8

OUTA

VSSA

C_IN

C_BOOT

R_GS

SW

Functional

Isolation

VDD

VDDB

C_Z

V_Z

R_OFF

R_ON

11

10

9

OUTB

VSSB

C_VDD

R_GS

VSS

图 41. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path

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9.2.3 Application Curves

图 42 and 图 43 shows the bench test waveforms for the design example shown in 图 38 under these conditions:

VCC = 5.0 V, VDD = 12 V, f_SW= 100 kHz, V_DC-Link= 400 V.

Channel 1 (Blue): Gate-source signal on the high side power transistor.

Channel 2 (Cyan): Gate-source signal on the low side power transistor.

Channel 3 (Pink): INA pin signal.

Channel 4 (Green): INB pin signal.

In 图 42, INA and INB are sent complimentary 3.3-V, 20%/80% duty-cycle signals. The gate drive signals on the

power transistor have a 200-ns dead time with 400V high voltage on the DC-Link, shown in the measurement

section of 图 42. Note that with high voltage present, lower bandwidth differential probes are required, which

limits the achievable accuracy of the measurement.

图 43 shows a zoomed-in version of the waveform of 图 42, with measurements for propagation delay and dead

time. Importantly, the output waveform is measured between the power transistors’ gate and source pins, and is

not measured directly from the driver OUTA and OUTB pins.

图 42. Bench Test Waveform for INA/B and OUTA/B

图 43. Zoomed-In bench-test waveform

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10 Power Supply Recommendations

The recommended input supply voltage (VCCI) for the UCC21222-Q1 is between 3 V and 5.5 V. The output bias

supply voltage (VDDA/VDDB) ranges from 9.2 V to 18 V. The lower end of this bias supply range is governed by

the internal under voltage lockout (UVLO) protection feature of each device. VDD and VCCI must not fall below

their respective UVLO thresholds during normal operation. (For more information on UVLO see VDD, VCCI, and

Under Voltage Lock Out (UVLO)). The upper end of the VDDA/VDDB range depends on the maximum gate

voltage of the power device being driven by the UCC21222-Q1. The recommended maximum VDDA/VDDB is 18

V.

A local bypass capacitor should be placed between the VDD and VSS pins, to supply current when the output

goes high into a capacitive load. This capacitor should be positioned as close to the device as possible to

minimize parasitic impedance. A low ESR, ceramic surface mount capacitor is recommended. If the bypass

capacitor impedance is too large, resistive and inductive parasitics could cause the supply voltage seen at the IC

pins to dip below the UVLO threshold unexpectedly. To filter high frequency noise between VDD and VSS, it can

be helpful to place a second capacitor with lower impedance at higher frequency. As an example, the primary

bypass capacitor could be 1 µF, with a secondary high frequency bypass capacitor of 100 pF.

Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of

current drawn by the logic circuitry within the input side of the UCC21222-Q1, this bypass capacitor has a

minimum recommended value of 100 nF.

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11 Layout

11.1 Layout Guidelines

Consider these PCB layout guidelines for in order to achieve optimum performance for the UCC21222-Q1.

11.1.1 Component Placement Considerations

•

Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins

and between the VDD and VSS pins to support high peak currents when turning on the external power

transistor.

•

To avoid large negative transients on the switch node VSSA (HS) pin in bridge configurations, the parasitic

inductances between the source of the top transistor and the source of the bottom transistor must be

minimized.

•

To improve noise immunity when driving the DIS pin from a distant microcontroller, TI recommends adding a

small bypass capacitor, ≥ 1000 pF, between the DIS pin and GND.

If the dead time feature is used, TI recommends placing the programming resistor R_DTand capacitor close to

the DT pin of the UCC21222-Q1 to prevent noise from unintentionally coupling to the internal dead time

circuit. The capacitor should be ≥ 2.2 nF.

11.1.2 Grounding Considerations

•

It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal

physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the

transistors. The gate driver must be placed as close as possible to the transistors.

•

Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-

referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is

recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This

recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and

area on the circuit board is important for ensuring reliable operation.

11.1.3 High-Voltage Considerations

•

To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or

copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may

compromise the isolation performance.

•

For half-bridge or high-side/low-side configurations, maximize the clearance distance of the PCB layout

between the high and low-side PCB traces.

11.1.4 Thermal Considerations

•

A large amount of power may be dissipated by the UCC21222-Q1 if the driving voltage is high, the load is

heavy, or the switching frequency is high (refer to Estimating Gate Driver Power Loss for more details).

Proper PCB layout can help dissipate heat from the device to the PCB and minimize junction to board thermal

impedance (θ_JB).

•

Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority

on maximizing the connection to VSSA and VSSB (see 图 45 and 图 46). However, high voltage PCB

considerations mentioned above must be maintained.

If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and

VSSB pins to internal ground or power planes through multiple vias of adequate size. Ensure that no traces

or copper from different high-voltage planes overlap.

36

UCC21222-Q1

www.ti.com.cn

ZHCSHQ7 –FEBRUARY 2018

11.2 Layout Example

图 44 shows a 2-layer PCB layout example with the signals and key components labeled.

图 44. Layout Example

图 45 and 图 46 shows top and bottom layer traces and copper.

注

There are no PCB traces or copper between the primary and secondary side, which

ensures isolation performance.

PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the

creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node

VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.

图 45. Top Layer Traces and Copper

图 46. Bottom Layer Traces and Copper (Flipped)

37

UCC21222-Q1

ZHCSHQ7 –FEBRUARY 2018

www.ti.com.cn

Layout Example (接下页)

图 47 and 图 48 are 3-D layout pictures with top view and bottom views.

注

The location of the PCB cutout between the primary side and secondary sides, which

ensures isolation performance.

图 47. 3-D PCB Top View

图 48. 3-D PCB Bottom View

38

UCC21222-Q1

www.ti.com.cn

ZHCSHQ7 –FEBRUARY 2018

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

如需相关文档，请参阅：

•

隔离相关术语

12.2 相关链接

下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件以及申请样片或购买产品的快速访问

链接。

表 5. 相关链接

器件

产品文件夹

请单击此处

样片与购买

请单击此处

技术文档

工具和软件

请单击此处

支持和社区

请单击此处

UCC21222-Q1

请单击此处

12.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。请单击右上角的提醒我进行注册，即可每周接收

产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，也

不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

39

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

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束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

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型号：	UCC21222-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有禁用可编程死区时间和 8V UVLO 的汽车类 3.0kVrms 4A/6A 双通道隔离式栅极驱动器栅极驱动驱动器
文件：	总43页 (文件大小：2400K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC21222-Q1 [TI]

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