UCC21222DR [TI]
具有禁用引脚、可编程死区时间和 8V UVLO 的 3.0kVrms 4A/6A 双通道隔离式栅极驱动器 | D | 16 | -40 to 125;型号: | UCC21222DR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有禁用引脚、可编程死区时间和 8V UVLO 的 3.0kVrms 4A/6A 双通道隔离式栅极驱动器 | D | 16 | -40 to 125 栅极驱动 光电二极管 接口集成电路 驱动器 |
文件: | 总46页 (文件大小:2348K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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UCC21222
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
UCC21222 4A、6A、3.0kVRMS 隔离式双通道栅极驱动器(具有死区时
间)
1 特性
3 说明
1
•
可通过电阻器编程的死区时间
UCC21222 器件是具有可编程死区时间的隔离式双通
道栅极驱动器。该器件采用 4A 峰值拉电流和 6A 峰值
灌电流来驱动功率 MOSFET、IGBT 和 GaN 晶体管。
•
•
•
•
通用:双路低侧、双路高侧或半桥驱动器
4A 峰值拉电流、6A 峰值灌电流输出
3V 至 5.5V 输入 VCCI 范围
UCC21222 器件可配置为两个低侧驱动器、两个高侧
驱动器或一个半桥驱动器。该器件的 5ns 延迟匹配性
能允许并联两个输出,能够在重负载条件下将驱动强度
提高一倍,而无内部击穿风险。
高达 18V 的 VDD 输出驱动电源
–
8V VDD UVLO
•
开关参数:
–
–
–
–
28ns 典型传播延迟
输入侧通过一个 3.0kVRMS 隔离栅与两个输出驱动器隔
离,共模瞬态抗扰度 (CMTI) 的最小值为 100V/ns。
10ns 最小脉冲宽度
5ns 最大延迟匹配度
5.5ns 最大脉宽失真度
可通过电阻器编程的死区时间可让您调整系统限制的死
区时间,从而提高效率并防止输出重叠。其他保护 特
性 包括:当 DIS 设置为高电平时,通过禁用功能同时
关闭两路输出;集成的抗尖峰滤波器可抑制短于 5ns
的输入瞬变;以及在输入和输出引脚上对高达 -2V 的
尖峰进行 200ns 的负电压处理。所有电源都有 UVLO
保护。
•
•
•
•
•
•
•
•
TTL 和 CMOS 兼容输入
集成抗尖峰滤波器
I/O 承受 –2V 电压的时间达 200ns
共模瞬态抗扰度 (CMTI) 大于 100V/ns
隔离栅寿命大于 40 年
浪涌抗扰度高达 7800VPK
窄体 SOIC-16 (D) 封装
器件信息(1)
安全相关认证(计划):
器件型号
封装
封装尺寸(标称值)
–
–
–
–
符合 DIN V VDE V 0884-11:2017-01 和 DIN
EN 61010-1 标准的 4242VPK 隔离
UCC21222
SOIC (16)
9.9mm × 3.91mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
符合 UL 1577 标准且长达 1 分钟的 3000VRMS
隔离
功能方框图
获得 CSA 认证,符合 IEC 60950-1、IEC
62368-1 和 IEC 61010-1 终端设备标准
VCCI 3,8
16 VDDA
符合 GB4943.1-2011 的 CQC 认证
使用 UCC21222 并借助 WEBENCH® 电源设计器
Driver
DEMOD UVLO
•
MOD
15 OUTA
14 VSSA
INA
DIS
DT
1
5
6
7
创建定制设计方案
Input
Logic,
Disable,
UVLO,
Dead
2 应用
13 NC
12 NC
Functional Isolation
•
•
•
•
•
•
交流/直流和直流/直流电源中的隔离转换器
服务器、电信、IT 和工业基础设施
电机驱动器和光伏逆变器
HEV 和 EV 电池充电器
工业运输
Time
NC
11 VDDB
10 OUTB
Driver
INB
2
4
MOD
DEMOD UVLO
GND
9
VSSB
不间断电源 (UPS)
Copyright © 2018, Texas Instruments Incorporated
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLUSCX6
UCC21222
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
目录
7.6 Power-up UVLO Delay to OUTPUT........................ 17
7.7 CMTI Testing........................................................... 18
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2 Functional Block Diagram ....................................... 19
8.3 Feature Description................................................. 20
8.4 Device Functional Modes........................................ 23
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application .................................................. 25
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Power Ratings........................................................... 5
6.6 Insulation Specifications............................................ 6
6.7 Safety-Related Certifications..................................... 7
6.8 Safety-Limiting Values .............................................. 7
6.9 Electrical Characteristics........................................... 8
6.10 Switching Characteristics........................................ 9
6.11 Thermal Derating Curves...................................... 10
6.12 Typical Characteristics.......................................... 11
Parameter Measurement Information ................ 15
7.1 Minimum Pulses...................................................... 15
7.2 Propagation Delay and Pulse Width Distortion....... 15
7.3 Rising and Falling Time ......................................... 15
7.4 Input and Disable Response Time.......................... 16
7.5 Programmable Dead Time...................................... 16
8
9
10 Power Supply Recommendations ..................... 36
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Layout Example .................................................... 38
12 器件和文档支持 ..................................................... 40
12.1 器件支持................................................................ 40
12.2 文档支持 ............................................................... 40
12.3 相关链接................................................................ 40
12.4 接收文档更新通知 ................................................. 40
12.5 社区资源................................................................ 40
12.6 商标....................................................................... 40
12.7 静电放电警告......................................................... 41
12.8 术语表 ................................................................... 41
13 机械、封装和可订购信息....................................... 41
7
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2018 年 4 月
*
初始发行版。
2
Copyright © 2018, Texas Instruments Incorporated
UCC21222
www.ti.com.cn
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
5 Pin Configuration and Functions
D Package
16-Pin SOIC
Top View
Pin Functions
PIN
(1)
I/O
Description
NAME
NO.
Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low
internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise
immunity. Bypass using a ≈ 1-nF low ESR/ESL capacitor close to DIS pin when connecting to a µC with
distance.
DIS
5
I
I
Programmable dead time function.
Tying DT to VCCI or leaving DT open allows the outputs to overlap. Placing a resistor (RDT) between DT
and GND adjusts dead time according to the equation: DT (in ns) = 10 × RDT (in kΩ). TI recommends
bypassing this pin with a ceramic capacitor, 2.2 nF or greater, to achieve better noise immunity. Place
this capacitor and RDT close to the DT pin.
DT
6
GND
INA
4
1
P
I
Primary-side ground reference. All signals in the primary side are referenced to this ground.
Input signal for A channel. INA input has a TTL/CMOS compatible input threshold. This pin is pulled low
internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise
immunity.
Input signal for B channel. INB input has a TTL/CMOS compatible input threshold. This pin is pulled low
internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise
immunity.
INB
NC
2
I
7
12
13
15
10
-
No internal connection.
OUTA
OUTB
O
O
Output of driver A. Connect to the gate of the A channel FET or IGBT.
Output of driver B. Connect to the gate of the B channel FET or IGBT.
Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close
to the device as possible.
VCCI
VCCI
VDDA
3
8
P
P
P
This pin is internally shorted to pin 3.
Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located
as close to the device as possible.
16
Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located
as close to the device as possible.
VDDB
11
P
VSSA
VSSB
14
9
P
P
Ground for secondary-side driver A. Ground reference for secondary side A channel.
Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1) P = power, I = input, O = output
Copyright © 2018, Texas Instruments Incorporated
3
UCC21222
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
MAX
6
UNIT
V
Input bias pin supply voltage
Driver bias supply
VCCI to GND
VDDA-VSSA, VDDB-VSSB
20
V
VVDDA+0.5,
VVDDB+0.5
OUTA to VSSA, OUTB to VSSB
–0.5
–2
V
V
Output signal voltage
Input signal voltage
OUTA to VSSA, OUTB to VSSB, Transient for 200
ns(2)
VVDDA+0.5,
VVDDB+0.5
INA, INB, DIS to GND
INA, INB Transient to GND for 200ns(2)
–0.5
–2
VVCCI+0.5
VVCCI+0.5
150
V
V
(3)
Junction temperature, TJ
–40
–65
°C
°C
Storage temperature, Tstg
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Values are verified by characterization and are not production tested.
(3) To maintain the recommended operating conditions for TJ, see the Thermal Information.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCI
VCCI Input supply voltage
Driver output bias supply
3
5.5
V
VDDA,
VDDB
9.2
18
V
TJ
Junction Temperature
Ambient Temperature
–40
–40
130
125
°C
°C
TA
4
Copyright © 2018, Texas Instruments Incorporated
UCC21222
www.ti.com.cn
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
6.4 Thermal Information
UCC21222
THERMAL METRIC(1)
D (SOIC)
16 PINS
68.5
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
30.5
22.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
17.1
ψJB
22.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Power Ratings
VALUE
1825
15
UNIT
mW
mW
mW
PD
Power dissipation
VCCI = 5.5 V, VDDA/B = 12 V, INA/B = 3.3
V, 5.4 MHz 50% duty cycle square wave 1.0-
nF load
PDI
Power dissipation by transmitter side
Power dissipation by each driver side
PDA, PDB
905
Copyright © 2018, Texas Instruments Incorporated
5
UCC21222
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
6.6 Insulation Specifications
PARAMETER
TEST CONDITIONS
Shortest pin-to-pin distance through air
VALUE
> 4
UNIT
mm
CLR
CPG
External clearance(1)
External creepage(1)
Shortest pin-to-pin distance across the package surface
> 4
mm
Distance through the
insulation
DTI
CTI
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
>17
µm
V
Comparative tracking index
Material group
> 600
I
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
I-IV
I-III
I-II
Overvoltage category per
IEC 60664-1
DIN V VDE V 0884-11:2017-01(2)
Maximum repetitive peak
VIORM
AC voltage (bipolar)
990
VPK
isolation voltage
AC voltage (sine wave); time dependent dielectric breakdown
(TDDB) test;
700
990
VRMS
VDC
VPK
Maximum working isolation
voltage
VIOWM
DC Voltage
Maximum transient isolation VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t
VIOTM
VIOSM
4242
voltage
= 1 s (100% production)
Maximum surge isolation
voltage(3)
Test method per IEC 62368-1, 1.2/50 μs waveform, VTEST =
1.3 × VIOSM = 7800 VPK (qualification)
6000
<5
VPK
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM, tm = 10s
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM, tm = 10s
<5
qpd
Apparent charge(4)
pC
Method b1; At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM; tini = 1 s;
<5
Vpd(m) = 1.5 × VIORM , tm = 1s
Barrier capacitance, input to
output(5)
CIO
RIO
VIO = 0.4 sin (2πft), f =1 MHz
0.5
pF
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Isolation resistance, input to
output
VIO = 500 V at 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS =150°C
Ω
Pollution degree
Climatic category
2
40/125/21
UL 1577
VTEST = VISO = 3000 VRMS, t = 60 sec. (qualification),
VTEST = 1.2 × VISO = 3600VRMS, t = 1 sec (100% production)
VISO
Withstand isolation voltage
3000
VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on
the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.
6
Copyright © 2018, Texas Instruments Incorporated
UCC21222
www.ti.com.cn
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
6.7 Safety-Related Certifications
VDE
CSA
UL
CQC
Plan to certify according to
DIN V VDE V 0884-11:2017- Plan to certify according to IEC 60950-
01 and DIN EN 61010-1
(VDE 0411-1):2011-07
Plan to be recognized under
UL 1577 Component
Recognition Program
Plan to certify according to GB
4943.1-2011
1, IEC 62368-1 and IEC 61010-1
6.8 Safety-Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
SIDE
MIN
TYP
MAX
UNIT
θJA = 68.5ºC/W, VVDDA/B = 12 V, TJ =
150°C, TA = 25°C
See
Safety output supply
current
DRIVER A,
DRIVER B
IS
75
mA
INPUT
DRIVER A
DRIVER B
TOTAL
15
905
θJA = 68.5ºC/W, VVCCI = 5.5 V, TJ = 150°C,
TA = 25°C
See
PS
TS
Safety supply power
Safety temperature(1)
mW
°C
905
1825
150
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be
exceeded. These limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum allowed junction temperature.
PS = IS × VI, where VI is the maximum input voltage.
Copyright © 2018, Texas Instruments Incorporated
7
UCC21222
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
6.9 Electrical Characteristics
VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1-µF capacitor from VDDA/B to VSSA/B, VVDDA = VVDDB = 12
V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C unless
otherwise noted(1)(2)
.
PARAMETER
SUPPLY CURRENTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVCCI
VCCI quiescent current
VINA = 0 V, VINB = 0 V
1.5
1.0
2.5
2.0
1.8
mA
mA
mA
VDDA and VDDB quiescent
current
IVDDA, IVDDB
IVCCI
VINA = 0 V, VINB = 0 V
VCCI operating current
(f = 500 kHz) current per channel
(f = 500 kHz) current per channel,
COUT = 100 pF,
VVDDA, VVDDB = 12 V
VDDA and VDDB operating
current
IVDDA, IVDDB
2.5
mA
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCCI_ON
VVCCI_OFF
VVCCI_HYS
UVLO Rising threshold
UVLO Falling threshold
UVLO Threshold hysteresis
2.55
2.35
2.7
2.5
0.2
2.85
2.65
V
V
V
VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVDDA_ON
VVDDB_ON
,
UVLO Rising threshold
UVLO Falling threshold
UVLO Threshold hysteresis
8
8.5
8
9
V
V
V
VVDDA_OFF
VVDDB_OFF
,
7.5
8.5
VVDDA_HYS
VVDDB_HYS
,
0.5
INA, INB AND DISABLE
VINAH, VINBH
VDISH
,
Input high threshold voltage
Input low threshold voltage
1.6
0.8
1.8
1
2
V
V
VINAL, VINBL
VDISL
,
1.25
VINA_HYS
VINB_HYS
VDIS_HYS
,
,
Input threshold hysteresis
0.8
V
OUTPUT
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
IOA+, IOB+
Peak output source current
Peak output sink current
4
6
A
A
CVDD = 10 µF, CLOAD = 0.18 µF, f
= 1 kHz, bench measurement
IOA-, IOB-
IOUT = –10 mA, ROHA, ROHB do not
represent drive pull-up
ROHA, ROHB
Output resistance at high state
performance. See tRISE in
Switching Characteristics and
Output Stage for details.
5
Ω
ROLA, ROLB
VOHA, VOHB
Output resistance at low state
Output voltage at high state
IOUT = 10 mA
0.55
Ω
VVDDA, VVDDB = 12 V, IOUT = –10
mA
11.95
V
VVDDA, VVDDB = 12 V, IOUT = 10
mA
VOLA, VOLB
Output voltage at low state
5.5
mV
V
Driver output (VOUTA, VOUTB
active pull down
)
VVDDA and VVDDB unpowered,
IOUTA, IOUTB = 200 mA
VOAPDA, VOAPDB
1.75
2.1
(1) Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless
otherwise noted).
(2) Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for
purposes of TI's product warranty.
8
Copyright © 2018, Texas Instruments Incorporated
UCC21222
www.ti.com.cn
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
Electrical Characteristics (continued)
VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1-µF capacitor from VDDA/B to VSSA/B, VVDDA = VVDDB = 12
V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, DT pin tied to VCCI, CL = 0 pF, TA = –40°C to +125°C unless
otherwise noted(1)(2)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEAD TIME AND OVERLAP PROGRAMMING
DT pin open or pull DT pin to
VCCI
Overlap determined by INA, INB
-
RDT = 10 kΩ
RDT = 20 kΩ
RDT = 50 kΩ
RDT = 10 kΩ
RDT = 20 kΩ
RDT = 50 kΩ
80
100
200
500
0
120
240
600
10
Dead time, DT
160
ns
400
-
-
-
Dead time matching, |DTAB-DTBA
|
0
20
ns
0
65
6.10 Switching Characteristics
VVCCI = 3.3 V or 5.5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to
VSSA and VSSB, load capacitance COUT = 0 pF, TA = –40°C to +125°C unless otherwise noted(1)
.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tRISE
Output rise time, see 图 28
CVDD = 10 µF, COUT = 1.8 nF,
VVDDA, VVDDB = 12 V, f = 1 kHz
5
16
ns
tFALL
tPWmin
Output fall time, see 图 28
CVDD = 10 µF, COUT = 1.8 nF ,
VVDDA, VVDDB = 12 V, f = 1 kHz
6
12
20
ns
ns
Minimum input pulse width that
passes to output,
see 图 25 and 图 26
10
Output does not change the state if
input signal less than tPWmin
tPDHL
tPDLH
tPWD
tDM
Propagation delay at falling edge,
see 图 27
INx high threshold, VINH, to 10% of
the output
28
28
40
40
5.5
5
ns
ns
ns
ns
Propagation delay at rising edge,
see 图 27
INx low threshold, VINL, to 90% of
the output
Pulse width distortion in each
channel, see 图 27
|tPDLHA – tPDHLA|, |tPDLHB– tPDHLB
|
Propagation delays matching,
|tPDLHA – tPDLHB|, |tPDHLA – tPDHLB|,
see 图 27
f = 250kHz
tVCCI+ to
OUT
VCCI Power-up Delay Time: UVLO
Rise to OUTA, OUTB,
See 图 31
40
22
INA or INB tied to VCCI
INA or INB tied to VCCI
µs
tVDD+ to
OUT
VDDA, VDDB Power-up Delay Time:
UVLO Rise to OUTA, OUTB
See 图 32
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM=1000 V;
High-level common-mode transient
immunity (See CMTI Testing)
|CMH|
|CML|
100
100
V/ns
Slew rate of GND vs. VSSA/B, INA
and INB both are tied to GND or
VCCI; VCM=1000 V;
Low-level common-mode transient
immunity (See CMTI Testing)
(1) Parameters with only a typical value are provided for reference only, and do not constitute part of TI's published device specifications for
purposes of TI's product warranty.
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6.11 Thermal Derating Curves
100
2000
1600
1200
800
400
0
IVDDA/B for VDD=12V
IVDDA/B for VDD=18V
80
60
40
20
0
0
50
100
150
200
0
50
100
150
200
Ambient Temperature (°C)
Ambient Temperature (°C)
D001
D001
Current in Each Channel with Both Channels Running
Simultaneously
图 2. Thermal Derating Curve for Limiting Power Per VDE
图 1. Thermal Derating Curve for Limiting Current Per VDE
10
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6.12 Typical Characteristics
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
2.68
2.64
2.6
1.6
1.5
1.4
1.3
1.2
VCCI = 3.3V
VCCI = 5.0V
2.56
2.52
2.48
2.44
2.4
VCCI = 3.3V, fS=50kHz
VCCI = 3.3V, fS=1.0MHz
VCCI = 5.0V, fS=50kHz
VCCI = 5.0V, fS=1.0MHz
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D001
D001
No Load
INA = INB = GND
图 3. VCCI Quiescent Current
图 4. VCCI Operating Current - IVCCI
2.6
2.58
2.56
2.54
2.52
2.5
1.6
1.4
1.2
1
VCCI = 3.3V
VCCI = 5.0V
VDD = 12V
VDD = 18V
0.8
0
100 200 300 400 500 600 700 800 900 1000
-40
-20
0
20
40
60
80
100 120 140
Frequency (kHz)
Temperature (°C)
D001
D001
No Load
INA = INB = GND
图 5. VCCI Operating Current vs. Frequency
图 6. VDD Per Channel Quiescent Current (IVDDA, IVDDB)
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
3
2.8
2.6
2.4
2.2
2
VDD = 12V, fS=50kHz
VDD = 12V, fS=1.0MHz
VDD = 15V, fS=50kHz
VDD = 15V, fS=1.0MHz
1.8
1.6
1.4
1.2
1
VDD = 12V
VDD = 15V
-40
-20
0
20
40
60
80
100 120 140
0
100 200 300 400 500 600 700 800 900 1000
Temperature (°C)
Frequency (kHz)
D001
D001
No Load
No Load
INA and INB both switching
图 7. VDD Per Channel Operating Current - IVDDA/B
图 8. Per Channel Operating Current (IVDDA/B) vs. Frequency
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Typical Characteristics (接下页)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
212
208
204
200
196
192
188
2.9
2.8
2.7
2.6
2.5
2.4
VVCCI_ON
VVCCI_OFF
-40
-20
-20
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D001
D001
图 9. VCCI UVLO Threshold Voltage
图 10. VCCI UVLO Threshold Hysteresis Voltage
540
530
520
510
500
9
8.7
8.4
8.1
7.8
7.5
VVDD_ON
VVDD_OFF
-40
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D001
D001
图 11. VDD UVLO Threshold Voltage
图 12. VDD UVLO Threshold Hysteresis Voltage
875
850
825
800
775
750
2.5
2
IN/DIS High
IN/DIS Low
1.5
1
0.5
-40
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D001
D001
图 13. INA/INB/DIS High and Low Threshold Voltage
图 14. INA/INB/DIS High and Low Threshold Hysteresis
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Typical Characteristics (接下页)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
10
37.5
OUTPUT Pull-Up
Rising Edge (tPDLH
)
OUTPUT Pull-Down
Falling Edge (tPDHL
)
35
8
32.5
30
6
27.5
25
4
2
22.5
0
20
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D001
D001
图 15. OUT Pullup and Pulldown Resistance
图 16. Propagation Delay, Rising and Falling Edge
3
2
3
2
Rising Edge
Falling Edge
1
1
0
0
-1
-2
-3
-1
-2
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D001
D001
tPDLH – tPDHL
图 17. Propagation Delay Matching, Rising and Falling Edge
图 18. Pulse Width Distortion
10
60
56
52
48
44
40
36
Rising
Falling
DIS Low to High
DIS High to Low
8
6
4
2
0
32
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D001
D001
CL = 1.8 nF
图 19. Rise Time and Fall Time
图 20. DISABLE Response Time
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Typical Characteristics (接下页)
VDDA = VDDB = 12 V, VCCI = 3.3 V or 5.0 V, DT pin tied to VCCI, TA = 25°C, CL = 0 pF unless otherwise noted.
2.5
10
VDD Open
VDD = 0V
9
2
8
1.5
1
7
6
0.5
5
0
4
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D001
D001
图 21. OUTPUT Active Pulldown Voltage
图 22. Minimum Pulse that Changes Output
700
600
500
400
300
200
100
0
6
5
RDT = 10kW
RDT = 20kW
RDT = 50kW
RDT = 10kW
RDT = 20kW
RDT = 50kW
4
3
2
1
0
-1
-2
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
D024
D025
图 23. Dead Time Temperature Drift
图 24. Dead Time Matching
14
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7 Parameter Measurement Information
7.1 Minimum Pulses
A typical 5-ns deglitch filter removes small input pulses introduced by ground bounce or switching transients. An
input pulse with duration longer than tPWmin, typically 10 ns, must be asserted on INA or INB to guarantee an
output state change at OUTA or OUTB. See 图 25 and 图 26 for detailed information of the operation of deglitch
filter.
INx
VINH
VINL
VINL
VINH
INx
tPWM < tPWmin
tPWM < tPWmin
OUTx
OUTx
图 25. Deglitch Filter – Turn ON
图 26. Deglitch Filter – Turn OFF
7.2 Propagation Delay and Pulse Width Distortion
图 27 shows calculation of pulse width distortion (tPWD) and delay matching (tDM) from the propagation delays of
channels A and B. To measure delay matching, both inputs must be in phase, and the DT pin must be shorted to
VCCI to enable output overlap.
INA/B
tPDHLA
tPDLHA
tDM
OUTA
OUTB
tPDLHB
tPDHLB
tPWDB = |tPDLHB t tPDHLB|
图 27. Delay Matching and Pulse Width Distortion
7.3 Rising and Falling Time
图 28 shows the criteria for measuring rising (tRISE) and falling (tFALL) times. For more information on how short
rising and falling times are achieved see Output Stage.
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Rising and Falling Time (接下页)
90%
tFALL
80%
tRISE
20%
10%
图 28. Rising and Falling Time Criteria
7.4 Input and Disable Response Time
图 29 shows the response time of the disable function. For more information, see Disable Pin.
INx
DIS High
Response Time
DIS
DIS Low
Response Time
OUTx
tPDLH
90%
90%
tPDHL
10%
10%
10%
图 29. Disable Pin Timing
7.5 Programmable Dead Time
Tying DT to VCCI or leaving DT open allows the outputs to overlap. Placing a resistor (RDT) between DT and
GND adjusts dead time according to the equation: DT (in ns) = 10 × RDT (in kΩ). TI recommends bypassing this
pin with a ceramic capacitor, 2.2 nF or greater, to achieve better noise immunity. Place this capacitor and RDT
close to the DT pin.. For more details on dead time, refer to Programmable Dead Time (DT) Pin.
16
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Programmable Dead Time (接下页)
INA
INB
90%
10%
OUTA
tPDHL
tPDLH
90%
10%
OUTB
tPDHL
Dead Time
Dead Time
(Determined by Input signals if
longer than DT set by RDT
(Set by RDT
)
)
图 30. Dead Time Switching Parameters
7.6 Power-up UVLO Delay to OUTPUT
Whenever the supply voltage VCCI crosses from below the falling threshold VVCCI_OFF to above the rising
threshold VVCCI_ON, and whenever the supply voltage VDDx crosses from below the falling threshold VVDDx_OFF to
above the rising threshold VVDDx_ON, there is a delay before the outputs begin responding to the inputs. For VCCI
UVLO this delay is defined as tVCCI+ to OUT, and is typically 40 µs. For VDDx UVLO this delay is defined as tVDD+ to
OUT, and is typically 22 µs. TI recommends allowing some margin before driving input signals, to ensure the
driver VCCI and VDD bias supplies are fully activated. 图 31 and 图 32 show the power-up UVLO delay timing
diagram for VCCI and VDD.
Whenever the supply voltage VCCI crosses below the falling threshold VVCCI_OFF, or VDDx crosses below the
falling threshold VVDDx_OFF, the outputs stop responding to the inputs and are held low within 1 µs. This
asymmetric delay is designed to ensure safe operation during VCCI or VDDx brownouts.
VCCI,
INx
VCCI,
INx
VVCCI_ON
VVCCI_OFF
VDDx
VDDx
tVCCI+ to OUT
tVDD+ to OUT
VVDD_ON
VVDD_OFF
OUTx
OUTx
图 31. VCCI Power-up UVLO Delay
图 32. VDDA/B Power-up UVLO Delay
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7.7 CMTI Testing
图 33 is a simplified diagram of the CMTI testing configuration.
VCC
VDD
VDDA
OUTA
VSSA
INA
1
16
15
14
OUTA
INB
2
VCC
VCCI
3
GND
4
Functional
Isolation
DIS
5
VDDB
11
10
9
OUTB
DT
6
OUTB
VSSB
GND
VCCI
8
VSS
Common Mode Surge
Generator
Copyright © 2018, Texas Instruments Incorporated
图 33. Simplified CMTI Testing Setup
18
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8 Detailed Description
8.1 Overview
In order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are
often placed between the output of control devices and the gates of power transistors. There are several
instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors.
This is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-V
logic signal capable of only delivering a few mA.
The UCC21222 is a flexible dual gate driver which can be configured to fit a variety of power supply and motor
drive topologies, as well as drive several types of transistors. The UCC21222 has many features that allow it to
integrate well with control circuitry and protect the gates it drives such as: resistor-programmable dead time (DT)
control, disable pin, and under voltage lock out (UVLO) for both input and output supplies. The UCC21222 also
holds its outputs low when the inputs are left open or when the input pulse duration is too short. The driver inputs
are CMOS and TTL compatible for interfacing with digital and analog power controllers alike. Each channel is
controlled by its respective input pins (INA and INB), allowing full and independent control of each of the outputs.
8.2 Functional Block Diagram
INA
1
16 VDDA
200 kW
VCCI
Driver
MOD
DEMOD
Deglitch
Filter
15 OUTA
14 VSSA
UVLO
VCCI 3,8
UVLO
GND
DT
4
6
13 NC
12 NC
Dead Time
Control
Functional Isolation
DIS
5
11 VDDB
Driver
50 kW
MOD
DEMOD
Deglitch
Filter
10 OUTB
UVLO
INB
NC
2
7
9
VSSB
200 kW
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8.3 Feature Description
8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
The UCC21222 has an internal under voltage lock out (UVLO) protection feature on each supply voltage
between the VDD and VSS pins for both outputs. When the VDD bias voltage is lower than VVDD_ON at device
start-up or lower than VVDD_OFF after start-up, the VDD UVLO feature holds the channel output low, regardless of
the status of the input pins.
When the output stages of the driver are in an unbiased or UVLO condition, the driver outputs are held low by an
active clamp circuit that limits the voltage rise on the driver outputs (illustrated in 图 34). In this condition, the
upper PMOS is resistively held off by RHi-Z while the lower NMOS gate is tied to the driver output through RCLAMP
.
In this configuration, the output is effectively clamped to the threshold voltage of the lower NMOS device,
typically around 1.5V, regardless of whether bias power is available.
VDD
RHI_Z
Output
Control
OUT
RCLAMP
RCLAMP is activated
during UVLO
VSS
图 34. Simplified Representation of Active Pull Down Feature
The VDD UVLO protection has a hysteresis feature (VVDD_HYS). This hysteresis prevents chatter when there is
ground noise from the power supply. This also allows the device to accept small drops in bias voltage, which
commonly occurs when the device starts switching and operating current consumption increases suddenly.
The inputs of the UCC21222 also have an internal under voltage lock out (UVLO) protection feature. The inputs
cannot affect the outputs unless the supply voltage VCCI exceeds VVCCI_ON on start-up. The outputs are held low
and cannot respond to inputs when the supply voltage VCCI drops below VVCCI_OFF after start-up. Like the UVLO
for VDD, there is hystersis (VVCCI_HYS) to ensure stable operation.
表 1. VCCI UVLO Feature Logic
CONDITION
INPUTS
OUTPUTS
INA
H
L
INB
L
OUTA
OUTB
VCCI-GND < VVCCI_ON during device start up
VCCI-GND < VVCCI_ON during device start up
VCCI-GND < VVCCI_ON during device start up
VCCI-GND < VVCCI_ON during device start up
VCCI-GND < VVCCI_OFF after device start up
VCCI-GND < VVCCI_OFF after device start up
VCCI-GND < VVCCI_OFF after device start up
VCCI-GND < VVCCI_OFF after device start up
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
L
H
H
L
H
L
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表 2. VDD UVLO Feature Logic
CONDITION
INPUTS
OUTPUTS
INA
H
L
INB
OUTA
OUTB
VDD-VSS < VVDD_ON during device start up
VDD-VSS < VVDD_ON during device start up
VDD-VSS < VVDD_ON during device start up
VDD-VSS < VVDD_ON during device start up
VDD-VSS < VVDD_OFF after device start up
VDD-VSS < VVDD_OFF after device start up
VDD-VSS < VVDD_OFF after device start up
VDD-VSS < VVDD_OFF after device start up
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
L
H
L
8.3.2 Input and Output Logic Table
Assume VCCI, VDDA, VDDB are powered up (see VDD, VCCI, and Under Voltage Lock Out (UVLO) for more information on
UVLO operation modes). 表 3 shows the operation with INA, INB and DIS and the corresponding output state.
表 3. INPUT/OUTPUT Logic Table(1)
INPUTS
OUTPUTS
DIS
NOTE
INA
L
INB
L
OUTA
OUTB
L or Left Open
L or Left Open
L or Left Open
L or Left Open
L or Left Open
L
L
L
H
L
If the dead time function is used, output transitions occur after the dead
time expires. See Programmable Dead Time (DT) Pin.
L
H
H
L
H
L
H
H
L
DT is programmed with RDT
.
H
H
H
L
H
L
DT pin is left open or pulled to VCCI.
Left Open Left Open L or Left Open
X
X
H
L
L
(1) "X" means L, H or left open. For improved noise immunity, TI recommends connecting INA, INB, and DIS to GND, and DT to VCCI,
when these pins are not used.
8.3.3 Input Stage
The input pins (INA, INB, and DIS) of the UCC21222 are based on a TTL and CMOS compatible input-threshold
logic that is totally isolated from the VDD supply voltage of the output channels. The input pins are easy to drive
with logic-level control signals (such as those from 3.3-V microcontrollers), since the UCC21222 has a typical
high threshold (VINAH) of 1.8 V and a typical low threshold of 1 V, which vary little with temperature (see 图 11
and 图 13). A wide hysterisis (VINA_HYS) of 0.8 V makes for good noise immunity and stable operation. If any of
the inputs are ever left open, internal pull-down resistors force the pin low. These resistors are typically 200 kΩ
for INA/B and 50 kΩ for DIS (see Functional Block Diagram). TI recommends grounding any unused inputs.
The amplitude of any signal applied to the inputs must never be at a voltage higher than VCCI.
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8.3.4 Output Stage
The UCC21222 output stage features a pull-up structure which delivers the highest peak-source current when it
is most needed: during the Miller plateau region of the power-switch turn on transition (when the power switch
drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-channel MOSFET
and an additional pull-up N-channel MOSFET in parallel. The function of the N-channel MOSFET is to provide a
boost in the peak-sourcing current, enabling fast turn on. This is accomplished by briefly turning on the N-
channel MOSFET during a narrow instant when the output is changing states from low to high. The on-resistance
of this N-channel MOSFET (RNMOS) is approximately 1.47 Ω when activated.
The ROH parameter is a DC measurement and it is representative of the on-resistance of the P-channel device
only. This is because the pull-up N-channel device is held in the off state in DC condition and is turned on only
for a brief instant when the output is changing states from low to high. Therefore the effective resistance of the
UCC21222 pull-up stage during this brief turn-on phase is much lower than what is represented by the ROH
parameter.
The pull-down structure of the UCC21222 is composed of an N-channel MOSFET. The ROL parameter, which is
also a DC measurement, is representative of the impedance of the pull-down state in the device. Both outputs of
the UCC21222 are capable of delivering 4-A peak source and 6-A peak sink current pulses. The output voltage
swings between VDD and VSS for rail-to-rail operation.
VDD
ROH
Shoot-
RNMOS
Input
Signal
Through
Prevention
Circuitry
OUT
VSS
ROL
Pull Up
图 35. Output Stage
22
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8.3.5 Diode Structure in the UCC21222
图 36 illustrates the multiple diodes involved in the ESD protection components. This provides a pictorial
representation of the absolute maximum rating for the device.
VCCI
3,8
VDDA
16
20 V
15 OUTA
14 VSSA
6 V 6 V
INA
INB
DIS
DT
1
2
5
6
11 VDDB
10 OUTB
20 V
4
9
GND
VSSB
图 36. ESD Structure
8.4 Device Functional Modes
8.4.1 Disable Pin
When the DIS pin is set high, both outputs are shut down simultaneously. When the DIS pin is set low or left
open, the UCC21222 operates normally. The DIS circuit logic structure is nearly identical compared to INA or
INB, and the propagation delay is similar (see 图 20). The DIS pin is only functional (and necessary) when VCCI
stays above the UVLO threshold. It is recommended to tie this pin to GND if the DIS pin is not used to achieve
better noise immunity.
8.4.2 Programmable Dead Time (DT) Pin
The UCC21222 allows the user to adjust dead time (DT) in the following ways:
8.4.2.1 DT Pin Tied to VCCI or DT Pin Left Open
Outputs completely match inputs, so no minimum dead time is asserted. This allows the outputs to overlap. TI
recommends connecting this pin directly to VCCI if it is not used to achieve better noise immunity.
8.4.2.2 Connecting a Programming Resistor between DT and GND Pins
Program tDT by placing a resistor, RDT, between the DT pin and GND. The appropriate RDT value can be
determined from:
tDT ö 10ìRDT
where
•
•
tDT is the programmed dead time, in nanoseconds.
RDT is the value of resistance between DT pin and GND, in kilo-ohms.
(1)
23
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UCC21222
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Device Functional Modes (接下页)
The steady state voltage at the DT pin is about 0.8 V. RDT programs a small current at this pin, which sets the
dead time. As the value of RDT increases, the current sourced by the DT pin decreases. The DT pin current will
be less than 10 µA when RDT = 100 kΩ. For larger values of RDT, TI recommends placing RDT and a ceramic
capacitor, 2.2 nF or greater, as close to the DT pin as possible to achieve greater noise immunity and better
dead time matching between both channels.
The falling edge of an input signal initiates the programmed dead time for the other signal. The programmed
dead time is the minimum enforced duration in which both outputs are held low by the driver. The outputs may
also be held low for a duration greater than the programmed dead time, if the INA and INB signals include a
dead time duration greater than the programmed minimum. If both inputs are high simultaneously, both outputs
will immediately be set low. This feature is used to prevent shoot-through in half-bridge applications, and it does
not affect the programmed dead time setting for normal operation. Various driver dead time logic operating
conditions are illustrated and explained in 图 37.
INA
INB
DT
OUTA
OUTB
A
B
C
D
E
F
图 37. Input and Output Logic Relationship with Input Signals
Condition A: INB goes low, INA goes high. INB sets OUTB low immediately and assigns the programmed dead
time to OUTA. OUTA is allowed to go high after the programmed dead time.
Condition B: INB goes high, INA goes low. Now INA sets OUTA low immediately and assigns the programmed
dead time to OUTB. OUTB is allowed to go high after the programmed dead time.
Condition C: INB goes low, INA is still low. INB sets OUTB low immediately and assigns the programmed dead
time for OUTA. In this case, the input signal dead time is longer than the programmed dead time. When INA
goes high after the duration of the input signal dead time, it immediately sets OUTA high.
Condition D: INA goes low, INB is still low. INA sets OUTA low immediately and assigns the programmed dead
time to OUTB. In this case, the input signal dead time is longer than the programmed dead time. When INB goes
high after the duration of the input signal dead time, it immediately sets OUTB high.
Condition E: INA goes high, while INB and OUTB are still high. To avoid overshoot, OUTB is immediately pulled
low. After some time OUTB goes low and assigns the programmed dead time to OUTA. OUTB is already low.
After the programmed dead time, OUTA is allowed to go high.
Condition F: INB goes high, while INA and OUTA are still high. To avoid overshoot, OUTA is immediately pulled
low. After some time OUTA goes low and assigns the programmed dead time to OUTB. OUTA is already low.
After the programmed dead time, OUTB is allowed to go high.
24
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UCC21222
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The UCC21222 effectively combines both isolation and buffer-drive functions. The flexible, universal capability of
the UCC21222 (with up to 5.5-V VCCI and 18-V VDDA/VDDB) allows the device to be used as a low-side, high-
side, high-side/low-side or half-bridge driver for MOSFETs, IGBTs or GaN transistor. With integrated
components, advanced protection features (UVLO, dead time, and disable) and optimized switching
performance, the UCC21222 enables designers to build smaller, more robust designs for enterprise, telecom,
automotive, and industrial applications with a faster time to market.
9.2 Typical Application
The circuit in 图 38 shows a reference design with the UCC21222 driving a typical half-bridge configuration which
could be used in several popular power converter topologies such as synchronous buck, synchronous boost,
half-bridge/full bridge isolated topologies, and 3-phase motor drive applications.
VCC
VDD
RBOOT
HV DC-Link
CIN
VCC
VDDA
INA
INB
ROFF
RON
16
15
14
PWM-A
1
2
3
4
5
6
8
RIN
OUTA
VSSA
PWM-B
RGS
CIN
CBOOT
VCCI
GND
mC
CVCC
SW
Functional
Isolation
VDD
DIS
DT
DIS
VDDB
I/O
ROFF
RON
11
10
9
RDIS
CDIS
OUTB
VSSB
RDT
CDT
RGS
VCCI
CBOOT
Copyright © 2018, Texas Instruments Incorporated
图 38. Typical Application Schematic
版权 © 2018, Texas Instruments Incorporated
25
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www.ti.com.cn
Typical Application (接下页)
9.2.1 Design Requirements
表 4 lists reference design parameters for the example application: UCC21222 driving 650-V MOSFETs in a high
side-low side configuration.
表 4. UCC21222 Design Requirements
PARAMETER
Power transistor
VCC
VALUE
UNITS
650-V, 150-mΩ RDS_ON with 12-V VGS
-
V
5.0
12
VDD
V
Input signal amplitude
Switching frequency (fs)
Dead Time
3.3
100
200
400
V
kHz
ns
V
DC link voltage
9.2.2 Detailed Design Procedure
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the UCC21222 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Designing INA/INB Input Filter
It is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay)
the signal at the output. However, a small input RIN-CIN filter can be used to filter out the ringing introduced by
non-ideal layout or long PCB traces.
Such a filter should use an RIN in the range of 0 Ω to 100 Ω and a CIN between 10 pF and 100 pF. In the
example, an RIN = 51 Ω and a CIN = 33 pF are selected, with a corner frequency of approximately 100 MHz.
When selecting these components, it is important to pay attention to the trade-off between good noise immunity
and propagation delay.
9.2.2.3 Select Dead Time Resistor and Capacitor
From 公式 1, a 20-kΩ resistor is selected to set the dead time to 200 ns. A 2.2-nF capacitor is placed in parallel
close to the DT pin to improve noise immunity.
9.2.2.4 Select External Bootstrap Diode and its Series Resistor
The bootstrap capacitor is charged by VDD through an external bootstrap diode every cycle when the low side
transistor turns on. Charging the capacitor involves high-peak currents, and therefore transient power dissipation
in the bootstrap diode may be significant. Conduction loss also depends on the diode’s forward voltage drop.
Both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver
circuit.
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UCC21222
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When selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes
or SiC Schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the loss
introduced by reverse recovery and related grounding noise bouncing. In the example, the DC-link voltage is 400
VDC. The voltage rating of the bootstrap diode should be higher than the DC-link voltage with a good margin.
Therefore, a 600-V ultrafast diode, MURA160T3G, is chosen in this example.
A bootstrap resistor, RBOOT, is used to reduce the inrush current in DBOOT and limit the ramp up slew rate of
voltage of VDDA-VSSA during each switching cycle, especially when the VSSA(SW) pin has an excessive
negative transient voltage. The recommended value for RBOOT is between 1 Ω and 20 Ω depending on the diode
used. In the example, a current limiting resistor of 2.2 Ω is selected to limit the inrush current of bootstrap diode.
The estimated worst case peak current through DBoot is,
VDD - VBDF
12V -1.5V
2.7W
IDBoot pk
=
=
ö 4A
(
)
RBoot
where
•
VBDF is the estimated bootstrap diode forward voltage drop around 4 A.
(2)
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9.2.2.5 Gate Driver Output Resistor
The external gate driver resistors, RON/ROFF, are used to:
1. Limit ringing caused by parasitic inductances/capacitances.
2. Limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery.
3. Fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss.
4. Reduce electromagnetic interference (EMI).
As mentioned in Output Stage, the UCC21222 has a pull-up structure with a P-channel MOSFET and an
additional pull-up N-channel MOSFET in parallel. The combined peak source current is 4 A. Therefore, the peak
source current can be predicted with:
≈
’
VDD - VBDF
RNMOS ||ROH + RON + RGFET _Int
IOA+ = min 4A,
∆
÷
÷
◊
∆
«
(3)
≈
’
VDD
IOB+ = min 4A,
∆
÷
÷
◊
∆
«
RNMOS ||ROH + RON + RGFET _Int
where
•
•
•
RON: External turn-on resistance.
RGFET_INT: Power transistor internal gate resistance, found in the power transistor datasheet.
IO+ = Peak source current – The minimum value between 4 A, the gate driver peak source current, and the
calculated value based on the gate drive loop resistance.
(4)
In this example:
VDD - VBDF
RNMOS ||ROH + RON + RGFET _Int 1.47W || 5W + 2.2W +1.5W
12V - 0.8V
IOA+
=
=
ö 2.3A
ö 2.5A
(5)
(6)
VDD
RNMOS ||ROH + RON + RGFET _Int 1.47W || 5W + 2.2W +1.5W
12V
IOB+
=
=
Therefore, the high-side and low-side peak source current is 2.3 A and 2.5 A respectively. Similarly, the peak
sink current can be calculated with:
≈
’
VDD - VBDF - VGDF
ROL +ROFF ||RON +RGFET _Int
IOA- = min 6A,
∆
÷
÷
◊
∆
«
(7)
≈
’
VDD - VGDF
ROL + ROFF ||RON + RGFET _Int
IOB- = min 6A,
∆
÷
÷
◊
∆
«
where
•
•
ROFF: External turn-off resistance, ROFF=0 in this example;
VGDF: The anti-parallel diode forward voltage drop which is in series with ROFF. The diode in this example is an
MSS1P4.
•
IO-: Peak sink current – the minimum value between 6 A, the gate driver peak sink current, and the calculated
value based on the gate drive loop resistance.
(8)
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UCC21222
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In this example,
VDD - VBDF - VGDF
ROL +ROFF ||RON +RGFET _Int
12V - 0.8V -0.85V
0.55W + 0W +1.5W
IOA-
=
=
ö 5.0A
(9)
VDD - VGDF
12V - 0.85V
IOB-
=
=
ö 5.4A
ROL + ROFF ||RON + RGFET _Int 0.55W + 0W +1.5W
(10)
Therefore, the high-side and low-side peak sink current is 5.0 A and 5.4A respectively.
Importantly, the estimated peak current is also influenced by PCB layout and load capacitance. Parasitic
inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and
undershoot. Therefore, it is strongly recommended that the gate driver loop should be minimized. On the other
hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (CISS) of the power
transistor is very small (typically less than 1 nF), because the rising and falling time is too small and close to the
parasitic ringing period.
9.2.2.6 Estimating Gate Driver Power Loss
The total loss, PG, in the gate driver subsystem includes the power losses of the UCC21222 (PGD) and the power
losses in the peripheral circuitry, such as the external gate drive resistor. Bootstrap diode loss is not included in
PG and not discussed in this section.
PGD is the key power loss which determines the thermal safety-related limits of the UCC21222, and it can be
estimated by calculating losses from several components.
The first component is the static power loss, PGDQ, which includes quiescent power loss on the driver as well as
driver self-power consumption when operating with a certain switching frequency. PGDQ is measured on the
bench with no load connected to OUTA and OUTB at a given VCCI, VDDA/VDDB, switching frequency and
ambient temperature. 图 5 and 图 8 show the operating current consumption vs. operating frequency with no
load. In this example, VVCCI = 5 V and VVDD = 12 V. The current on each power supply, with INA/INB switching
from 0 V to 3.3 V at 100 kHz is measured to be IVCCI ≈ 2.5 mA, and IVDDA = IVDDB ≈ 1.5 mA. Therefore, the PGDQ
can be calculated with
PGDQ = VVCCI ìIVCCI + VVDDA ìIDDA + VVDDB ìIDDB = 50mW
(11)
The second component is switching operation loss, PGDO, with a given load capacitance which the driver charges
and discharges the load during each switching cycle. Total dynamic loss due to load switching, PGSW, can be
estimated with
PGSW = 2ì VDD ìQG ì fSW
where
•
QG is the gate charge of the power transistor.
(12)
If a split rail is used to turn on and turn off, then VDD is going to be equal to difference between the positive rail
to the negative rail.
So, for this example application:
PGSW = 2ì12V ì100nCì100kHz = 240mW
(13)
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www.ti.com.cn
QG represents the total gate charge of the power transistor switching 480 V at 14 A provided by the datasheet,
and is subject to change with different testing conditions. The UCC21222 gate driver loss on the output stage,
PGDO, is part of PGSW. PGDO will be equal to PGSW if the external gate driver resistances are zero, and all the gate
driver loss is dissipated inside the UCC21222. If there are external turn-on and turn-off resistances, the total loss
will be distributed between the gate driver pull-up/down resistances and external gate resistances. Importantly,
the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 A/6 A,
however, it will be non-linear if the source/sink current is saturated. Therefore, PGDO is different in these two
scenarios.
Case 1 - Linear Pull-Up/Down Resistor:
≈
’
PGSW
2
ROH ||RNMOS
ROL
PGDO
=
ì
+
∆
∆
«
÷
÷
◊
ROH ||RNMOS +RON +RGFET _Int ROL +ROFF ||RON + RGFET _Int
(14)
In this design example, all the predicted source/sink currents are less than 4 A/6 A, therefore, the the UCC21222
gate driver loss can be estimated with:
≈
∆
«
’
÷
◊
240mW
2
5W ||1.47W
0.55W
PGDO
=
ì
+
ö 60mW
5W ||1.47W + 2.2W +1.5W 0.55W + 0W +1.5W
(15)
Case 2 - Nonlinear Pull-Up/Down Resistor:
TR _ Sys
TF _ Sys
»
ÿ
Ÿ
…
PGDO = 2ì fSW ì 4A ì
VDD - VOUTA/B
t
( )
dt + 6A ì
VOUTA/B t dt
( )
(
)
—
—
…
Ÿ
0
0
…
Ÿ
⁄
where
•
VOUTA/B(t) is the gate driver OUTA and OUTB pin voltage during the turn on and off transient, and it can be
simplified that a constant current source (4 A at turn-on and 6 A at turn-off) is charging/discharging a load
capacitor. Then, the VOUTA/B(t) waveform will be linear and the TR_Sys and TF_Sys can be easily predicted.
(16)
For some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the PGDO
will be a combination of Case 1 and Case 2, and the equations can be easily identified for the pull-up and pull-
down based on the above discussion. Therefore, total gate driver loss dissipated in the gate driver UCC21222
PGD, is:
PGD = PGDQ + PGDO
(17)
which is equal to 127 mW in the design example.
9.2.2.7 Estimating Junction Temperature
The junction temperature of the UCC21222 can be estimated with:
TJ = TC + YJT ìPGD
where
•
•
•
TJ is the junction temperature.
TC is the UCC21222 case-top temperature measured with a thermocouple or some other instrument.
ψJT is the junction-to-top characterization parameter from the Thermal Information table.
(18)
Using the junction-to-top characterization parameter (ΨJT) instead of the junction-to-case thermal resistance
(RΘJC) can greatly improve the accuracy of the junction temperature estimation. The majority of the thermal
energy of most ICs is released into the PCB through the package leads, whereas only a small percentage of the
total energy is released through the top of the case (where thermocouple measurements are usually conducted).
RΘJC can only be used effectively when most of the thermal energy is released through the case, such as with
metal packages or when a heatsink is applied to an IC package. In all other cases, use of RΘJC will inaccurately
30
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UCC21222
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ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
estimate the true junction temperature. ΨJT is experimentally derived by assuming that the amount of energy
leaving through the top of the IC will be similar in both the testing environment and the application environment.
As long as the recommended layout guidelines are observed, junction temperature estimates can be made
accurately to within a few degrees Celsius. For more information, see the Layout Guidelines and Semiconductor
and IC Package Thermal Metrics application report.
9.2.2.8 Selecting VCCI, VDDA/B Capacitor
Bypass capacitors for VCCI, VDDA, and VDDB are essential for achieving reliable performance. It is
recommended that one choose low ESR and low ESL surface-mount multi-layer ceramic capacitors (MLCC) with
sufficient voltage ratings, temperature coefficients and capacitance tolerances. Importantly, DC bias on an MLCC
will impact the actual capacitance value. For example, a 25-V, 1-µF X7R capacitor is measured to be only 500
nF when a DC bias of 15 VDC is applied.
9.2.2.8.1 Selecting a VCCI Capacitor
A bypass capacitor connected to VCCI supports the transient current needed for the primary logic and the total
current consumption, which is only a few mA. Therefore, a 25-V MLCC with over 100 nF is recommended for this
application. If the bias power supply output is a relatively long distance from the VCCI pin, a tantalum or
electrolytic capacitor, with a value over 1 µF, should be placed in parallel with the MLCC.
9.2.2.8.2 Selecting a VDDA (Bootstrap) Capacitor
A VDDA capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for
gate drive current transients up to 6 A, and needs to maintain a stable gate drive voltage for the power transistor.
The total charge needed per switching cycle can be estimated with
IVDD @100kHz No Load
(
)
= 100nC +
1.5mA
QTotal = QG +
= 115nC
fSW
100kHz
where
•
•
•
QG: Gate charge of the power transistor.
IVDD: The channel self-current consumption with no load at 100kHz.
(19)
(20)
Therefore, the absolute minimum CBoot requirement is:
QTotal
115nC
0.5V
CBoot
=
=
= 230nF
DVVDDA
where
•
ΔVVDDA is the voltage ripple at VDDA, which is 0.5 V in this example.
In practice, the value of CBoot is greater than the calculated value. This allows for the capacitance shift caused by
the DC bias voltage and for situations where the power stage would otherwise skip pulses due to load transients.
Therefore, it is recommended to include a safety-related margin in the CBoot value and place it as close to the
VDD and VSS pins as possible. A 50-V 1-µF capacitor is chosen in this example.
CBoot=1ꢀF
(21)
To further lower the AC impedance for a wide frequency range, it is recommended to have bypass capacitor with
a low capacitance value, in this example a 100 nF, in parallel with CBoot to optimize the transient performance.
注
Too large CBOOT is not good. CBOOT may not be charged within the first few cycles and
VBOOT could stay below UVLO. As a result, the high-side FET does not follow input signal
command. Also during initial CBOOT charging cycles, the bootstrap diode has highest
reverse recovery current and losses.
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9.2.2.8.3 Select a VDDB Capacitor
Chanel B has the same current requirements as Channel A, Therefore, a VDDB capacitor (Shown as CVDD in 图
38) is needed. In this example with a bootstrap configuration, the VDDB capacitor will also supply current for
VDDA through the bootstrap diode. A 50-V, 10-µF MLCC and a 50-V, 220-nF MLCC are chosen for CVDD. If the
bias power supply output is a relatively long distance from the VDDB pin, a tantalum or electrolytic capacitor with
a value over 10 µF, should be used in parallel with CVDD
.
9.2.2.9 Application Circuits with Output Stage Negative Bias
When parasitic inductances are introduced by non-ideal PCB layout and long package leads (e.g. TO-220 and
TO-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during
high di/dt and dv/dt switching. If the ringing is over the threshold voltage, there is the risk of unintended turn-on
and even shoot-through. Applying a negative bias on the gate drive is a popular way to keep such ringing below
the threshold. Below are a few examples of implementing negative gate drive bias.
图 39 shows the first example with negative bias turn-off on the channel-A driver using a Zener diode on the
isolated power supply output stage. The negative bias is set by the Zener diode voltage. If the isolated power
supply, VA, is equal to 17 V, the turn-off voltage will be –5.1 V and turn-on voltage will be 17 V – 5.1 V ≈ 12 V.
The channel-B driver circuit is the same as channel-A, therefore, this configuration needs two power supplies for
a half-bridge configuration, and there will be steady state power consumption from RZ.
HV DC-Link
VDDA
ROFF
16
1
CA1
+
VA
œ
CIN
RZ
RON
OUTA
VSSA
15
14
2
3
4
5
6
8
CA2
VZ
SW
Functional
Isolation
VDDB
11
10
9
OUTB
VSSB
Copyright © 2018, Texas Instruments Incorporated
图 39. Negative Bias with Zener Diode on Iso-Bias Power Supply Output
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ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
图 40 shows another example which uses two supplies (or single-input-double-output power supply). Power
supply VA+ determines the positive drive output voltage and VA– determines the negative turn-off voltage. The
configuration for channel B is the same as channel A. This solution requires more power supplies than the first
example, however, it provides more flexibility when setting the positive and negative rail voltages.
HV DC-Link
VDDA
OUTA
ROFF
RON
16
15
1
2
3
4
5
6
8
CA1
+
VA+
œ
CIN
CA2
+
VA-
œ
VSSA
SW
14
Functional
Isolation
VDDB
11
10
9
OUTB
VSSB
Copyright © 2018, Texas Instruments Incorporated
图 40. Negative Bias with Two Iso-Bias Power Supplies
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UCC21222
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The last example, shown in 图 41, is a single power supply configuration and generates negative bias through a
Zener diode in the gate drive loop. The benefit of this solution is that it only uses one power supply and the
bootstrap power supply can be used for the high side drive. This design requires the least cost and design effort
among the three solutions. However, this solution has limitations:
1. The negative gate drive bias is not only determined by the Zener diode, but also by the duty cycle, which
means the negative bias voltage will change when the duty cycle changes. Therefore, converters with a fixed
duty cycle (~50%) such as variable frequency resonant convertors or phase shift convertors which favor this
solution.
2. The high side VDDA-VSSA must maintain enough voltage to stay in the recommended power supply range,
which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel)
diode for a certain period during each switching cycle to refresh the bootstrap capacitor. Therefore, a 100%
duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in
the other two example circuits.
VDD
RBOOT
HV DC-Link
VDDA
CZ
VZ
ROFF
RON
16
15
14
1
2
3
4
5
6
8
OUTA
VSSA
CIN
CBOOT
RGS
SW
Functional
Isolation
VDD
VDDB
CZ
VZ
ROFF
RON
11
10
9
OUTB
VSSB
CVDD
RGS
VSS
Copyright © 2018, Texas Instruments Incorporated
图 41. Negative Bias with Single Power Supply and Zener Diode in Gate Drive Path
34
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UCC21222
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ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
9.2.3 Application Curves
图 42 and 图 43 shows the bench test waveforms for the design example shown in 图 38 under these conditions:
VCC = 5.0 V, VDD = 12 V, fSW = 100 kHz, VDC-Link = 400 V.
Channel 1 (Blue): Gate-source signal on the high side power transistor.
Channel 2 (Cyan): Gate-source signal on the low side power transistor.
Channel 3 (Pink): INA pin signal.
Channel 4 (Green): INB pin signal.
In 图 42, INA and INB are sent complimentary 3.3-V, 20%/80% duty-cycle signals. The gate drive signals on the
power transistor have a 200-ns dead time with 400V high voltage on the DC-Link, shown in the measurement
section of 图 42. Note that with high voltage present, lower bandwidth differential probes are required, which
limits the achievable accuracy of the measurement.
图 43 shows a zoomed-in version of the waveform of 图 42, with measurements for propagation delay and dead
time. Importantly, the output waveform is measured between the power transistors’ gate and source pins, and is
not measured directly from the driver OUTA and OUTB pins.
图 42. Bench Test Waveform for INA/B and OUTA/B
图 43. Zoomed-In bench-test waveform
版权 © 2018, Texas Instruments Incorporated
35
UCC21222
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
10 Power Supply Recommendations
The recommended input supply voltage (VCCI) for the UCC21222 is between 3 V and 5.5 V. The output bias
supply voltage (VDDA/VDDB) ranges from 9.2 V to 18 V. The lower end of this bias supply range is governed by
the internal under voltage lockout (UVLO) protection feature of each device. VDD and VCCI must not fall below
their respective UVLO thresholds during normal operation. (For more information on UVLO see VDD, VCCI, and
Under Voltage Lock Out (UVLO)). The upper end of the VDDA/VDDB range depends on the maximum gate
voltage of the power device being driven by the UCC21222. The recommended maximum VDDA/VDDB is 18 V.
A local bypass capacitor should be placed between the VDD and VSS pins, to supply current when the output
goes high into a capacitive load. This capacitor should be positioned as close to the device as possible to
minimize parasitic impedance. A low ESR, ceramic surface mount capacitor is recommended. If the bypass
capacitor impedance is too large, resistive and inductive parasitics could cause the supply voltage seen at the IC
pins to dip below the UVLO threshold unexpectedly. To filter high frequency noise between VDD and VSS, it can
be helpful to place a second capacitor with lower impedance at higher frequency. As an example, the primary
bypass capacitor could be 1 µF, with a secondary high frequency bypass capacitor of 100 pF.
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of
current drawn by the logic circuitry within the input side of the UCC21222, this bypass capacitor has a minimum
recommended value of 100 nF.
36
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UCC21222
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ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
11 Layout
11.1 Layout Guidelines
Consider these PCB layout guidelines for in order to achieve optimum performance for the UCC21222.
11.1.1 Component Placement Considerations
•
Low-ESR and low-ESL capacitors must be connected close to the device between the VCCI and GND pins
and between the VDD and VSS pins to support high peak currents when turning on the external power
transistor.
•
To avoid large negative transients on the switch node VSSA (HS) pin in bridge configurations, the parasitic
inductances between the source of the top transistor and the source of the bottom transistor must be
minimized.
•
•
To improve noise immunity when driving the DIS pin from a distant microcontroller, TI recommends adding a
small bypass capacitor, ≥ 1000 pF, between the DIS pin and GND.
If the dead time feature is used, TI recommends placing the programming resistor RDT and capacitor close to
the DT pin of the UCC21222 to prevent noise from unintentionally coupling to the internal dead time circuit.
The capacitor should be ≥ 2.2 nF.
11.1.2 Grounding Considerations
•
It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal
physical area. This will decrease the loop inductance and minimize noise on the gate terminals of the
transistors. The gate driver must be placed as close as possible to the transistors.
•
Pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local VSSB-
referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. The bootstrap capacitor is
recharged on a cycle-by-cycle basis through the bootstrap diode by the VDD bypass capacitor. This
recharging occurs in a short time interval and involves a high peak current. Minimizing this loop length and
area on the circuit board is important for ensuring reliable operation.
11.1.3 High-Voltage Considerations
•
To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or
copper below the driver device. A PCB cutout is recommended in order to prevent contamination that may
compromise the isolation performance.
•
For half-bridge or high-side/low-side configurations, maximize the clearance distance of the PCB layout
between the high and low-side PCB traces.
11.1.4 Thermal Considerations
•
A large amount of power may be dissipated by the UCC21222 if the driving voltage is high, the load is heavy,
or the switching frequency is high (refer to Estimating Gate Driver Power Loss for more details). Proper PCB
layout can help dissipate heat from the device to the PCB and minimize junction to board thermal impedance
(θJB).
•
•
Increasing the PCB copper connecting to VDDA, VDDB, VSSA and VSSB pins is recommended, with priority
on maximizing the connection to VSSA and VSSB (see 图 45 and 图 46). However, high voltage PCB
considerations mentioned above must be maintained.
If there are multiple layers in the system, it is also recommended to connect the VDDA, VDDB, VSSA and
VSSB pins to internal ground or power planes through multiple vias of adequate size. Ensure that no traces
or copper from different high-voltage planes overlap.
版权 © 2018, Texas Instruments Incorporated
37
UCC21222
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
11.2 Layout Example
图 44 shows a 2-layer PCB layout example with the signals and key components labeled.
图 44. Layout Example
图 45 and 图 46 shows top and bottom layer traces and copper.
注
There are no PCB traces or copper between the primary and secondary side, which
ensures isolation performance.
PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the
creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node
VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.
图 45. Top Layer Traces and Copper
图 46. Bottom Layer Traces and Copper (Flipped)
38
版权 © 2018, Texas Instruments Incorporated
UCC21222
www.ti.com.cn
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
Layout Example (接下页)
图 47 and 图 48 are 3-D layout pictures with top view and bottom views.
注
The location of the PCB cutout between the primary side and secondary sides, which
ensures isolation performance.
图 47. 3-D PCB Top View
图 48. 3-D PCB Bottom View
版权 © 2018, Texas Instruments Incorporated
39
UCC21222
ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
12.1.1.1 使用 WEBENCH® 工具创建定制设计
请单击此处,使用 UCC21222 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数,如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下,可执行以下操作:
•
•
•
•
运行电气仿真,观察重要波形以及电路性能
运行热性能仿真,了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息,请访问 www.ti.com.cn/WEBENCH。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档:
•
隔离相关术语
12.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件,以及申请样片或购买产品的快速链
接。
表 5. 相关链接
器件
产品文件夹
请单击此处
样片与购买
请单击此处
技术文档
工具与软件
请单击此处
支持和社区
请单击此处
UCC21222
请单击此处
12.4 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.6 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
40
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UCC21222
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ZHCSHS5A –FEBRUARY 2018–REVISED APRIL 2018
12.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
12.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
41
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资
源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、
验证并测试您的应用;(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更,恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2019 德州仪器半导体技术(上海)有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
UCC21222D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
16
16
40
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
21222
21222
UCC21222DR
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资
源,不保证其中不含任何瑕疵,且不做任何明示或暗示的担保,包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任:(1) 针对您的应用选择合适的TI 产品;(2) 设计、
验证并测试您的应用;(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更,恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源,也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等,TI对此概不负责,并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址:上海市浦东新区世纪大道 1568 号中建大厦 32 楼,邮政编码:200122
Copyright © 2020 德州仪器半导体技术(上海)有限公司
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