UCC21710DWR_技术文档

UCC21710

ZHCSMQ3B –AUGUST 2020 –REVISED MAY 2023

UCC21710 适用于SiC/IGBT 并具有主动保护、隔离式模拟检测和

高CMTI 的10A 拉电流/灌电流增强型隔离式单通道栅极驱动器

1 特性

3 说明

• 5.7kV _RMS单通道隔离式栅极驱动器

• 驱动高达2121V_pk的SiC MOSFET 和IGBT

• 33V 最大输出驱动电压(VDD-VEE)

• ±10A 驱动强度和分离输出

UCC21710 是一款电隔离单通道栅极驱动器，设计用

于驱动高达 1700V 的 SiC MOSFET 和 IGBT。它具有

先进的集成保护特性、出色的动态性能和稳健性。

UCC21710 具有高达±10A 的峰值拉电流和灌电流。

• 150V/ns 最小CMTI

• 4A 内部有源米勒钳位

• 故障状况下400 mA 软关断

• 具有PWM 输出的隔离式模拟传感器

输入侧通过 SiO₂电容隔离技术与输出侧相隔离，支持

高达 1.5kV_RMS的工作电压、12.8kV_PK的浪涌抗扰

度，隔离栅寿命超过 40 年，并提供较低的器件间偏

斜，共模噪声抗扰度(CMTI) 大于150V/ns。

– 采用NTC、PTC 或热敏二极管的温度感应

– 高电压直流链路或相电压

UCC21710 具有高级保护功能，如快速过流和短路检

测、分流电流检测支持、故障报告、有源米勒钳位以及

输入和输出侧电源 UVLO（用于优化 SiC 和 IGBT 开

关行为和稳健性）。可以利用隔离式模拟至PWM 传感

器更轻松地进行温度或电压感测，从而进一步提高驱动

器的多功能性并简化系统设计工作量、尺寸和成本。

• 过流警报FLT 和通过RST/EN 重置

• 针对RST/EN 的快速启用/禁用响应

• 抑制输入引脚上的<40 ns 噪声瞬态和脉冲

• RDY 上的12V VDD UVLO（具有电源正常指示功

能）

• 具有高达5V 的过冲/欠冲瞬态电压抗扰度的输入/输

器件信息

封装⁽¹⁾

出

• 130ns（最大）传播延迟和30ns（最大）脉冲/器件

间偏移

封装尺寸（标称值）

器件型号

UCC21710

DW SOIC-16

10.3mm × 7.5mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

• SOIC-16 DW 封装，爬电距离和间隙> 8mm

• 工作结温范围：-40°C 至+150°C

• 安全相关认证：

– 符合DIN EN IEC 60747-17 (VDE 0884-17) 标

准的增强型绝缘

– UL 1577 组件认证计划

APWM

VCC

RST/EN

FLT

AIN

OC

1

2

3

4

5

6

7

8

16

15

COM

OUTH

VDD

14

13

12

11

10

9

2 应用

• 工业电机驱动

RDY

INÅ

• 服务器、电信和工业电源

• 不间断电源(UPS)

• 光伏逆变器

OUTL

CLMPI

VEE

IN+

• 可再生能源存储转换器

GND

Not to scale

器件引脚配置

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSD43

UCC21710

ZHCSMQ3B –AUGUST 2020 –REVISED MAY 2023

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Table of Contents

7.5 OC (Over Current) Protection................................... 21

8 Detailed Description......................................................22

8.1 Overview...................................................................22

8.2 Functional Block Diagram.........................................23

8.3 Feature Description...................................................23

8.4 Device Functional Modes..........................................29

9 Applications and Implementation................................31

9.1 Application Information............................................. 31

9.2 Typical Application.................................................... 31

10 Power Supply Recommendations..............................45

11 Layout...........................................................................46

11.1 Layout Guidelines................................................... 46

11.2 Layout Example...................................................... 47

12 Device and Documentation Support..........................48

12.1 Device Support....................................................... 48

12.2 Documentation Support.......................................... 48

12.3 Receiving Notification of Documentation Updates..48

12.4 支持资源..................................................................48

12.5 Trademarks.............................................................48

12.6 静电放电警告.......................................................... 48

12.7 术语表..................................................................... 48

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Power Ratings.............................................................5

6.6 Insulation Specifications............................................. 6

6.7 Safety-Related Certifications...................................... 7

6.8 Safety Limiting Values.................................................7

6.9 Electrical Characteristics.............................................8

6.10 Switching Characteristics........................................10

6.11 Insulation Characteristics Curves............................11

6.12 Typical Characteristics............................................12

7 Parameter Measurement Information..........................16

7.1 Propagation Delay.................................................... 16

7.2 Input Deglitch Filter...................................................17

7.3 Active Miller Clamp................................................... 18

7.4 Under Voltage Lockout (UVLO)................................ 19

Information.................................................................... 48

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision A (November 2020) to Revision B (May 2023)

Page

• 向特性中添加了安全相关认证.............................................................................................................................1

• Added what to do with unused pins to pin functions table..................................................................................3

• Changed recommended value of decoupling capacitors. ..................................................................................3

• Added recommended decoupling capacitor layout placement. ......................................................................... 3

• Changed test conditions per DIN EN IEC 60747-17 (VDE 0884-17)..................................................................6

• Changed certification status............................................................................................................................... 7

• Changed VAin lower limit to 0.6V........................................................................................................................8

• Changed direction of I_CLMPIin V_CLP-CLMPItest condition.....................................................................................8

• Added test condition for soft turn-off current.......................................................................................................8

• Deleted short circuit clamping max condition..................................................................................................... 8

• Change OC figure.............................................................................................................................................27

• Added function state showing gate driver turning on. Changed RDY condition when VCC is PD. ................. 29

• Changed OC figure...........................................................................................................................................38

• Changed OC figure...........................................................................................................................................39

• Changed OC figure...........................................................................................................................................40

• Deleted tie dot in 图9-16 .................................................................................................................................44

Changes from Revision * (August 2020) to Revision A (November 2020)

Page

• 将销售状态从“预告信息”更改为“量产数据”................................................................................................1

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5 Pin Configuration and Functions

APWM

VCC

RST/EN

FLT

AIN

OC

1

2

3

4

5

6

7

8

16

15

COM

OUTH

VDD

14

13

12

11

10

9

RDY

INÅ

OUTL

CLMPI

VEE

IN+

GND

Not to scale

图5-1. UCC21710 DW SOIC (16) Top View

表5-1. Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. Tie to COM if

unused.

AIN

1

I

Over current detection pin, support lower threshold for SenseFET, DESAT, and shunt resistor sensing. Tie to

COM if unused.

OC

2

COM

3

4

P

Common ground reference, connecting to emitter pin for IGBT or source pin for SiC-MOSFET

Gate driver output pull up

OUTH

O

Positive supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified gate

driver source peak current capability. Place decoupling capacitor close to the pin.

VDD

5

6

7

P

O

OUTL

CLMPI

Gate driver output pull down

Internal Active miller clamp, connecting this pin directly to the gate of the power transistor. Leave floating or

tie to VEE if unused.

Negative supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified

gate driver sink peak current capability. Place decoupling capacitor close to the pin.

VEE

8

P

GND

IN+

9

P

I

Input power supply and logic ground reference

10

11

Non-inverting gate driver control input. Tie to VCC if unused.

Inverting gate driver control input. Tie to GND if unused.

I

IN–

Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other

RDY signals

RDY

FLT

12

13

O

Active low fault alarm output upon over current or short circuit. FLT is in open drain configuration and can be

paralleled with other faults

The RST/EN serves two purposes:

1) Enable / shutdown of the output side. The FET is turned off by a regular turn-off, if terminal EN is set to

low;

RST/EN

14

I

2) Resets the OC condition signaled on FLT pin. if terminal RST/EN is set to low for more than 1000ns. A

reset of signal FLT is asserted at the rising edge of terminal RST/EN.

For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The

FET is turned off by a general turn-off, if terminal EN is set to low.

Input power supply from 3V to 5.5V. Bypass with a >1-μF capacitor to GND. Place decoupling capacitor

close to the pin.

VCC

15

16

P

APWM

O

Isolated Analog Sensing PWM output. Leave floating if unused.

(1) P = Power, G = Ground, I = Input, O = Output

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER

MIN

–0.3

MAX

6

UNIT

V

VCC

VDD

VEE

V_MAX

VCC –GND

VDD –COM

VEE –COM

VDD –VEE

36

V

–0.3

0.3

V

–17.5

36

V

–0.3

DC

VCC

VCC+5.0

5

V

GND–0.3

GND–5.0

–0.3

IN+, IN–, RST/EN

Transient, less than 100 ns⁽²⁾

V

Reference to COM

AIN

OC

V

-0.3

6

DC

VDD

VDD+5.0

VCC

20

V

VEE–0.3

VEE–5.0

GND–0.3

OUTH, OUTL , CLMPI

Transient, less than 100 ns⁽²⁾

RDY, FLT, APWM

V

I_FLT, I_RDY

I_APWM

T_J

FLT, and RDY pin input current

APWM pin output current

mA

°C

20

Junction temperature range

Storage temperature range

150

–40

–65

T_stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Values are verified by characterization on bench.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC

JS-001⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC

specification JESD22-C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

PARAMETER

VCC

MIN

3.0

13

MAX

5.5

UNIT

V

VCC–GND

VDD–COM

VDD–VEE

VDD

33

V_MAX

33

–

0.7×VCC

0

High level input voltage

Low level input voltage

VCC

0.3×VCC

4.5

Reference to GND

V

IN+, IN–, RST/EN

AIN

t_RST/EN

T_A

Reference to COM

0.6

V

Minimum pulse width that reset the fault

Ambient Temperature

1000

ns

°C

125

150

–40

T_J

Junction temperature

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6.4 Thermal Information

UCC21710

THERMAL METRIC⁽¹⁾

DW (SOIC)

16-PINS

68.3

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

27.5

32.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

14.1

32.3

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

Value

UNIT

P_D

Maximum power dissipation (both sides)

985

mW

Maximum power dissipation by

transmitter side

P_D1

VCC = 5V, VDD-COM = 20V, COM-VEE = 5V, IN+/- = 5V, 150kHz,

50% Duty Cycle for 10nF load, T_a=25^oC

20

mW

Maximum power dissipation by receiver

side

P_D2

965

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UNIT

6.6 Insulation Specifications

PARAMETER

GENERAL

TEST CONDITIONS

VALUE

CLR

CPG

External clearance⁽¹⁾

Shortest terminal-to-terminal distance through air

> 8

mm

Shortest terminal-to-terminal distance across the

package surface

External creepage⁽¹⁾

Minimum internal gap (Internal clearance) of the

double insulation (2 × 0.0085 mm)

DTI

CTI

Distance through the insulation

> 17

µm

V

Comparative tracking index

Material group

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664–1

> 600

I

I-IV

I-III

Rated mains voltage ≤300 V_RMS

Rated mains voltage ≤600 V_RMS

Rated mains voltage ≤1000 V_RMS

Overvoltage Category per IEC 60664–1

DIN EN IEC 60747-17 (VDE 0884-17)⁽²⁾

V_IORMMaximum repetitive peak isolation voltage AC voltage (bipolar)

2121

1500

V_PK

AC voltage (sine wave) Time dependent dielectric

breakdown (TDDB) test

V_RMS

V_IOWM

Maximum isolation working voltage

DC voltage

2121

8000

V_DC

V_PK

V_IMP

Maximum impulse voltage

Tested in air, 1.2/50-μs waveform per IEC 62368-1

V_TEST=V_IOTM, t = 60 s (qualification test)

V_TEST=1.2 x V_IOTM, t = 1 s (100% production test)

V_IOTM

Maximum transient isolation voltage

8000

V_PK

Test method per IEC 62368-1, 1.2/50 µs waveform,

V_TEST= 1.6 × V_IOSM= 12800 V_PK(qualification)

V_IOSM

Maximum surge isolation voltage⁽³⁾

Method a: After I/O safety test subgroup 2/3, V_ini

=

V_IOTM, t_ini= 60 s; V_pd(m)= 1.2 × V_IORM= 2545 V_PK

t_m= 10 s

,

≤5

Method a: After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s; V_pd(m)= 1.6 × V_IORM= 3394

V_PK, t_m= 10 s

q_pd

Apparent charge⁽⁴⁾

pC

Method b1: At routine test (100% production) and

preconditioning (type test) V_ini= V_IOTM, t_ini= 1 s;

V_pd(m)= 1.875 × V_IORM= 3977 V_PK, t_m= 1 s

≤5

C_IO

R_IO

Barrier capacitance, input to output⁽⁵⁾

Insulation resistance, input to output⁽⁵⁾

~ 1

pF

V_IO= 0.5 sin (2πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

≥10¹²

≥10¹¹

≥10⁹

2

V_IO= 500 V, 100°C ≤T_A≤125°C

V_IO= 500 V at T_S= 150°C

Ω

Pollution degree

Climatic category

40/125/21

UL 1577

V_TEST= V_ISO= 5700 V_RMS, t = 60 s (qualification);

V_TEST= 1.2 × V_ISO= 6840 V_RMS, t = 1 s (100%

production)

V_ISO

Withstand isolation voltage

5700

V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be

taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the

printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques

such as inserting grooves and ribs on the PCB are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured

by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device

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6.7 Safety-Related Certifications

VDE

Certified according to DIN EN IEC 60747-17 (VDE 0884-17)

Reinforced insulation

UL

Recognized under UL 1577 Component Recognition

Program, CSA Component Acceptance Notice 5A

Maximum transient isolation voltage, 8000 V_PK

Maximum repetitive peak isolation voltage, 2121 V_PK

Maximum surge isolation voltage, 8000 V_PK

;

Single protection, 5700 V_RMS

File Number: E181974

;

Certificate number: 40040142

6.8 Safety Limiting Values

Safety limiting ⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure

of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat

the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

R

_θJA=68.3°C/W, V_DD= 15V, V_EE=-5V, T_J= 150°C, T_A

61

= 25°C

_θJA=68.3°C/W, V_DD= 20V, V_EE=-5V, T_J= 150°C, T_A

= 25°C

_θJA=68.3°C/W, V_DD= 20V, V_EE=-5V, T_J= 150°C, T_A

= 25°C

Safety input, output, or supply

current

I_S

mA

49

R

P_S

T_S

Safety input, output, or total power

Safety temperature

1220

150

mW

°C

(1) The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-

air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-

to-air thermal resistance in the 节6.4 table is that of a device installed on a high-K test board for leaded surface-mount packages. The

power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus

the power times the junction-to-air thermal resistance. These limits vary with the ambient temperature, the junction-to-air thermal

resistance, and the power supply voltages in different applications.

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6.9 Electrical Characteristics

VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V,

C_L=100pF, –40°C<T_J<150°C (unless otherwise noted)^{(1) (2)}

.

PARAMETER

VCC UVLO THRESHOLD AND DELAY

V_{VCC_ON}

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2.55

2.35

2.7

2.5

0.2

10

2.85

2.65

V_{VCC_OFF}

V_{VCC_HYS}

t_VCCFIL

V

VCC–GND

VCC UVLO Deglitch time

VCC UVLO on delay to output

high

t_{VCC+ to OUT}

t_{VCC–to OUT}

t_{VCC+ to RDY}

t_{VCC–to RDY}

28

5

37.8

10

50

15

50

15

IN+ = VCC, IN–= GND

VCC UVLO off delay to output

low

µs

VCC UVLO on delay to RDY

high

30

5

37.8

10

RST/EN = VCC

VCC UVLO off delay to RDY

low

VDD UVLO THRESHOLD AND DELAY

V_{VDD_ON}

10.5

9.9

12.0

10.7

0.8

5

12.8

11.8

V_{VDD_OFF}

V_{VDD_HYS}

t_VDDFIL

V

VDD–COM

VDD UVLO Deglitch time

VDD UVLO on delay to output

high

t_{VDD+ to OUT}

t_{VDD–to OUT}

t_{VDD+ to RDY}

t_{VDD–to RDY}

2

5

8

10

15

IN+ = VCC, IN–= GND

VDD UVLO off delay to output

low

µs

VDD UVLO on delay to RDY

high

10

RST/EN = FLT=High

VDD UVLO off delay to RDY

low

VCC, VDD QUIESCENT CURRENT

I_VCCQVCC quiescent current

OUT(H) = High, f_S= 0Hz, AIN=2V

OUT(L) = Low, f_S= 0Hz, AIN=2V

OUT(H) = High, f_S= 0Hz, AIN=2V

OUT(L) = Low, f_S= 0Hz, AIN=2V

2.5

1.45

3.6

3

2

4

2.75

5.9

mA

4

I_VDDQ

VDD quiescent current

3.1

3.7

5.3

LOGIC INPUTS —IN+, IN–and RST/EN

V_INH

Input high threshold

V_CC=3.3V

1.85

1.52

0.33

2.31

V

V_INL

Input low threshold

0.99

V_INHYS

Input threshold hysteresis

Input high level input leakage

current

I_IH

V_IN= VCC

90

–90

55

µA

I_IL

Input low level input leakage

V_IN= GND

Input pins pull down

resistance

R_IND

R_INU

see 节8 for more information

kΩ

Input pins pull up resistance

55

IN+, IN–and RST/EN

deglitch (ON and OFF) filter

time

T_INFIL

f_S= 50kHz

28

40

60

ns

Deglitch filter time to

reset /FLT

T_RSTFIL

400

650

800

GATE DRIVER STAGE

I_OUT, I_OUTH

Peak source current

10

A

C_L=0.18µF, f_S=1kHz

I_OUT, I_OUTL

Peak sink current

(3)

R_OUTH

Output pull-up resistance

Output pull-down resistance

2.5

0.3

I_OUT= –0.1A

Ω

R_OUTL

I_OUT= 0.1A

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6.9 Electrical Characteristics (continued)

VCC=3.3V or 5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE =0V, 5V, 8V or 15V,

C_L=100pF, –40°C<T_J<150°C (unless otherwise noted)^{(1) (2)}

.

PARAMETER

TEST CONDITIONS

MIN

TYP

17.5

60

MAX

UNIT

V

V_OUTH

High level output voltage

I_OUT= –0.2A, V_DD=18V

V_OUTL

Low level output voltage

I_OUT= 0.2A

mV

ACTIVE PULLDOWN

Output active pull down on

OUT, OUTL

I_OUTLor I_OUT= 0.1×I_OUT(L)(tpy)

VDD=OPEN, VEE=COM

,

V_OUTPD

1.5

2

2.5

V

INTERNAL ACTIVE MILLER CLAMP

V_CLMPTH

V_CLMPI

I_CLMPI

Miller clamp threshold voltage Reference to VEE

2.0

VEE + 0.5

4

V

A

Output low clamp voltage

Output low clamp current

I_CLMPI= 1A

V_CLMPI= 0V, VEE = –2.5V

Miller clamp pull down

resistance

R_CLMPI

I_CLMPI= 0.2A

C_L= 1.8nF

0.6

15

Ω

t_DCLMPI

Miller clamp ON delay time

50

ns

SHORT CIRCUIT CLAMPING

V_CLP-OUT(H)

V_CLP-OUT(L)

V_CLP-CLMPI

OC PROTECTION

I_DCHG

OUT = Low, I_OUT(H)= 500mA, t_CLP=10us

OUT = High, I_OUT(L)= 500mA, t_CLP=10us

OUT = High, I_CLMPI= 20mA, t_CLP=10us

0.9

1.8

1.0

V

_OUT–VDD, V_OUTH–VDD

_OUT–VDD, V_OUTL–VDD

_CLMPI–VDD

OC pull down current when

Detection Threshold

V_OC= 1V

40

mA

V

V_OCTH

0.63

0.7

0.77

Voltage when OUT(L) = LOW,

Reference to COM

V_OCL

I_OC= 5mA

0.13

120

270

530

V

t_OCFIL

t_OCOFF

OC fault deglitch filter

95

150

300

180

400

750

ns

OC propagation delay to

OUT(L) 90%

t_OCFLT

OC to FLT low delay

INTERNAL SOFT TURN-OFF

Soft turn-off current on fault

conditions

I_STO

V_DD-V_EE=20V, V_OUTL-COM=8V

250

400

570

mA

ISOLATED TEMPERATURE SENSE AND MONITOR (AIN–APWM)

V_AIN

Analog sensing voltage range

Internal current source

0.6

196

380

4.5

209

420

V

I_AIN

V_AIN=2.5V, -40°C< T_J< 150°C

V_AIN=2.5V

203

400

10

µA

f_APWM

BW_AIN

APWM output frequency

AIN–APWM bandwidth

kHz

V_AIN= 0.6V

V_AIN= 2.5V

V_AIN= 4.5V

86.5

48.5

7.5

88

89.5

51.5

11.5

D_APWM

APWM Dutycycle

50

%

10

FLT AND RDY REPORTING

VDD UVLO RDY low

minimum holding time

t_RDYHLD

t_FLTMUTE

R_ODON

V_ODL

0.55

1

ms

Output mute time on fault

Reset fault through RST/EN

I_ODON= 5mA

Open drain output on

resistance

30

Ω

Open drain low output voltage IODON = 5mA

0.3

V

COMMON MODE TRANSIENT IMMUNITY

Common-mode transient

immunity

CMTI

150

V/ns

(1) Current are positive into and negative out of the specified terminal.

(2) All voltages are referenced to COM unless otherwise notified.

(3) For internal PMOS only. Refer to 节8.3 for effective pull-up resistance.

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6.10 Switching Characteristics

VCC=5.0V, 1uF capacitor from VCC to GND, VDD–COM=20V, 18V or 15V, COM–VEE = 3V, 5V or 8V, C_L=100pF, –

40°C<T_J<150°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Propagation delay time –

High to Low

t_PDHL

t_PDLH

PWD

60

90

130

Propagation delay time –

Low to High

60

90

130

Pulse width distortion |

ns

30

t_PDHL–t_PDLH|

t_sk-pp

Part to Part skew

Rising or Falling Propagation Delay

t_r

t_f

Driver output rise time

Driver output fall time

C_L=10nF

33

27

Maximum switching

frequency

f_MAX

1

MHz

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6.11 Insulation Characteristics Curves

80

1400

1200

1000

800

600

400

200

0

VDD=15V; VEE=-5V

VDD=20V; VEE=-5V

60

40

20

0

25

50

75

100

125

150

0

20

40

60

80

100

120

140

160

Ambient Temperature (^oC)

Safe

图6-1. Thermal Derating Curve for Limiting Current 图6-2. Thermal Derating Curve for Limiting Power

per VDE

1.E+12

1.E+11

1.E+10

1.E+09

1.E+08

1.E+07

1.E+06

1.E+05

1.E+04

1.E+03

1.E+02

1.E+01

54 Yrs

TDDB Line (< 1 ppm Fail Rate)

VDE Safety Margin Zone

1800V_RMS

2200

200

1200

3200

4200

5200

6200

Applied Voltage (V_RMS

)

图6-3. Reinforced Isolation Capacitor Life Time Projection

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6.12 Typical Characteristics

22

20

18

16

14

12

10

8

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

20

18

16

14

12

10

8

6

4

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D016

D017

图6-4. Output High Drive Current vs. Temperature 图6-5. Output Low Driver Current vs. Temperature

6

5.5

5

4

3.5

3

VCC = 3.3V

VCC = 5V

VCC = 3.3V

VCC = 5V

4.5

4

2.5

2

3.5

1.5

3

1

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D015

D014

IN+ = High

IN- = Low

IN+ = Low

IN- = Low

图6-6. I_VCCQSupply Current vs. Temperature

图6-7. I_VCCQSupply Current vs. Temperature

5

6

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

4.5

5.5

4

3.5

3

5

4.5

4

2.5

3.5

2

3

30

70

110

150 190

Frequency (kHz)

230

270

310

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D018

D012

IN+ = High

IN- = Low

图6-8. I_VCCQSupply Current vs. Input Frequency

图6-9. I_VDDQSupply Current vs. Temperature

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6

10

9

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

VDD/VEE = 18V/0V

VDD/VEE = 20V/-5V

5.5

5

8

7

4.5

4

6

5

4

3.5

3

2

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

30

70

110

150

190

Frequency (kHz)

230

270

310

D013

D019

IN+ = Low

IN- = Low

图6-11. I_VDDQSupply Current vs. Input Frequency

图6-10. I_VDDQSupply Current vs. Temperature

4

14

13.5

13

3.5

3

12.5

12

2.5

2

11.5

11

10.5

10

1.5

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D002

D001

图6-13. VDD UVLO vs. Temperature

图6-12. VCC UVLO vs. Temperature

100

90

80

70

60

50

100

90

80

70

60

50

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D022

D021

V_CC= 3.3V

V_DD=18V

R_OFF= 0Ω

C_L= 100pF

V_CC= 3.3V

V_DD=18V

R_OFF= 0Ω

C_L= 100pF

R_ON= 0Ω

图6-15. Propagation Delay t_PDHLvs. Temperature

图6-14. Propagation Delay t_PDLHvs. Temperature

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60

50

40

30

20

10

60

50

40

30

20

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

V_DD=18V

R_OFF= 0Ω

D023

D024

V_CC= 3.3V

V_DD=18V

C_L= 10nF

V_CC= 3.3V

C_L= 10nF

R_ON= 0Ω

R_OFF= 0Ω

R_ON= 0Ω

图6-16. t_rRise Time vs. Temperature

图6-17. t_fFall Time vs. Temperature

2.5

3

2.75

2.5

2.25

2

1.75

1.5

1.25

1

2.25

2

1.75

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D025

1.5

图6-19. V_CLP-OUT(H)Short Circuit Clamping Voltage

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

vs. Temperature

D008

图6-18. V_OUTPDOutput Active Pulldown Voltage vs.

Temperature

2

1.75

1.5

3

2.75

2.5

1.25

1

2.25

2

0.75

0.5

0.25

-60 -40 -20

1.75

0

20 40 60 80 100 120 140 160

Temperature (èC)

D026

1.5

50

图6-20. V_CLP-OUT(L)Short Circuit Clamping Voltage

70

90

110

130

150 160

vs. Temperature

Temperature (èC)

D009

图6-21. V_CLMPTHMiller Clamp Threshold Voltage

vs. Temperature

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8.5

7.5

6.5

5.5

4.5

3.5

2.5

1.5

0.5

18

17

16

15

14

13

12

11

10

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (°C)

D011

D010

图6-22. I_CLMPIMiller Clamp Sink Current vs.

图6-23. t_DCLMPIMiller Clamp ON Delay Time vs.

Temperature

330

1

0.8

0.6

0.4

0.2

VCC = 3.3V

VCC = 5V

320

310

300

290

280

270

260

250

240

230

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D020

D003

图6-24. t_OCOFFOC Propagation Delay vs.

图6-25. V_OCTHOC Detection Threshold vs.

Temperature

700

650

600

550

500

450

400

-60 -40 -20

0

20 40 60 80 100 120 140 160

Temperature (èC)

D004

图6-26. t_OCFLTOC to FLT Low Delay Time vs. Temperature

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7 Parameter Measurement Information

7.1 Propagation Delay

7.1.1 Non-Inverting and Inverting Propagation Delay

图7-1 shows the propagation delay measurement for non-inverting configurations. 图7-2 shows the propagation

delay measurement with the inverting configurations.

50%

IN+

INÅ

t_PDLH

t_PDHL

90%

10%

OUT

图7-1. Non-inverting Logic Propagation Delay Measurement

IN+

INÅ

50%

t_PDLH

t_PDHL

90%

OUT

10%

图7-2. Inverting Logic Propagation Delay Measurement

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7.2 Input Deglitch Filter

In order to increase the robustness of gate driver over noise transient and accidental small pulses on the input

pins, i.e. IN+, IN–, RST/EN, a 40ns deglitch filter is designed to filter out the transients and make sure there is

no faulty output responses or accidental driver malfunctions. When the IN+ or IN– PWM pulse is smaller than

the input deglitch filter width, T_INFIL, there will be no responses on OUT drive signal. 图7-3 and 图7-4 shows the

IN+ pin ON and OFF pulse deglitch filter effect. 图7-5 and 图7-6 shows the IN–pin ON and OFF pulse deglitch

filter effect.

IN+

t_PWM< T_INFIL

IN+

INÅ

OUT

图7-3. IN+ ON Deglitch Filter

图7-4. IN+ OFF Deglitch Filter

IN+

INÅ

t_PWM< T_INFIL

INÅ

OUT

图7-5. IN–ON Deglitch Filter

图7-6. IN–OFF Deglitch Filter

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7.3 Active Miller Clamp

7.3.1 Internal Active Miller Clamp

For gate driver application with unipolar bias supply or bipolar supply with small negative turn-off voltage, active

Miller clamp can help add a additional low impedance path to bypass the Miller current and prevent the

unintentional turn-on through the Miller capacitance. 图 7-7 shows the timing diagram for on-chip internal Miller

clamp function.

IN

(”IN+‘ Å ”INÅ‘)

t_DCLMPI

V_CLMPTH

OUT

HIGH

CLMPI

Ctrl.

LOW

图7-7. Timing Diagram for Internal Active Miller Clamp Function

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7.4 Under Voltage Lockout (UVLO)

UVLO is one of the key protection features designed to protect the system in case of bias supply failures on VCC

—primary side power supply, and VDD —secondary side power supply.

7.4.1 VCC UVLO

The VCC UVLO protection details are discussed in this section. 图 7-8 shows the timing diagram illustrating the

definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

IN

(”IN+‘ Å ”INÅ‘)

t_VCCFIL

t_{VCCÅ to OUT}

V_{VCC_ON}

VCC

V_{VCC_OFF}

VDD

COM

VEE

t_{VCC+ to OUT}

90%

V_CLMPTH

OUT

10%

t_{VCC+ to RDY}

t_RDYHLD

t_{VCCÅ to RDY}

Hi-Z

RDY

VCC

APWM

图7-8. VCC UVLO Protection Timing Diagram

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7.4.2 VDD UVLO

The VDD UVLO protection details are discussed in this section. 图 7-9 shows the timing diagram illustrating the

definition of UVLO ON/OFF threshold, deglitch filter, response time, RDY and AIN–APWM.

IN

(”IN+‘ Å ”INÅ‘)

t_VDDFIL

VDD

t_{VDDÅ to OUT}

V_{VDD_ON}

V_{VDD_OFF}

COM

VEE

VCC

t_{VDD+ to OUT}

V_CLMPTH

OUT

90%

t_RDYHLD

10%

t_{VDD+ to RDY}

t_{VDDÅ to RDY}

RDY

Hi-Z

VCC

APWM

图7-9. VDD UVLO Protection Timing Diagram

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7.5 OC (Over Current) Protection

7.5.1 OC Protection with Soft Turn-OFF

OC Protection is used to sense the current of SiC-MOSFETs and IGBTs under over current or shoot-through

condition. 图7-10 shows the timing diagram of OC operation with soft turn-off.

IN

(”IN+‘ Å ”INÅ‘)

t_OCFIL

V_OCTH

OC

t_OCOFF

90%

GATE

V_CLMPTH

t_OCFLT

t_FLTMUTE

Hi-Z

FLT

t_RSTFIL

RST/EN

HIGH

Hi-Z

OUTH

OUTL

LOW

Hi-Z

LOW

图7-10. OC Protection with Soft Turn-OFF

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8 Detailed Description

8.1 Overview

The UCC21710 device is an advanced isolated gate driver with state-of-art protection and sensing features for

SiC MOSFETs and IGBTs. The device can support up to 2121V DC operating voltage based on SiC MOSFETs

and IGBTs, and can be used to above 10kW applications such as HEV/EV traction inverter, motor drive, on-

board and off-board battery charger, solar inverter, etc. The galvanic isolation is implemented by the capacitive

isolation technology, which can realize a reliable reinforced isolation between the low voltage DSP/MCU and

high voltage side.

The ±10A peak sink and source current of UCC21710 can drive the SiC MOSFET modules and IGBT modules

directly without an extra buffer. The driver can also be used to drive higher power modules or parallel modules

with external buffer stage. The device can support up to 1.5-kV_RMSworking voltage, 12.8-kV_PKsurge immunity

with longer than 40 years isolation barrier life. The strong drive strength helps to switch the device fast and

reduce the switching loss. While the 150V/ns minimum CMTI guarantees the reliability of the system with fast

switching speed. The small propagation delay and part-to-part skew can minimize the deadtime setting, so the

conduction loss can be reduced.

The device includes extensive protection and monitor features to increase the reliability and robustness of the

SiC MOSFET and IGBT based systems. The 12V output side power supply UVLO is suitable for switches with

gate voltage ≥ 15V. The active Miller clamp feature prevents the false turn on causing by Miller capacitance

during fast switching. The device has the state-of-art overcurrent and short circuit detection time, and fault

reporting function to the low voltage side DSP/MCU. The soft turn-off with soft turn off is triggered when the

overcurrent or short circuit fault is detected, minimizing the short circuit energy while reducing the overshoot

voltage on the switches.

The isolated analog to PWM sensor can be used as switch temperature sensing, DC bus voltage sensing,

auxiliary power supply sensing, etc. The PWM signal can be fed directly to DSP/MCU or through a low-pass-filter

as an analog signal.

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8.2 Functional Block Diagram

CLMPI

OUTH

7

4

6

10

11

15

9

IN+

IN-

55kohm

PWM Inputs

MOD

DEMOD

Output Stage

-

ON/OFF Control

STO

VCC

OUTL

VDD

VCC

UVLO

VCC Supply

5

GND

RDY

LDO's for VEE,

UVLO

COM and channel

3

8

COM

VEE

OC

12

13

14

16

Fault Decode

FLT

OC Protec on

Analog 2 PWM

2

Fault Encode

RST/EN

50kohm

PWM Driver

AIN

1

APWM

DEMOD

MOD

8.3 Feature Description

8.3.1 Power Supply

The input side power supply VCC can support a wide voltage range from 3V to 5.5V. The device supports both

unipolar and bipolar power supply on the output side, with a wide range from 13V to 33V from VDD to VEE. The

negative power supply with respect to switch source or emitter is usually adopted to avoid false turn on when the

other switch in the phase leg is turned on. The negative voltage is especially important for SiC MOSFET due to

its fast switching speed and low threshold voltage.

8.3.2 Driver Stage

UCC21710 has ±10A peak drive strength and is suitable for high power applications. The high drive strength can

drive a SiC MOSFET module, IGBT module or paralleled discrete devices directly without extra buffer stage.

UCC21710 can also be used to drive higher power modules or parallel modules with extra buffer stage.

Regardless of the values of VDD, the peak sink and source current can be kept at 10A. The driver features an

important safety function wherein, when the input pins are in floating condition, the OUTH/OUTL is held in LOW

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state. The split output of the driver stage is depicted in 图8-1. The driver has rail-to-rail output by implementing a

hybrid pull-up structure with a P-Channel MOSFET in parallel with an N-Channel MOSFET, and an N-Channel

MOSFET to pulldown. The pull-up NMOS is the same as the pull down NMOS, so the on resistance R_NMOSis

the same as R_OL. The hybrid pull-up structure delivers the highest peak-source current when it is most needed,

during the Miller plateau region of the power semiconductor turn-on transient. The R_OHin represents the on-

resistance of the pull-up P-Channel MOSFET. However, the effective pull-up resistance is much smaller than

R_OH. Since the pull-up N-Channel MOSFET has much smaller on-resistance than the P-Channel MOSFET, the

pull-up N-Channel MOSFET dominates most of the turn-on transient, until the voltage on OUTH pin is about 3V

below VDD voltage. The effective resistance of the hybrid pull-up structure during this period is about 2 x R_OL

.

Then the P-Channel MOSFET pulls up the OUTH voltage to VDD rail. The low pull-up impedance results in

strong drive strength during the turn-on transient, which shortens the charging time of the input capacitance of

the power semiconductor and reduces the turn on switching loss.

The pull-down structure of the driver stage is implemented solely by a pull-down N-Channel MOSFET. This

MOSFET can ensure the OUTL voltage be pulled down to VEE rail. The low pull-down impedance not only

results in high sink current to reduce the turn-off time, but also helps to increase the noise immunity considering

the Miller effect.

VDD

R_OH

R_NMOS

OUTH

Input

Signal

Anti Shoot-

through

Circuitry

OUTL

R_OL

图8-1. Gate Driver Output Stage

8.3.3 VCC and VDD Undervoltage Lockout (UVLO)

UCC21710 implements the internal UVLO protection feature for both input and output power supplies VCC and

VDD. When the supply voltage is lower than the threshold voltage, the driver output is held as LOW. The output

only goes HIGH when both VCC and VDD are out of the UVLO status. The UVLO protection feature not only

reduces the power consumption of the driver itself during low power supply voltage condition, but also increases

the efficiency of the power stage. For SiC MOSFET and IGBT, the on-resistance reduces while the gate-source

voltage or gate-emitter voltage increases. If the power semiconductor is turned on with a low VDD value, the

conduction loss increases significantly and can lead to a thermal issue and efficiency reduction of the power

stage. UCC21710 implements 12V threshold voltage of VDD UVLO, with 800mV hysteresis. This threshold

voltage is suitable for both SiC MOSFET and IGBT.

The UVLO protection block features with hysteresis and deglitch filter, which help to improve the noise immunity

of the power supply. During the turn on and turn off switching transient, the driver sources and sinks a peak

transient current from the power supply, which can result in sudden voltage drop of the power supply. With

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hysteresis and UVLO deglitch filter, the internal UVLO protection block will ignore small noises during the normal

switching transients.

The timing diagrams of the UVLO feature of VCC and VDD are shown in 图7-8, and 图7-9. The RDY pin on the

input side is used to indicate the power good condition. The RDY pin is open drain. During UVLO condition, the

RDY pin is held in low status and connected to GND. Normally the pin is pulled up externally to VCC to indicate

the power good. The AIN-APWM function stops working during the UVLO status. The APWM pin on the input

side will be held LOW.

8.3.4 Active Pulldown

UCC21710 implements an active pulldown feature to ensure the OUTH/OUTL pin clamping to VEE when the

VDD is open. The OUTH/OUTL pin is in high-impedance status when VDD is open, the active pulldown feature

can prevent the output be false turned on before the device is back to control.

VDD

OUTL

R_a

Control

Circuit

VEE

COM

图8-2. Active Pulldown

8.3.5 Short Circuit Clamping

During short circuit condition, the Miller capacitance can cause a current sinking to the OUTH/OUTL pin due to

the high dV/dt and boost the OUTH/OUTL voltage. The short circuit clamping feature of UCC21710 can clamp

the OUTH/OUTL pin voltage to be slightly higher than VDD, which can protect the power semiconductors from a

gate-source and gate-emitter overvoltage breakdown. This feature is realized by an internal diode from the

OUTH/OUTL to VDD.

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VDD

D₁D₂D₃

OUTH

Control

Circuitry

OUTL

CLMPI

图8-3. Short Circuit Clamping

8.3.6 Internal Active Miller Clamp

Active Miller clamp feature is important to prevent the false turn-on while the driver is in OFF state. In

applications which the device can be in synchronous rectifier mode, the body diode conducts the current during

the deadtime while the device is in OFF state, the drain-source or collector-emitter voltage remains the same

and the dV/dt happens when the other power semiconductor of the phase leg turns on. The low internal pull-

down impedance of UCC21710 can provide a strong pulldown to hold the OUTL to VEE. However, external gate

resistance is usually adopted to limit the dV/dt. The Miller effect during the turn on transient of the other power

semiconductor can cause a voltage drop on the external gate resistor, which boost the gate-source or gate-

emitter voltage. If the voltage on V_GSor V_GEis higher than the threshold voltage of the power semiconductor, a

shoot through can happen and cause catastrophic damage. The active Miller clamp feature of UCC21710 drives

an internal MOSFET, which connects to the device gate. The internal MOSFET is triggered when the gate

voltage is lower than V_CLMPTH, which is 2V above VEE, and creates a low impedance path to avoid the false turn

on issue.

V_CLMPTH

VCC

OUTH

+

3V to 5.5V

IN+

œ

CLMPI

OUTL

Control

Circuitry

µC

MOD

DEMOD

IN-

VEE

COM

VCC

图8-4. Active Miller Clamp

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8.3.7 Overcurrent and Short Circuit Protection

The UCC21710 implements a fast overcurrent and short circuit protection feature to protect the SiC MOSFET or

IGBT from catastrophic breakdown during fault. The OC pin of the device has a typical 0.7V threshold with

respect to COM, source or emitter of the power semiconductor. When the input is in floating condition, or the

output is held in low state, the OC pin is pulled down by an internal MOSFET and held in LOW state, which

prevents the overcurrent and short circuit fault from false triggering. The OC pin is in high-impedance state when

the output is in high state, which means the overcurrent and short circuit protection feature only works when the

power semiconductor is in on state. The internal pulldown MOSFET helps to discharge the voltage of OC pin

when the power semiconductor is turned off.

The overcurrent and short circuit protection feature can be used to SiC MOSFET module or IGBT module with

SenseFET, traditional desaturation circuit and shunt resistor in series with the power loop for lower power

applications. For SiC MOSFET module or IGBT module with SenseFET, the SenseFET integrated in the module

can scale down the drain current or collector current. With an external high precision sense resistor, the drain

current or collector current can be accurately measured. If the voltage of the sensed resistor higher than the

overcurrent threshold V_OCTHis detected, the soft turn-off is initiated. A fault will be reported to the input side FLT

pin to DSP/MCU. The output is held to LOW after the fault is detected, and can only be reset by the RST/EN pin.

The state-of-art overcurrent and short circuit detection time helps to ensure a short shutdown time for SiC

MOSFET and IGBT.

The overcurrent and short circuit protection feature can also be paired with desaturation circuit and shunt

resistors. The DESAT threshold can be programmable in this case, which increases the versatility of the device.

Detailed application diagrams of desaturation circuit and shunt resistor will be given in 节9.2.2.6.

• High current and high dI/dt during the overcurrent and short circuit fault can cause a voltage bounce on shunt

resistor’s parasitic inductance and board layout parasitic, which results in false trigger of OC pin. High

precision, low ESL and small value resistor must be used in this approach.

• Shunt resistor approach is not recommended for high power applications and short circuit protection of the

low power applications.

The detailed applications of the overcurrent and short circuit feature will be discussed in the Application and

Implementation section.

OUTL

R_OFF

OC

R_FLT

+

FLT

DEMOD

MOD

+

R_S

C_FLT

V_OCTH

–

Control

Logic

GND

COM

VEE

图8-5. Overcurrent and Short Circuit Protection

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8.3.8 Soft Turn-off

UCC21710 initiates a soft turn-off when the overcurrent and short circuit protection is triggered. When the

overcurrent and short circuit fault happens, the power power semiconductor transits from the linear region to the

saturation region very fast. The channel current is controlled by the gate voltage. By pulling down the gate

voltage with a soft turn off current, the dI/dt of the channel current is controlled by the gate voltage and

decreasing in a soft manner, thus the overshoot of the power semiconductor is limited and prevents the

overvoltage breakdown. The timing diagram of soft turn-off shows in 图7-10.

UCC21710

OC

SenseFET

Kelvin

Connection

+

V_OCTH

œ

C_{_FLT}

R_S

Control

Logic

COM

OUTL

Soft Turn-Off

VEE

图8-6. Soft Turn-off

8.3.9 Fault ( FLT, Reset and Enable ( RST/EN)

The FLT pin of UCC21710 is open drain and can report a fault signal to the DSP/MCU when the fault is detected

through the OC pin. The FLT pin will be pulled down to GND after the fault is detected, and is held low until a

reset signal is received from RST/EN. The device has a fault mute time t_FLTMUTE, within which the device ignores

any reset signal.

The RST/EN is pulled down internally by a 50kΩ resistor, and is thus disabled by default when this pin is

floating. It must be pulled up externally to enable the driver. The pin has two purposes:

• To reset the FLT pin. To reset, then RST/EN pin is pulled low; if the pin is set and held in low state for more

than t_RSTFILafter the mute time t_FLTMUTE, then the fault signal is reset and FLT is reset back to the high

impedance status at the rising edge of the input signal at RST/EN pin.

• Enable and shutdown the device. If the RST/EN pin is pulled low for longer than t_RSTFIL, the driver will be

disabled and OUTL will be activated to pull down the gate of the IGBT or SiC MOSFET. The pin must be

pulled up externally to enable the part, otherwise the device is disabled by default.

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8.3.10 Isolated Analog to PWM Signal Function

The UCC21710 features an isolated analog to PWM signal function from AIN to APWM pin, which allows the

isolated temperature sensing, high voltage dc bus voltage sensing, etc. An internal current source I_AINin AIN pin

is implemented in the device to bias an external thermal diode or temperature sensing resistor. The UCC21710

encodes the voltage signal V_AINto a PWM signal, passing through the reinforced isolation barrier, and output to

APWM pin on the input side. The PWM signal can either be transferred directly to DSP/MCU to calculate the

duty cycle, or filtered by a simple RC filter as an analog signal. The AIN voltage input range is from 0.6V to 4.5V,

and the corresponding duty cycle of the APWM output ranges from 88% to 10%. The duty cycle increases

linearly from 10% to 88% while the AIN voltage decreases from 4.5V to 0.6V. This corresponds to the

temperature coefficient of the negative temperature coefficient (NTC) resistor and thermal diode. When AIN is

floating, the AIN voltage is 5V and the APWM operates at 400kHz with approximately 10% duty cycle. The duty

cycle absolute error is ±1.5% at 0.6V and 2.5V and is +1.5% / -2.5% at 4.5V across both process and

temperature. The in-system accuracy can be improved using calibration to account for any offset. The accuracy

of the internal current source I_AINis ±3% across process and temperature.

The isolated analog to PWM signal feature can also support other analog signal sensing, such as the high

voltage DC bus voltage, etc. The internal current source I_AINshould be taken into account when designing the

potential divider if sensing a high voltage.

VDD

In Module or

Discrete

VCC

13V to

33V

+

œ

3V to 5.5V

APWM

œ

AIN

+

DEMOD

MOD

µC

R_{filt_1}

R_{filt_2}

C_{filt_2}

GND

OSC

C_{filt_1}

COM

Thermal

Diode

NTC or

PTC

图8-7. Isolated Analog to PWM Signal

表8-1. Function Table

8.4 Device Functional Modes

The 表8-1 lists the device function.

INPUT

OUTPUT

OUTH/

OUTL

VCC

VDD

VEE

IN+

IN-

RST/EN

AIN

RDY

FLT

CLMPI

APWM

PU

PD

PU

PD

PU

X

Low

HiZ

Low

HiZ

Low

HiZ

Low

HiZ

Low

HiZ

Low

P^*

PU

X

Low

X

Open

PU

X

Open

PU

X

Low

High

Low

HiZ

PU

Low

X

High

PU

High

Low

P^*

PU

High

P^*

PU

P^*

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PU: Power Up (VCC ≥ 2.85 V, VDD ≥ 13.1 V, VEE ≤ 0 V); PD: Power Down (VCC ≤ 2.35 V, VDD ≤ 9.9 V);

X: Irrelevant; P^*: PWM Pulse; HiZ: High Impedance

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9 Applications and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

9.1 Application Information

The UCC21710 device is very versatile because of the strong drive strength, wide range of output power supply,

high isolation ratings, high CMTI and superior protection and sensing features. The 1.5-kVRMS working voltage

and 12.8-kVPK surge immunity can support up both SiC MOSFET and IGBT modules with DC bus voltage up to

2121V. The device can be used in both low power and high power applications such as the traction inverter in

HEV/EV, on-board charger and charging pile, motor driver, solar inverter, industrial power supplies and etc. The

device can drive the high power SiC MOSFET module, IGBT module or paralleled discrete device directly

without external buffer drive circuit based on NPN/PNP bipolar transistor in totem-pole structure, which allows

the driver to have more control to the power semiconductor and saves the cost and space of the board design.

UCC21710 can also be used to drive very high power modules or paralleled modules with external buffer stage.

The input side can support power supply and microcontroller signal from 3.3V to 5V, and the device level shifts

the signal to output side through reinforced isolation barrier. The device has wide output power supply range

from 13V to 33V and support wide range of negative power supply. This allows the driver to be used in SiC

MOSFET applications, IGBT application and many others. The 12V UVLO benefits the power semiconductor

with lower conduction loss and improves the system efficiency. As a reinforced isolated single channel driver, the

device can be used to drive either a low-side or high-side driver.

UCC21710 device features extensive protection and monitoring features, which can monitor, report and protect

the system from various fault conditions.

• Fast detection and protection for the overcurrent and short circuit fault. The feature is preferable in a split

source SiC MOSFET module or a split emitter IGBT module. For the modules with no integrated current

mirror or paralleled discrete semiconductors, the traditional desaturation circuit can be modified to implement

short circuit protection. The semiconductor is shutdown when the fault is detected and FLT pin is pulled down

to indicate the fault detection. The device is latched unless reset signal is received from the RST/EN pin.

• Soft turn-off feature to protect the power semiconductor from catastrophic breakdown during overcurrent and

short circuit fault. The shutdown energy can be controlled while the overshoot of the power semiconductor is

limited.

• UVLO detection to protect the semiconductor from excessive conduction loss. Once the device is detected to

be in UVLO mode, the output is pulled down and RDY pin indicates the power supply is lost. The device is

back to normal operation mode once the power supply is out of the UVLO status. The power good status can

be monitored from the RDY pin.

• Analog signal sensing with isolated analog to PWM signal feature. This feature allows the device to sense the

temperature of the semiconductor from the thermal diode or temperature sensing resistor, or dc bus voltage

with resistor divider. A PWM signal is generated on the low voltage side with reinforced isolated from the high

voltage side. The signal can be fed back to the microcontroller for the temperature monitoring, voltage

monitoring and etc.

• The active Miller clamp feature protects the power semiconductor from false turn on by driving an external

MOSFET. This feature allows the flexibility of the board layout design and the pulldown strength of Miller

clamp FET.

• Enable and disable function through the RST/EN pin.

• Short circuit clamping.

• Active pulldown.

9.2 Typical Application

图9-1 shows the typical application of a half bridge using two UCC21710 isolated gate drivers. The half bridge is

a basic element in various power electronics applications such as traction inverter in HEV/EV to convert the DC

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current of the electric vehicle’s battery to the AC current to drive the electric motor in the propulsion system.

The topology can also be used in motor drive applications to control the operating speed and torque of the AC

motors.

UCC

21710

1

2

3

4

5

6

PWM

3-Phase

Input

1

2

3

4

5

6

µC

M

APWM

FLT

UCC

21710

图9-1. Typical Application Schematic

9.2.1 Design Requirements

The design of the power system for end equipment should consider some design requirements to ensure the

reliable operation of UCC1710 through the load range. The design considerations include the peak source and

sink current, power dissipation, overcurrent and short circuit protection, AIN-APWM function for analog signal

sensing and etc.

A design example for a half bridge based on IGBT is given in this subsection. The design parameters are show

in 表9-1.

表9-1. Design Parameters

Parameter

Input Supply Voltage

IN-OUT Configuration

Positive Output Voltage VDD

Negative Output Voltage VEE

DC Bus Voltage

Value

5V

Non-inverting

15V

-5V

800V

Peak Drain Current

Switching Frequency

Switch Type

300A

50kHz

IGBT Module

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9.2.2 Detailed Design Procedure

9.2.2.1 Input filters for IN+, IN- and RST/EN

In the applications of traction inverter or motor drive, the power semiconductors are in hard switching mode. With

the strong drive strength of UCC21710, the dV/dt can be high, especially for SiC MOSFET. Noise can not only

be coupled to the gate voltage due to the parasitic inductance, but also to the input side as the non-ideal PCB

layout and coupled capacitance.

UCC21710 features a 40ns internal deglitch filter to IN+, IN- and RST/EN pin. Any signal less than 40ns can be

filtered out from the input pins. For noisy systems, external low pass filter can be added externally to the input

pins. Adding low pass filters to IN+, IN- and RST/EN pins can effectively increase the noise immunity and

increase the signal integrity. When not in use, the IN+, IN- and RST/EN pins should not be floating. IN- should be

tied to GND if only IN+ is used for non-inverting input to output configuration. The purpose of the low pass filter is

to filter out the high frequency noise generated by the layout parasitics. While choosing the low pass filter

resistors and capacitors, both the noise immunity effect and delay time should be considered according to the

system requirements.

9.2.2.2 PWM Interlock of IN+ and IN-

UCC21710 features the PWM interlock for IN+ and IN- pins, which can be used to prevent the phase leg shoot

through issue. As shown in Function Table, the output is logic low while both IN+ and IN- are logic high. When

only IN+ is used, IN- can be tied to GND. To utilize the PWM interlock function, the PWM signal of the other

switch in the phase leg can be sent to the IN- pin. As shown in PWM Interlock for a Half Bridge, the PWM_T is

the PWM signal to top side switch, the PWM_B is the PWM signal to bottom side switch. For the top side gate

driver, the PWM_T signal is given to the IN+ pin, while the PWM_B signal is given to the IN- pin; for the bottom

side gate driver, the PWM_B signal is given to the IN+ pin, while PWM_T signal is given to the IN- pin. When

both PWM_T and PWM_B signals are high, the outputs of both gate drivers are logic low to prevent the shoot

through condition.

IN+

IN-

R_ON

OUTH

OUTL

R_OFF

PWM_T

PWM_B

R_ON

IN+

IN-

OUTH

OUTL

R_OFF

图9-2. PWM Interlock for a Half Bridge

9.2.2.3 FLT, RDY and RST/EN Pin Circuitry

Both FLT and RDY pin are open-drain output. The RST/EN pin has 50kΩinternal pulldown resistor, so the driver

is in OFF status if the RST/EN pin is not pulled up externally. A 5kΩ resistor can be used as pullup resistor for

the FLT, RDY and RST/EN pins.

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To improve the noise immunity due to the parasitic coupling and common mode noise, low pass filters can be

added between the FLT, RDY and RST/EN pins and the microcontroller. A filter capacitor between 100pF to

300pF can be added.

3.3V to 5V

VCC

15

1µF

0.1µF

GND

IN+

9

10

INt

11

5kQ

5kQ 5kQ

FLT

12

13

100pF

RDY

100pF

RST/EN

14

16

100pF

APWM

图9-3. FLT, RDY and RST/EN Pins Circuitry

9.2.2.4 RST/EN Pin Control

RST/EN pin has two functions. It is used to enable or shutdown the outputs of the driver and to reset the fault

signaled on the FLT pin after OC is detected. RST/EN pin needs to be pulled up to enable the device; when the

pin is pulled down, the device is in disabled status. By default the driver is disabled with the internal 50kΩ

pulldown resistor at this pin.

When the driver is latched after overcurrent or short circuit fault is detected, the FLT pin and output are latched

low and need to be reset by the RST/EN pin. The microcontroller must send a signal to RST/EN pin after the

fault to reset the driver. The driver will not respond until after the mute time t_FLTMUTE. The reset signal must be

held low for at least t_RSTFILafter the mute time.

This pin can also be used to automatically reset the driver. The continuous input signal IN+ or IN- can be applied

to RST/EN pin. There is no separate reset signal from the microcontroller when configuring the driver this way. If

the PWM is applied to the non-inverting input IN+, then IN+ can also be tied to RST/EN pin. If the PWM is

applied to the inverting input IN-, then a NOT logic is needed between the PWM signal from the microcontroller

and the RST/EN pin. Using either configuration results in the driver being reset in every switching cycle without

an extra control signal from microcontroller tied to RST/EN pin. One must ensure the PWM off-time is greater

than t_RSTFILin order to reset the driver in cause of a OC fault.

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3.3V to 5V

0.1µF

3.3V to 5V

VCC

15

1µF

0.1µF

GND

IN+

GND

IN+

9

10

INt

5kQ

11

5kQ

11

5kQ

FLT

12

13

12

13

100pF

RDY

RST/EN

APWM

RST/EN

APWM

14

16

14

16

图9-4. Automatic Reset Control

9.2.2.5 Turn on and turn off gate resistors

UCC21710 features split outputs OUTH and OUTL, which enables the independent control of the turn on and

turn off switching speed. The turn on and turn off resistance determine the peak source and sink current, which

controls the switching speed in turn. Meanwhile, the power dissipation in the gate driver should be considered to

ensure the device is in the thermal limit. At first, the peak source and sink current are calculated as:

VDD - VEE

R_{OH_EFF}+R_ON+R_{G _Int}

I_{source _ pk}= min(10A,

I_{sink _ pk}= min(10A,

)

VDD - VEE

R_OL+R_OFF+R_{G _Int}

)

(1)

Where

• R_{OH_EFF}is the effective internal pull up resistance of the hybrid pull-up structure, which is approximately 2 x

_OL, about 0.7 Ω

R

• R_OLis the internal pulldown resistance, about 0.3 Ω

• R_ONis the external turn on gate resistance

• R_OFFis the external turn off gate resistance

• R_{G_Int}is the internal resistance of the SiC MOSFET or IGBT module

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VDD

C_ies=C_gc+C_ge

+

C_gc

VDD

R_{OH_EFF}

t

OUTH

OUTL

R_ON

R_{G_Int}

R_OFF

C_ge

+

VEE

R_OL

t

VEE

COM

图9-5. Output Model for Calculating Peak Gate Current

For example, for an IGBT module based system with the following parameters:

• Q_g= 3300 nC

• R_{G_Int}= 1.7 Ω

• R_ON=R_OFF= 1 Ω

The peak source and sink current in this case are:

VDD - VEE

R_{OH_EFF}+R_ON+R_{G _Int}

I_{source _ pk}= min(10A,

) ö 5.9A

VDD - VEE

R_OL+R_OFF+R_{G _Int}

I_{sink _ pk}= min(10A,

) ö 6.7A

(2)

Thus by using 1Ω external gate resistance, the peak source current is 5.9A, the peak sink current is 6.7A. The

collector-to-emitter dV/dt during the turn on switching transient is dominated by the gate current at the Miller

plateau voltage. The hybrid pullup structure ensures the peak source current at the Miller plateau voltage, unless

the turn on gate resistor is too high. The faster the collector-to-emitter, V_ce, voltage rises to V_DC, the smaller the

turn on switching loss is. The dV/dt can be estimated as Q_gc/I_{source_pk}. For the turn off switching transient, the

drain-to-source dV/dt is dominated by the load current, unless the turn off gate resistor is too high. After V_ce

reaches the dc bus voltage, the power semiconductor is in saturation mode and the channel current is controlled

by V_ge. The peak sink current determines the dI/dt, which dominates the V_cevoltage overshoot accordingly. If

using relatively large turn off gate resistance, the V_ceovershoot can be limited. The overshoot can be estimated

by:

DV = L_stray∂I_load/ ((R_OFF+R_OL+R_{G_Int})∂C_ies∂ln(V_plat/ V ))

ce

th

(3)

Where

• L_strayis the stray inductance in power switching loop, as shown in 图9-6

• I_loadis the load current, which is the turn off current of the power semiconductor

• C_iesis the input capacitance of the power semiconductor

• V_platis the plateau voltage of the power semiconductor

• V_this the threshold voltage of the power semiconductor

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L_DC

L_c1

L_stray=L_DC+L_e1+L_c1+L_e1+L_c1

R_G

L_load

t

+

L_e1

+

VDC

t

L_c2

VDD

C_gc

C_ies=C_gc+C_ge

R_G

OUTH

OUTL

COM

C_ge

L_e2

图9-6. Stray Parasitic Inductance of IGBTs in a Half-Bridge Configuration

The power dissipation should be taken into account to maintain the gate driver within the thermal limit. The

power loss of the gate driver includes the quiescent loss and the switching loss, which can be calculated as:

P

= P_Q+P

DR

SW

(4)

P_Qis the quiescent power loss for the driver, which is I_qx (VDD-VEE) = 5mA x 20V = 0.100W. The quiescent

power loss is the power consumed by the internal circuits such as the input stage, reference voltage, logic

circuits, protection circuits when the driver is switching when the driver is biased with VDD and VEE, and also

the charging and discharging current of the internal circuit when the driver is switching. The power dissipation

when the driver is switching can be calculated as:

R_{OH_EFF}

2 R_{OH_EFF}+R_ON+R_{G _Int}R_OL+R_OFF+R_{G _Int}

R_OL

1

P

=

∂(

+

)∂(VDD - VEE)∂ f_sw∂Q_g

SW

(5)

Where

• Q_gis the gate charge required at the operation point to fully charge the gate voltage from VEE to VDD

• f_swis the switching frequency

In this example, the P_SWcan be calculated as:

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R_{OH_EFF}

2 R_{OH_EFF}+ R_ON+ R_{G _Int}R_OL+R_OFF+R_{G _Int}

R_OL

1

P

=

∂(

+

)∂(VDD - VEE)∂ f_sw∂Q_g= 0.505W

SW

(6)

Thus, the total power loss is:

P =P +P = 0.10W +0.505W = 0.605W

DR

Q

SW

(7)

When the board temperature is 125°C, the junction temperature can be estimated as:

T_j= T + y_jb∂P ö 150^oC

b

DR

(8)

Therefore, for the application in this example, with 125°C board temperature, the maximum switching frequency

is ~50kHz to keep the gate driver in the thermal limit. By using a lower switching frequency, or increasing

external gate resistance, the gate driver can be operated at a higher switching frequency.

9.2.2.6 Overcurrent and Short Circuit Protection

Fast and reliable overcurrent and short circuit protection is important to protect the catastrophic break down of

the SiC MOSFET and IGBT modules, and improve the system reliability. The UCC21710 features a state-of-art

overcurrent and short circuit protection, which can be applied to both SiC MOSFET and IGBT modules with

various detection circuits.

9.2.2.6.1 Protection Based on Power Modules with Integrated SenseFET

The overcurrent and short circuit protection function is suitable for the SiC MOSFET and IGBT modules with

integrated SenseFET. The SenseFET scales down the main power loop current and outputs the current with a

dedicated pin of the power module. With external high precision sensing resistor, the scaled down current can be

measured and the main power loop current can be calculated. The value of the sensing resistor R_Ssets the

protection threshold of the main current. For example, with a ratio of 1:N = 1:50000 of the integrated current

mirror, by using the R_Sas 20Ω, the threshold protection current is:

V_OCTH

I_{OC _ TH}

=

∂N = 1750A

R_S

(9)

The overcurrent and short circuit protection based on integrated SenseFET has high precision, as it is sensing

the current directly. The accuracy of the method is related to two factors: the scaling down ratio of the main

power loop current and the SenseFET, and the precision of the sensing resistor. Since the current is sensed from

the SenseFET, which is isolated from the main power loop, and the current is scaled down significantly with

much less dI/dt, the sensing loop has good noise immunity. To further improve the noise immunity, a low pass

filter can be added. A 100pF to 10nF filter capacitor can be added. The delay time caused by the low pass filter

should also be considered for the protection circuitry design.

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+

C_FLT

Control

Logic

图9-7. Overcurrent and Short Circuit Protection Based on IGBT Module with SenseFET

9.2.2.6.2 Protection Based on Desaturation Circuit

For SiC MOSFET and IGBT modules without SenseFET, desaturation (DESAT) circuit is the most popular circuit

which is adopted for overcurrent and short circuit protection. The circuit consists of a current source, a resistor, a

blanking capacitor and a diode. Normally the current source is provided from the gate driver, when the device

turns on, a current source charges the blanking capacitor and the diode forward biased. During normal

operation, the capacitor voltage is clamped by the switch V_CEvoltage. When short circuit happens, the capacitor

voltage is quickly charged to the threshold voltage which triggers the device shutdown. For the UCC21710, the

OC pin does not feature an internal current source. The current source should be generated externally from the

output power supply. When UCC21710 is in OFF state, the OC pin is pulled down by an internal MOSFET, which

creates an offset voltage on OC pin. By choosing R1 and R2 significantly higher than the pulldown resistance of

the internal MOSFET, the offset can be ignored. When UCC21710 is in ON state, the OC pin is high impedance.

The current source is generated by the output power supply VDD and the external resistor divider R1, R2 and

R3. The overcurrent detection threshold voltage of the IGBT is:

R₂+ R₃

R₃

V_DET=V_OCTH

∂

-V_F

(10)

(11)

The blanking time of the detection circuit is:

R₁+ R₂

R₁+ R₂+ R₃

R₁+ R₂+ R₃V_OCTH

t_BLK= -

∂R₃∂C_BLK∂ln(1-

∂

)

R₃

V_DD

Where:

• V_OCTHis the detection threshold voltage of the gate driver

• R₁, R₂and R₃are the resistance of the voltage divider

• C_BLKis the blanking capacitor

• V_Fis the forward voltage of the high voltage diode D_HV

The modified desaturation circuit has all the benefits of the conventional desaturation circuit. The circuit has

negligible power loss, and is easy to implement. The detection threshold voltage of IGBT and blanking time can

be programmed by external components. Different with the conventional desaturation circuit, the overcurrent

detection threshold voltage of the IGBT can be modified to any voltage level, either higher or lower than the

detection threshold voltage of the driver. A parallel schottky diode can be connected between OC and COM pins

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to prevent the negative voltage on the OC pin in noisy system. Since the desaturation circuit measures the V_CE

of the IGBT or V_DSof the SiC MOSFET, not directly the current, the accuracy of the protection is not as high as

the SenseFET based protection method. The current threshold cannot be accurately controlled in the protection.

R_OFF

D_HV

VDD

R₁

OC

R₂

+

FLT

DEMOD

MOD

+

V_OCTH

R₃

C_BLK

Control

Logic

GND

COM

VEE

图9-8. Overcurrent and Short Circuit Protection Based on Desaturation Circuit

9.2.2.6.3 Protection Based on Shunt Resistor in Power Loop

In lower power applications, to simplify the circuit and reduce the cost, a shunt resistor can be used in series in

the power loop and measure the current directly. Since the resistor is in series in the power loop, it directly

measures the current and can have high accuracy by using a high precision resistor. The resistance needs to be

small to reduce the power loss, and should have large enough voltage resolution for the protection. Since the

sensing resistor is also in series in the gate driver loop, the voltage drop on the sensing resistor can cause the

voltage drop on the gate voltage of the IGBT or SiC MOSFET modules. The parasitic inductance of the sensing

resistor and the PCB trace of the sensing loop will also cause a noise voltage source during switching transient,

which makes the gate voltage oscillate. Thus, this method is not recommended for high power application, or

when dI/dt is high. To use it in low power application, the shunt resistor loop should be designed to have the

optimal voltage drop and minimum noise injection to the gate loop.

+

C_FLT

Control

Logic

图9-9. Overcurrent and Short Circuit Protection Based on Shunt Resistor

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9.2.2.7 Isolated Analog Signal Sensing

The isolated analog signal sensing feature provides a simple isolated channel for the isolated temperature

detection, voltage sensing and etc. One typical application of this function is the temperature monitor of the

power semiconductor. Thermal diodes or temperature sensing resistors are integrated in the SiC MOSFET or

IGBT module close to the dies to monitor the junction temperature. UCC21710 has an internal 203uA current

source with ±3% accuracy across temperature, which can forward bias the thermal diodes or create a voltage

drop on the temperature sensing resistors. The sensed voltage from the AIN pin is passed through the isolation

barrier to the input side and transformed to a PWM signal. The duty cycle of the PWM changes linearly from

10% to 88% when the AIN voltage changes from 4.5V to 0.6V and can be represented using 方程式12.

D_APWM(%) = -20 * V_AIN+100

(12)

9.2.2.7.1 Isolated Temperature Sensing

A typical application circuit is shown in 图 9-10. To sense temperature, the AIN pin is connected to the thermal

diode or thermistor which can be discrete or integrated within the power module. A low pass filter is

recommended for the AIN input. Since the temperature signal does not have a high bandwidth, the low pass

filter is mainly used for filtering the noise introduced by the switching of the power device, which does not require

stringent control for propagation delay. The filter capacitance for C_filtcan be chosen between 1nF to 100nF and

the filter resistance R_filtbetween 1Ω to 10Ω according to the noise level.

The output of APWM is directly connected to the microcontroller to measure the duty cycle dependent on the

voltage input at AIN, using 方程式12.

UCC217xx

In Module or

VCC

VDD

AIN

Discrete

13V to

33V

+

3V to 5.5V

APWM

œ

+

DEMOD

MOD

µC

R_filt

C_filt

OSC

GND

COM

Thermal

Diode

NTC or

PTC

图9-10. Thermal Diode or Thermistor Temperature Sensing Configuration

When a high-precision voltage supply for VCC is used on the primary side of UCC21710 the duty cycle output of

APWM may also be filtered and the voltage measured using the microcontroller's ADC input pin, as shown in 图

9-11. The frequency of APWM is 400kHz, so the value for R_{filt_2}and C_{filt_2}should be such that the cutoff

frequency is below 400kHz. Temperature does not change rapidly, thus the rise time due to the RC constant of

the filter is not under a strict requirement.

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UCC217xx

VDD

AIN

In Module or

Discrete

VCC

13V to

33V

+

œ

3V to 5.5V

œ

APWM

+

DEMOD

MOD

µC

R_{filt_1}

R_{filt_2}

C_{filt_2}

GND

OSC

C_{filt_1}

COM

Thermal

Diode

NTC or

PTC

图9-11. APWM Channel with Filtered Output

The example below shows the results using a 4.7kΩ NTC, NTCS0805E3472FMT, in series with a 3kΩ resistor

and also the thermal diode using four diode-connected MMBT3904 NPN transistors. The sensed voltage of the 4

MMBT3904 thermal diodes connected in series ranges from about 2.5V to 1.6V from 25°C to 135°C,

corresponding to 50% to 68% duty cycle. The sensed voltage of the NTC thermistor connected in series with the

3kΩresistor ranges from about 1.5V to 0.6V from 25°C to 135°C, corresponding to 70% to 88% duty cycle. The

voltage at VAIN of both sensors and the corresponding measured duty cycle at APWM is shown in 图9-12.

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

90

84

78

72

66

60

54

Thermal Diode V_AIN

NTC V_AIN

Thermal Diode APWM

NTC APWM

48

20

40

60

80

Temperature (èC)

100

120

140

VAIN

图9-12. Thermal diode and NTC V_AINand Corresponding Duty Cycle at APWM

The duty cycle output has an accuracy of ±3% throughout temperature without any calibration, as shown in 图

9-13 but with single-point calibration at 25°C, the duty accuracy can be improved to ±1%, as shown in 图9-14.

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1.5

Thermal Diode APWM Duty Error

NTC APWM Duty Error

1.25

1

0.75

0.5

0.25

0

-0.25

20

40

60

80

Temperature (èC)

100

120

140

APWM

图9-13. APWM Duty Error Without Calibration

0.8

0.6

0.4

0.2

0

Thermal Diode APWM Duty Error

NTC APWM Duty Error

-0.2

20

40

60

80

Temperature (èC)

100

120

140

APWM

图9-14. APWM Duty Error with Single-Point Calibration

9.2.2.7.2 Isolated DC Bus Voltage Sensing

The AIN to APWM channel may be used for other applications such as the DC-link voltage sensing, as shown in

图 9-15. The same filtering requirements as given above may be used in this case, as well. The number of

attenuation resistors, R_{atten_1}through R_{atten_n}, is dependent on the voltage level and power rating of the resistor.

The voltage is finally measured across R_{LV_DC}to monitor the stepped-down voltage of the HV DC-link which

must fall within the voltage range of AIN from 0.6V to 4.5V. The driver should be referenced to the same point as

the measurement reference, thus in the case shown below the UCC21710 is driving the lower IGBT in the half-

bridge and the DC-link voltage measurement is referenced to COM. The internal current source I_AINshould be

taken into account when designing the resistor divider. The AIN pin voltage is:

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R_{LV _DC}

n

V_AIN

=

∂ V_DC+R_{LV _DC}∂I_AIN

R_{LV _DC}

+

R

atten _ i

ƒ

i=1

(13)

R_{atten_1}

R_{atten_2}

VDD

VCC

R_{atten_n}

13V to

33V

+

3V to 5.5V

APWM

œ

C_DC

+

AIN

DEMOD

MOD

µC

R_filt

C_filt

R_{filt_2}

C_{filt_2}

GND

R_{LV_DC}

OSC

COM

图9-15. DC-link Voltage Sensing Configuration

9.2.2.8 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the NPN/PNP buffer shown in 图

9-16) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be

avoided. The MJD44H11/MJD45H11 pair is appropriate for peak currents up to 15 A, the D44VH10/ D45VH10

pair is up to 20 A peak.

In the case of a over-current detection, the soft turn off (STO) is activated. External components must be added

to implement STO instead of normal turn off speed when an external buffer is used. C_STOsets the timing for soft

turn off and R_STOlimits the inrush current to below the current rating of the internal FET (10A). R_STOshould be at

least (VDD-VEE)/10. The soft turn off timing is determined by the internal current source of 400mA and the

capacitor C_STO. C_STOis calculated using 方程式14.

I_STO∂ t_STO

VDD - VEE

C_STO

=

(14)

• I_STOis the the internal STO current source, 400mA

• t_STOis the desired STO timing

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图9-16. Current Buffer for Increased Drive Strength

10 Power Supply Recommendations

During the turn on and turn off switching transient, the peak source and sink current is provided by the VDD and

VEE power supply. The large peak current is possible to drain the VDD and VEE voltage level and cause a

voltage droop on the power supplies. To stabilize the power supply and ensure a reliable operation, a set of

decoupling capacitors are recommended at the power supplies. Considering UCC21710 has ±10A peak drive

strength and can generate high dV/dt, a 10µF bypass cap is recommended between VDD and COM, VEE and

COM. A 1µF bypass cap is recommended between VCC and GND due to less current comparing with output

side power supplies. A 0.1µF decoupling cap is also recommended for each power supply to filter out high

frequency noise. The decoupling capacitors must be low ESR and ESL to avoid high frequency noise, and

should be placed as close as possible to the VCC, VDD and VEE pins to prevent noise coupling from the system

parasitics of PCB layout.

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11 Layout

11.1 Layout Guidelines

Due to the strong drive strength of UCC21710, careful considerations must be taken in PCB design. Below are

some key points:

• The driver should be placed as close as possible to the power semiconductor to reduce the parasitic

inductance of the gate loop on the PCB traces

• The decoupling capacitors of the input and output power supplies should be placed as close as possible to

the power supply pins. The peak current generated at each switching transient can cause high dI/dt and

voltage spike on the parasitic inductance of PCB traces

• The driver COM pin should be connected to the Kelvin connection of SiC MOSFET source or IGBT emitter. If

the power device does not have a split Kelvin source or emitter, the COM pin should be connected as close

as possible to the source or emitter terminal of the power device package to separate the gate loop from the

high power switching loop

• Use a ground plane on the input side to shield the input signals. The input signals can be distorted by the

high frequency noise generated by the output side switching transients. The ground plane provides a low-

inductance filter for the return current flow

• If the gate driver is used for the low side switch which the COM pin connected to the dc bus negative, use the

ground plane on the output side to shield the output signals from the noise generated by the switch node; if

the gate driver is used for the high side switch, which the COM pin is connected to the switch node, ground

plane is not recommended

• If ground plane is not used on the output side, separate the return path of the OC and AIN ground loop from

the gate loop ground which has large peak source and sink current

• No PCB trace or copper is allowed under the gate driver. A PCB cutout is recommended to avoid any noise

coupling between the input and output side which can contaminate the isolation barrier

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11.2 Layout Example

图11-1. Layout Example

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12 Device and Documentation Support

12.1 Device Support

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此

类产品或服务单独或与任何TI 产品或服务一起的表示或认可。

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

• Isolation Glossary

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.5 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.6 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.7 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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GENERIC PACKAGE VIEW

DW 16

7.5 x 10.3, 1.27 mm pitch

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224780/A

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PACKAGE OUTLINE

DW0016B

SOIC - 2.65 mm max height

S

C

A

L

E

1

.

5

0

SOIC

C

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

14X 1.27

16

1

2X

10.5

10.1

NOTE 3

8.89

8

9

0.51

0.31

16X

7.6

7.4

B

2.65 MAX

0.25

C A

B

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4221009/B 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

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EXAMPLE BOARD LAYOUT

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (2)

1

16X (1.65)

SEE

DETAILS

SEE

DETAILS

1

16

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

9

8

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

LAND PATTERN EXAMPLE

SCALE:4X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221009/B 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DW0016B

SOIC - 2.65 mm max height

SOIC

SYMM

16X (1.65)

16X (2)

1

16

16X (0.6)

SYMM

14X (1.27)

8

9

8

9

R0.05 TYP

(9.75)

(9.3)

HV / ISOLATION OPTION

8.1 mm CLEARANCE/CREEPAGE

IPC-7351 NOMINAL

7.3 mm CLEARANCE/CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:4X

4221009/B 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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保。

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型号：	UCC21710DWR
厂家：	TEXAS INSTRUMENTS
描述：	适用于 IGBT/SiC MOSFET、具有 OC 检测和内部钳位的 5.7kVrms ±10A 单通道隔离式栅极驱动器 \| DW \| 16 \| -40 to 125 栅极驱动双极性晶体管驱动器
文件：	总55页 (文件大小：2713K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UCC21710DWR [TI]

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