V62/03666-01XE [TI]
TRIPLE 2-CHANNEL ANALOG MULTIPLEXER/DEMULTIP LEXER; ???三重2通道模拟多路复用器/ DEMULTIP LEXER
| 型号： | V62/03666-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TRIPLE 2-CHANNEL ANALOG MULTIPLEXER/DEMULTIP LEXER |
| 文件： | 总14页 (文件大小：500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢃꢆ ꢇꢈ ꢉꢊ ꢋꢌ
ꢍꢎ ꢏ ꢌ ꢄꢋ ꢐ ꢊꢑꢒꢉ ꢁꢁꢋꢄ ꢉꢁꢉ ꢄꢓ ꢔ ꢕ ꢖꢄꢍ ꢏꢌ ꢄꢋ ꢗꢋꢎꢘ ꢙꢋꢕ ꢖꢄꢍꢏ ꢌ ꢄꢋ ꢗꢋ ꢎ
SCLS503C − MAY 2003 − REVISED MAY 2004
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
Low Crosstalk Between Switches
Individual Switch Controls
D
D
D
Extremely Low Input Current
D
D
D
D
D
D
Extended Temperature Performance of
−40°C to 105°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Enhanced Product-Change Notification
†
Qualification Pedigree
− 1000-V Charged-Device Model (C101)
2-V to 5.5-V V
Operation
D OR PW PACKAGE
(TOP VIEW)
CC
Supports Mixed-Mode Voltage Operation on
All Ports
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y1
2Y0
3Y1
V
CC
D
High On-Off Output-Voltage Ratio
2-COM
1-COM
1Y1
1Y0
A
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
3-COM
3Y0
INH
GND
GND
B
C
description/ordering information
This triple 2-channel CMOS analog multiplexer/demultiplexer is designed for 2-V to 5.5-V V
operation.
CC
The SN74LV4053A handles both analog and digital signals. Each channel permits signals with amplitudes up
to 5.5 V (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
SOIC − D
Tape and reel
SN74LV4053ATDREP
SN74LV4053ATPWREP
LV4053ATEP
L4053EP
−40°C to 105°C
TSSOP − PW Tape and reel
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
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SCLS503C − MAY 2003 − REVISED MAY 2004
FUNCTION TABLE
INPUTS
ON CHANNELS
INH
L
C
L
B
L
A
L
1Y0, 2Y0, 3Y0
1Y1, 2Y0, 3Y0
1Y0, 2Y1, 3Y0
1Y1, 2Y1, 3Y0
1Y0, 2Y0, 3Y1
1Y1, 2Y0, 3Y1
1Y0, 2Y1, 3Y1
1Y1, 2Y1, 3Y1
None
L
L
L
H
L
L
L
H
H
L
L
L
H
L
L
H
H
H
H
X
L
L
H
L
L
H
H
X
L
H
X
H
logic diagram (positive logic)
15
14
2-COM
1-COM
11
A
12
13
1Y0
1Y1
2Y0
2Y1
3Y0
10
B
2
1
5
9
C
3
4
3Y1
6
INH
3-COM
2
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SCLS503C − MAY 2003 − REVISED MAY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.0 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7.0 V
I
Switch I/O voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
IO
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
I/O diode current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IOK IO
Switch through current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
T
IO
CC
CC
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
‡
V
Supply voltage
2
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
CC
CC
CC
V
High-level input voltage, control inputs
V
V
× 0.7
× 0.7
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
CC
CC
CC
V
IL
Low-level input voltage, control inputs
× 0.3
× 0.3
5.5
V
V
Control input voltage
Input/output voltage
0
0
V
V
I
V
IO
CC
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
200
100
20
∆t/∆v Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
−40
105
°C
‡
With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals
be transmitted at these low supply voltages.
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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SCLS503C − MAY 2003 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
41
TEST
CONDITIONS
PARAMETER
MIN
MAX
UNIT
V
CC
MIN
MAX
180
150
75
2.3 V
3 V
225
190
100
600
225
125
40
On-state switch
resistance
I
V
= 2 mA, V = V
or GND,
T
INH
I
CC
30
r
r
Ω
on
= V , (see Figure 1)
IL
4.5 V
2.3 V
3 V
23
139
63
500
180
100
30
I
V
= 2 mA, V = V
to GND,
to GND,
T
I
CC
Peak on-state resistance
Ω
Ω
on(p)
= V
INH
IL
4.5 V
2.3 V
3 V
35
2
Difference in on-state
resistance between
switches
I
V
= 2 mA, V = V
I
T
CC
1.6
1.3
20
30
∆r
on
= V
INH
IL
4.5 V
15
20
0 to
5.5 V
I
I
Control input current
V = 5.5 V or GND
0.1
0.1
0.1
1
µA
µA
µA
I
I
V = V
CC
and V = GND, or
O
I
Off-state switch leakage
current
V = GND and V = V
,
5.5 V
1
S(off)
I
V
O
CC
= V , (see Figure 2)
INH
IH
On-state switch leakage
current
V = V
CC
or GND, V
(see Figure 3)
= V
INH IH
I
I
I
5.5 V
5.5 V
1
S(on)
Supply current
V = V or GND
20
µA
CC
I
CC
C
Control input capacitance
2
pF
IC
IS
Common terminal
capacitance
C
8.2
pF
Switch terminal
capacitance
C
C
5.6
0.5
pF
pF
OS
F
Feedthrough capacitance
switching characteristics over recommended operating free-air temperature range,
= 2.5 V 0.2 V (unless otherwise noted)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
MIN
MAX
16
UNIT
ns
MIN
TYP
MAX
t
t
Propagation
delay time
C
= 15 pF,
(see Figure 4)
PLH
PHL
L
COM or Yn
INH
Yn or COM
COM or Yn
COM or Yn
Yn or COM
COM or Yn
COM or Yn
2.5
7.6
10
t
t
Enable
delay time
C
= 15 pF,
(see Figure 5)
PZH
PZL
L
18
18
12
28
28
23
ns
t
t
Disable
delay time
C
= 15 pF,
(see Figure 5)
PHZ
PLZ
L
INH
7.7
23
ns
t
t
Propagation
delay time
C
= 50 pF,
(see Figure 4)
PLH
PHL
L
COM or Yn
INH
4.4
18
ns
t
t
Enable
delay time
C
= 50 pF,
(see Figure 5)
PZH
PZL
L
8.8
35
ns
t
t
Disable
delay time
C
= 50 pF,
(see Figure 5)
PHZ
PLZ
L
INH
11.7
35
ns
4
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SCLS503C − MAY 2003 − REVISED MAY 2004
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
MIN
MAX
10
UNIT
ns
MIN
TYP
MAX
t
t
Propagation
delay time
C
= 15 pF,
(see Figure 4)
PLH
PHL
L
COM or Yn
INH
Yn or COM
COM or Yn
COM or Yn
Yn or COM
COM or Yn
COM or Yn
1.6
5.3
6.1
2.9
6.1
8.9
6
t
t
Enable
delay time
C
= 15 pF,
(see Figure 5)
PZH
PZL
L
12
12
9
15
ns
t
t
Disable
delay time
C
= 15 pF,
(see Figure 5)
PHZ
PLZ
L
INH
15
ns
t
t
Propagation
delay time
C
= 50 pF,
(see Figure 4)
PLH
PHL
L
COM or Yn
INH
12
ns
t
t
Enable
delay time
C
= 50 pF,
(see Figure 5)
PZH
PZL
L
20
20
25
ns
t
t
Disable
delay time
C
= 50 pF,
(see Figure 5)
PHZ
PLZ
L
INH
25
ns
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted)
V
CC
T = 25°C
A
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
MIN
MAX
7
UNIT
ns
MIN
TYP
MAX
t
t
Propagation
delay time
C
= 15 pF,
(see Figure 4)
PLH
PHL
L
COM or Yn
INH
Yn or COM
COM or Yn
COM or Yn
Yn or COM
COM or Yn
COM or Yn
0.9
3.8
4.6
1.8
4.3
6.3
4
t
t
Enable
delay time
C
= 15 pF,
(see Figure 5)
PZH
PZL
L
8
8
10
10
8
ns
t
t
Disable
delay time
C
= 15 pF,
(see Figure 5)
PHZ
PLZ
L
INH
ns
t
t
Propagation
delay time
C
= 50 pF,
(see Figure 4)
PLH
PHL
L
COM or Yn
INH
6
ns
t
t
Enable
delay time
C
= 50 pF,
(see Figure 5)
PZH
PZL
L
14
14
18
18
ns
t
t
Disable
delay time
C
= 50 pF,
(see Figure 5)
PHZ
PLZ
L
INH
ns
5
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SCLS503C − MAY 2003 − REVISED MAY 2004
analog switch characteristics
T
A
= 25°C
TYP
30
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
MAX
2.3 V
3 V
C
R
= 50 pF,
= 600 Ω,
= 1 MHz (sine wave)
(see Note 5 and Figure 6)
L
L
Frequency response
(switch on)
35
COM or Yn
Yn or COM
MHz
f
in
4.5 V
2.3 V
3 V
50
−45
−45
−45
20
C
R
= 50 pF,
= 600 Ω,
= 1 MHz (sine wave)
(see Note 6 and Figure 7)
L
L
Crosstalk
(between any switches)
COM or Yn
INH
Yn or COM
COM or Yn
Yn or COM
dB
mV
dB
f
in
4.5 V
2.3 V
3 V
C
R
= 50 pF,
= 600 Ω,
= 1 MHz (square wave)
(see Figure 8)
L
L
Crosstalk
(control input to signal
output)
35
f
in
4.5 V
2.3 V
3 V
65
−45
−45
−45
C
R
= 50 pF,
= 600 Ω,
= 1 MHz
L
L
Feedthrough attenuation
(switch off)
COM or Yn
f
in
4.5 V
(see Note 6 and Figure 9)
C
R
= 50 pF,
= 10 kΩ,
= 1 kHz
2.3 V
3 V
0.1
0.1
0.1
V = 2 V
p-p
L
L
I
V = 2.5 V
I p-p
Sine-wave distortion
COM or Yn
Yn or COM
f
in
%
(sine wave)
4.5 V
V = 4 V
I p-p
(see Figure 10)
NOTES: 5. Adjust f voltage to obtain 0-dBm output. Increase f frequency until dB meter reads −3 dB.
in in
6. Adjust f voltage to obtain 0-dBm input.
in
operating characteristics, V
= 3.3 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
TYP
UNIT
f = 10
MHz
C
Power dissipation capacitance
C
= 50 pF,
5.3
pF
pd
L
PARAMETER MEASUREMENT INFORMATION
V
CC
V
INH
= V
IL
V
CC
V = V
I CC
or GND
V
O
(ON)
GND
VI – VO
2 10–3
ron
+
W
2 mA
V
V − V
I
O
Figure 1. On-State Resistance Test Circuit
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢃꢆ ꢇꢈ ꢉꢊ ꢋꢌ
ꢍꢎ ꢏ ꢌ ꢄꢋ ꢐ ꢊꢑꢒꢉ ꢁꢁꢋꢄ ꢉꢁꢉ ꢄꢓ ꢔ ꢕ ꢖꢄꢍ ꢏꢌ ꢄꢋ ꢗꢋꢎꢘ ꢙꢋꢕ ꢖꢄꢍꢏ ꢌ ꢄꢋ ꢗꢋ ꢎ
SCLS503C − MAY 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
V
= V
INH
I
IH
V
CC
V
O
A
V
(OFF)
GND
Condition 1: V = 0, V = V
CC
I
O
Condition 2: V = V , V = 0
I
CC
O
Figure 2. Off-State Switch Leakage-Current Test Circuit
V
V
CC
V
INH
= V
IL
CC
A
V
I
Open
(ON)
GND
V = V
I CC
or GND
Figure 3. On-State Switch Leakage-Current Test Circuit
V
V
CC
V
INH
= V
IH
CC
Input
Output
(ON)
GND
C
50 Ω
L
Figure 4. Propagation Delay Time, Signal Input to Signal Output
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢇꢈ ꢉ ꢊꢋ ꢌ
ꢍ ꢎꢏ ꢌ ꢄ ꢋ ꢐ ꢊꢑ ꢒꢉ ꢁ ꢁꢋ ꢄ ꢉꢁ ꢉꢄ ꢓꢔ ꢕꢖ ꢄꢍꢏ ꢌ ꢄꢋ ꢗꢋꢎꢘ ꢙꢋꢕ ꢖꢄꢍ ꢏꢌ ꢄꢋ ꢗꢋꢎ
SCLS503C − MAY 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
50 Ω
V
INH
TEST
S1
S2
t
/t
/t
GND
V
CC
GND
V
CC
PLZ PZL
t
V
CC
1 kΩ
V
I
V
O
PHZ PZH
S1
S2
GND
C
L
TEST CIRCUIT
50%
V
CC
V
CC
V
INH
50%
0 V
0 V
t
t
PZH
PZL
≈V
CC
V
OH
V
O
50%
50%
V
OL
≈0 V
(t
, t )
PZL PZH
V
CC
V
CC
V
INH
50%
50%
0 V
0 V
t
t
PLZ
PHZ
≈V
CC
V
OH
V
OH
− 0.3 V
V
O
V
OL
+ 0.3 V
V
≈0 V
OL
(t
, t )
PLZ PHZ
VOLTAGE WAVEFORMS
Figure 5. Switching Time (t
, t
t
, t
), Control to Signal Output
PZL PLZ, PZH PHZ
V
CC
V
INH
= GND
V
CC
f
V
O
in
(ON)
GND
0.1 µF
R
L
50 Ω
C
L
V
CC
/2
NOTE A: f is a sine wave.
in
Figure 6. Frequency Response (Switch On)
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢃꢆ ꢇꢈ ꢉꢊ ꢋꢌ
ꢍꢎ ꢏ ꢌ ꢄꢋ ꢐ ꢊꢑꢒꢉ ꢁꢁꢋꢄ ꢉꢁꢉ ꢄꢓ ꢔ ꢕ ꢖꢄꢍ ꢏꢌ ꢄꢋ ꢗꢋꢎꢘ ꢙꢋꢕ ꢖꢄꢍꢏ ꢌ ꢄꢋ ꢗꢋ ꢎ
SCLS503C − MAY 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
V
INH
= GND
V
CC
f
V
O1
in
50 Ω
(ON)
GND
600 Ω
0.1 µF
R
C
L
L
V
CC
/2
V
CC
V
INH
= V
CC
V
CC
f
(OFF)
GND
V
O2
in
R
C
L
600 Ω
L
V
CC
/2
Figure 7. Crosstalk Between Any Two Switches
50 Ω
V
V
CC
V
INH
CC
V
O
GND
600 Ω
R
L
C
L
V
CC
/2
V
CC
/2
Figure 8. Crosstalk Between Control Input and Switch Output
V
CC
CC
V
INH
= GND
0.1 µF
V
f
in
V
O
(OFF)
GND
600 Ω
R
L
C
50 Ω
L
V
CC
/2
V
CC
/2
Figure 9. Feedthrough Attenuation (Switch Off)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢇꢈ ꢉ ꢊꢋ ꢌ
ꢍ ꢎꢏ ꢌ ꢄ ꢋ ꢐ ꢊꢑ ꢒꢉ ꢁ ꢁꢋ ꢄ ꢉꢁ ꢉꢄ ꢓꢔ ꢕꢖ ꢄꢍꢏ ꢌ ꢄꢋ ꢗꢋꢎꢘ ꢙꢋꢕ ꢖꢄꢍ ꢏꢌ ꢄꢋ ꢗꢋꢎ
SCLS503C − MAY 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
V
INH
= GND
10 µF
10 µF
V
CC
f
in
V
O
(ON)
GND
R
L
600 Ω
C
L
V
CC
/2
Figure 10. Sine-Wave Distortion
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN74LV4053ATDREP
SN74LV4053ATPWREP
V62/03666-01XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
SOIC
PW
PW
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
V62/03666-01YE
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV4053A-EP :
Catalog: SN74LV4053A
Automotive: SN74LV4053A-Q1
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV4053ATDREP
SOIC
D
16
16
2500
2000
330.0
330.0
16.4
12.4
6.5
6.9
10.3
5.6
2.1
1.6
8.0
8.0
16.0
12.0
Q1
Q1
SN74LV4053ATPWREP TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV4053ATDREP
SN74LV4053ATPWREP
SOIC
D
16
16
2500
2000
333.2
367.0
345.9
367.0
28.6
35.0
TSSOP
PW
Pack Materials-Page 2
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