V62/03670-03XE_技术文档

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ꢊ ꢈ ꢈꢈ ꢄ ꢆ ꢋ ꢃ ꢌ ꢀ ꢍꢎꢈꢈ ꢇꢉꢏ ꢎꢀ ꢐꢅꢂ ꢑꢈ ꢀ ꢎꢅꢒꢁ ꢐꢈꢊ ꢓꢈꢎ ꢔꢅ ꢎ ꢂꢊ ꢀꢈ ꢎ

SGLS362—MAY 2006

D

Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D

Low-Power Automotive Sleep Mode

Support

Fully Compliant With Open Host Controller

Interface (OHCI) Requirements

D

Extended Temperature Performance of

−40°C to 110°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

D

Cable Power Presence Monitoring

D

Cable Ports Monitor Line Conditions for

Active Connection to Remote Node

Enhanced Product-Change Notification

D

Register Bits Give Software Control of

Contender Bit, Power Class Bits, Link

Active Control Bit, and 1394a-2000

Features

†

Qualification Pedigree

Fully Supports Provisions of IEEE

1394b-2002 at S100, S100B, S200, S200B,

S400, and S400B Signaling Rates

(B Signifies 1394b Signaling)

Data Interface to Link-Layer Controller

Pin-Selectable From 1394a-2000 Mode

(2/4/8 Parallel Bits at 49.152 MHz) or 1394b

Mode (8 Parallel Bits at 98.304 MHz)

D

Fully Supports Provisions of IEEE

1394a-2000 and 1394-1995 Standards for

High-Performance Serial Bus

Interface to Link-Layer Controller Supports

Low-Cost Texas Instruments Bus-Holder

Isolation

Fully Interoperable With Firewire,

DTVLink, SB1394, DishWire, and i.LINK

Implementation of IEEE Std 1394

D

Interoperable With Link-Layer Controllers

Using 3.3-V Supplies

Provides Three Fully Backward

Compatible, (1394a-2000 Fully Compliant)

Bilingual 1394b Cable Ports at

Interoperable With Other 1394 Physical

Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V

Supplies

400 Megabits per Second (Mbps)

D

Same Three Fully Backward Compatible

Ports Are 1394a-2000 Fully Compliant

Cable Ports at 100/200/400 Mbps

D

Low-Cost 49.152-MHz Crystal Provides

Transmit and Receive Data at

100/200/400 Mbps and Link-Layer

Controller Clock at 49.152 MHz and

98.304 MHz

Full 1394a-2000 Support Includes:

− Connection Debounce

− Arbitrated Short Reset

− Multispeed Concatenation

− Arbitration Acceleration

− Fly-By Concatenation

− Port Disable/Suspend/Resume

− Extended Resume Signaling for

Compatibility With Legacy DV Devices

D

Separate Bias (TPBIAS) for Each Port

Low-Cost, High-Performance, 80-Pin TQFP

(PFP) Thermally Enhanced Package

D

Software Device Reset (SWR)

D

Fail-Safe Circuitry Senses Sudden Loss of

Power to the Device and Disables the Ports

to Ensure That the TSB41BA3B-EP Does

Not Load the TPBIAS of Any Connected

Device and Blocks Any Leakage From the

Port Back to Power Plane

D

Power-Down Features to Conserve Energy

in Battery Powered Applications

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D

1394a-2000-Compliant Common-Mode

Noise Filter on the Incoming Bias Detect

Circuit to Filter Out Cross-Talk Noise

Cable/Transceiver Hardware Speed and

Port Mode Are Selectable by Pin States

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited.

i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation.

FireWire is a trademark of Apple Computer, Inc. PowerPAD is a trademark of Texas Instruments.

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Copyright  2006, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ ꢁ ꢂꢃ ꢄꢂ ꢅ ꢆꢂ ꢇꢈ ꢉ

ꢊ ꢈꢈ ꢈ ꢄ ꢆꢋ ꢃ ꢌ ꢀ ꢍ ꢎ ꢈꢈ ꢇꢉ ꢏꢎ ꢀ ꢐꢅ ꢂꢑ ꢈ ꢀꢎ ꢅꢒꢁ ꢐꢈꢊ ꢓꢈꢎꢔ ꢅꢎꢂ ꢊꢀ ꢈꢎ

SGLS362—MAY 2006

D

Supports Connection to CAT5 Cable

Transceiver by Allowing Ports to be Forced

to Beta-Only S100 Mbps

description/ordering information

The TSB41BA3B-EP provides the digital and

analog transceiver functions needed to imple-

ment a three-port node in a cable-based IEEE

1394 network. Each cable port incorporates two

differential line transceivers. The transceivers

include circuitry to monitor the line conditions as

needed for determining connection status, for

initialization and arbitration, and for packet

reception and transmission. The TSB41BA3B-EP

interfaces with a link-layer controller (LLC), such

as the TSB82AA2, TSB12LV21, TSB12LV26,

Supports Connection to S200 Plastic

Optical Fiber Transceivers by Allowing

Ports to be Forced to 1394b Beta-Only S200

Mbps and Beta-Only S100 Mbps

D

Optical Signal Detect Input for All Ports in

Beta Mode Enables Connection to Optical

Transceivers

Supports Use of 1394a Connectors by

Allowing Ports 1 and 2 to Be Forced to

1394a-Only Mode

TSB12LV32,

TSB42AA4,

TSB42AB4,

TSB12LV01B, or TSB12LV01C. It can also be

connected via cable port to an integrated 1394

Link + PHY layer such as the TSB43AB2.

The TSB41BA3B-EP is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal

voltage regulator to the PLLVDD-CORE and DVDD-CORE terminals. To protect the phase-locked loop (PLL)

from noise, the PLLVDD-CORE terminals must be separately decoupled from the DVDD-CORE terminals. The

PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors and the DVDD-CORE

terminals are separately decoupled with 1-µF and smaller decoupling capacitors. The separation between

DVDD-CORE and PLLVDD-CORE must be implemented by separate power supply rails or planes.

The TSB41BA3B-EP may be powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The

core voltage supply to the PLLVDD-CORE and DVDD-CORE terminals must meet the requirements in the

recommended operating conditions section of this data sheet. The PLLVDD-CORE terminals must be

separated from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1-µF and smaller

decoupling capacitors, and the DVDD-CORE terminals separately decoupled with 1-µF and smaller decoupling

capacitors. The separation between DVDD-CORE and PLLVDD-CORE can be implemented by separate power

supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by

a filter network to keep noise from the PLLVDD-CORE supply.

The TSB41BA3B-EP requires an external 49.152-MHz crystal to generate a reference clock. The external clock

drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal

provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock

signal is supplied by the PHY to the associated LLC for synchronization of the two devices and is used for

resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE

1394a-2000 standard. A 98.304-MHz clock signal is supplied by the PHY to the associated LLC for

synchronization of the two devices when operating the PHY-link interface in compliance with the

IEEE 1394b-2002 standard. The power down (PD) function, when enabled by asserting the PD terminal high,

stops operation of the PLL.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

T

A

PACKAGE

−40°C to 110°C

HTQFP − PFP

TSB41BA3BTPFPEP TSB41B3BTEP

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SGLS362—MAY 2006

description (continued)

Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths

(depending on the requested transmission speed and PHY-link interface mode of operation). They are latched

internally, combined serially, encoded, and transmitted at 98.304, 122.78, 196.608, 245.76, 393.216, or

491.52 Mbps (referred to as S100, S100B, S200, S200B, S400, or S400B speed, respectively) as the outbound

information stream.

The PHY-link interface can follow either the IEEE 1394a-2000 protocol or the IEEE 1394b-2002 protocol. When

using a 1394a-2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link

interface then operates in accordance with the legacy 1394a-2000 standard. When using a 1394b LLC such

as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the

1394b-2002 standard.

The cable interface can follow either the IEEE 1394a-2000 protocol or the 1394b protocol on all ports. The mode

of operation is determined by the interface capabilities of the ports being connected. When any of the three ports

is connected to a 1394a-2000-compliant device, the cable interface on that port operates in the 1394a-2000

data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a

1394b-compliant node, the cable interface on that port operates per the 1394b-2002 standard at S100B, S200B,

or S400B speed. The TSB41BA3B-EP automatically determines the correct cable interface connection method

for the bilingual ports.

NOTE:

The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal

selects the PHY-link interface mode of operation and affects the arbitration modes on the cable.

When the BMODE terminal is deasserted, the PHY-link interface is placed in 1394a-2000 mode and

BOSS arbitration is disabled. When the BMODE terminal is asserted, the PHY-link interface is

placed in 1394b-2002 mode and BOSS arbitration is enabled.

During packet reception, the serial data bits are split into 2-, 4-, or 8-bit parallel streams (depending on the

indicated receive speed and the PHY-link interface mode of operation), resynchronized to the local system

clock, and sent to the associated LLC. The received data is also transmitted (repeated) on the other connected

and active cable ports.

Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators

to monitor the line states during initialization and arbitration when connected to a 1394a-2000-compliant device.

The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA

channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used

during 1394a-mode arbitration and sets the speed of the next packet transmission. In addition, the TPB channel

monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied

twisted pair bias (TPBIAS) voltage.

When connected to a 1394a-2000-compliant node, the TSB41BA3B-EP provides a 1.86-V nominal bias voltage

at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits (one for each

port). This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active

connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF.

The line drivers in the TSB41BA3B-EP are designed to work with external 112-Ω termination resistor networks

in order to match the 110-Ω cable impedance. One termination network is required at each end of a twisted-pair

cable. Each network is composed of a pair of series-connected ~56-Ω resistors. The midpoint of the pair of

resistors that is connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal. The

midpoint of the pair of resistors that is directly connected to the TPB terminals is coupled to ground through a

parallel RC network with recommended values of 5 kΩ and 270 pF. The values of the external line-termination

resistors are designed to meet the standard specifications when connected in parallel with the internal receiver

circuits. A precision external resistor connected between the R0 and R1 terminals sets the driver output current,

along with other internal operating currents.

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SGLS362—MAY 2006

description (continued)

When the power supply of the TSB41BA3B-EP is off while the twisted-pair cables are connected, the

TSB41BA3B-EP transmitter and receiver circuitry present a high-impedance signal to the cable that does not

load the device at the other end of the cable.

When the TSB41BA3B-EP is used without one or more of the ports brought out to a connector, the twisted-pair

terminals of the unused ports must be terminated for reliable operation. For each unused port, the preferred

method is for the port to be forced to the 1394a-only mode (data-strobe-only mode, DS), then the TPB+ and

TPB– terminals can be tied together and then pulled to ground; or the TPB+ and TPB– terminals can be

connected to the suggested normal termination network. The TPA+ and TPA– terminals of an unused port can

be left unconnected. The TPBIAS_SD terminal can be left unconnected.

If the port is left in bilingual (Bi) mode, then the TPB+ and TPB– terminals can be left unconnected or the TPB+

and TPB– terminals can be connected to the suggested normal termination network. The TPA+ and TPA–

terminals of an unused port can be left unconnected. The TPBIAS_SD terminal can be left unconnected.

If the port is left in a forced 1394b Beta-only (B1, B2, or B4) mode, then the TPB+ and TPB– terminals can be

left unconnected or the TPB+ and TPB– terminals can be connected to the suggested normal termination

network. The TPA+ and TPA– terminals of an unused port can be left unconnected. The TPBIAS_SD terminal

must be pulled to ground through a 1.2-kΩ or less resistor.

To operate a port as a 1394b bilingual port, the speed/mode selections terminals (S5_LKON, S4, S3, S2_PC0,

S1_PC1, and S0_PC2) need to be pulled to VCC or ground through a 1-kΩ resistor. The port must be operated

in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b Beta-only connector is connected to the

port. To operate the port as a 1394a-only port, the speed/mode selection terminals must be configured correctly

to force 1394a-2000-only operation on that port. The only time the port must be forced to the data-strobe-only

mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode

is provided to ensure that 1394b signaling is never sent across a 1394a cable.

NOTE:

A bilingual port can only connect to a 1394b-only port that operates at S400b. It can not establish

a connection to a S200b or S100b port. A port that has been forced to S400b (B4) can connect to

a 1394b-only port at S400b (B4) or S200b (B2) or S100b (B1). A port that has been forced to S200b

can connect to a 1394b-only port at S200b or S100b. A port that has been forced to S100b can only

connect to a 1394b-only port at S100b.

The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal

operation, the TESTM terminal must be connected to V

must be tied to ground through a 1-kΩ resistor.

through a 1-kΩ resistor. The SE and SM terminals

DD

Three package terminals are used as inputs to set the default value for three configuration status bits in the

self-ID packet. They can be pulled high through a 1-kΩ resistor or hardwired low as a function of the equipment

design. In some speed/mode selections the S2_PC0, S1_PC1, and S0_PC2 terminals indicate the default

power class status for the node (the need for power from the cable or the ability to supply power to the cable);

see Table 1. The contender bit in the PHY register set indicates that the node is a contender either for the

isochronous resource manager (IRM) or for the bus manager (BM). On the TSB41BA3B-EP, this bit can only

be set by a write to the PHY register set. If a node is a contender for IRM or BM, then the node software must

set this bit in the PHY register set.

The LPS (link power status) terminal works with the S5_LKON terminal to manage the power usage in the node.

The LPS signal from the LLC is used with the LCtrl bit (see Table 2 and Table 3 in the application information

section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the

PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the

state of the LCtrl bit).

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ ꢁꢂꢃ ꢄ ꢂ ꢅꢆ ꢂꢇ ꢈꢉ

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SGLS362—MAY 2006

description (continued)

NOTE:

The TSB41BA3B-EP does not have a cable-not-active (CNA) pin. To achieve a similar function, the

individual PHY ports can be set up to issue interrupts whenever the port changes state. If the LPS

pin is low, then this generates a link-on (LKON) output clock. Please see register bits PIE, PEI, and

WDIE along with the individual interrupt bits.

The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal

definition) and is considered active otherwise. When the TSB41BA3B-EP detects that the LPS input is inactive,

the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the

logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains

low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put

into a low-power disabled state in which the PCLK output is also held inactive. The TSB41BA3B-EP continues

the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC

interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the

PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled

state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having

entered the LPS_DISABLE time, the TSB41BA3B-EP issues a bus reset. This broadcasts the node self-ID

packet, which contains the updated L bit state (the PHY LLC now being accessible).

The PHY uses the S5_LKON terminal to notify the LLC to power up and become active. When activated, the

output S5_LKON signal is a square wave. The PHY activates the S5_LKON output when the LLC is inactive

and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described

above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet addressed to this node

is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the S5_LKON output when the

LLC becomes active (both LPS sensed as active and the LCtrl bit set to 1). The PHY also deasserts the

S5_LKON output when a bus reset occurs, unless a PHY interrupt condition exists which would otherwise cause

S5_LKON to be active. If the PHY is power-cycled and the power class is 0 through 4, then the PHY asserts

S5_LKON for approximately 167 µs or until both the LPS is active and the LCtrl bit is 1.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SGLS362—MAY 2006

pin assignments

PFP PACKAGE

(TOP VIEW)

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

40

AGND

AVDD

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

AVDD

DGND

DVDD-CORE

SM

SE

CPS

DVDD-CORE

S2_PC0

S1_PC1

S0_PC2

DVDD-3.3

DVDD-CORE

DGND

S3

S4

PLLVDD-3.3

PLLVDD-CORE

PLLGND

XI

XO

PLLGND

AVDD

TSB41BA3B-EP

VREG_PD

BMODE

RESET

DGND

PD

TESTM

R0

R1

AGND

SLPEN

LPS

1

2

3

4

5

6

7 8 9 10 11 12 13 14 15 16 17 18 19 20

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢊ ꢈ ꢈꢈ ꢄ ꢆ ꢋ ꢃ ꢌ ꢀ ꢍꢎꢈꢈ ꢇꢉꢏ ꢎꢀ ꢐꢅꢂ ꢑꢈ ꢀ ꢎꢅꢒꢁ ꢐꢈꢊ ꢓꢈꢎꢔ ꢅ ꢎꢂ ꢊ ꢀꢈ ꢎ

SGLS362—MAY 2006

functional block diagram

R0

CPS

LPS

Bias Voltage

and

Current

R1

Received Data

Decoder/Retimer

TPBIAS0_SD0

TPBIAS1_SD1

TPBIAS2_SD2

SLPEN

PINT

Generator

PCLK

LCLK_PMC

LREQ

Link

CTL0

Interface

TPA0+

TPA0−

CTL1

I/O

D0

D1

D2

D3

D4

D5

D6

D7

Cable Port 0

TPB0+

TPB0−

Arbitration

and Control

State Machine

Logic

RESET

S5_LKON

BMODE

PD

TPA1+

TPA1−

S2_PC0

S1_PC1

S0_PC2

SE

Cable Port 1

Cable Port 2

TPB1+

TPB1−

SM

TPA2+

TPA2−

S3

S4

TESTM

TPB2+

TPB2−

XO

XI

Crystal Oscillator,

PLL System,

and Transmit

Clock Generator

Transmit

Data

Encoder

Voltage

Regulator

VREG_PD

7

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SGLS362—MAY 2006

Terminal Functions

TERMINAL

TYPE

I/O

−

DESCRIPTION

NAME

AGND

PFP

NO.

Supply 21, 40, 43,

50, 61, 62

Analog circuit ground terminals. These terminals must be tied together to the low-impedance

circuit board ground plane.

AVDD

Supply 24, 39, 44,

51, 57, 63

−

Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each

terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering

capacitors are also recommended. These supply terminals are separated from the

PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and DVDD-3.3 terminals internal to the device to

provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together

with a low dc impedance connection on the circuit board.

BMODE

CMOS

74

34

I

Beta-mode input. This terminal determines the PHY-link interface connection protocol. When

logic high (asserted), the PHY-link interface complies with the 1394b-2002 B PHY-link interface.

When logic low (deasserted), the PHY-link interface complies with the legacy 1394a-2000

standard. When using an LLC such as the 1394b-2002 TSB82AA2, this terminal must be pulled

high. When using an LLC such as the 1394a-2000 TSB12LV26, this terminal must be tied low.

NOTE: The PHY-link interface cannot be changed between the different protocols during

operation.

CPS

CMOS

Cable power status input. This terminal is normally connected to cable power through a 400-kΩ

resistor. This circuit drives an internal comparator that detects the presence of cable power. This

transition from cable power sensed to cable power not sensed can be used to generate an

interrupt to the LLC.

CTL0

CTL1

9

10

I/O Control I/Os. These bidirectional signals control communication between the TSB41BA3B-EP

and the LLC. Bus holders are built into these terminals.

D0−D7

CMOS 11, 12, 13, I/O Data I/Os. These are bidirectional data signals between the TSB82BA3 and the LLC. Bus holders

15, 16, 17,

19, 20

are built into these terminals.

If power management control (PMC) is selected using LCLK_PMC, then some of these terminals

can be used for PMC. See the LCLK_PMC terminal description for more information.

DGND

Supply 4, 14, 38,

64, 72, 76

Digital circuit ground terminals. These terminals must be tied together to the low-impedance

circuit board ground plane.

DVDD-CORE Supply 8, 37, 65,

71

−

Digital core circuit power terminals. A combination of high-frequency decoupling capacitors near

each terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. An additional 1-µF capacitor

is required for voltage regulation. These supply terminals are separated from the DVDD-3.3,

PLLVDD-CORE, PLLVDD-3.3, and AVDD terminals internal to the device to provide noise

isolation.

DVDD-3.3

Supply 6, 18, 69,

70

Digital 3.3-V circuit power terminals. A combination of high-frequency decoupling capacitors near

each terminal is suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF

filtering capacitors are also recommended. The DVDD-3.3 terminals must be tied together at a

low-impedance point on the circuit board. These supply terminals are separated from the

PLLVDD-CORE, PLLVDD-3.3, DVDD-CORE, and AVDD terminals internal to the device to

provide noise isolation. The PLLVDD-3.3, AVDD, and DVDD-3.3 terminals must be tied together

with a low dc impedance connection on the circuit board.

8

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SGLS362—MAY 2006

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

TYPE PFP

NO.

LCLK_PMC

CMOS

7

I

Link clock. Link-provided 98.304-MHz clock signal to synchronize data transfers from link to the PHY.

On hardware reset this terminal is sampled to determine the power management control (PMC)

mode.

LCLK_PMC

H

n/c†

LCLK_PMC‡

LPS

L

lps

BMODE

Mode

H

L

H

No LLC (PMC mode)

Legacy LLC

Beta LLC

†

‡

internal pulldown on LCLK_PMC

LCLK_PMC from LLC normally low during reset

In PMC mode, because no LLC is attached, the data lines (D7−D0) are available to indicate

power states. In PMC mode, the following signals are output:

− D0—port 0 cable-power disable (see Note 1)

−

D1—port 1 cable-power disable (port in sleep or disabled)

D2—port 2 cable-power disable (port in sleep or disabled)

D6—All ports cable-power disable (all ports in sleep/disable) logical AND of bits 0−2

D3−D5 and D7 are reserved for future use.

Note 1: The cable-power disable is asserted when the port is either:

−

Hard-disabled (both the disabled and hard-disabled bits are set)

Sleep-disabled (both the disabled and sleep_enable bits are set)

Disconnected

Asleep

Connected in DS mode, but nonactive (that is, suspended or disabled)

Otherwise, the cable-powered disable output is deasserted (that is, cable power enabled) when

the port is dc-connected or active. A bus holder is built into this terminal.

LPS

CMOS

80

I

Link power status input. This terminal monitors the active/power status of the link-layer controller

(LLC) and controls the state of the PHY-LLC interface. This terminal must be connected to either the

V

DD

supplying the LLC through an approximately 1-kΩ resistor or to a pulsed output which is active

when the LLC is powered. A pulsed signal must be used when an isolation barrier exists between the

LLC and PHY (see Figure 8).

The LPS input is considered inactive if it is sampled low by the PHY for more than a LPS_RESET time

(~2.6µs) and is considered active otherwise (that is, asserted steady high or an oscillating signal with

a low time less than 2.6 µs). The LPS input must be high for at least 22 ns to be observed as high by

the PHY.

When the TSB41BA3B-EP detects that the LPS input is inactive, it places the PHY-LLC interface into

a low-power reset state. In the reset state, the CTL (CTL0 and CTL1) and D (D0 to D7) outputs are

held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If

the LPS input remains low for more than a LPS_DISABLE time (~26 µs), then the PHY-LLC interface

is put into a low-power disabled state in which the PCLK output is also held inactive.

The LLC state that is communicated in the self-ID packet is considered active only if both the LPS

input is active and the LCtrl register bit is set to 1. The LLC state that is communicated in the self-ID

packet is considered inactive if either the LPS input is inactive or the LCtrl register bit is cleared to 0.

LREQ

PCLK

CMOS

3

5

I

LLC request input. The LLC uses this input to initiate a service request to the TSB41BA3B-EP. A bus

holder is built into this terminal.

O

PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the LLC when

the PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK output provides a

49.152-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is

in legacy 1394a-2000 (BMODE input deasserted).

9

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SGLS362—MAY 2006

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

TYPE

PFP

NO.

PD

CMOS

77

I

Power-down input. A high on this terminal turns off all internal circuitry. Asserting the PD input high

also activates an internal pulldown on the RESET terminal to force a reset of the internal control

logic.

PINT

CMOS

Supply

1

O

−

PHY Interrupt. The PHY uses this output to serially transfer status and interrupt information to the

link when PHY-link interface is in the 1394b mode. A bus holder is built into this terminal.

PLLGND

25,

28

PLL circuit ground terminals. These terminals must be tied together to the low-impedance circuit

board ground plane.

PLLVDD-CORE Supply

29,

30

−

PLL core circuit power terminals. A combination of high-frequency decoupling capacitors near each

terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. An additional 1-µF capacitor is

required for voltage regulation. The PLLVDD-CORE terminals must be separate from the

DVDD-CORE terminals. These supply terminals are separated from the DVDD-CORE, DVDD-3.3,

PLLVDD-3.3, and AVDD-3.3 terminals internal to the device to provide noise isolation.

PLLVDD-3.3

Supply

31

75

−

PLL 3.3-V circuit power terminal. A combination of high-frequency decoupling capacitors near the

terminal are suggested, such as paralleled 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering

capacitors are also recommended. This supply terminal is separated from the DVDD-CORE,

DVDD-3.3, PLLVDD-CORE, and AVDD-3.3 terminals internal to the device to provide noise

isolation. The DVDD-3.3 terminals must be tied together at a low-impedance point on the circuit

board. The PLLVDD-3.3, AVDD-3.3, and DVDD-3.3 terminals must be tied together with a low dc

impedance connection.

RESET

CMOS

Bias

I

Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to

V

DD

is provided so only an external delay capacitor is required for proper power-up operation (see

power-up reset in the application information section). The RESET terminal also incorporates an

internal pulldown which is activated when the PD input is asserted high. This input is otherwise a

standard logic input and can also be driven by an open-drain-type driver.

R0

R1

23

22

−

Current setting resistor terminals. These terminals are connected to a precision external resistance

to set the internal operating currents and cable driver output currents. A resistance of 6.34 kΩ 1% is

required to meet the IEEE Std 1394-1995 output voltage limits.

SE

CMOS

35

79

36

I

Test control input. This input is used in the manufacturing test of the TSB41BA3B-EP. For normal

use, this terminal must be pulled low either through a 1-kΩ resistor to GND or directly to GND.

SLPEN

SM

Automotive sleep mode enable input. This terminal enables the automotive sleep mode. When

deasserted (logic low), normal 1394.b functionality is maintained.

Test control input. This input is used in the manufacturing test of the TSB41BA3B-EP. For normal

use this terminal must be pulled low either through a 1-kΩ resistor to GND or directly to GND.

S2_PC0

S1_PC1

S0_PC2

66

67

68

Port sleep/mode selection terminals 2−0 and power-class programming. On hardware reset, this

terminal when used with the other five selection pins allows the user to select the speed and mode of

the ports. See Table 1. Depending on the selection, these inputs may set the default value of the

power class indicated during self-ID.

Programming is done by tying the terminals high through a 1-kΩ or smaller resistor or by tying

directly to ground through a 1-kΩ or smaller resistor. Bus holders are built into these terminals.

10

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SGLS362—MAY 2006

Terminal Functions (Continued)

TERMINAL

NAME TYPE

I/O

DESCRIPTION

PFP

NO.

S3

S4

CMOS

33

32

2

I

Port sleep/mode selection terminal 3. On hardware reset, this terminal when used with the other five

selection pins allows the user to select the speed and mode of the ports. See Table 1. Programming

is done by tying the terminals high through a 1-kΩ or smaller resistor or by tying directly to ground

through a 1-kΩ or smaller resistor. A bus holder is built into this terminal.

I

Port sleep/mode selection terminal 4. On hardware reset, this terminal when used with the other five

selection pins allows the user to select the speed and mode of the ports. See Table 1. Programming

is done by tying the terminals high through a 1-kΩ or smaller resistor or by tying directly to ground

through a 1-kΩ or smaller resistor. A bus holder is built into this terminal.

S5_LKON

I/O

Port sleep/mode selection terminal 5 and link-on output. This terminal can be connected to the link-

on input terminal of the LLC through a 1-kΩ resistor if the link-on input is available on the link layer.

On hardware reset, this terminal when used with the other five selection pins allows the user to se-

lect the speed and mode of the ports. See Table 1. A bus holder is built into this terminal.

After hardware reset, this terminal is the link-on output, which notifies the LLC or other power-up

logic to power up and become active. The link-on output is a square wave signal with a period of

approximately 163 ns (8 PCLK cycles) when active. The link-on output is otherwise driven low,

except during hardware reset when it is high impedance.

The link-on output is activated if the LLC is inactive (the LPS input inactive or the LCtrl bit cleared)

and when one of the following occrurs:

a) The PHY receives a link-on PHY packet addressed to this node

b) The PEI (port-event interrupt) register bit is 1, or

c) Any of the CTOI (configuration-time-out interrupt), CPSI (cable-power-status interrupt), or

d) The PHY is power-cycled and the power class is 0 through 4

Once activated, the link-on output is active until the LLC becomes active (both the LPS input active

and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset occurs unless the

link-on output is otherwise active because one of the interrupt bits is set (that is, the link-on output is

active due solely to the reception of a link-on PHY packet).

In the case of power-cycling the PHY, the LKON signal must stop after 167 µs if the above conditions

have not been met.

NOTE: If an interrupt condition exists which otherwise causes the link-on output to be activated if

the LLC were inactive, then the link-on output is activated when the LLC subsequently becomes

inactive.

TESTM

CMOS

Cable

78

I

Test control input. This input is used in the manufacturing test of the TSB41BA3B-EP. For normal

use, this terminal must be pulled high through a 1-kΩ resistor to V

.

DD

TPA0−

TPA0+

TPB0−

TPB0+

45,

46,

41,

42

I/O

Port 0 twisted-pair differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals must be kept matched and as short as possible to the

external load resistors and to the cable connector. Request the S800 1394b layout

recommendations document from your Texas Instruments representative.

TPA1−

TPA1+

TPB1−

TPB1+

Cable

52

53

48

49

I/O

Port 1 twisted-pair differential-signal terminals. Board traces from each pair of positive and

negative differential signal terminals must be kept matched and as short as possible to the

external load resistors and to the cable connector. Request the S800 1394b layout

recommendations document from your Texas Instruments representative.

11

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SGLS362—MAY 2006

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

TYPE

PFP

NO.

TPA2−

TPA2+

TPB2−

TPB2+

Cable

58

59

55

56

I/O

Port 2 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative

differential signal terminals must be kept matched and as short as possible to the external load

resistors and to the cable connector. Request the S800 1394b layout recommendations document

from your Texas Instruments representative.

TPBIAS0_SD0

TPBIAS1_SD1

TPBIAS2_SD2

Cable

In

47

54

60

I/O

Twisted-pair bias output and signal detect input. This provides the 1.86-V nominal bias voltage

needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the

remote nodes that there is an active cable connection in 1394a-2000 mode. Each of these

terminals, except for an unused port, must be decoupled with a 1-µF capacitor to ground. For the

unused port, this terminal can be left unconnected.

When a port is configured as a Beta-mode port (B1, B2, B4) this terminal becomes an input and

must be high when a valid signal is present. For optical transceivers, the signal detect of the

transceiver must be connected to this terminal. The input is an LVCMOS level input.

VREG_PD

CMOS

Crystal

73

I

Voltage regulator power-down input. When asserted logic high, this pin powers down the

internal 3.3-V-to-1.8-V regulator. For single-supply (3.3-V only) operation, this pin must be tied

to GND.

XI

XO

27

26

I

O

Crystal oscillator inputs. These terminals connect to a 49.152-MHz parallel resonant fundamental

mode crystal. The optimum values for the external shunt capacitors depend on the specifications of

the crystal used (see the crystal selection section in the document SLLS418). XI is a 1.8-V CMOS

input.

12

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SGLS362—MAY 2006

Table 1. Port Speed/Mode Selection

INPUT SELECTION

RESULTING PORT, POWER CLASS, AND SELF-ID

MODE

NO.

S5_LINK

ON

S2_

S1_

PC1

S0_

PC2

PORT 2 PORT 1 PORT 0

S4

S3

POWER CLASS

SELF-ID

†

PC0

1

2

3

4

5

6

7

8

0

1

0

1

0

1

PC0

0

PC1

0

PC2

0

Bi

T

S

Bi

T

S

T

Bi

T

S

T

PC = (PC0, PC1, PC2)

PC = 000

1394b

1394a

DS

B1

B2

B4

B2

B1

DS

B1

B2

B4

Bi

B1

B2

B4

0

1

PC = 000

0

1

0

PC = 000

0

1

PC = 100

1

0

DS

PC = 100

‡

S100

9

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

DS

B2

B1

B2

B4

B1

Bi

T

S

T

S

T

S

DS

Bi

T

B2

B4

B1

B2

B4

B2

B1

B2

B4

B1

B2

B4

B2

B1

B2

B4

S

PC = 100

1394b

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

1

PC = 100

1

PC = 100

PC0

PC = PC0,0,0 (100 or 000)

Bi

B1

DS

B1

B2

B4

B1

Bi

DS

†

LEGEND:

Bi = 1394b-2002 Bilingual (S400b only Beta operating speed and data strobe: S400, S200, and S100 operating speeds)

DS = 1394a-2000, data strobe-only, S400, S200, and S100 operating speeds

B1 = 1394b-2002 Beta-only, S100b operating speed

B2 = 1394b-2002 Beta-only, S200b and S100b operating speeds

B4 = 1394b-2002 Beta-only, S400b, S200b, and S100b operating speeds

S = TPBIAS_SD pin is in signal detect input mode

T = TPBIAS_SD pin is in TPBIAS output mode

‡

Mode 8 must only be used to do an S100 home network translation. It must not be used as a nominal end equation mode.

13

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SGLS362—MAY 2006

port mode/speed selection example connections

3.3 V

TSB41BA3B-EP

3.3 V

Signal Detect

S5

S4

TPBIAS0_SD0

Port 0

POF

S200

TPBIAS

1394b

9-Pin

Bilingual

S3

TPBIAS1_SD1

Port 1

PC0 (Don’t Care)

3.3 V

S2_PC0

TPBIAS

S1_PC1

S0_PC2

TPBIAS2_SD2

Port 2

1394a

6-Pin DS

Mode 21, Port/Speed Mode (1, 1, 0, PC0, 0, 1)

SD High

3.3 V

TSB41BA3B-EP

Signal

Detect

S5

S4

TPBIAS0_SD0

Port 0

RJ45

S100

TSB17BA1

Transformer

3.3 V

TPBIAS

S3

TPBIAS1_SD1

Port 1

1394a

6-Pin DS

PC0 (Don’t Care)

S2_PC0

Signal Detect

S1_PC1

S0_PC2

TPBIAS2_SD2

Port 2

POF

S100

Mode 24, Port/Speed Mode (1, 1, 1, PC0, 0, 0)

14

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SGLS362—MAY 2006

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V

DD

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

I

DD

Output voltage range at any output, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

O

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

Operating free-air temperature, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 110°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

A

Storage temperature range, T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground.

DISSIPATION RATING TABLE

‡

T

≤ 25°C

DERATING FACTOR

T

= 70°C

T = 110°C

A

POWER RATING

A

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING

A

§

PFP

5.05 W

52.5 mW/°C

31.7 mW/°C

20.3 mW/°C

2.69 W

587 mW

¶

PFP

3.05 W

1.62 W

355 mW

#

PFP

2.01 W

1.1 W

284 mW

‡

§

¶

#

This is the inverse of the traditional junction-to-ambient thermal resistance (R

2-oz. trace and copper pad with solder.

2-oz. trace and copper pad without solder.

For more information, see the Texas Instruments application report PowerPAD Thermally Enhanced Package,

).

θJA

(SLMA002).

15

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SGLS362—MAY 2006

recommended operating conditions

†

MIN TYP

MAX

3.6

2

UNIT

Source power node

Nonsource power node

3

‡

3.3

Supply voltage, 3.3 V

Supply voltage, 1.8 V

V

DD

3

1.75

2.6

1.85

DD

LREQ, CTL0, CTL1, D0−D7, LCLK_PMC

S5_LKON, S4, S3, S2_PC0, S1_PC1, S0_PC2,

SLPEN, PD, BMODE, TPBIAS0_SD0,

TPBIAS1_SD1, TPBIAS2_SD2

0.7 V

High-level input voltage, V

V

DD

IH

RESET

0.6 V

DD

LREQ, CTL0, CTL1, D0−D7, LCLK_PMC

1.2

S5_LKON, S4, S3, S2_PC0, S1_PC1, S0_PC2,

SLPEN, PD, BMODE, TPBIAS0_SD0,

TPBIAS1_SD1, TPBIAS2_SD2

0.2 V

Low-level input voltage, V

DD

IL

RESET

0.3 V

DD

4

Output current, I

CTL0, CTL1, D0−D7, S5_LKON, PINT, PCLK

TPBIAS outputs

−4

mA

OL/OH

−5.6

1.3

O

Maximum junction temperature, T

J

(see R

values listed in thermal

R

= 19°C/W,

T

A

= 110°C

PFP

124.13

°C

θJA

characteristics table)

1394b differential input voltage, V

Cable inputs, during data reception

Cable inputs, during arbitration

200

118

800

260

mV

ID

1394a differential input voltage, V

ID

168

265

TPB cable inputs, source power node

TPB cable inputs, nonsource power node

RESET input

0.4706

2.515

1394a common-mode input voltage, V

IC

V

‡

2.015

§

2

Power-up reset time, t

pu

ms

TPA, TPB cable inputs, S100 operation

TPA, TPB cable inputs, S200 operation

TPA, TPB cable inputs, S400 operation

1.08

0.5

1394a receive input jitter

1394a receive input skew

ns

0.315

0.8

Between TPA and TPB cable inputs, S100 operation

Between TPA and TPB cable inputs, S200 operation

Between TPA and TPB cable inputs, S400 operation

0.55

0.5

†

All typical values are at V

DD

For a node that does not source power; see Section 4.2.2.2 in IEEE 1394a-2000.

Time after valid clock received at PHY XI input terminal.

= 3.3 V and T = 25°C.

A

‡

§

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SGLS362—MAY 2006

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)

driver

PARAMETER

TEST CONDITION

MIN TYP

MAX

265

UNIT

mV

mA

mV

V

1394a differential output voltage

56 Ω,

See Figure 1

172

OD

1394b differential output voltage

300

700

800

OD

†

1.05

I

Driver difference current, TPA+, TPA−, TPB+, TPB−

Drivers enabled, speed signaling off −1.05

DIFF

SP200

SP400

‡

−2.53

Common-mode speed signaling current, TPB+, TPB− S200 speed signaling enabled

Common-mode speed signaling current, TPB+, TPB− S400 speed signaling enabled

−4.84

‡

−12.4

−8.10

V

OFF

Off-state differential voltage

Drivers disabled,

See Figure 1

20

†

‡

Limits defined as algebraic sum of TPA+ and TPA− driver currents. Limits also apply to TPB+ and TPB− algebraic sum of driver currents.

Limits defined as absolute limit of each of TPB+ and TPB− driver currents.

receiver

PARAMETER

TEST CONDITION

Drivers disabled

MIN TYP

MAX

UNIT

kΩ

pF

4

7

Z

Differential impedance

ID

4

20

kΩ

pF

Common-mode impedance

Drivers disabled

IC

24

30

V

Receiver input threshold voltage

Drivers disabled

−30

0.6

mV

V

TH−R

Cable bias detect threshold, TPBx cable inputs

Positive arbitration comparator threshold voltage

Negative arbitration comparator threshold voltage

Speed signal threshold

1

TH−CB

+

−

89

168

−89

131

396

mV

TH

−168

49

TPBIAS−TPA common-mode

voltage, drivers disabled

TH−SP200

TH−SP400

Speed signal threshold

314

device

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

mA

V

I

Supply current 3.3 V

See Note 2

75

DD

†

V

TH

Power status threshold, CPS input

400-kΩ resistor

4.7

2.8

7.5

High-level output voltage, CTL0, CTL1, D0−D7, PCLK,

S5_LKON outputs

V

I

= 3 to 3.6 V,

DD

= −4 mA

OH

V

OH

V

Low-level output voltage, CTL0, CTL1, D0−D7, PCLK,

S5_LKON outputs

V

I

= 4 mA

OL

0.4

1

OL

BH+

BH−

V

= 3.6 V,

DD

V = 0 V to V

I

Positive peak bus holder current, D0−D7, CTL0−CTL1, LREQ

Negative peak bus holder current, D0−D7, CTL0−CTL1, LREQ

0.05

−1

mA

I

DD

V

= 3.6 V,

DD

V = 0 V to V

−0.05

I

DD

I

Off-state output current, CTL0, CTL1, D0−D7, S5_LKON I/Os

Pullup current, RESET input

V

= V

or 0 V

30

−20

µA

V

OZ

O DD

V = 1.5 V or 0 V

I

−90

IRST

V

TPBIAS output voltage

At rated I current

1.665

2.015

O

†

Measured at cable power side of resistor.

NOTE 2: Repeat Max Packet (1 port receiving maximum size isochronous packet—4096 bytes, sent on every isochronous interval, data value

of 0x00FF00FFh; 2 ports repeating; all ports with S400 Beta-mode connection), V

= 3.3 V, internal regulator, T = 25_C.

DD3.3

A

17

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SGLS362—MAY 2006

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)

(continued)

thermal characteristics

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Board mounted, No air flow, High conductivity Texas

Instruments recommended test board, chip soldered or

greased to thermal land with 2-oz. copper

R

Junction-to-free air thermal resistance

19.04

°C/W

θJA

θJC

Junction-to-case thermal resistance

Junction-to-free air thermal resistance

0.17

°C/W

Board mounted, No air flow, High conductivity Texas

Instruments recommended test board with thermal land

but no solder or grease thermal connection to thermal

land with 2-oz. copper

R

31.52

θJA

θJC

Junction-to-case thermal resistance

0.17

°C/W

R

Junction-to-free air thermal resistance

Junction-to-case thermal resistance

49.17

3.11

°C/W

θJA

θJC

Board mounted, No air flow, High conductivity JEDEC

test board with 1-oz. copper

switching characteristics

PARAMETER

TP differential rise time, transmit

TP differential fall time, transmit

TEST CONDITION

MIN

0.3

2.5

TYP

MAX

0.8

UNIT

ns

t

10% to 90%, At 1394 connector

90% to 10%, At 1394 connector

r

0.8

ns

f

Setup time, CTL0, CTL1, D1−D7, LREQ to 1394a-2000 50% to 50%, See Figure 2

PCLK

ns

su

t

Hold time, CTL0, CTL1, D1−D7, LREQ

after PCLK

1394a-2000 50% to 50%, See Figure 2

0

2.5

0

ns

h

Setup time, CTL0, CTL1, D1−D7, LREQ to 1394b

LCLK_PMC

50% to 50%, See Figure 2

su

h

Hold time, CTL0, CTL1, D1−D7, LREQ

after LCLK_PMC

1394b

Delay time, PCLK to CTL0, CTL1, D1−D7, 1394a-2000 50% to 50%, See Figure 3

PINT

0.5

7

d

and 1394b

PARAMETER MEASUREMENT INFORMATION

TPAx+

TPBx+

56 Ω

TPAx–

TPBx–

Figure 1. Test Load Diagram

18

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SGLS362—MAY 2006

PARAMETER MEASUREMENT INFORMATION

xCLK

t

h

su

D, CTL, LREQ

Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms

xCLK

t

d

D, CTL

Figure 3. Dx and CTLx Output Delay Relative to xCLK Waveforms

APPLICATION INFORMATION

Obtain from the Texas Instruments Web site or your local Texas Instruments representative the reference

schematics, reference layouts, debug documents, and software recommendations for the TSB41BA3B-EP.

internal register configuration

The TSB41BA3B-EP has 16 accessible internal registers. The configuration of the registers at addresses 0h

through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh

(the paged registers) depends on which one of eight pages, numbered 0h through 7h, is currently selected. The

selected page is set in base register 7h. Note that while this register set is compatible with 1394a-2000 register

sets, some fields have been redefined, and this register set contains additional fields.

Table 2 shows the configuration of the base registers, and Table 3 gives the corresponding field descriptions.

The base register field definitions are unaffected by the selected page number.

A reserved register or register field (marked as Reserved or Rsvd in the following register configuration tables)

is read as 0, but is subject to future usage. All registers in address pages 2 through 6 are reserved.

19

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SGLS362—MAY 2006

APPLICATION INFORMATION

Table 2. Base Register Configuration

BIT POSITION

Address

0

1

2

3

4

5

6

7

0000

0001

0010

0011

0100

0101

0110

0111

Physical ID

R

CPS

RHB

IBR

Gap_Count

Num_Ports (0011b)

Delay (1111b)

Extended (111b)

PHY_Speed (111b)

C

SREN

Jitter (000b)

CPSI

LCtrl

Pwr_Class

EAA

WDIE

ISBR

CTOI

STOI

PEI

EMC

Max Legacy SPD

Page_Select

BLINK

Bridge

Rsvd

Port_Select

Table 3. Base Register Field Descriptions

FIELD

SIZE TYPE

DESCRIPTION

Physical ID

6

Rd

This field contains the physical address ID of this node determined during self-ID. The physical-ID is invalid after

a bus reset until the self-ID has completed as indicated by an unsolicited register 0 status transfer from the PHY

to the LLC.

R

1

Rd

Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to 1 during

tree-ID if this node becomes root.

CPS

Cable-power status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied to

serial bus cable power through a 400-kΩ resistor. A 0 in this bit indicates that the cable power voltage has

dropped below its threshold for ensured reliable operation.

RHB

IBR

1

Rd/Wr Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB is reset to

0 by a hardware reset and is unaffected by a bus reset. If two nodes on a single bus have their root holdoff bit set,

then the result is not defined. To prevent two nodes from having their root-holdoff bit set, this bit must only be

written using a PHY configuration packet.

Rd/Wr Initiate bus reset. This bit instructs the PHY to initiate a long (166 µs) bus reset at the next opportunity. Any

receive or transmit operation in progress when this bit is set completes before the bus reset is initiated. The IBR

bit is reset to 0 after a hardware reset or a bus reset. Care must be exercised when writing to this bit to not change

the other bits in this register. It is recommended that whenever possible a bus reset be initiated using the ISBR bit

and not the IBR bit.

Gap_Count

6

Rd/Wr Arbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap count

can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet. The gap

count is reset to 3Fh by hardware reset or after two consecutive bus resets without an intervening write to the gap

count register (either by a write to the PHY register or by a PHY_CONFIG packet). It is strongly recommended

that this field only be changed using PHY configuration packets.

Extended

Num_Ports

PHY_Speed

SREN

3

4

3

1

Rd

Extended register definition. For the TSB41BA3B-EP, this field is 111b, indicating that the extended register set

is implemented.

Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB41BA3B-EP, this

field is 3.

PHY speed capability. This field is no longer used. For the TSB41BA3B-EP PHY, this field is 111b. Speeds for

1394b PHYs must be checked on a port-by-port basis.

Rd/Wr Standby/restore enable. This bit when set to 1 enables the port to go into the standby reduced power state when

commanded by a Standby PHY command packet. This enable works for all ports of the local device. Note the

1394b standard only allows leaf (one port connected) nodes to be placed into standby mode.

Delay

4

Rd

PHY repeater data delay. This field indicates the worst-case repeater data delay of the PHY, expressed as

144+(delay×20) ns. For the TSB41BA3B-EP, this field is Fh. The worst-case repeater delay for S100B is 538 ns.

20

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SGLS362—MAY 2006

APPLICATION INFORMATION

Table 3. Base Register Field Descriptions (Continued)

FIELD

LCtrl

SIZE TYPE

1

DESCRIPTION

Rd/Wr Link-active status control. This bit controls the indicated active status of the LLC reported in the self-ID packet.

The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The

LLC bit in the node self-ID packet is set active only if both the LPS input is active and the LCtrl bit is set.

The LCtrl bit provides a software-controllable means to indicate the LLC self-ID active status in lieu of using the

LPS input terminal.

The LCtrl bit is set to 1 by hardware reset and is unaffected by bus-reset.

NOTE: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the

LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then received

packets and status information continue to be presented on the interface, and any requests indicated on the

LREQ input are processed, even if the LCtrl bit is cleared to 0.

C

1

Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource manager.

This bit is replicated in the c field (bit 20) of the self-ID packet. This bit is set to 0 on hardware reset. After

hardware reset, this bit can only be set via a software register write. This bit is unaffected by a bus reset.

Jitter

3

Rd

PHY repeater jitter. This field indicates the worst-case difference between the fastest and slowest repeater data

delay, expressed as (jitter+1) × 20 ns. For the TSB41BA3B-EP, this field is 0.

Pwr_Class

Rd/Wr Node power class. This field indicates this node power consumption and source characteristics and is

replicated in the pwr field (bits 21−23) of the self-ID packet. This field is reset to the state specified by the S5−S0

input terminals on a hardware reset and is unaffected by a bus reset. See Table 1 and Table 10.

WDIE

ISBR

1

Rd/Wr Watchdog interrupt enable. This bit, if set to 1, enables the port event interrupt (PIE) bit to be set whenever

resume operations begin on any port, or when any of the CTOI, CPSI, or STOI interrupt bits are set and the link

interface is nonoperational. This bit is reset to 0 by hardware reset and is unaffected by bus reset.

Rd/Wr Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 µs) arbitrated bus

reset at the next opportunity. This bit is reset to 0 by a bus reset. It is recommended that short bus reset is the

only reset type initiated by software. IEC 61883-6 requires that a node initiate short bus resets to minimize any

disturbance to an audio stream.

NOTE: Legacy IEEE Std 1394-1995-compliant PHYs are not capable of performing short bus resets.

Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long bus

reset being performed.

CTOI

1

Rd/Wr Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times out during tree-ID start

and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware reset or by writing a 1 to

this register bit.

If the CTOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the

S5_LKON output to notify the LLC to service the interrupt.

NOTE: If the network is configured in a loop, then only those nodes which are part of the loop generate a

configuration-time-out interrupt. All other nodes instead time out waiting for the tree-ID and/or self-ID process

to complete and then generate a state time-out interrupt and bus-reset. This bit is only set when the bus

topology includes 1394a nodes; otherwise, 1394b loop healing prevents loops from being formed in the

topology.

CPSI

1

Rd/Wr Cable power status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low indicating

that cable power may be too low for reliable operation. This bit is reset to 1 by hardware reset. It can be cleared

by writing a 1 to this register bit.

If the CPSI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the

S5_LKON output to notify the LLC to service the interrupt.

STOI

PEI

1

Rd/Wr State-time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus-reset to

occur). This bit is reset to 0 by hardware reset or by writing a 1 to this register bit.

If the STOI and WDIE bits are both set and the LLC is or becomes inactive, then the PHY activates the

S5_LKON output to notify the LLC to service the interrupt.

Rd/Wr Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for any port

for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt enable (WDIE) bit is

set, then the PEI bit is set to 1 at the start of resume operations on any port. This bit is reset to 0 by hardware

reset, or by writing a 1 to this register bit.

21

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SGLS362—MAY 2006

APPLICATION INFORMATION

Table 3. Base Register Field Descriptions (Continued)

FIELD

EAA

SIZE TYPE

DESCRIPTION

1

Rd/Wr Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration

enhancements defined in 1394a-2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation, and

isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus reset. This

bit has no effect when the device is operating in 1394b mode.

NOTE: The use of accelerated arbitration is completely compatible with networks containing legacy IEEE Std

1394-1995 PHYs. The EAA bit is set only if the attached LLC is 1394a-2000-compliant. If the LLC is not

1394a-2000 or 1394b-2002-compliant, then the use of the arbitration acceleration enhancements can interfere

with isochronous traffic by excessively delaying the transmission of cycle-start packets.

EMC

1

3

Rd/Wr Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of

differing speeds in accordance with the protocols defined in 1394a-2000. This bit is reset to 0 by hardware reset

and is unaffected by bus reset. This bit has no effect when the device is operating in 1394b mode.

NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy IEEE

Std 1394-1995 PHYs. However, use of multispeed concatenation requires that the attached LLC be

1394a-2000 or 1394b-2002-compliant.

Max Legacy

SPD

Rd

Maximum legacy-path speed. This field holds the maximum speed capability of any legacy node (1394a-2000

or 1394-1995-compliant) as indicated in the self-ID packets received during bus initialization. Encoding is the

same as for the PHY_SPEED field (but limited to S400 maximum).

BLINK

1

2

3

4

Rd

Beta-mode link. This bit indicates that a Beta-mode-capable link is attached to the PHY. This bit is set by the

BMODE input terminal on the TSB41BA3B-EP.

Bridge

Rd/Wr This field controls the value of the bridge (brdg) field in self-ID packet. The power reset value is 0. Details for

when to set these bits are specified in the IEEE 1394.1 bridging specification.

Page_Select

Port_Select

Rd/Wr Page_Select. This field selects the register page to use when accessing register addresses 8 through 15. This

field is reset to 0 by a hardware reset and is unaffected by bus-reset.

Rd/Wr Port_Select. This field selects the port when accessing per-port status or control (for example, when one of the

port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset to 0 by

hardware-reset and is unaffected by bus-reset.

The port status page provides access to configuration and status information for each of the ports. The port is

selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base

register 7. Table 4 shows the configuration of the port status page registers, and Table 5 gives the corresponding

field descriptions. If the selected port is unimplemented, then all registers in the port status page are read as 0.

Table 4. Page 0 (Port Status) Register Configuration

BIT POSITION

Address

1000

1001

1010

1011

1100

1101

1110

0

1

2

3

4

Ch

5

6

7

Astat

Negotiated_speed

BStat

Con

RXOK

Dis

PIE

Fault

Standby_fault

Disscrm

Cable_speed

Reserved

B_Only(0)

DC_connected

Max_port_speed

Reserved

LPP

Connection_unreliable

Beta_mode

Port_error

Reserved

Sleep_Flag Sleep_enable Loop_disable In_standby Hard_disable

Reserved

1111

22

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SGLS362—MAY 2006

APPLICATION INFORMATION

Table 5. Page 0 (Port Status) Register Field Descriptions

FIELD

SIZE TYPE

DESCRIPTION

Astat

2

Rd

TPA line state. This field indicates the instantaneous TPA line state of the selected port, encoded

as follows:

Code

11

Arb Value

Z

01

1

10

0

00

invalid

Bstat

Ch

2

1

Rd

TPB line state. This field indicates the TPB line state of the selected port. This field has the same

encoding as the AStat field.

Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected

port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The

Ch bit is invalid after a bus-reset until tree-ID has completed.

Con

1

Rd

Debounced port connection status. This bit indicates that the selected port is connected. The

connection must be stable for the debounce time of approximately 341 ms for the Con bit to be set

to 1. The Con bit is reset to 0 by hardware reset and is unaffected by bus-reset.

NOTE: The Con bit indicates that the port is physically connected to a peer PHY, but this does not

mean that the port is necessarily active. For 1394b coupled connections, the Con bit is set when a

port detects connection tones from the peer PHY and operating speed negotiation is completed.

RxOK

Dis

1

Rd

Receive OK. In 1394a-2000 mode this bit indicates the reception of a debounced TPBias signal. In

Beta_mode, this bit indicates the reception of a continuous electrically valid signal.

Note: RxOK is set to false during the time that only connection tones are detected in Beta mode.

Rd/Wr Port disabled control. If this bit is 1, then the selected port is disabled. The Dis bit is reset to 0 by

hardware reset (all ports are enabled for normal operation following hardware reset). The Dis bit is

not affected by bus-reset. When this bit is set, the port cannot become active; however, the port still

tones, but does not establish an active connection.

Negotiated_speed

3

1

Rd

Indicates the maximum speed negotiated between this PHY port and its immediately connected port.

The encoding is as for Max_port_speed. It is set on connection when in Beta_mode or to a value

established during self-ID when in 1394a-2000 mode.

PIE

Rd/Wr Port event interrupt enable. When this bit is 1, a port event on the selected port sets the port event

interrupt (PEI) bit and notifies the link. This bit is reset to 0 by a hardware reset and is unaffected by

bus-reset.

Fault

Rd/Wr Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and

that the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect

incoming cable bias from its attached peer. A suspend-fault occurs when a suspending port

continues to detect incoming cable bias from its attached peer. Writing 1 to this bit clears the Fault

bit to 0. This bit is reset to 0 by hardware reset and is unaffected by bus reset.

Standby_fault

1

Rd/Wr This bit is set to 1 if an error is detected during a standby operation and cleared on exit from the

standby state. A write of 1 to this bit or receipt of the appropriate remote command packet clears it

to 0. When this bit is cleared, standby errors are cleared.

Disscrm

B_Only

1

Rd/Wr Disable scrambler. If this bit is set to 1, then the data sent during packet transmission is not

scrambled.

Rd

Beta-mode operation only. For the TSB41BA3B-EP, this bit is set to 0 for all ports when all ports are

programmed as bilingual or a combination of bilingual and data-strobe (1394a) only. If a port has

been programmed to be Beta-only at a selected speed (for example B1 is Beta-only S100), then this

bit is set to 1.

DC_connected

1

Rd

If this bit is set to 1, the port has detected a dc connection to the peer port by means of a 1394a-style

connect detect circuit.

23

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SGLS362—MAY 2006

APPLICATION INFORMATION

Table 5. Page 0 (Port Status) Register Field Descriptions (Continued)

FIELD

SIZE TYPE

DESCRIPTION

Max_port_speed

3

Rd/Wr Max_port_speed

The maximum speed at which a port is allowed to operate in Beta mode. The encoding is:

000 = S100

001 = S200

010 = S400

011 = S800

100 = S1600

101 = S3200

110 = reserved

111 = reserved

An attempt to write to the register with a value greater than the hardware capability of the port results

in the maximum value that the port is capable of being stored in the register. The port uses this

register only when a new connection is established in the Beta mode when a port is programmed

as a Beta-only port. When a port is programmed as a bilingual port, it is fixed at S400 for the Beta

speed and is not updated by a write to this register. The power reset value is the maximum speed

capable of the port. Software can modify this value to force a port to train at a lower than maximum

(when in a Beta-only mode), but no lower than minimum speed.

LPP

1

3

1

Rd

This flag is set permanently to 1.

(Local_plug_present)

Cable_speed

This variable is set to the maximum speed that the port is capable of in Beta mode. The encoding

is the same as for Max_port_speed.

Connection_unreliable

Beta_mode

Rd/Wr If this bit is set to 1, then a Beta-mode speed negotiation has failed or synchronization has failed.

A write of 1 to this field resets the value to 0.

Rd

Operating in Beta mode. If this bit is 1, the port is operating in Beta mode; it is equal to 0 otherwise

(that is, when operating in 1394a-2000 mode, or when disconnected). If Con is 1, RxOK is 1, and

Beta_mode is 0, then the port is active and operating in the 1394a-2000 mode.

Port_error

8

Rd/Wr Incremented whenever the port receives an invalid code word, unless the value is already 255.

Cleared when read (including being read by means of a remote access packet). Intended for use

by a single bus-wide diagnostic program.

Sleep_Flag

1

Rd

This bit is set to 1 if the port is in the sleep state. The transition to the sleep state occurs only if the

port has been enabled for the sleep mode.

Sleep_enable

Rd/Wr This bit is set to 1 if the port has been enabled for sleep mode. If SLPEN pin is sampled high during

reset, then this bit is set high for all ports. If sampled low, then it is 0. Software can individually enable

or disable sleep mode for a port by writing to this bit. Sleep mode operation is described in IDB−1394

specification. In PMC mode when no link is present, the sleep state of each port can be monitored

on the data lines as described in the Terminal Functions table entry for LCLK_PMC.

Loop_disable

1

Rd

This bit is set to 1 if the port has been placed in the loop-disable state as part of the loop-free build

process (the PHYs at either end of the connection are active, but if the connection itself were

activated, then a loop would exist). Cleared on bus reset and on disconnection.

In_standby

1

Rd

This bit is set to 1 if the port is in standby power-management state.

Hard_disable

Rd/Wr No effect unless the port is disabled. If this bit is set to 1, the port does not maintain connectivity status

on an ac connection when disabled. The values of the Con and RxOK bits are forced to 0. This flag

can be used to force renegotiation of the speed of a connection. It can also be used to place the

device into a lower power state because when hard disabled, a port no longer tones to maintain

1394b ac-connectivity status.

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SGLS362—MAY 2006

APPLICATION INFORMATION

The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected

by writing 1 to the Page_Select field in base register 7. Table 6 shows the configuration of the vendor

identification page, and Table 7 shows the corresponding field descriptions.

Table 6. Page 1 (Vendor ID) Register Configuration

BIT POSITION

Address

1000

1001

1010

1011

1100

1101

1110

0

1

2

3

4

5

6

7

Compliance

Reserved

Vendor_ID[0]

Vendor_ID[1]

Vendor_ID[2]

Product_ID[0]

Product_ID[1]

Product_ID[2]

1111

Table 7. Page 1 (Vendor ID) Register Field Descriptions

FIELD

SIZE

TYPE

DESCRIPTION

Compliance

8

Rd

Compliance level. For the TSB41BA3B-EP, this field is 02h, indicating compliance with the 1394b-2002

specification.

Vendor_ID

Product_ID

24

Rd

Manufacturer’s organizationally unique identifier (OUI). For the TSB41BA3B-EP, this field is 08 0028h (Texas

Instruments) (the MSB is at register address 1010b).

Product identifier. For the TSB41BA3B-EP, this field is 83 3003h (the MSB is at register address 1101b).

The vendor-dependent page provides access to the special control features of the TSB41BA3B-EP, as well as

configuration and status information used in manufacturing test and debug. This page is selected by writing 7

to the Page_Select field in base register 7. Table 8 shows the configuration of the vendor-dependent page and

Table 9 shows the corresponding field descriptions.

Table 8. Page 7 (Vendor-Dependent) Register Configuration

BIT POSITION

Address

1000

1001

1010

1011

1100

1101

1110

0

1

2

3

4

5

6

7

Reserved

Reserved for test

SWR

Reserved for test

1111

Table 9. Page 7 (Vendor-Dependent) Register Field Descriptions

FIELD

SWR

SIZE TYPE

Rd/Wr

DESCRIPTION

1

Software hard reset. Writing a 1 to this bit forces a hard reset of the PHY (same effect as momentarily

asserting the RESET terminal low). This bit is always read as a 0.

25

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SGLS362—MAY 2006

APPLICATION INFORMATION

power-class programming

The S2_PC0, S1_PC1, and S2_PC2 terminals can be used in some port speed/mode selections to set the

default value of the power-class indicated in the pwr field (bits 21−23) of the transmitted self-ID packet.

Descriptions of the various power-classes are given in Table 10. The default power-class value is loaded

following a hardware reset, but is overridden by any value subsequently loaded into the Pwr_Class field in

register 4.

Table 10. Power-Class Descriptions

PC0−PC2 DESCRIPTION

000

001

010

011

100

Node does not need power and does not repeat power.

Node is self-powered and provides a minimum of 15 W to the bus.

Node is self-powered and provides a minimum of 30 W to the bus.

Node is self-powered and provides a minimum of 45 W to the bus.

Node can be powered from the bus and is using up to 3 W; no additional power is needed to enable the link. The node can also

provide power to the bus. The amount of bus power that it provides can be found in the configuration ROM.

101

110

111

Reserved for future standardization.

Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.

Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.

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SGLS362—MAY 2006

APPLICATION INFORMATION

power-class programming (continued)

Outer Shield

Termination

400 kΩ

CPS

VP

TSB41BA3B-EP

Cable

Power

Pair

270 µF

TPBIAS

1 µF

56 Ω

TPA+

TPA−

Cable

Pair

A

1 MΩ

0.1 µF

Cable Port

TPB+

TPB−

Cable

Pair

B

56 Ω

VG

270 pF

(see Note A)

5 kΩ

NOTE A: The IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 270-pF capacitor is recommended.

Figure 4. Typical TP Cable Connections

Outer Cable Shield

1 MΩ

0.01 µF

0.001µF

Chassis Ground

Figure 5. Typical DC Isolated Outer Shield Termination

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SGLS362—MAY 2006

APPLICATION INFORMATION

power-class programming (continued)

Outer Cable Shield

Chassis Ground

Figure 6. Non-DC Isolated Outer Shield Termination

10 kΩ

LPS

Link Power

Square Wave Input

10 kΩ

Figure 7. Nonisolated Connection Variations for LPS

PHY V

DD

18 kΩ

LPS

Square Wave Signal

0.033 µF

13 kΩ

PHY GND

Figure 8. Isolated Circuit Connection for LPS

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SGLS362—MAY 2006

APPLICATION INFORMATION

designing with PowerPAD devices

The TSB41BA3B-EP is housed in a high-performance, thermally enhanced, 80-terminal PFP PowerPAD

package. Use of the PowerPAD package does not require any special considerations except to note that the

thermal pad, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical

conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly

techniques) might be required to prevent any inadvertent shorting by the exposed thermal pad of connection

etches or vias under the package. The recommended option, however, is not to run any etches or signal vias

under the device, but to have only a grounded thermal land as explained in the following paragraphs. Although

the actual size of the exposed die pad can vary, the maximum size required for the keepout area for the

80-terminal PFP PowerPAD package is 10 mm × 10 mm. The actual thermal pad size for the TSB41BA3B-EP

is 6 mm × 6 mm.

It is required that there be a thermal land, which is an area of solder-tinned copper, underneath the PowerPAD

package. The thermal land varies in size, depending on the PowerPAD package being used, the PCB

construction, and the amount of heat that needs to be removed. In addition, the thermal land might or might not

contain numerous thermal vias depending on PCB construction.

Other requirements for thermal lands and thermal vias are detailed in the Texas Instruments PowerPAD

Thermally Enhanced Package application report, (SLMA002), available via the Texas Instruments Web pages

at URL: http://www.ti.com.

Figure 9. Example of a Thermal Land for the TSB41BA3B-EP PHY

For the TSB41BA3B-EP, this thermal land must be grounded to the low-impedance ground plane of the device.

This improves not only thermal performance but also the electrical grounding of the device. It is also

recommended that the device ground terminal landing pads be connected directly to the grounded thermal land.

The land size ought to be as large as possible without shorting the device signal terminals. The thermal land

can be soldered to the exposed thermal pad using standard reflow soldering techniques.

Although the thermal land can be electrically floated and configured to remove heat to an external heat sink,

it is recommended that the thermal land be connected to the low-impedance ground plane for the device. More

information can be obtained from the Texas Instruments application report PHY Layout, (SLLA020).

29

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SGLS362—MAY 2006

APPLICATION INFORMATION

using the TSB41BA3B-EP with a 1394-1995 or 1394a-2000 link layer

The TSB41BA3B-EP implements the PHY-LLC interface specified in the 1394b Supplement. This interface is

based on the interface described in Section 17 of IEEE 1394b-2002. When using an LLC that is compliant with

an IEEE 1394b-2002 interface, the BMODE input must be tied high.

The TSB41BA3B-EP also functions with a LLC that is compliant with the older 1394 standards. This interface

is compatible with both the older Annex J interface specified in the IEEE Std 1394-1995 (with the exception of

the Annex J isolation interfacing method) and the PHY-LLC interface specified in 1394a-2000. When using an

LLC compliant with an IEEE 1394b-2002 interface, the BMODE input must be tied low.

When the BMODE input is tied low, the TSB41BA3B-EP implements the PHY-LLC interface specified in the

1394a-2000 Supplement. This interface is based on the interface described in informative Annex J of IEEE Std

1394-1995, which is the interface used in the oldest Texas Instruments PHY devices. The PHY-LLC interface

specified in 1394a-2000 is compatible with the older Annex J. However, the TSB41BA3B-EP does not support

the Annex J isolation interfacing method. When implementing the 1394a-2000 interface, certain signals are not

used:

−

The PINT output (terminal 1) can be left open.

The LCLK_PMC input (terminal 7) must be tied directly to ground or through a pulldown resistor of ~1 kΩ

or less, unless the PMC mode is desired (see LCLK_PMC terminal description).

All other signals are connected to their counterparts on the 1394a link-layer controller. The PCLK output

corresponds to the SCLK input signal on most LLCs.

The 1394a-2000 Supplement includes enhancements to the Annex J interface that should be comprehended

when using the TSB41BA3B-EP with a 1394-1995 LLC device.

D

A new LLC service request was added which allows the LLC to temporarily enable and disable

asynchronous arbitration accelerations. If the LLC does not implement this new service request, then the

arbitration enhancements must not be enabled (see the EAA bit in PHY register 5).

D

The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was

added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not

support multispeed concatenation, then multispeed concatenation must not be enabled in the PHY (see the

EMC bit in PHY register 5).

D

In order to accommodate the higher transmission speeds expected in future revisions of the standard,

1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus

request from 7 bits to 8 bits. The new speed codes were carefully selected so that new 1394a-2000 PHY

and LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices

that use the 2-bit speed codes. The TSB41BA3B-EP correctly interprets both 7-bit bus requests (with 2-bit

speed code) and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately

followed by another request (for example, a register read or write request), then the TSB41BA3B-EP

correctly interprets both requests. Although the TSB41BA3B-EP correctly interprets 8-bit bus requests, a

request with a speed code exceeding S400 while in 1394a-2000 PHY-link interface mode results in the

TSB41BA3B-EP transmitting a null packet (data-prefix followed by data-end, with no data in the packet).

30

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SGLS362—MAY 2006

APPLICATION INFORMATION

power-up reset

To ensure proper operation of the TSB41BA3B-EP, the RESET terminal must be asserted low for a minimum

of 2 ms from the time that PHY power reaches the minimum required supply voltage and the input clock to the

PHY is valid. When using a passive capacitor on the RESET terminal to generate a power-on-reset signal, the

minimum reset time is ensured if the value of the capacitor satisfies the following equation (the value must be

no smaller than approximately 0.1 µF):

C

= 0.0077 x T + 0.085 + (external_oscillator_start-up_time x 0.05)

min

Where C

is the minimum capacitance on the RESET terminal in µF, T is the V

ramp time, 10%–90%, in

min

DD

ms, external_oscillator_start-up_time is the time from power applied to the external oscillator until the oscillator

outputs a valid clock in ms. If a crystal is used rather than an oscillator, then the external_oscillator_start-up_time

may be set to 0.

For example, with a 2-ms power ramp time and a 2-ms oscillator start-up time:

C

= 0.0077 x 2 + 0.085 + (2 x 0.05) = 0.2 µF

min

It is appropriate to select the nearest standard value capacitor that exceeds this value, for example 0.22 µF.

Or with a 2-ms power ramp time and a 49.152-MHz fundamental crystal:

C

= 0.0077 x 2 + 0.085 + (0 x 0.05) = 0.1 µF

min

crystal selection

The TSB41BA3B-EP and other Texas Instruments PHY devices are designed to use an external 49.152-MHz

crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit. This

oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and

resynchronization of data at the S100 through S400 media data rates.

A variation of less than 100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent

PHYs can therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must

be able to compensate for this difference over the maximum packet length. Larger clock variations may cause

resynchronization overflows or underflows, resulting in corrupted packet data or even PHY lockup.

For the TSB41BA3B-EP, the PCLK output can be used to measure the frequency accuracy and stability of the

internal oscillator and PLL from which it is derived. When operating the PHY-LLC interface with a non-1394b

LLC, the frequency of the PCLK output must be within 100 ppm of the nominal frequency of 49.152 MHz. When

operating the PHY-LLC interface with a 1394b LLC, the frequency of the PCLK output must be within 100 ppm

of the nominal frequency of 98.304 MHz.

The following are some typical specifications for crystals used with the physical layers from Texas Instruments

in order to achieve the required frequency accuracy and stability:

D

Crystal mode of operation: Fundamental

Frequency tolerance at 25_C: Total frequency variation for the complete circuit is 100 ppm. A crystal with

30 ppm frequency tolerance is recommended for adequate margin.

D

Frequency stability (over temperature and age): A crystal with 30 ppm frequency stability is recommended

for adequate margin.

31

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SGLS362—MAY 2006

APPLICATION INFORMATION

crystal selection (continued)

NOTE:

The total frequency variation must be kept below 100 ppm from nominal with some allowance for

error introduced by board and device variations. Trade-offs between frequency tolerance and

stability can be made as long as the total frequency variation is less than 100 ppm. For example,

the frequency tolerance of the crystal may be specified at 50 ppm, and the temperature tolerance

may be specified at 30 ppm to give a total of 80 ppm possible variation due to the oscillator alone.

Aging also contributes to the frequency variation.

D

Load capacitance: For parallel resonant mode crystal circuits, the frequency of oscillation depends on the

load capacitance specified for the crystal. Total load capacitance (C ) is a function of not only the discrete

L

load capacitors, but also board layout and circuit. It may be necessary to iteratively select discrete load

capacitors until the PCLK output is within specification. It is recommended that load capacitors with a

maximum of 5% tolerance be used.

As an example, for the OHCI + 41LV03 evaluation module (EVM) which uses a crystal specified for 12-pF

loading, load capacitors (C9 and C10 in Figure 10) of 16 pF each were appropriate for the layout of that particular

board. The load specified for the crystal includes the load capacitors (C9, C10), the loading of the PHY terminals

(C

), and the loading of the board itself (C ). The value of C

is typically about 1 pF and C

is typically

PHY

BD

PHY

BD

0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more. The load capacitors C9 and

C10 combine as capacitors in series so that the total load capacitance is:

C9 C10

C9 ) C10

C

+

) C

L

PHY

BD

C9

X1

C

+ C

BD

PHY

49.152 MHz

I

S

X0

C10

Figure 10. Load Capacitance for the TSB41BA3B-EP PHY

NOTE:

The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency,

minimizing noise introduced into the PHY’s phase lock loop, and minimizing any emissions from

the circuit. The crystal and two load capacitors must be considered as a unit during layout. The

crystal and load capacitors must be placed as close as possible to one another while minimizing

the loop area created by the combination of the three components. Varying the size of the capacitors

may help in this. Minimizing the loop area minimizes the effect of the resonant current (I ) that flows

S

in this resonant circuit. This layout unit (crystal and load capacitors) must then be placed as close

as possible to the PHY XI and XO terminals to minimize trace lengths.

32

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SGLS362—MAY 2006

APPLICATION INFORMATION

crystal selection (continued)

C9

C10

X1

Figure 11. Recommended Crystal and Capacitor Layout

It is strongly recommended that part of the verification process for the design is to measure the frequency of

the PCLK output of the PHY. This should be done with a frequency counter with an accuracy of six digits or better.

If the PCLK frequency is more than the crystal’s tolerance from 49.152 MHz or 98.304 MHz, then the load

capacitance of the crystal can be varied to improve frequency accuracy. If the frequency is too high, add more

load capacitance; if the frequency is too low, decrease load capacitance. Typically, changes must be done to

both load capacitors (C9 and C10 above) at the same time, and both must be of the same value. Additional

design details and requirements can be provided by the crystal vendor.

bus reset

It is recommended, that whenever the user has a choice, the user should initiate a bus reset by writing to the

initiate short bus reset (ISBR) bit (bit 1 PHY register 0101b). Care must be taken to not change the value of any

of the other writable bits in this register when the ISBR bit is written to.

In the TSB41BA3B-EP, the initiate bus reset (IBR) bit can be set to 1 in order to initiate a bus reset and

initialization sequence; however, it is recommended to use the ISBR bit instead. The IBR bit is located in PHY

register 1 along with the root-holdoff bit (RHB) and gap-count register. As required by the 1394b Supplement,

this configuration maintains compatibility with older Texas Instruments PHY designs which were based on either

the suggested register set defined in Annex J of IEEE Std 1394-1995 or the 1394a-2000 Supplement.

Therefore, whenever the IBR bit is written, the RHB and gap-count register are also necessarily written.

It is recommended that the RHB and gap-count register only be updated by PHY configuration packets. The

TSB41BA3B-EP is 1394a- and 1394b-compliant, and therefore, both the reception and transmission of PHY

configuration packets cause the RHB and gap-count register to be loaded, unlike older IEEE Std

1394-1995-compliant PHYs which decode only received PHY configuration packets.

The gap-count register is set to the maximum value of 63 after two consecutive bus resets without an intervening

write to the gap-count register, either by a write to PHY register 1 or by a PHY configuration packet. This

mechanism allows a PHY configuration packet to be transmitted and then a bus reset to be initiated so as to

verify that all nodes on the bus have updated their RHBs and gap-count values, without having the gap-count

register set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which initiates

a bus reset, then causes the gap-count register of each node to be set to 63. Note, however, that if a subsequent

bus reset is instead initiated by a write to register 1 to set the IBR bit, then all other nodes on the bus have their

gap-count values set to 63, while this node’s gap-count register remains set to the value just loaded by the write

to PHY register 1.

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SGLS362—MAY 2006

APPLICATION INFORMATION

bus reset (continued)

Therefore, in order to maintain consistent gap counts throughout the bus, the following rules apply to the use

of the IBR bit, RHB, and gap count in PHY register 1:

D

Following the transmission of a PHY configuration packet, a bus reset must be initiated in order to verify

that all nodes have correctly updated their RHBs and gap-count values and to ensure that a subsequent

new connection to the bus causes the gap-count register to be set to 63 on all nodes in the bus. If this bus

reset is initiated by setting the IBR bit to 1, then the RHB and gap-count register must also be loaded with

the correct values consistent with the just transmitted PHY configuration packet. In the TSB41BA3B-EP,

the RHB and gap-count register have been updated to their correct values on the transmission of the PHY

configuration packet, and so these values can first be read from register 1 and then rewritten.

D

Other than to initiate the bus reset which must follow the transmission of a PHY configuration packet,

whenever the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63

so as to be consistent with other nodes on the bus, and the RHB must be maintained with its current value.

D

The PHY register 1 must not be written to except to set the IBR bit. The RHB and gap-count register must

not be written without also setting the IBR bit to 1.

To avoid these problems, all bus resets initiated by software must be initiated by writing the ISBR bit (bit

1 PHY register 0101b). Care must be taken to not change the value of any of the other writable bits in this

register when the ISBR bit is written to. Also, the only means to change the gap count of any node must

be by means of the PHY configuration packet, which changes all nodes to the same gap count.

34

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

The TSB41BA3B-EP is designed to operate with an LLC such as the Texas Instruments TSB12LV21B,

TSB12LV26, TSB12LV32, TSB42AA4, or TSB12LV01B when the BMODE terminal is tied low. Details of

operation for the Texas Instruments LLC devices are found in the respective LLC data sheets. The following

paragraphs describe the operation of the PHY-LLC interface. This interface is formally defined in IEEE

1394a-2000, Section 5A.

The interface to the LLC consists of the PCLK, CTL0−CTL1, D0−D7, LREQ, LPS, and S5_LKON terminals on

the TSB41BA3B-EP, as shown in Figure 12.

TSB41BA3B-EP

PCLK (SYSCLK)

CTL0–CTL1

Link-Layer

Controller

D0–D7

LREQ

LPS

S5_LKON

Figure 12. PHY-LLC Interface

The PCLK terminal provides a 49.152-MHz interface system clock. All control and data signals are synchronized

to, and sampled on, the rising edge of PCLK. This terminal serves the same function as the SYSCLK terminal

of 1394a-2000-compliant PHY devices.

The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data

between the TSB41BA3B-EP and LLC.

The D0−D7 terminals form a bidirectional data bus, which transfers status information, control information, or

packet data between the devices. The TSB41BA3B-EP supports S100, S200, and S400 data transfers over the

D0−D7 data bus. In S100 operation, only the D0 and D1 terminals are used; in S200 operation, only the D0−D3

terminals are used; and in S400 operation, all D0−D7 terminals are used for data transfer. When the

TSB41BA3B-EP is in control of the D0−D7 bus, unused Dn terminals are driven low during S100 and S200

operations. When the LLC is in control of the D0−D7 bus, unused Dn terminals are ignored by the

TSB41BA3B-EP.

The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access

to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration.

The LPS and S5_LKON terminals are used for power management of the PHY and LLC. The LPS terminal

indicates the power status of the LLC, and can be used to reset the PHY-LLC interface or to disable PCLK. The

S5_LKON terminal sends a wake-up notification to the LLC or external circuitry and indicates an interrupt to the

LLC when either LPS is inactive or the PHY register L bit is 0.

The TSB41BA3B-EP normally controls the CTL0−CTL1 and D0−D7 bidirectional buses. The LLC is allowed to

drive these buses only after the LLC has been granted permission to do so by the PHY.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

Four operations can occur on the PHY-LLC interface: link service request, status transfer, data transmit, and

data receive. The LLC issues a service request to read or write a PHY register, to request the PHY to gain control

of the serial bus in order to transmit a packet or to control arbitration acceleration.

The PHY can initiate a status transfer either autonomously or in response to a register read request from

the LLC.

The PHY initiates a receive operation whenever a packet is received from the serial bus.

The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC.

The transmit operation is initiated when the PHY grants control of the interface to the LLC.

Table 11 and Table 12 show the encoding of the CTL0−CTL1 bus.

Table 11. CTL Encoding When PHY Has Control of the Bus

CTL0

CTL1

NAME

Idle

DESCRIPTION

0

1

0

1

0

1

No activity (this is the default mode)

Status

Receive

Grant

Status information is being sent from the PHY to the LLC.

An incoming packet is being sent from the PHY to the LLC.

The LLC has been given control of the bus to send an outgoing packet.

Table 12. CTL Encoding When LLC Has Control of the Bus

CTL0

CTL1

NAME

Idle

DESCRIPTION

0

1

The LLC releases the bus (transmission has been completed)

Hold

The LLC is holding the bus while data is being prepared for transmission or indicating that another packet is to

be transmitted (concatenated) without arbitrating

1

0

1

Transmit

An outgoing packet is being sent from the LLC to the PHY

None

Reserved

LLC service request

To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends

a serial bit stream on the LREQ terminal as shown in Figure 13.

LR0

LR1

LR2

LR3

LR (n-2)

LR (n-1)

Note: Each cell represents one clock sample time and n is the number of bits in the request stream.

Figure 13. LREQ Request Stream

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

LLC service request (continued)

The length of the stream varies depending on the type of request as shown in Table 13.

Table 13. Request Stream Bit Length

REQUEST TYPE

NUMBER OF BITS

Bus request

7 or 8

Read register request

Write register request

9

17

6

Acceleration control request

Regardless of the type of request, a start bit of 1 is required at the beginning of the stream and a stop bit of 0

is required at the end of the stream. The second through fourth bits of the request stream indicate the type of

the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit stream.

The LREQ terminal is normally low.

Table 14 shows the encoding for the request type.

Table 14. Request Type Encoding

LR1−LR3

000

NAME

ImmReq

IsoReq

DESCRIPTION

Immediate bus request. On detection of idle, the PHY takes control of the bus immediately without arbitration.

Isochronous bus request. On detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap.

Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol.

Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol.

The PHY returns the specified register contents through a status transfer.

Write to the specified register

001

010

PriReq

011

FairReq

RdReg

100

101

WrReg

110

AccelCtl

Reserved

Enable or disable asynchronous arbitration acceleration

111

Reserved

For a bus request, the length of the LREQ bit stream is 7 or 8 bits as shown in Table 15.

Table 15. Bus Request

BIT(s)

0

NAME

Start bit

DESCRIPTION

Indicates the beginning of the transfer (always 1)

1−3

4−6

7

Request type

Request speed

Stop bit

Indicates the type of bus request. See Table 14.

Indicates the speed at which the PHY sends the data for this request. See Table 16 for the encoding of this field.

Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit can be omitted.

Table 16 shows the 3-bit request speed field used in bus requests.

Table 16. Bus Request Speed Encoding

LR4−LR6

000

DATA RATE

S100

010

S200

100

S400

All Others

Invalid

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

LLC service request (continued)

NOTE:

The TSB41BA3B-EP accepts a bus request with an invalid speed code and processes the bus

request normally. However, during packet transmission for such a request, the TSB41BA3B-EP

ignores any data presented by the LLC and transmits a null packet.

For a read register request, the length of the LREQ bit stream is 9 bits as shown in Table 17.

Table 17. Read Register Request

BIT(s)

0

NAME

Start bit

DESCRIPTION

Indicates the beginning of the transfer (always 1)

1−3

4−7

8

Request type

Address

A 100 indicates this is a read register request.

Identifies the address of the PHY register to be read

Indicates the end of the transfer (always 0)

Stop bit

For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 18.

Table 18. Write Register Request

BIT(s)

0

NAME

Start bit

DESCRIPTION

Indicates the beginning of the transfer (always 1)

1−3

4−7

8−15

16

Request type

Address

Data

A 101 indicates this is a write register request.

Identifies the address of the PHY register to be written to

Gives the data that is to be written to the specified register address

Indicates the end of the transfer (always 0)

Stop bit

For an acceleration control request, the length of the LREQ data stream is 6 bits as shown in Table 19.

Table 19. Acceleration Control Request

BIT(s)

NAME

Start bit

DESCRIPTION

Indicates the beginning of the transfer (always 1)

0

1−3

4

Request type

Control

A 110 indicates this is an acceleration control request.

Asynchronous period arbitration acceleration is enabled if 1 and disabled if 0

Indicates the end of the transfer (always 0)

5

Stop bIt

For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the

PHY-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the PHY, then

any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests

if the receive state is asserted while the LLC is sending the request. The LLC can then reissue the request one

clock after the next interface idle.

The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or

transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears

an isochronous request only when the serial bus has been won.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

LLC service request (continued)

To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception

of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received

packet and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY

immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the

header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but

instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant

to send another type of packet. After the interface is released, the LLC can proceed with another request.

The LLC can make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq,

IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request

was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted

control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are

cleared on a bus reset.

For write register requests, the PHY loads the specified data into the addressed register as soon as the request

transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the

LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the

PHY continues to attempt the transfer of the requested register until it is successful. A write or read register

request can be made at any time, including while a bus request is pending. Once a read register request is made,

the PHY ignores further read register requests until the register contents are successfully transferred to the LLC.

A bus reset does not clear a pending read register request.

The TSB41BA3B-EP includes several arbitration acceleration enhancements, which allow the PHY to improve

bus performance and throughput by reducing the number and length of interpacket gaps. These enhancements

include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet

concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following

acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set.

The arbitration acceleration enhancements may interfere with the ability of the cycle master node to transmit

the cycle start message under certain circumstances. The acceleration control request is therefore provided

to allow the LLC to temporarily enable or disable the arbitration acceleration enhancements of the

TSB41BA3B-EP during the asynchronous period. The LLC typically disables the enhancements when its

internal cycle counter rolls over indicating that a cycle start message is imminent, and then re-enables the

enhancements when it receives a cycle start message. The acceleration control request can be made at any

time, however, and is immediately serviced by the PHY. Additionally, a bus reset or isochronous bus request

causes the enhancements to be re-enabled, if the EAA bit is set.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

status transfer

A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY

waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting status

(01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals. The PHY

maintains CTL = Status for the duration of the status transfer. The PHY can prematurely end a status transfer

by asserting something other than status on the CTL terminals. This occurs if a packet is received before the

status transfer completes. The PHY continues to attempt to complete the transfer until all status information has

been successfully transmitted. At least one idle cycle occurs between consecutive status transfers.

The PHY normally sends just the first 4 bits of status to the LLC. These bits are status flags that are needed

by the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read register

request, or when the PHY has pertinent information to send to the LLC or transaction layers. The only defined

condition where the PHY automatically sends a register to the LLC is after self-ID, where the PHY sends the

physical-ID register that contains the new node address. All status transfers are either 4 or 16 bits unless

interrupted by a received packet. The status flags are considered to have been successfully transmitted to the

LLC immediately on being sent, even if a received packet subsequently interrupts the status transfer. Register

contents are considered to have been successfully transmitted only when all 8 bits of the register have been

sent. A status transfer is retried after being interrupted only if any status flags remain to be sent or if a register

transfer has not yet completed.

Table 20 shows the definition of the bits in the status transfer, and Figure 14 shows the timing.

Table 20. Status Bits

BIT(s)

NAME

DESCRIPTION

0

Arbitration reset gap

Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as defined in

the IEEE 1394a-2000 standard). This bit is used by the LLC in the busy/retry state machine.

1

Subaction gap

Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in the

IEEE 1394a-2000 standard). This bit is used by the LLC to detect the completion of an isochronous cycle.

2

3

Bus reset

Interrupt

Indicates that the PHY has entered the bus reset state

Indicates that a PHY interrupt event has occurred. An interrupt event can be a configuration time-out, a

cable-power voltage falling too low, a state time-out, or a port status change.

4−7

Address

Data

This field holds the address of the PHY register whose contents are being transferred to the LLC.

This field holds the register contents.

8−15

SYSCLK

CTL0, CTL1

D0, D1

00

01

00

(a)

(b)

00

S[0:1]

S[14:15]

Figure 14. Status Transfer Timing

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

status transfer (continued)

The sequence of events for a status transfer is as follows:

(a) Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with

the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally (unless

interrupted by a receive operation), a status transfer is either 2 or 8 cycles long. A 2-cycle (4-bit) transfer

occurs when only status information is to be sent. An 8-cycle (16-bit) transfer occurs when register data is

to be sent in addition to any status information.

(b) Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL lines.

The PHY can also interrupt a status transfer at any cycle by asserting receive on the CTL lines to begin a

receive operation. The PHY asserts at least one idle cycle between consecutive status transfers.

receive

Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting

receive on the CTL terminals and a logic 1 on each of the D bus terminals (data-on indication). The PHY

indicates the start of a packet by placing the speed code (encoded as shown in Table 21) on the D terminals,

followed by packet data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet

has been transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All

received packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is

not included in the calculation of CRC or any other data protection mechanisms.

It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed

by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds

the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any

data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D

bus terminals, followed by Idle on the CTL terminals, without any speed code or data being transferred. In all

cases, in normal operation, the TSB41BA3B-EP sends at least one data-on indication before sending the speed

code or terminating the receive operation.

The TSB41BA3B-EP also transfers its own self-ID packet, transmitted during the self-ID phase of bus

initialization, to the LLC. This packet it transferred to the LLC just as any other received self-ID packet.

SYSCLK

CTL0, CTL1

D0–D7

10

00

(e)

(a)

(b)

(c)

SPD

(d)

d0

XX

FF (data-on)

dn

00

NOTE A: SPD = Speed code, see Table 21. d0–dn = Packet data

Figure 15. Normal Packet Reception Timing

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

receive (continued)

The sequence of events for a normal packet reception is as follows:

(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a

status transfer operation that is in progress so that the CTL lines can change from status to receive without

an intervening idle.

(b) Data-on indication. The PHY can assert the data-on indication code on the D lines for one or more cycles

preceding the speed code.

(c) Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines

for one cycle immediately preceding packet data. The link decodes the speed code on the first receive cycle

for which the D lines are not the data-on code. If the speed code is invalid or indicates a speed higher that

that which the link is capable of handling, then the link must ignore the subsequent data.

(d) Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data

on the D lines with receive on the CTL lines for the remainder of the receive operation.

(e) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one idle cycle following a receive operation.

SYSCLK

CTL0, CTL1

D0–D7

10

00

(c)

(a)

(b)

XX

FF (data-on)

00

Figure 16. Null Packet Reception Timing

The sequence of events for a null packet reception is as follows:

(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a

status transfer operation that is in progress so that the CTL lines can change from status to receive without

an intervening idle.

(b) Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.

(c) Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one idle cycle following a receive operation.

Table 21. Receive Speed Codes

D0−D7

DATA RATE

S100

00XX XXXX

0100 XXXX

0101 0000

11YY YYYY

S200

S400

data-on indication

NOTE: X = Output as 0 by PHY, ignored by LLC.

Y = Output as 1 by PHY, ignored by LLC.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

transmit

When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus.

If the PHY wins arbitration for the serial bus, then the PHY-LLC interface bus is granted to the LLC by asserting

the grant state (11b) on the CTL terminals for one PCLK cycle, followed by idle for one clock cycle. The LLC

then takes control of the bus by asserting either idle (00b), hold (01b), or transmit (10b) on the CTL terminals.

Unless the LLC is immediately releasing the interface, the LLC can assert the idle state for at most one clock

before it must assert either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain

control of the bus while it prepares data for transmission. The LLC can assert hold for zero or more clock cycles

(that is, the LLC need not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this

time.

When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first

bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have

been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle, and then asserts

idle for one additional cycle before releasing the interface bus and putting the CTL and D terminals in a

high-impedance state. The PHY then regains control of the interface bus.

The hold state asserted at the end-of-packet transmission indicates to the PHY that the LLC requests to send

another packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation

request by waiting the required minimum packet separation time and then asserting grant as before. This

function can be used to send a unified response after sending an acknowledge, or to send consecutive

isochronous packets during a single isochronous period. Unless multispeed concatenation is enabled, all

packets transmitted during a single bus ownership must be of the same speed (because the speed of the packet

is set before the first packet). If multispeed concatenation is enabled (when the EMSC bit of PHY register 5 is

set), then the LLC must specify the speed code of the next concatenated packet on the D terminals when it

asserts hold on the CTL terminals at the end of a packet. The encoding for this speed code is the same as the

speed code that precedes received packet data as given in Table 21.

After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on the

CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after sampling

idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC,

an extra clock period is allowed so that both sides of the interface can operate on registered versions of the

interface signals.

SYSCLK

(a)

(b)

(c)

(d)

(e)/(f)

00/01

(g)

CTL0, CTL1

D0–D7

00

11

00

01

10

00

d0, d1, . . .

dn

00/SP

00

Link Controls CTL and D

PHY High-Impedance CTL and D Outputs

NOTE A: SPD = Speed code, see Table 21. d0–dn = Packet data

Figure 17. Normal Packet Transmission Timing

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION

transmit (continued)

The sequence of events for a normal packet transmission is as follows:

(a) Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over control

of the interface to the link so that the link can transmit a packet. The PHY releases control of the interface

(that is, it places its CTL and D outputs in a high-impedance state) following the idle cycle.

(b) Optional idle cycle. The link can assert at most one idle cycle preceding assertion of either hold or transmit.

This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit.

(c) Optional hold cycles. The link can assert hold for up to 47 cycles preceding assertion of transmit. These

hold cycle(s) are optional; the link is not required to assert hold preceding transmit.

(d) Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along with

the data on the D lines.

(e) Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle on the

CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in order to

transmit a concatenated packet. The link asserts idle to indicate that packet transmission is complete and

the PHY can release the serial bus. The link then asserts idle for one more cycle following this hold or idle

cycle before releasing the interface and returning control to the PHY.

(f) Concatenated packet speed code. If multispeed concatenation is enabled in the PHY, then the link asserts

a speed code on the D lines when it asserts hold to terminate packet transmission. This speed code

indicates the transmission speed for the concatenated packet that is to follow. The encoding for this

concatenated packet speed code is the same as the encoding for the received packet speed code (see

Table 21). The link may not concatenate an S100 packet onto any higher-speed packet.

(g) After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status

transfer, receive operation, or transmit operation.

SYSCLK

(a)

11

(b)

00

(c)

(d)

(e)

CTL0, CTL1

D0–D7

00

01

00

Link Controls CTL and D

PHY High-Impedance CTL and D Outputs

Figure 18. Cancelled/Null Packet Transmission

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

transmit (continued)

The sequence of events for a cancelled/null packet transmission is as follows:

(a) Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the

interface to the link.

(b) Optional idle cycle. The link can assert at most one idle cycle preceding assertion of hold. This idle cycle

is optional; the link is not required to assert idle preceding hold.

(c) Optional hold cycles. The link can assert hold for up to 47 cycles preceding assertion of idle. These hold

cycle(s) are optional; the link is not required to assert hold preceding idle.

(d) Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle

on the CTL lines and then releasing the interface and returning control to the PHY. Note that the link can

assert idle for a total of three consecutive cycles if it asserts the optional first idle cycle but does not assert

hold. It is recommended that the link assert three cycles of idle to cancel a packet transmission if no hold

cycles are asserted. This ensures that either the link or PHY controls the interface in all cycles.

(e) After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status

transfer, receive operation, or transmit operation.

interface reset and disable

The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface can be placed into a

reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface

is not operational (whether reset, disabled, or in the process of initialization), the PHY cancels any outstanding

bus request or register read request, and ignores any requests made via the LREQ line. Additionally, any status

information generated by the PHY is not queued and does not cause a status transfer on restoration of the

interface to normal operation.

The LPS signal can be either a level signal or a pulsed signal, depending on whether the PHY-LLC interface

is a direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY

and LLC, the LPS signal must be pulsed. In a direct connection, the LPS signal can be either a pulsed or a level

signal. Timing parameters for the LPS signal are given in Table 22.

Table 22. LPS Timing Parameters

PARAMETER

DESCRIPTION

LPS low time (when pulsed) (see Note 1)

MIN

0.09

0.021

20%

2.6

MAX

2.6

UNIT

µs

t

LPSL

LPS high time (when pulsed) (see Note 1)

2.6

µs

LPSH

LPS duty cycle (when pulsed) (see Note 2)

60%

2.68

t

Time for PHY to recognize LPS deasserted and reset the interface

Time for PHY to recognize LPS deasserted and disable the interface

Time to permit optional isolation circuits to restore during an interface reset

µs

ns

ms

LPS_RESET

LPS_DISABLE

RESTORE

26.03 26.11

†

15

23

PHY not in low-power state

PHY in low-power state

60

7.3

t

Time for PCLK to be activated from reassertion of LPS

CLK_ACTIVATE

5.3

†

The maximum value for t

does not apply when the PHY-LLC interface is disabled, in which case an indefinite time can elapse before

RESTORE

LPS is reasserted. Otherwise, in order to reset but not disable the interface, it is necessary that the LLC ensure that LPS is deasserted for less

than t

.

LPS_DISABLE

NOTES: 1. The specified t

and t

LPSH

times are worst-case values appropriate for operation with the TSB41BA3B-EP. These values are

LPSL

broader than those specified for the same parameters in the 1394a-2000 Supplement (that is, an implementation of LPS that meets

the requirements of 1394a-2000 operates correctly with the TSB41BA3B-EP).

2. A pulsed LPS signal must have a duty cycle (ratio of t

to cycle period) in the specified range to ensure proper operation when

LPSH

using an isolation barrier on the LPS signal (for example, as shown in Figure 8).

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

interface reset and disable (continued)

The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request

activity. When the PHY observes that LPS has been deasserted for t

, it resets the interface. When

LPS_RESET

the interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity

on the LREQ signal. Figure 19 shows the timing for interface reset.

(a)

(c)

PCLK

CTL0, CTL1

D0 − D7

(b)

LREQ

LPS

(d)

t

RESTORE

LPS_RESET

Figure 19. Interface Reset

The sequence of events for resetting the PHY-LLC interface is as follows:

(a) Normal operation. Interface is operating normally, with LPS asserted, PCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line. In the above

diagram, the LPS signal is shown as a nonpulsed level signal. However, it is permissible to use a pulsed

signal for LPS in a direct connection between the PHY and LLC; a pulsed signal is required when using an

isolation barrier.

(b) LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface

bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.

(c) Interface reset. After t

time, the PHY determines that LPS is inactive, terminates any interface

LPS_RESET

bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.

(d) Interface restored. After the minimum t time, the LLC can again assert LPS active. When LPS is

RESTORE

asserted, the interface is initialized as described in the following paragraphs.

If the LLC continues to keep the LPS signal deasserted, it then requests that the interface be disabled. The PHY

disables the interface when it observes that LPS has been deasserted for t

. When the interface is

LPS_DISABLE

disabled, the PHY sets its CTL and D outputs as previously stated for interface reset, but also stops PCLK

activity. The interface is also placed into the disabled condition on a hardware reset of the PHY. Figure 20 shows

the timing for the interface disable.

When the interface is disabled, the PHY enters a low-power state if none of its ports are active.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

interface reset and disable (continued)

(a)

(c)

(d)

PCLK

CTL0, CTL1

D0 − D7

(b)

LREQ

LPS

t

LPS_RESET

t

LPS_DISABLE

Figure 20. Interface Disable

The sequence of events for disabling the PHY-LLC is as follows:

(a) Normal operation. Interface is operating normally, with LPS active, PCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line.

(b) LPS deasserted. The LLC deasserts the LPS signal and, within 1 µs, terminates any request or interface

bus activity, places its CTL and D outputs into a high-impedance state, and drives its LREQ output low.

(c) Interface reset. After t

time, the PHY determines that LPS is inactive, terminates any interface

LPS_RESET

bus activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.

(d) Interface disabled. If the LPS signal remains inactive for t time, then the PHY terminates PCLK

LPS_DISABLE

activity by driving the PCLK output low. The PHY-LLC interface is now in the disabled state.

After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal

operation when LPS is reasserted by the LLC. Figure 21 shows the timing for interface initialization.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

interface reset and disable (continued)

ISO

(high)

7 Cycles

SYSCLK

CTL0

(b)

(c)

(d)

CTL1

D0 − D7

LREQ

(a)

LPS

t

CLK_ACTIVATE

Figure 21. Interface Initialization

The sequence of events for initialization of the PHY-LLC is as follows:

(a) LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum t

RESTORE

time, the LLC causes the interface to be initialized and restored to normal operation by reasserting the LPS

signal. (In Figure 21, the interface is shown in the disabled state with PCLK low inactive. However, the

interface initialization sequence described here is also executed if the interface is merely reset but not yet

disabled.)

(b) PCLK activated. If the interface is disabled, then the PHY reactivates its PCLK output when it detects that

LPS has been reasserted. If the PHY has entered a low-power state, then it takes between 5.3 ms and

7.3 ms for PCLK to be restored; if the PHY is not in a low-power state, then the PCLK is restored within 60

ns. The PCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz 100 ppm (period

of 20.345 ns). During the first seven cycles of PCLK, the PHY continues to drive the CTL and D terminals

low. The LLC is also required to drive its CTL and D outputs low for one of the first six cycles of PCLK but

otherwise to place its CTL and D outputs in a high-impedance state. The LLC continues to drive its LREQ

output low during this time.

(c) Receive indicated. On the eighth PCLK cycle following reassertion of LPS, the PHY asserts the receive

state on the CTL lines and the data-on indication (all 1s) on the D lines for one or more cycles.

(d) Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This

indicates that the PHY-LLC interface initialization is complete and normal operation can commence. The

PHY now accepts requests from the LLC via the LREQ line.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394b INTERFACE)

The TSB41BA3B-EP is designed to operate with a LLC such as the Texas Instruments TSB82AA2 when the

BMODE terminal is tied high. Details of operation for the Texas Instruments LLC devices are found in the

respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface. This

interface is formally specified in the IEEE 1394b-2002 standard.

The interface to the LLC consists of the PCLK, LCLK_PMC, CTL0−CTL1, D0−D7, LREQ, PINT, LPS, and

S5_LKON terminals on the TSB41BA3B-EP, as shown in Figure 22.

TSB41BA3B-EP

LCLK_PMC

PCLK

CTL0–CTL1

Link-Layer

Controller

D0–D7

LREQ

LPS

S5_LKON

PINT

Figure 22. PHY-LLC Interface

The LCLK_PMC terminal provides a clock signal to the PHY. The LLC derives this clock from the PCLK signal

and is phase-locked to the PCLK signal. All LLC to PHY transfers are synchronous to LCLK_PMC.

The PCLK terminal provides a 98.304-MHz interface system clock. All control, data, and PHY interrupt signals

are synchronized to the rising edge of PCLK.

The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data

between the TSB41BA3B-EP and LLC.

The D0−D7 terminals form a bidirectional data bus, which transfers status information, control information, or

packet data between the devices. The TSB41BA3B-EP supports S400B, S200B, and S100B data transfers over

the D0−D7 data bus. In S400B, S200B, and S100B operation, all Dn terminals are used.

The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access

to the serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration. All data

on LREQ is synchronous to LCLK_PMC.

The LPS and S5_LKON terminals are used for power management of the PHY and LLC. The LPS terminal

indicates the power status of the LLC and can be used to reset the PHY-LLC interface or to disable PCLK. The

S5_LKON terminal sends a wake-up notification to the LLC and indicates an interrupt to the LLC when either

LPS is inactive or the PHY register L bit is 0.

The PINT terminal is used by the PHY for the serial transfer of status, interrupt, and other information to the LLC.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394b INTERFACE)

The TSB41BA3B-EP normally controls the CTL0−CTL1 and D0−D7 bidirectional buses. The LLC is allowed to

drive these buses only after the LLC has been granted permission to do so by the PHY.

Four operations can occur on the PHY-LLC interface: link service request, status transfer, data transmit, and

data receive. The LLC issues a service request to read or write a PHY register or to request the PHY to gain

control of the serial bus in order to transmit a packet.

The PHY can initiate a status transfer either autonomously or in response to a register read request from the

LLC.

The PHY initiates a receive operation whenever a packet is received from the serial bus.

The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC.

The transmit operation is initiated when the PHY grants control of the interface to the LLC.

Table 23 and Table 24 show the encoding of the CTL0−CTL1 bus.

Table 23. CTL Encoding When PHY Has Control of the Bus

CTL0

CTL1

NAME

Idle

DESCRIPTION

0

1

0

1

0

1

No activity (this is the default mode)

Status

Receive

Grant

Status information is being sent from the PHY to the LLC.

An incoming packet is being sent from the PHY to the LLC.

The LLC has been given control of the bus to send an outgoing packet.

Table 24. CTL Encoding When LLC Has Control of the Bus

CTL0

CTL1

NAME

DESCRIPTION

The LLC releases the bus (transmission has been completed).

An outgoing packet is being sent from the LLC to the PHY.

Reserved

0

1

0

1

0

1

Idle

Transmit

Reserved

Hold/More

The LLC is holding the bus while data is being prepared for transmission, or the LLC is sending a request to

Information

arbitrate for access to the bus, or the LLC is identifying the end of a subaction gap to the PHY.

LLC service request

To request access to the bus, to read or write a PHY register, or to send a link notification to PHY, the LLC sends

a serial bit stream on the LREQ terminal as shown in Figure 23.

LR0

LR1

LR2

LR3

LR (n-2)

LR (n-1)

Each cell represents one clock sample time and n is the number of bits in the request stream.

Figure 23. LREQ Request Stream

The length of the stream varies depending on the type of request as shown in Table 25.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394b INTERFACE)

LLC service request (continued)

Table 25. Request Stream Bit Length

REQUEST TYPE

NUMBER OF BITS

Bus request

11

10

18

6

Read register request

Write register request

Link notification request

PHY-link interface reset request

6

Regardless of the type of request, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0

is required at the end of the stream. The second through fifth bits of the request stream indicate the type of the

request. In the descriptions of Table 26, bit LR1 is the most significant and is transmitted first in the request bit

stream. The LREQ terminal is normally low.

Table 26 shows the encoding for the request type.

Table 26. Request Type Encoding

LR1−LR4

0000

NAME

Reserved

DESCRIPTION

Reserved

0001

Immed_Req

Next_Even

Immediate request. On detection of idle, the PHY arbitrates for the bus.

0010

Next even request. The PHY arbitrates for the bus to send an asynchronous packet in the even fairness

interval phase.

0011

0100

Next_Odd

Current

Next odd request. The PHY arbitrates for the bus to send an asynchronous packet in the odd fairness

interval phase.

Current request. The PHY arbitrates for the bus to send an asynchronous packet in the current fairness

interval.

0101

0110

Reserved

Isoch_Req_Even

Isochronous even request. The PHY arbitrates for the bus to send an isochronous packet in the even

isochronous period.

0111

Isoch_Req_Odd

Isochronous odd request. The PHY arbitrates for the bus to send an isochronous packet in the odd

isochronous period.

1000

1001

1010

1011

1100

Cyc_Start_Req

Reserved

Cycle start request. The PHY arbitrates for the bus to send a cycle start packet.

Reserved

Reg_Read

Reg_Write

Register read request. The PHY returns the specified register contents through a status transfer.

Register write request. Write to the specified register in the PHY.

Isoch_Phase_Even Isochronous phase even notification. The link reports to the PHY that:

1) A cycle start packet has been received.

2) The link has set the isochronous phase to even.

1101

Isoch_Phase_Odd

Isochronous phase odd notification. The link reports to the PHY that:

1) A cycle start packet has been received.

2) The link has set the isochronous phase to odd.

1110

1111

Cycle_Start_Due

Reserved

Cycle start due notification. The link reports to the PHY that a cycle start packet is due for reception.

Reserved

For a bus request, the length of the LREQ bit stream is 11 bits as shown in Table 27.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394b INTERFACE)

LLC service request (continued)

Table 27. Bus Request

BIT(s)

0

NAME

Start bit

DESCRIPTION

Indicates the beginning of the transfer (always 1)

1−4

5

Request type

Request format

Request speed

Stop bit

Indicates the type of bus request. See Table 26.

Indicates the packet format to be used for packet transmission. See Table 28.

Indicates the speed at which the link sends the data to the PHY. See Table 29 for the encoding of this field.

Indicates the end of the transfer (always 0). If bit 6 is 0, then this bit can be omitted.

6−9

10

Table 28 shows the 1-bit request format field used in bus requests.

Table 28. Bus Request Format Encoding

LR5

0

DATA RATE

Link does not request either Beta or legacy packet format for bus transmission

Link requests Beta packet format for bus transmission

1

Table 29 shows the 4-bit request speed field used in bus requests.

Table 29. TBus Request Speed Encoding

LR6−LR9

0000

DATA RATE

S100

0001

Reserved

S200

0010

0011

Reserved

S400

0100

0101

Reserved

S800

0110

All Others

Invalid

NOTE:

The TSB41BA3B-EP accepts a bus request with an invalid speed code and processes the bus

request normally. However, during packet transmission for such a request, the TSB41BA3B-EP

ignores any data presented by the LLC and transmits a null packet.

For a read register request, the length of the LREQ bit stream is 10 bits as shown in Table 30.

Table 30. Read Register Request

BIT(s)

0

NAME

Start bit

DESCRIPTION

Indicates the beginning of the transfer (always 1)

1−4

5−8

9

Request type

Address

A 1010 indicates this is a read register request.

Identifies the address of the PHY register to be read

Indicates the end of the transfer (always 0)

Stop bit

For a write register request, the length of the LREQ bit stream is 18 bits as shown in Table 31.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394b INTERFACE)

LLC service request (continued)

Table 31. Write Register Request

BIT(s)

0

NAME

Start bit

DESCRIPTION

Indicates the beginning of the transfer (always 1)

1−4

5−8

9−16

17

Request type

Address

Data

A 1011 indicates this is a write register request.

Identifies the address of the PHY register to be written

Gives the data that is to be written to the specified register address

Indicates the end of the transfer (always 0)

Stop bit

For a link notification request, the length of the LREQ bit stream is 6 bits as shown in Table 32.

Table 32. Link Notification Request

BIT(s)

NAME

Start bit

DESCRIPTION

Indicates the beginning of the transfer (always 1)

0

1−4

5

Request type

Stop bit

A 1100, 1101, or 1110 indicates this is a link notification request

Indicates the end of the transfer (always 0)

For fair or priority access, the LLC sends a bus request at least one clock after the PHY-LLC interface becomes

idle. The PHY queues all bus requests and can queue one request of each type. If the LLC issues a different

request of the same type, then the new request overwrites any nonserviced request of that type. On the receipt

(CTL terminals are asserted to the receive state, 10b) of a packet, queued requests are not cleared by the PHY.

The cycle master node uses a cycle start request (Cyc_Start_Req) to send a cycle start message. After

receiving or transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The

PHY clears an isochronous request only when the serial bus has been won.

To send an acknowledge packet, the LLC must issue an immediate bus request (Immed_Req) during the

reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of

the received packet and the start of the transmitted acknowledge packet. As soon as the received packet ends,

the PHY immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender

unless the header CRC of the received packet is corrupted. In this case, the LLC does not transmit an

acknowledge, but instead cancels the transmit operation and releases the interface immediately; the LLC must

not use this grant to send another type of packet. After the interface is released the LLC can proceed with

another request.

For write register requests, the PHY loads the specified data into the addressed register as soon as the request

transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the

LLC at the next opportunity through a PHY status transfer. A write or read register request can be made at any

time, including while a bus request is pending. Once a read register request is made, the PHY ignores further

read register requests until the register contents are successfully transferred to the LLC. A bus reset does not

clear a pending read register request.

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394b INTERFACE)

status transfer

A status transfer is initiated by the PHY when status information is to be transferred to the LLC. Two types of

status transfers can occur: bus status transfer and PHY status transfer. Bus status transfers send the following

status information: bus reset indications, subaction and arbitration reset gap indications, cycle start indications,

and PHY interface reset indications. PHY status transfers send the following information: PHY interrupt

indications, unsolicited and solicited PHY register data, bus initialization indications, and PHY-link interface

error indications. The PHY uses a different mechanism to send the bus status transfer and the PHY status

transfer.

Bus status transfers use the CTL0−CTL1 and D0−D7 terminals to transfer status information. Bus status trans-

fers can occur during idle periods on the PHY-link interface or during packet reception. When the status transfer

occurs, a single PCLK cycle of status information is sent to the LLC. The information is sent such that each indi-

vidual Dn terminal conveys a different bus status transfer event. During any bus status transfer, only one status

bit is set. If the PHY-link interface is inactive, then the status information is not sent. When a bus reset on the

serial bus occurs, the PHY sends a bus reset indication (via the CTLn and Dn terminals), cancels all packet

transfer requests, sets asynchronous and isochronous phases to even, forwards self-ID packets to the link, and

sends an unsolicited PHY register 0 status transfer (via the PINT terminal) to the LLC. In the case of a PHY

interface reset operation, the PHY-link interface is reset on the following PCLK cycle.

Table 33 shows the definition of the bits during the bus status transfer and Figure 24 shows the timing.

Table 33. Status Bits

STATUS BIT

DESCRIPTION

D0

D1

D2

D3

D4

D5

D6

D7

Bus reset

Arbitration reset gap—odd

Arbitration reset gap—even

Cycle start—odd

Cycle start—even

Subaction gap

PHY interface reset

Reserved

XX

01

XX

CTL[0:1]

D[0:7]

ST

XX

Status Bits

Figure 24. Bus Status Transfer Timing

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394b INTERFACE)

status transfer (continued)

The PHY status transfers use the PINT terminal to serially send status information to the LLC as shown in

Figure 25. The PHY status transfers (Table 34) can occur at any time during normal operation. The PHY uses

the PHY_INTERRUPT PHY status transfer when required to interrupt the LLC due to a configuration time-out,

a cable power failure, a port interrupt, or an arbitration time-out. When transferring PHY register contents, the

PHY uses either the solicited or the unsolicited register read status transfer. The unsolicited register 0 contents

are passed to the LLC only during initialization of the serial bus. After any PHY-link interface initialization, the

PHY sends a PHY status transfer indicating whether or not a bus reset occurred during the inactive period of

the PHY-link interface. If the PHY receives an illegal request from the LLC, then the PHY issues an

INTERFACE_ERROR PHY status transfer.

LR0

LR1

LR2

LR3

LR (n-2)

LR (n-1)

Each cell represents one clock sample time and n is the number of bits in the request stream.

Figure 25. PINT (PHY Interrupt) Stream

Table 34. PHY Status Transfer Encoding

PI[1:3]

000

NAME

DESCRIPTION

NUMBER OF BITS

NOP

No status indication

5

001

PHY_INTERRUPT

Interrupt indication: configuration time-out, cable power failure, port event

interrupt, or arbitration state machine time-out

010

011

100

101

110

111

PHY_REGISTER_SOL

PHY_REGISTER_UNSOL

PH_RESTORE_NO_RESET

PH_RESTORE_RESET

INTERFACE_ERROR

Reserved

Solicited PHY register read

17

Unsolicited PHY register read

17

PHY-link interface initialized; no bus resets occurred.

PHY-link interface initialized; a bus reset occurred.

PHY received illegal request.

5

Reserved

Most PHY status transfers are 5 bits long. The transfer consists of a start bit (always 1), followed by a request

type (see Table 34), and lastly followed by a stop bit (always 0). The only exception is when the transfer of a

register contents occurs. Solicited and unsolicited PHY register read transfers are 17 bits long and include the

additional information of the register address and the data contents of the register (see Table 35).

Table 35. Register Read (Solicited and Unsolicited) PHY Status Transfer Encoding

BIT(s)

0

NAME

DESCRIPTION

Indicates the beginning of the transfer (always 1)

Start bit

1−3

4−7

8−15

16

Request type

Address

Data

A 010 or a 011 indicates a solicited or unsolicited register contents transfer.

Identifies the address of the PHY register whose contents are being transferred

The contents of the register specified in bits 4 through 7

Stop bit

Indicates the end of the transfer (always 0)

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394b INTERFACE)

receive

When the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting receive

on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates the start

of a packet by placing the speed code (encoded as shown in Table 36) on the D terminals, followed by packet

data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet has been

transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received

packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included

in the calculation of CRC or any other data protection mechanisms.

The PHY may optionally send status information to the LLC at anytime during the data-on indication. Only bus

status transfer information can be sent during a data-on indication. The PHY holds the CTL terminals in the

status state for 1 PCLK cycle and modifies the D terminals to the correct status state. Note that the status transfer

during the data-on indication does not need to be preceded or followed by a data-on indication.

It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed

by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds

the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any

data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D

terminals, followed by Idle on the CTL terminals, without any speed code or data being transferred. In all cases,

in normal operation, the TSB41BA3B-EP sends at least one data-on indication before sending the speed code

or terminating the receive operation.

The TSB41BA3B-EP also transfers its own self-ID packet, transmitted during the self-ID phase of bus

initialization, to the LLC. This packet it transferred to the LLC just as any other received self-ID packet.

PCLK

CTL0, CTL1

D0–D7

10

00

(e)

(a)

(b)

(c)

SPD

(d)

d0

XX

FF (data-on)

dn

00

NOTE A: SPD = Speed code, see Table 36. d0 – dn = Packet data

Figure 26. Normal Packet Reception Timing

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SGLS362—MAY 2006

PRINCIPLES OF OPERATION (1394b INTERFACE)

receive (continued)

PCLK

CTL0, CTL1

10

(a)

01

10

00

(e)

(b)

(c)

(d)

d0

FF

(data-on)

D0–D7

XX

FF (data-on)

STATUS

SPD

dn

00

NOTE A: SPD = Speed code, see Table 36. d0 – dn = Packet data. STATUS = status bits, see Table 33.

Figure 27. Normal Packet Reception Timing With Optional Bus Status Transfer

The sequence of events for a normal packet reception is as follows:

(a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a

status transfer operation that is in progress so that the CTL lines can change from status to receive without

an intervening idle.

(b) Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more cycles

preceding the speed code. The PHY may optionally send a bus status transfer during the data-on indication

for one PCLK cycle. During this cycle, the PHY asserts status (01b) on the CTL lines while sending status

information on the D lines.