V62/05613-01XE [TI]
14 位、125MSPS 模数转换器 (ADC) - 增强型产品 | PAP | 64 | -55 to 125;
| 型号： | V62/05613-01XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14 位、125MSPS 模数转换器 (ADC) - 增强型产品 | PAP | 64 | -55 to 125 转换器 模数转换器 |
| 文件： | 总36页 (文件大小：932K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢌꢒꢊ ꢇꢇ ꢗꢗ ꢈꢘ ꢋ
SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢀꢆ ꢇꢈ ꢉꢊ ꢋꢊ
ꢌ ꢍꢎ ꢏꢐꢑ ꢂ ꢅꢐ ꢂ ꢒꢄ ꢑꢄ ꢅ ꢎꢏ ꢓꢐ ꢍꢔꢕ ꢖ ꢅꢕ ꢖ
D
D
D
D
D
D
One Assembly/Test Site
One Fabrication Site
FEATURES
D
D
D
14-Bit Resolution
125−MSPS Sample Rate
High Signal−to−Noise Ratio (SNR):
70.5 dBFS at 100 MHz f (TYP)
Available in Military (−555C/1255C)
(1)
Temperature Range
Extended Product Life Cycle
Extended Product−Change Notification
Product Traceability
IN
D
High Spurious−Free Dynamic Range (SFDR):
82 dBc at 100−MHz f (TYP)
IN
D
D
D
D
2.3-V Differential Input Voltage
PP
APPLICATIONS
Internal Voltage Reference
3.3-V Single-Supply Voltage
D
D
D
D
Wireless Communication
Test and Measurement Instrumentation
Single and Multichannel Digital Receivers
Analog Power Dissipation: 578 mW
− Total Power Dissipation: 780 mW
D
Serial Programming Interface
Communication Instrumentation
− Radar, Infrared
D
TQFP-64 PowerPADE Package
D
Video and Imaging
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
D
Controlled Baseline
(1)
Custom temperature ranges available.
DESCRIPTION
The ADS5500 is a high-performance, 14-bit 125−MSPS analog-to-digital converter (ADC). To provide a complete
converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed
for applications demanding the highest speed and highest dynamic performance in a small space, the ADS5500 has
excellent power consumption of 780 mW at 3.3-V single-supply voltage. This allows an even higher system
integration density. The provided internal reference simplifies system design requirements. A parallel CMOS-
compatible output ensures seamless interfacing with common logic.
The ADS5500 is available in a 64-pin TQFP PowerPAD package and is specified over the full temperature range of
−55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
ꢋꢙ ꢚ ꢒꢛ ꢓ ꢜꢝ ꢚꢞ ꢒ ꢌꢜꢌ ꢄꢍ ꢟꢐ ꢖ ꢠꢎ ꢅꢄꢐꢍ ꢄꢡ ꢢꢣ ꢖ ꢖ ꢕꢍꢅ ꢎꢡ ꢐꢟ ꢤꢣꢥ ꢏꢄꢢ ꢎꢅꢄ ꢐꢍ ꢦꢎ ꢅꢕꢧ ꢋꢖ ꢐꢦꢣ ꢢꢅꢡ
ꢢ ꢐꢍ ꢟꢐꢖ ꢠ ꢅꢐ ꢡ ꢤꢕ ꢢ ꢄ ꢟꢄ ꢢ ꢎ ꢅꢄ ꢐꢍꢡ ꢤ ꢕꢖ ꢅꢨꢕ ꢅꢕ ꢖ ꢠꢡ ꢐꢟ ꢜꢕꢩ ꢎꢡ ꢝꢍꢡ ꢅꢖ ꢣꢠ ꢕꢍꢅ ꢡ ꢡꢅ ꢎꢍꢦ ꢎꢖ ꢦ ꢪ ꢎꢖ ꢖ ꢎ ꢍꢅꢫꢧ
ꢋꢖ ꢐ ꢦꢣꢢ ꢅ ꢄꢐ ꢍ ꢤꢖ ꢐ ꢢ ꢕ ꢡ ꢡ ꢄꢍ ꢑ ꢦꢐ ꢕ ꢡ ꢍꢐꢅ ꢍꢕ ꢢꢕ ꢡꢡ ꢎꢖ ꢄꢏ ꢫ ꢄꢍꢢ ꢏꢣꢦ ꢕ ꢅꢕ ꢡꢅꢄ ꢍꢑ ꢐꢟ ꢎꢏ ꢏ ꢤꢎ ꢖ ꢎꢠ ꢕꢅꢕ ꢖ ꢡꢧ
Copyright 2008, Texas Instruments Incorporated
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
AV
DD
DRV
DD
CLK+
CLK
CLKOUT
Timing Circuitry
-
D0
V +
IN
Digital
Error
Correction
14-Bit
Pipeline
ADC Core
.
.
.
Output
Control
S&H
V
-
IN
D13
OVR
DFS
Control Logic
Internal
Reference
CM
Serial Programming Register
A D S 5500
DR
A
GND
SCLK
SEN SDATA
GND
(1)
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
PACKAGE LEAD
(2)
HTQFP-64
PowerPAD
ADS5500MPAPEP
ADS5500MPAPREP
Tray, 160
ADS5500−EP
PAP
−55°C to 125°C ADS5500M
Tape and Reel, 1000
(1)
(2)
For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
Thermal pad size: 3,5 mm x 3,5 mm (min), 4 mm x 4 mm (max).
2
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
(1)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
proper handling and installation procedures can cause damage.
ADS5500-EP
UNIT
AV
to
,
DD
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because small parametric changes could cause
the device not to meet its published specifications.
A
DRV
GND
−0.3 to +3.7
V
to
DD
Supply
Voltage
DR
GND
A
DR
to
GND
0.1
V
V
V
GND
RECOMMENDED OPERATING CONDITIONS
Analog input to A
Logic input to DR
−0.15 to +2.5
GND
MIN
TYP
MAX
UNIT
PARAMETER
−0.3to DRV
+ 0.3
DD
GND
Supplies
Analog supply voltage, AV
3
3
3.3
3.3
3.6
3.6
V
V
DD
−0.3to DRV
+ 0.3
DD
Digital data output to DR
Input current (any input)
V
GND
Output driver supply voltage, DRV
Analog Input
DD
30
mA
°C
°C
°C
Operating temperature range
Junction temperature
−55 to +125
+142
Differential input range
2.3
V
PP
Input common-mode voltage,
1.5
1.6
V
(1)
V
CM
Storage temperature range
−65 to +150
Digital Output
Maximum output load
Clock Input
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
10
pF
DLL ON
DLL OFF
60
10
125
80
ADCLK input sample
rate (sine wave) 1/t
C
MSPS
TM
TQFP−64 PowerPAD
Thermal Characteristics
Package
Clock amplitude, sine wave,
(2)
3
V
PP
differential
Clock duty cycle
Open free-air temperature
(3)
50%
SAME
PACKAGE
FORM
PowerPAD NOT
CONNECTED
TO PCB
PowerPAD
CONNECTED
TO PCB
−55
125
°C
PARAMETER
(1)
(2)
(3)
Input common-mode should be connected to CM.
See Figure 14 for more information.
See Figure 13 for more information.
WITHOUT
PowerPAD
THERMAL
PLAN
THERMAL
PLANE
(2)
Thermal
resistance
,
junction to
75.83ºC/W
7.8ºC/W
42.2ºC/W
0.38ºC/W
21.47ºC/W
0.38ºC/W
ambient (see
(1)
(2)
and ),
R
TJA
Thermal
resistance,
junction to
(1)
case (see
(2)
and ), R
TJC
(1)
(2)
Specified with the PowerPAD bond pad on the backside of the
package soldered to a 2-oz Cu plate PCB thermal plane.
Airflow is at 0 LFM (no airflow)
3
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
Long-term high−temperature storage and/or extended use at maximum recommended operating conditions may
result in a reduction of overall device life. See Figure 1 for additional information on thermal derating.
Electromigration failure mode applies to powered part; Kirkendall voiding failure mode is a function of temperature
only.
0.0001
Estimated Device life
ElectroMigration Fail Mode
150 °C (10.5 kHours, 1.2 Years)
150 °C
(21 kHours, 2.4 Years)
125 °C (32 kHours, 3.8 Years)
0.00001
0.000001
0.0000001
105 °C (87 kHours, >10 Years)
125 °C (47 kHours, 55.8 Years)
Estimated Device Life
Wire Bond Kirkendall
Voiding Fail Mode
105 °C (8 MHours, >100 Years)
1/T − Constant Device Junction Temperature
J
Figure 1. Time-to-Failure vs Junction Temperature
4
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS
Typ, min, and max values at T = 25°C, full temperature range is T
= −55°C to T
MAX
= 125°C, sampling rate = 125 MSPS, 50% clock duty
differential clock (unless otherwise noted)
A
MIN
cycle, AV
= DRV
= 3.3 V, DLL On, −1−dBFS differential input, and 3-V
DD
DD
PP
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
14 Tested
Bits
Analog Inputs
Differential input range
2.3
6.6
4
V
PP
kΩ
pF
Differential input impedance
Differential input capacitance
Total analog input common-mode current
Analog input bandwidth
See Figure 5
See Figure 5
(1)
4
mA
MHz
Source impedance = 50 Ω
750
Conversion Characteristics
Maximum sample rate
See note (2)
125
MSPS
Data latency
See timing diagram, See Figure 2
16.5
Clock Cycles
Internal Reference Voltages
Reference bottom voltage, V
REFM
0.97
2.11
V
V
Reference top voltage, V
REFP
Room temp
−4%
−5%
4%
5%
Reference error
Full temp range
Common-mode voltage output, V
CM
1.55 0.05
V
Dynamic DC Characteristics and Accuracy
No missing codes
Tested
0.75
Differential linearity error, DNL
f
f
= 10 MHz
= 10 MHz
−0.9
−5
1.1
5
LSB
LSB
IN
Room temp
Integral linearity error, INL
IN
Full temp range
−8
8
Offset error
1.5
0.0007
0.45
mV
%/°C
%FS
∆%/°C
Offset temperature coefficient
Gain error
Gain temperature coefficient
Dynamic AC Characteristics
0.01
Room temp
70.5
68
71.5
71.5
71.5
71.5
71.2
71
f
= 10 MHz
IN
Full temp range
f
IN
f
IN
= 30 MHz
= 55 MHz
Room temp
70
Signal-to-noise ratio (SNR)
RMS output noise
dBFS
LSB
f
IN
= 70 MHz
Full temp range
66.5
f
f
f
= 100 MHz
= 150 MHz
= 225 MHz
70.5
70.1
69.1
1.1
84
IN
IN
IN
Input tied to common-mode
Room temp
82
76
f
IN
= 10 MHz
Full temp range
84
f
IN
f
IN
= 30 MHz
= 55 MHz
84
79
Room temp
80
75
83
Spurious-free dynamic range (SFDR)
dBc
f
IN
= 70 MHz
Full temp range
82
f
IN
f
IN
f
IN
= 100 MHz
= 150 MHz
= 225 MHz
82
78
74
(1)
(2)
2-mA per input
See Recommended Operating Conditions.
5
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS(continued)
Typ, min, and max values at T = 25°C, full temperature range is T
= −55°C to T
MAX
= 125°C, sampling rate = 125 MSPS, 50% clock duty
differential clock (unless otherwise noted)
A
MIN
cycle, AV
= DRV
= 3.3 V, DLL On, −1−dBFS differential input, and 3-V
DD
DD
PP
PARAMETER
CONDITIONS
MIN
82
TYP
91
MAX
UNIT
Room temp
f
IN
= 10 MHz
Full temp range
77
86
f
IN
f
IN
= 30 MHz
= 55 MHz
86
84
Room temp
80
75
87
Second−harmonic (HD2)
dBc
f
IN
= 70 MHz
Full temp range
83
f
IN
f
IN
f
IN
= 100 MHz
= 150 MHz
= 225 MHz
84
78
74
Room temp
82
77
89
f
IN
= 10 MHz
Full temp range
88
f
IN
f
IN
= 30 MHz
= 55 MHz
90
79
Room temp
80
75
85
Third harmonic (HD3)
dBc
dBc
dBc
f
= 70 MHz
IN
Full temp range
82
f
IN
f
IN
f
IN
f
IN
f
IN
= 100 MHz
= 150 MHz
= 225 MHz
82
80
76
= 10 MHz Room temp
= 70 MHz Room temp
88
Worst-harmonic/spur
(other than HD2 and HD3)
86
Room temp
= 10 MHz
69
70
f
IN
Full temp range
66.5
70
f
IN
f
IN
= 30 MHz
= 55 MHz
70
69.5
69
Room temp
68.5
65
Signal-to-noise + distortion (SINAD)
f
IN
= 70 MHz
Full temp range
69.5
69
f
IN
f
IN
f
IN
= 100 MHz
= 150 MHz
= 225 MHz
69
66.4
85
Room temp
80
76
f
IN
= 10 MHz
Full temp range
83
f
IN
f
IN
= 30 MHz
= 55 MHz
82
77
Room temp
77.5
74
81
Total harmonic distortion (THD)
dBc
f
= 70 MHz
IN
Full temp range
79.5
79
f
IN
f
IN
f
IN
= 100 MHz
= 150 MHz
= 225 MHz
75
71.8
6
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
ELECTRICAL CHARACTERISTICS(continued)
Typ, min, and max values at T = 25°C, full temperature range is T
= −55°C to T
MAX
= 125°C, sampling rate = 125 MSPS, 50% clock duty
differential clock (unless otherwise noted)
A
MIN
cycle, AV
= DRV
= 3.3 V, DLL On, −1−dBFS differential input, and 3-V
DD
DD
PP
PARAMETER
CONDITIONS
= 70 MHz
MIN
TYP
MAX
UNIT
Effective number of bits (ENOB)
Two-tone intermodulation distortion (IMD)
Power Supply
f
IN
11.3
Bits
f = 10.1 MHz, 15.1 MHz
(−7 dBFS each tone)
85
85
88
f = 30.1 MHz, 35.1 MHz
(−7 dBFS each tone)
dBc
f = 50.1 MHz, 55.1 MHz
(−7 dBFS each tone)
V
= full-scale, f = 5 5 MHz,
IN
IN
AV
Total supply current, I
CC
236
175
265
190
mA
mA
= DRV
= 3.3V
DD
DD
V
IN
AV
= full-scale, f = 5 5 MHz,
IN
= 3.3V
Analog supply current, I
AVDD
= DRV
DD
DD
V
= full-scale, f = 55 MHz,
= DRV
DD
IN
AV
IN
= 3.3 V
Output buffer supply current, I
61
75
mA
mW
mW
mW
DRVDD
DD
Analog only
578
780
181
627
875
250
Power dissipation
Standby power
Total power with 10−pF load on
digital output to ground
With clocks running
DIGITAL CHARACTERISTICS
Typ, min, and max values at T = 25°C, full temperature range is T
= −55°C to T
= 125°C, sampling rate = 125 MSPS, 50% clock duty
differential clock (unless otherwise noted)
A
MIN MAX
cycle, AV
= DRV
= 3.3 V, DLL On, −1 dBFS differential input, and 3-V
DD
DD
PP
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Digital Inputs
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Input current for RESET
Input capacitance
2.4
V
0.8
10
10
V
µA
µA
µA
pF
−20
4
(1)
Digital Outputs
(2)
= 10 pF , f = 125 MSPS
Low-level output voltage
High-level output voltage
Output capacitance
C
LOAD
C
LOAD
0.3
3
V
V
S
(2)
= 10 pF , f = 125 MSPS
S
3
pF
(1)
(2)
For optimal performance, all digital output lines (D0:D13), including the output clock, should see a similar load.
Equivalent capacitance to ground of (load + parasitics of transmission lines)
7
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TIMING CHARACTERISTCS
N + 4
N + 3
N + 2
Analog
Input
Signal
Sample
N
N + 1
N + 17
N + 16
N + 15
t
PDI
t
A
Input Clock
t
SETUP
Output Clock
t
HOLD
N
17
N
16
N
15
N
13
N
3
N
2
N 1
-
N
-
-
-
-
-
-
Data Out
(D0−D13)
Data Invalid
16.5 Clock Cycles
NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing
matches closely with the specified values.
Figure 2. Timing Diagram
(1)
TIMING CHARACTERISTICS
Typ, min, and max values at T = 25°C, min and max specified over the full recommended operating temperature range,
A
AV
DD
= DRV
DD
= 3.3 V, 3−V
PP
differential clock, and C = 10 pF (unless otherwise noted)
LOAD
PARAMETER
Switching Specification
Aperture delay, t
DESCRIPTION
TYP
UNIT
Input CLK falling edge to data sampling point
Uncertainty in sampling instant
1
ns
fs
A
Aperture jitter (uncertainty)
Data setup time, t
300
2.5
2.1
(2)
Data valid to 50% of CLKOUT rising edge
ns
ns
SU
(2)
Data hold time, t
50% of CLKOUT rising edge to data becoming invalid
h
Input clock to output data valid
(3)(4),
Input clock rising edge to Data valid start delay
2.2
ns
start
t
START
Input clock to output data valid
(3)(4),
Input clock rising edge to Data valid end delay
6.9
150
1.7
ns
ps
ns
end
t
END
Output clock jitter, t
JIT
Uncertainty in CLKOUT rising edge, peak−to−peak
Rise time of CLKOUT measured from 20% to 80% of
DRVDD
Output clock rise time, t
r
Fall time of CLKOUT measured from 80% to 20% of
DRVDD
Output clock fall time, t
1.5
4.8
ns
ns
f
Input clock to output clock delay, Input clock rising edge, zero crossing, to output clock
rising edge 50%
t
PDI
Data rise time, t
Data rise time measured from 20% to 80% of DRVDD
Data fall time measured from 80% to 20% of DRVDD
3.6
2.8
ns
ns
r
Data fall time, t
f
Latency Time for a sample to
propagate to the ADC outputs
17.5 clock cycles
17.5
Clock Cycles
(1)
(2)
(2)
(4)
Timing parameters are ensured by design and characterization and not tested in production.
Data valid refers to 2 V for LOGIC high and 0.8 V for LOGIC low.
See the Output Information section for details on using the input clock for data capture.
These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3). Add one−half clock period for the valid number
for a falling−edge CLKOUT polarity.
8
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RESET TIMING CHARACTERISTICS
Typ, min, and max values at T = 25°C, min and max specified over the full recommended operating temperature range,
A
AV
DD
= DRV
DD
= 3.3 V, 3−V
PP
differential clock (unless otherwise noted)
PARAMETER
DESCRIPTION
TYP
UNIT
Switching Specification
Delay from power−up of AV
stable
and DRV to output
DD
DD
Power−up time
40
ms
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The device has a three-wire serial interface. The device
latches the serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
D
D
D
Data is loaded at every 16th SCLK falling edge
while SEN is low.
In case the word length exceeds a multiple of
16 bits, the excess bits are ignored.
D
D
Serial shift of bits is enabled when SEN is low.
SCLK shifts serial data at falling edge.
Data can be loaded in multiple of 16-bit words within
a single active SEN pulse.
Minimum width of data stream for a valid loading is
16 clocks.
A3
A2
A1
A0
D11
D10
D9
D0
SDATA
ADDRESS
DATA
MSB
t
Figure 3. DATA Communication Is 2 Byte, MSB First
SLOADS
t
SLOADH
SEN
t
t
t
SCLK
WSCLK
WSCLK
SCLK
t
t
OH
OS
SDATA
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
(1)
MIN
(1)
TYP
(1)
MAX
SYMBOL
PARAMETER
UNIT
t
SCLK period
50
25%
8
ns
SCLK
t
SCLK duty cycle
50%
75%
WSCLK
t
SEN to SCLK setup time
SCLK to SEN hold time
Data setup time
ns
ns
ns
ns
SLOADS
t
6
SLOADH
t
8
DS
t
Data hold time
6
DH
(1)
Min, typ, and max values are characterized, but not production tested.
9
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
Table 2. Serial Register Table
A3 A2 A1 A0 D11
D10
D9
D8 D7 D6 D5 D4 D3 D2
D1
D0
DESCRIPTION
1
1
0
1
0
0
0
0
0
0
0
0
0
0
DLL
OFF
0
DLL OFF = 0: Internal DLL is on, recommended for
60−125 MSPS clock speed
DLL OFF = 1: Internal DLL is off, recommended for
10−80 MSPS clock speed
1
1
1
0
0
TP<1> TP<0>
0
0
0
0
0
0
0
0
0
0
0
TP<1:0>: Test modes for output data capture
TP<1> = 0, TP<0> = 0: Normal mode of operation,
TP<1> = 0
TP<0> = 1: All output lines are pulled to ’0’, TP<1> = 1
TP<0> = 0: All output lines are pulled to ’1’, TP<1> = 1
TP<0> = 1: A continuous stream of ’10’ comes out on
all output lines
1
1
1
1
PDN
0
0
0
0
0
0
0
0
0
PDN = 0: Normal mode of operation,
PDN = 1: Device is put in power down (low current)
mode
10
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Table 3. DATA FORMAT SELECT (DFS TABLE)
DFS-PIN VOLTAGE (V
)
DATA FORMAT
CLOCK OUTPUT POLARITY
DFS
1
6
Straight binary
Data valid on rising edge
V
t
AV
DD
1
DFS
5
12
Twos complement
Straight binary
Data valid on rising edge
Data valid on falling edge
Data valid on falling edge
AV
u V
u
AV
DD
DD
DD
DFS
3
2
3
7
12
AV
u V
u
AV
DD
DFS
5
6
Twos complement
V
u
AV
DD
DFS
PIN CONFIGURATION
PAP PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
DR
GND
DR
GND
SCLK
SDATA
SEN
47 D3
3
46
45
D2
D1
4
AV
DD
5
44 D0 (LSB)
43 CLKOUT
A
GND
6
AV
7
42 DR
GND
DD
A D S 5500
8
41
40
39
A
GND
OE
Po w erP A D
9
AV
DD
DFS
(Connected to Analog Ground)
10
CLKP
AV
DD
CLKM 11
38 A
GND
12
13
14
15
16
37
36
A
AV
DD
GND
A
GND
A
GND
A
35 RESET
GND
AV
34 AV
DD
DD
33
A
GND
AV
DD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
11
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PIN ASSIGNMENTS
TERMINAL
NO.
OF PINS
12
NAME
NO.
I/O
DESCRIPTION
AV
5, 7, 9, 15, 22, 24, 26,
28, 33, 34, 37, 39
I
Analog power supply
Analog ground
DD
A
GND
6, 8, 12, 13, 14, 16, 18,
21, 23, 25, 27, 32, 36, 38
14
I
DRV
49, 58
2
6
1
1
1
I
I
Output driver power supply
Output driver ground
DD
DR
1, 42, 48, 50, 57, 59
GND
INP
19
20
29
I
Differential analog input (positive)
Differential analog input (negative)
INM
I
REFP
O
Reference voltage (positive), 0.1-µF capacitor in series with a 1-Ω
resistor to GND
REFM
30
1
O
Reference voltage (negative), 0.1-µF capacitor in series with a
1-Ω resistor to GND
IREF
31
1
1
I
O
I
Current set, 56-kΩ resistor to GND, do not connect capacitors
CM
17
Common-mode output voltage
RESET
OE
35
1
Reset (active high), 200-kΩ resistor to AV
DD
41
1
I
Output enable (active high)
(1)
Data format and clock out polarity select
DFS
40
1
I
CLKP
10
1
I
Data converter differential input clock (positive)
Data converter differential input clock (negative)
Serial interface chip select
CLKM
11
1
I
SEN
4
1
I
SDATA
SCLK
3
1
I
Serial interface data
2
1
I
Serial interface clock
D0 (LSB)−D13 (MSB)
OVR
44−47, 51−56, 60−63
14
1
O
O
O
Parallel data output
64
43
Over-range indicator bit
CLKOUT
1
CMOS clock out in sync with data
:
NOTE PowerPAD is connected to analog ground.
(1)
The DFS pin is programmable to four discrete voltage levels: 0, 3/8 AV , 5/8 AV , and AV . The thresholds are centered. More details are
DD DD DD
listed in Table 3 on page 11.
12
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
Integral Nonlinearity (INL)
The analog input frequency at which the spectral power of
the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB
The deviation of the transfer function from a reference line
measured in fractions of one LSB using a best straight line
or best fit determined by a least square curve fit. INL is
independent from effects of offset, gain, or quantization
errors.
Aperture Delay
The delay in time between the falling edge of the input
sampling clock and the actual time at which the sampling
occurs
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
This is the maximum sampling rate where certified
operation is given.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay
Minimum Conversion Rate
Clock Pulse Width/Duty Cycle
The minimum sampling rate where the ADC still works.
A perfect differential sine−wave clock results in a 50%
clock duty cycle on the internal coversion clock. Pulse
width high is the minimum amount of time that the
ENCODE pulse should be left in logic 1 state to achieve
rated performance. Pulse width low is the minimum time
that the ENCODE pulse should be left in a low state (logic
0). At a given clock rate, these specifications define an
acceptable clock duty cycle.
Nyquist Sampling
When the sampled frequencies of the analog input signal
are below fCLOCK/2, it is called Nyquist sampling. The
Nyquist frequency is fCLOCK/2, which can vary depending
on the sample rate (fCLOCK).
Offset Error
The deviation of output code from mid-code when both
inputs are tied to common-mode
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly one
LSB apart. DNL is the deviation of any single LSB
transition at the digital output from an ideal one LSB step
at the analog input. If a device claims to have no missing
codes, it means that all possible codes (for a 14-bit
converter, 16384 codes) are present over the full operating
range.
Propagation Delay
The delay between the input clock rising edge and the time
when all data bits are within valid logic levels
Signal-to-Noise and Distortion (SINAD)
The RMS value of the sine wave fIN (input sine wave for an
ADC) to the RMS value of the noise of the converter from
DC to the Nyquist frequency, including harmonic content.
It is typically expressed in decibels (dB). SINAD includes
harmonics, but excludes DC.
Effective Number of Bits (ENOB)
The effective number of bits for a sine−wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
Input(VS )
SINAD + 20Log
(10) Noise ) Harmonics
SINAD * 1.76
ENOB +
6.02
Signal-to-Noise Ratio (Without Harmonics)
If SINAD is not known, SNR can be used exceptionally to
calculate ENOB (ENOBSNR).
SNR is a measure of signal strength relative to background
noise. The ratio is usually measured in dB. If the incoming
signal strength in µV is VS, and the noise level (also in µV)
is VN, the SNR in dB is given by the formula:
Effective Resolution Bandwidth
The highest input frequency where the SNR (dB) is
dropped by 3 dB for a full-scale input amplitude
VS
(10) VN
SNR + 20Log
Gain Error
The amount of deviation between the ideal transfer
function and the measured transfer function (with the offset
error removed) when a full-scale analog input voltage is
applied to the ADC, resulting in all ones in the digital code.
Gain error is usually given in LSB or as a percent of
full-scale range (%FSR).
This is the ratio of the RMS signal amplitude, VS (set one
dB below full-scale), to the RMS value of the sum of all
other spectral components, VN, excluding harmonics and
dc.
13
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Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
The ratio of the RMS value of the analog input sine wave
to the RMS value of the peak spur observed in the
frequency domain. It may be reported in dBc (that is, it
degrades as signal levels are lowered), or in dBFS (always
related back to converter full-scale). The peak spurious
component may or may not be a harmonic.
The ratio of the RMS signal amplitude of the input sine
wave to the RMS value of distortion appearing at multiples
(harmonics) of the input, typically given in dBc
Two-Tone Intermodulation Distortion Rejection
The ratio of the RMS value of either input tone (f1, f2) to the
RMS value of the worst third-order intermodulation
product (2f1 − f2; 2f2 − f1). It is reported in dBc.
Temperature Drift
Temperature drift (for offset error and gain error) specifies
the maximum change from the initial temperature value to
the value at TMIN or TMAX
.
14
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TYPICAL CHARACTERISTICS
Typical values are at T = 25°C, AV
otherwise noted)
= DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
DD
A
DD
SPECTRAL PERFORMANCE
(FFT for 2MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 15MHz Input Signal)
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFDR = 84.0dBc
SNR = 71.2dBFS
THD = 84.0dBc
SFDR = 84.8dBc
SNR = 71.5dBFS
THD = 83.2dBc
SINAD = 71.0dBFS
SINAD = 71.2dBFS
-
-
100
110
120
130
140
100
110
120
130
140
-
-
-
-
-
-
-
-
0
0
0
10
20
30
40
50
50
50
60
60
60
0
0
0
10
20
30
40
50
50
50
60
60
60
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE
(FFT for 60MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 70MHz Input Signal)
0
0
-
-
-
-
-
-
-
-
-
-
10
20
30
40
50
60
70
80
90
100
110
120
130
140
10
20
30
40
50
60
70
80
90
100
110
120
130
140
SFDR = 85.1dBc
SNR = 71.4dBFS
THD = 83.6dBc
SFDR = 81.0dBc
SNR = 71.2dBFS
THD = 80.2dBc
-
-
-
-
-
-
-
-
SINAD = 71.1dBFS
SINAD = 70.7dBFS
-
-
-
-
-
-
-
-
-
-
10
20
30
40
10
20
30
40
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE
(FFT for 80MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 100MHz Input Signal)
0
0
-
-
-
-
-
-
-
-
-
-
10
20
30
40
50
60
70
80
90
100
110
120
130
140
10
20
30
40
50
60
70
80
90
100
110
120
130
140
SFDR = 84.3dBc
SNR = 71.1dBFS
THD = 81.6dBc
SFDR = 84.4dBc
SNR = 71.2dBFS
THD = 81.3dBc
-
-
-
-
-
-
-
-
SINAD = 70.7dBFS
SINAD = 70.9dBFS
-
-
-
-
-
-
-
-
-
-
10
20
30
40
10
20
30
40
Frequency (MHz)
Frequency (MHz)
15
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TYPICAL CHARACTERISTICS (continued)
Typical values are at T = 25°C, AV
otherwise noted)
= DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
DD
A
DD
SPECTRAL PERFORMANCE
(FFT for 150MHz Input Signal)
SPECTRAL PERFORMANCE
(FFT for 225MHz Input Signal)
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SFDR = 73.0dBc
SNR = 69.1dBFS
THD = 70.0dBc
SFDR = 77.8dBc
SNR = 70.0dBFS
THD = 75.3dBc
SINAD = 69.0dBFS
SINAD = 66.5dBFS
-
-
100
110
120
130
140
100
110
120
130
140
-
-
-
-
-
-
-
-
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
SPECTRAL PERFORMANCE
(FFT for 300MHz Input Signal)
TWO−TONE INTERMODULATION
0
0
-
10
20
30
40
50
60
70
80
90
SFDR = 67.4dBc
SNR = 68.0dBFS
THD = 64.7dBc
-
-
-
-
-
-
-
-
-
-
-
-
20
40
60
80
SINAD = 63.0dBFS
-
-
-
-
100
110
120
130
140
100
120
140
-
-
-
-
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
TWO−TONE INTERMODULATION
TWO−TONE INTERMODULATION
0
0
-
-
-
-
-
-
-
-
20
40
60
80
20
40
60
80
-
-
-
-
100
120
140
100
120
140
-
-
0
10
20
30
40
50
60
0
10
20
30
40
50
60
Frequency (MHz)
Frequency (MHz)
16
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TYPICAL CHARACTERISTICS (continued)
Typical values are at T = 25°C, AV
otherwise noted)
= DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
DD
A
DD
DIFFERENTIAL NONLINEARITY (DNL)
INTEGRAL NONLINEARITY (INL)
1.50
1.25
1.00
0.75
0.50
0.25
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.25
0.50
0.75
1.00
1.25
1.50
fS = 125MSPS
fIN = 10MHz
-
= 0.5dBFS
AIN
Code
Code
SPURIOUS−FREE DYNAMIC RANGE vs
INPUT FREQUENCY
SIGNAL−TO−NOISE RATIO vs INPUT FREQUENCY
90
85
80
75
70
65
60
55
50
76
74
72
70
68
66
64
62
60
fS = 125MSPS
DLL On
fS = 125MSPS
DLL On
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Input Frequency (MHz)
Input Frequency (MHz)
AC PERFORMANCE vsANALOG SUPPLY VOLTAGE
AC PERFORMANCE vsANALOG SUPPLY VOLTAGE
SFDR
90
85
80
75
70
65
60
90
85
80
75
70
65
60
SFDR
SNR
SNR
fS = 125MSPS
fIN = 70MHz
DRVDD = 3.3V
fS = 125MSPS
fIN = 150MHz
DRVDD = 3.3V
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
AVDD (V)
AVDD (V)
17
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TYPICAL CHARACTERISTICS (continued)
Typical values are at T = 25°C, AV
otherwise noted)
= DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
DD
A
DD
AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE
SFDR
AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE
SFDR
79
78
77
76
75
74
73
72
71
70
69
84
82
80
78
76
74
72
70
fS = 125MSPS
fIN = 150MHz
AVDD = 3.3V
fS = 125MSPS
fIN = 70MHz
AVDD = 3.3V
SNR
SNR
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
DRVDD (V)
DRVDD (V)
POWER DISSIPATION vs SAMPLE RATE
POWER DISSIPATION vs SAMPLING FREQUENCY
800
750
700
650
600
550
500
850
800
750
700
650
600
550
500
AVDD = DRVDD = 3.3V
fIN = 150MHz
fIN = 70MHz
DLL On
DLL Off
10 20 30 40 50 60 70 80 90 100 110 120
Sampling Frequency (MSPS)
10
30
50
70
90
110
130
150
Sample Rate (MSPS)
SIGNAL−TO−NOISE RATIO AND
SPURIOUS−FREE DYNAMIC RANGE vs TEMPERATURE
AC PERFORMANCE vs INPUT AMPLITUDE
SNR (dBFS)
90
80
70
60
50
40
30
20
10
0
90
85
80
75
70
65
60
SFDR
SFDR (dBc)
SNR (dBc)
SNR
fS = 125MSPS
fIN = 70MHz
DLL On
fS = 125MSPS
fIN = 70MHz
DLL On
-
10
20
-
-
30
-
-
-
-
-
-
-
-
-
-
20 10
100 90
80
70
60
50
40
30
0
-
40
0
25
Temperature ( C)
40
85
InputAmplitude (dBFS)
_
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TYPICAL CHARACTERISTICS (continued)
Typical values are at T = 25°C, AV
otherwise noted)
= DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
DD
A
DD
AC PERFORMANCE vs INPUT AMPLITUDE
SNR (dBFS)
AC PERFORMANCE vs INPUT AMPLITUDE
SNR (dBFS)
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
SFDR (dBc)
SFDR (dBc)
SNR (dBc)
SNR (dBc)
fS = 125MSPS
fS = 125MSPS
f IN = 220MHz
DLL On
-
-
-
-
-
-
10
20
10
20
30
fIN = 150MHz
DLL On
30
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
100 90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
0
InputAmplitude (dBFS)
InputAmplitude (dBFS)
AC PERFORMANCE vs CLOCK AMPLITUDE
SFDR
OUTPUT NOISE HISTOGRAM
90
85
80
75
70
65
60
55
50
40
35
30
25
20
15
10
5
SNR
fS = 125MSPS
fIN = 70MHz
0
0
0.5
1.0
1.5
2.0
2.5
3.0
Differential Clock Amplitude (V)
Output Code
WCDMA TONE
0
20
40
60
80
fS = 150MSPS
fIN = 125MHz
-
-
-
-
-
-
-
100
120
140
0
10
20
30
40
50
60
Frequency (MHz)
19
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at T = 25°C, AV
otherwise noted)
= DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
DD
A
DD
SIGNAL−TO−NOISE RATIO (SNR) WITH DLL ON
150
140
130
120
110
100
90
73
72
71
70
69
68
67
66
71
71
69
71
69
72
70
69
68
72
71
80
68
73
69
73
70
70
60
70
72
69
50
71
72
69
67
68
40
0
50
100
150
Input Frequency (MHz)
200
250
300
SIGNAL−TO−NOISE RATIO (SNR) WITH DLL OFF
80
70
60
50
40
30
20
10
71
70
69
72
70
68
66
64
62
60
73
72
73
69
68
70
71
67
72
73
68
69
67
73
66
64
70
71
65
71
66
69
67
63
72
50
68
62
0
100
150
Input Frequency (MHz)
200
250
300
20
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at T = 25°C, AV
otherwise noted)
= DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On( unless
DD
A
DD
SPURIOUS−FREE DYNAMIC RANGE (SFDR) WITH DLL ON
150
140
130
120
110
100
90
83
77
71
68
80
77
80
85
80
75
70
65
83
83
74
77
86
83
86
71
80
68
86
74
77
80
83
89
70
83
86
80
60
89
71
86
68
83
50
74
77
40
0
50
100
150
200
250
300
Input Frequency (MHz)
SPURIOUS−FREE DYNAMIC RANGE (SFDR) WITH DLL OFF
80
70
60
50
40
30
20
10
88
86
84
82
80
78
76
74
72
70
68
66
70
78
80
88
82
84
84
88
74
86
76
86
88
86
72
78
70
68
80
86
86
76
82
78
74
72
84
88
80
70
86
84
68
76
74
72
82
70
0
50
100
150
Input Frequency (MHz)
200
250
300
21
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at T = 25°C, AV
otherwise noted)
= DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
DD
A
DD
SECOND HARMONIC (HD2) WITH DLL ON
150
86
95
98
83
77
68
86
83
80
140
130
120
110
100
90
86
95
90
85
80
75
70
65
71
89
89
92
92
86
86
89
74
92
77
80
89
89
83
86
86
86
95
71
92
92
89
80
77
74
98
89
86
83
92
89
83
80
68
74
71
95
77
98
70
86
89
98
60
92
95
83
95
98
92
68
50
89
74
92
71
86
80
77
95
40
0
50
100
150
Input Frequency (MHz)
200
250
300
SECOND HARMONIC (HD2) WITH DLL OFF
80
70
60
50
40
30
20
10
90
84
68
87
81
93
96
95
93
96
99
78
90
85
80
75
70
75
99
72
87
68
84 81
93
99
99
96
90
99
78
72
75
99
87
84
81
93
68
78
72
87
84
75
0
50
100
150
Input Frequency (MHz)
200
250
300
22
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS (continued)
Typical values are at T = 25°C, AV
otherwise noted)
= DRV = 3.3 V, differential input amplitude = −1 dBFS, sampling rate = 125 MSPS, and DLL On (unless
DD
A
DD
THIRD HARMONIC (HD3) WITH DLL ON
150
83
77
80
71
68
71
74
90
85
80
75
70
65
140
89
86
86
86
130
120
110
100
90
86
83
89
83
80
77
77
74
86
77
83
80
86
83
86
89
80
92
89
70
86
86
92
60
86
83
50
83
89
86
89
40
0
50
100
150
Input Frequency (MHz)
200
250
300
THIRD HARMONIC (HD3) WITH DLL OFF
80
90
87
87
90
84
78
81
90
87
70
60
50
40
30
20
10
84
78
85
80
75
70
84
72
75
78
84 81
87
72
75
87
84
84
81
81
90
78
84
72
72
75
87
0
50
100
150
Input Frequency (MHz)
200
250
300
23
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
APPLICATION INFORMATION
through the pipeline every half clock cycle. This process
results in a data latency of 16.5 clock cycles, after which
the output data is available as a 14-bit parallel word,
coded in either straight offset binary or binary
twos−complement format.
THEORY OF OPERATION
The ADS5500 is a low-power, 14-bit, 125−MSPS,
CMOS, switched−capacitor, pipeline ADC that
operates from a single 3.3-V supply. The conversion
process is initiated by a falling edge of the external input
clock. Once the signal is captured by the input S&H, the
input sample is sequentially converted by a series of
small resolution stages, with the outputs combined in a
digital correction logic block. Both the rising and the
falling clock edges are used to propagate the sample
INPUT CONFIGURATION
The analog input for the ADS5500 consists of a
differential architecture implemented using a switched
capacitor technique, shown in Figure 5.
SAMPLE
W3a
SAMPLE
PHASE
PHASE
W1a
L1
R1a
C1a
INP
CP1
CP3
R3
SAMPLE
PHASE
W2
CACROSS
SWITCH
L2
R1b
C1b
VINCM
1V
INM
CP2
W1b
CP4
SAMPLE
PHASE
SAMPLE
PHASE
W3a
L1, L2 : 6nh to 10nh effective
W
W
R1a, R1b : 25 to 35
C1a, C1b : 2.2pF to 2.6pF
CP1, CP2 : 2.5pF to 3.5pF
CP3, CP4, : 1.2pF to 1.8pF
CACROSS : 0.8pF to 1.2pF
W
W
R3 : 80 to 120
Switches:
W
W
W
W1a, W1b : On Resistance: 25 to 35
W
W
W2 : On Resistance: 7.5 to 15
W
3a, W3b : On Resistance: 40 to 60
1a, W1b, W2, W3a, W3b : Off Resistance: 1e10
W
W
All switches are on in sample phase.
Approximately half of every clock period is a sample phase.
Figure 5. Analog Input Stage
24
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
This differential input topology produces a high level of
ac performance for high sampling rates. It also results
in a high usable input bandwidth, especially important
for high intermediate frequency (IF) or undersampling
applications. The ADS5500 requires each of the analog
inputs (INP, INM) to be externally biased around the
common-mode level of the internal circuitry (CM, pin
17). For a full-scale differential input, each of the
differential lines of the input signal (pins 19 and 20)
swings symmetrically between CM + 0.575 V and CM
– 0.575 V. This means that each input is driven with a
signal of up to CM 0.575 V, so that each input has a
4mA fs
125MSPS
(1)
Where: f > 60 MSPS.
S
This equation designs the output capability and
impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the
incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF
transformer or to use a differential input/output amplifier
without a transformer to drive the input of the ADS5500.
Texas Instruments offers
a
wide selection of
single-ended operational amplifiers (including the
THS3201, THS3202, OPA847, and OPA695) that can
be selected, depending on the application. An RF gain
block amplifier, such as the TI THS9001, can also be
used with an RF transformer for very high input
frequency applications. The THS4503 is
recommended differential input/output amplifier.
Table 4 lists the recommended amplifiers.
maximum differential signal of 1.15 V
for a total
PP
differential input signal swing of 2.3 V . The maximum
PP
swing is determined by the two reference voltages − the
top reference (REFP, pin 29), and the bottom reference
(REFM, pin 30).
a
The ADS5500 obtains optimum performance when the
analog inputs are driven differentially. The circuit shown
in Figure 6 shows one possible configuration using an
RF transformer.
When using single-ended operational amplifiers (such
as the THS3201, THS3202, OPA847, or OPA695) to
provide gain, a three-amplifier circuit is recommended
with one amplifier driving the primary of an RF
transformer and one amplifier in each of the legs of the
secondary driving the two differential inputs of the
ADS5500. These three amplifier circuits minimize
even-order harmonics. For high frequency inputs, an
RF gain block amplifier can be used to drive a
transformer primary; in this case, the transformer
secondary connections can drive the input of the
ADS5500 directly (see Figure 6) or with the addition of
the filter circuit (see Figure 7).
R0
Z0
W
50
W
50
INP
1:1
R
50
AC Signal
Source
ADS5500
INM
W
CM
ADT1−1WT
W
10
m
0.1 F
1nF
Figure 7 shows how RIN and CIN can be placed to isolate
the signal source from the switching inputs of the ADC
and to implement a low-pass RC filter to limit the input
noise in the ADC. It is recommended that these
components be included in the ADS5500 circuit layout
when any of the amplifier circuits discussed previously
are used. The components allow fine tuning of the
circuit performance. Any mismatch between the
differential lines of the ADS5500 input produces a
degradation in performance at high input frequencies,
mainly characterized by an increase in the even-order
harmonics. In this case, special care should be taken to
keep as much electrical symmetry as possible between
both inputs.
Figure 6. Transformer Input to Convert
Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of
an RF transformer. Since the input signal must be
biased around the common-mode voltage of the
internal circuitry, the common-mode voltage (V ) from
CM
the ADS5500 is connected to the center tap of the
secondary winding. To ensure a steady low-noise V
reference, best performance is obtained when the CM
(pin 17) output is filtered to ground with 0.1−µF and
0.01-µF low-inductance capacitors.
CM
Output V
(pin 17) is designed to directly drive the
CM
Another possible configuration for lower-frequency
signals is the use of differential input/output amplifiers
that can simplify the driver circuit for applications
requiring dc coupling of the input. Flexible in their
configurations (see Figure 8), such amplifiers can be
used for single-ended-to-differential conversion signal
amplification.
ADC input. When providing a custom CM level, be
aware that the input structure of the ADC sinks a
common-mode current in the order of 4 mA (2 mA per
input). Equation 1 describes the dependency of the
common-mode current and the sampling frequency:
25
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
Table 4. Recommended Amplifiers to Drive Input of ADS5500
INPUT SIGNAL FREQUENCY
DC to 20 MHz
RECOMMENDED AMPLIFIER
TYPE OF AMPLIFIER
Differential in/out amplifier
Operational amplifier
Operational amplifier
Operational amplifier
Operational amplifier
RF gain block
USE WITH TRANSFORMER?
(1)
(1)
(1)
(1)
(1)
(1)
THS4503
OPA847
OPA695
THS3201
THS3202
THS9001
No
Yes
Yes
Yes
Yes
Yes
DC to 50 MHz
10 MHz to 120 MHz
Over 100 MHz
(1)
Potential EP devices
-
+5V 5V
RS
RIN
W
100
m
0.1 F
VIN
1:1
INP
OPA695
R1
RT
100
CIN
ADS5500
CM
1000pF
RIN
W
INM
W
400
AV = 8V/V
(18dB)
R2
57.5
W
10
W
m
0.1 F
Figure 7. Converting Single-Ended Input Signal to Differential Signal Using an RF Transformer
RS
RG
RF
+5V
RT
+3.3V
m
m
0.1 F
10 F
RIN
RIN
INP
ADS5500
14−Bit/125MSPS
VOCM
INM
m
1 F
THS4503
CM
m
m
0.1 F
10 F
W
10
-
5V
RG
RF
m
0.1 F
Figure 8. Using THS4503 With ADS5500
the same time works without any problem. If this
sequence is not followed, the device may stay in
power-down mode.
POWER−SUPPLY SEQUENCE
The ADS5500 requires a power-up sequence where the
DRV
supply must be at least 0.4 V by the time the
DD
AV
supply reaches 3 V. Powering up both supplies at
DD
26
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SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
POWER DOWN
CLOCK INPUT
The device enters power down in one of two ways −
either by reducing the clock speed to between dc and
1 MHz, or by setting a bit through the serial
programming interface. Using the reduced clock speed,
the power down may be initiated for clock frequencies
below 10 MHz. For clock frequencies between 1 MHz
and 10 MHz, this can vary from device to device, but will
power down for clock speeds below 1 MHz.
The ADS5500 clock input can be driven with either a
differential clock signal or a single-ended clock input,
with little or no difference in performance between both
configurations. The common-mode voltage of the clock
inputs is set internally to CM (pin 17) using internal 5-kΩ
resistors that connect CLKP (pin 10) and CLKM (pin 11)
to CM (pin 17) (see Figure 10).
CM
CM
The device can be powered down by programming the
internal register (see Serial Programming Interface
section). The outputs become 3-stated and only the
internal reference is powered up to shorten the
power-up time. The power-down mode reduces power
dissipation to a minimum of 180 mW.
W
5k
W
5k
CLKP
CLKM
REFERENCE CIRCUIT
The ADS5500 has built-in internal reference
generation, requiring no external circuitry on the printed
circuit board (PCB). For optimum performance, it is best
to connect both REFP and REFM to ground with a 1−µF
decoupling capacitor in series with a 1-Ω resistor (see
Figure 9). In addition, an external 56.2-kΩ resistor
should be connected from IREF (pin 31) to AGND to set
the proper current for the operation of the ADC (see
Figure 9). No capacitor should be connected between
pin 31 and ground; only the 56.2-kΩ resistor should be
used.
6pF
3pF
3pF
Figure 10. Clock Inputs
When driven with a single-ended CMOS clock input, it
is best to connect CLKM (pin 11) to ground with a
0.01-µF capacitor, while CLKP is ac coupled with a
0.01-µF capacitor to the clock source (see Figure 11).
m
0.01 F
Square Wave
or Sine Wave
W
1
1
CLKP
ADS5500
CLKM
REFP
REFM
29
30
(3VPP
)
m
1 F
W
m
1 F
m
0.01 F
31 IREF
W
56k
Figure 11. AC-Coupled Single-Ended Clock Input
The ADS5500 clock input can also be driven
differentially, reducing susceptibility to common-mode
noise. In this case, it is best to connect both clock inputs
to the differential input clock signal with 0.01-µF
capacitors (see Figure 12).
Figure 9. REFP, REFM, and IREF Connections for
Optimum Performance
m
0.01 F
CLKP
ADS5500
CLKM
Differential Square Wave
or Sine Wave
(3VPP
)
m
0.01 F
Figure 12. AC-Coupled Differential Clock Input
27
ꢌꢒ ꢊꢇ ꢇ ꢗ ꢗꢈ ꢘꢋ
www.ti.com
SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
For high input frequency sampling, it is recommended
to use a clock source with very low jitter. Additionally,
the internal ADC core uses both edges of the clock for
the conversion process. This means that, ideally, a 50%
duty cycle should be provided. Figure 13 shows the
performance variation of the ADC versus clock duty
cycle.
amplitudes without exceeding the supply rails and
absolute maximum ratings of the ADC clock input.
Figure 14 shows the performance variation of the
device versus input clock amplitude. For detailed
clocking schemes based on transformer or PECL-level
clocks, see the ADS5500EVM user’s guide
(SLWU010), available for download from www.ti.com.
90
AC PERFORMANCE vs CLOCK AMPLITUDE
90
fS = 125MSPS
fIN = 20MHz
SFDR
SFDR
85
80
75
70
65
60
85
80
75
SNR
SNR
70
65
60
fS = 125MSPS
fIN = 70MHz
55
50
30
35
40
45
50
55
60
65
70
0
0.5
1.0
1.5
2.0
2.5
3.0
Clock Duty Cycle (%)
Differential Clock Amplitude (V)
Figure 13. AC Performance vs Clock Duty Cycle
Figure 14. AC Performance vs Clock Amplitude
INTERNAL DLL
Bandpass filtering of the source can help produce a
50% duty cycle clock and reduce the effect of jitter.
When using a sinusoidal clock, the clock jitter further
improves as the amplitude is increased. In that sense,
using a differential clock allows for the use of larger
In order to obtain the fastest sampling rates achievable
with the ADS5500, the device uses an internal digital
phase lock loop (DLL). Nevertheless, the limited
frequency range of operation of DLL degrades the
performance at clock frequencies below 60 MSPS. In
order to operate the device below 60 MSPS, the internal
DLL must be shut off using the DLL OFF mode
described in the Serial Interface Programming section.
The Typical Performance Curves show the
performance obtained in both modes of operation − DLL
ON (default) and DLL OFF. In either of the two modes,
the device enters power-down mode if no clock or a
slow clock is provided. The limit of the clock frequency
where the device functions properly is ensured to be
over 10 MHz.
28
ꢌꢒꢊ ꢇꢇ ꢗꢗ ꢈꢘ ꢋ
www.ti.com
SGLS286C − JUNE 2005 – REVISED SEPTEMBER 2008
OUTPUT INFORMATION
SERIAL PROGRAMMING INTERFACE
The ADC provides 14 data outputs (D13 to D0, with D13
being the MSB and D0 the LSB), a data-ready signal
(CLKOUT, pin 43), and an out-of-range indicator (OVR,
pin 64) that equals 1 when the output reaches the
full-scale limits.
The ADS5500 has internal registers for the
programming of some of the modes described in the
previous sections. The registers should be reset after
power up by applying a 2−µs (minimum) high pulse on
RESET (pin 35); this also resets the entire ADC and
sets the data outputs to low. This pin has a 200-kΩ
Two different output formats (straight offset binary or
twos complement) and two different output clock
polarities (latching output data on rising or falling edge
of the output clock) can be selected by setting DFS
(pin 40) to one of four different voltages. Table 3 details
the four modes. In addition, output enable control (OE,
pin 41, active high) is provided to 3-state the outputs.
internal pullup resistor to AV . The programming is
DD
done through a three-wire interface. The timing diagram
and serial register setting in the Serial Programing
Interface section describe the programming of this
register.
Table 2 shows the different modes and the bit values to
be written on the register to enable them.
The output circuitry of the ADS5500 has being designed
to minimize the noise produced by the transients of the
data switching, and in particular its coupling to the ADC
analog circuitry. Output D4 (pin 51) senses the load
capacitance and adjusts the drive capability of all the
output pins of the ADC to maintain the same output slew
rate described in the timing diagram of Figure 2, as long
as all outputs (including CLKOUT) have a similar load
as the one at D4 (pin 51). This circuit also reduces the
sensitivity of the output timing versus supply voltage or
temperature. External series resistors with the output
are not necessary.
Note that some of these modes may modify the
standard operation of the device and possibly vary the
performance, with respect to the typical data shown in
this data sheet.
29
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
ADS5500MPAPEP
ADS5500MPAPREP
V62/05613-01XE
V62/05613-02XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PAP
64
64
64
64
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
HTQFP
HTQFP
HTQFP
PAP
PAP
PAP
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ADS5500-EP :
Catalog: ADS5500
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS5500MPAPREP
HTQFP
PAP
64
1000
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PAP 64
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
ADS5500MPAPREP
1000
Pack Materials-Page 2
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