V62/05619-02XE [TI]
14-Bit 400-MSPS Digital-to-Analog Converter; 14位400 MSPS数位类比转换器
| 型号： | V62/05619-02XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14-Bit 400-MSPS Digital-to-Analog Converter |
| 文件： | 总27页 (文件大小：1095K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DAC5675-EP
www.ti.com
SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
14-Bit 400-MSPS Digital-to-Analog Converter
FEATURES
•
Power Dissipation: 660 mW at
fCLK = 400 MSPS, fOUT = 20 MHz
•
400-MSPS Update Rate
Controlled Baseline
– One Assembly
•
Package: 48-Pin PowerPAD™
Thermally-Enhanced Thin Quad Flat Pack
(HTQFP) TJA = 29.1°C/W
•
– One Test Site
– One Fabrication Site
APPLICATIONS
•
•
Extended Temperature Performance of –55°C
to 125°C
•
Cellular Base Transceiver Station Transmit
Channel:
– CDMA: WCDMA, CDMA2000, IS-95
– TDMA: GSM, IS-136, EDGE/GPRS
Enhanced Diminishing Manufacturing
Sources (DMS) Support
– Supports Single-Carrier and Multicarrier
Applications
Test and Measurement: Arbitrary Waveform
Generation
•
•
•
Enhanced Product-Change Notification
LVDS-Compatible Input Interface
•
•
Spurious-Free Dynamic Range (SFDR) to
Nyquist
Military Communications
– 69 dBc at 70 MHz IF, 400 MSPS
•
W-CDMA Adjacent Channel Power Ratio
(ACPR)
– 73 dBc at 30.72-MHz IF, 122.88 MSPS
– 71 dBc at 61.44-MHz IF, 245.76 MSPS
•
Differential Scalable Current Outputs: 2 mA
to 20 mA
•
•
On-Chip 1.2-V Reference
Single 3.3-V Supply Operation
DESCRIPTION/ORDERING INFORMATION
The DAC5675 is a 14-bit resolution high-speed digital-to-analog converter (DAC). The DAC5675 is designed for
high-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digital
synthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675 has
excellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes it well-suited for
multicarrier transmission in TDMA- and CDMA-based cellular base transceiver stations (BTSs).
The DAC5675 operates from a single-supply voltage of 3.3 V. Power dissipation is 660 mW at
fCLK = 400 MSPS, fOUT = 70 MHz. The DAC5675 provides a nominal full-scale differential current output of 20
mA, supporting both single-ended and differential applications. The output current can be directly fed to the load
with no additional external output buffer required. The output is referred to the analog supply voltage AVDD
.
The DAC5675 comprises a low-voltage differential signaling (LVDS) interface for high-speed digital data input.
LVDS features a low differential voltage swing with a low constant power consumption across frequency,
allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference
(EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology for
high-speed interfacing between the DAC5675 and high-speed low-voltage CMOS ASICs or FPGAs. The
DAC5675 current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggered
input latches provide for minimum setup and hold times, thereby relaxing interface timing.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DAC5675-EP
www.ti.com
SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
The DAC5675 has been specifically designed for a differential transformer-coupled output with a 50-Ω
doubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in an
output power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration is
preferred for optimum performance at high output frequencies and update rates. The outputs are terminated to
AVDD and have voltage compliance ranges from AVDD – 1 to AVDD + 0.3 V.
An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user to
adjust this output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities.
Alternatively, an external reference voltage may be applied. The DAC5675 features a SLEEP mode, which
reduces the standby power to approximately 18 mW.
The DAC5675 is available in a 48-pin PowerPAD™ thermally-enhanced thin quad flat pack (HTQFP). This
package increases thermal efficiency in a standard size IC package. The device is specified for operation over
the military temperature range of –55°C to 125°C.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
PACKAGE
LEAD
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
DAC5675MPHPREP
DAC5675MPHPEP
Tape and reel, 1000
Tray, 250
DAC5675-EP
48 HTQFP
PHP
DAC5675-EP
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
TQFP-48 PACKAGE THERMAL CHARACTERISTICS
SAME PACKAGE
FORM WITHOUT
PowerPAD
PowerPAD
PARAMETER
CONNECTED TO
PCB THERMAL PLANE(1)
RθJA
RθJC
Thermal resistance, junction to ambient(1)(2)
Thermal resistance, junction to case(1)(2)
108.71°C/W
18.18°C/W
29.11°C/W
1.14°C/W
(1) Airflow is at 0 LFM (no airflow).
(2) Specified with the PowerPAD bond pad on the backside of the package soldered to a 2-oz CU plate PCB thermal plane
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
FUNCTIONAL BLOCK DIAGRAM
SLEEP
DAC5675-EP
Bandgap
Reference
1.2V
EXTIO
BIASJ
Current
Source
Array
Output
Current
Switches
Control Amp
14
14
D[13:0]A
D[13:0]B
DAC
Latch
+
LVDS
Input
Input
Decoder
Latches
Interface
Drivers
CLK
Clock Distribution
CLKC
AVDD(4x) AGND(4x)
DVDD(2x) DGND(2x)
3
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DAC5675-EP
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
DAC5675-EP
–0.3 to 3.6
–0.3 to 3.6
–3.6 to 3.6
–0.3 to 0.5
–0.3 to AVDD + 0.3
–0.3 to DVDD + 0.3
–1 to AVDD + 0.3
–1 to AVDD + 0.3
20
UNIT
(2)
AVDD
(3)
Supply voltage range
DVDD
V
AVDD to DVDD
Voltage between AGND and DGND
CLK, CLKC(2)
V
V
Digital input D[13:0]A, D[13:0]B(3), SLEEP, DLLOFF
IOUT1, IOUT2(2)
V
V
EXTIO, BIASJ(2)
V
Peak input current (any input)
mA
mA
°C
°C
°C
Peak total input current (all inputs)
Operating free-air temperature range, TA
Storage temperature range
–30
–55 to 125
–65 to 150
260
Lead temperature 1,6 mm (1/16 in) from the case for 10 s
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to AGND
(3) Measured with respect to DGND
4
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
DC Electrical Characteristics
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
DC Accuracy(1)
14
Bit
INL
Integral nonlinearity
Differential nonlinearity
–4
–2
±1.5
±0.6
4.6
2.2
LSB
LSB
TMIN to TMAX
DNL
Monotonicity
Monotonic 12b Level
Analog Output
IO(FS) Full-scale output current
2
20
mA
V
AVDD = 3.15 V to 3.45 V,
IO(FS) = 20 mA
Output compliance range
Offset error
AVDD – 1
AVDD + 0.3
0.01
5
%FSR
Without internal reference
With internal reference
–10
–10
10
10
Gain error
%FSR
2.5
300
5
Output resistance
Output capacitance
kΩ
pF
Reference Output
V(EXTIO) Reference voltage
Reference output current(2)
Reference Input
V(EXTIO) Input reference voltage
1.17
0.6
1.23
100
1.29
1.25
V
nA
1.2
1
V
Input resistance
MΩ
MHz
pF
Small-signal bandwidth
Input capacitance
1.4
100
Temperature Coefficients
Offset drift
12
ppm of FSR/°C
ppm/°C
∆V(EXTIO)
Reference voltage drift
±50
Power Supply
AVDD
Analog supply voltage
3.15
3.15
3.3
3.3
3.6
3.6
V
V
DVDD
I(AVDD)
I(DVDD)
Digital supply voltage
Analog supply current(3)
Digital supply current(3)
115
85
mA
mA
Sleep mode
18
PD
Power dissipation
mW
AVDD = 3.3 V, DVDD = 3.3 V
660
±0.1
±0.1
900
0.9
0.9
APSRR
DPSRR
–0.9
–0.9
Analog and digital
power-supply rejection ratio
AVDD = 3.15 V to 3.45 V
%FSR/V
(1) Measured differential at IOUT1 and IOUT2: 25 Ω to AVDD
(2) Use an external buffer amplifier with high impedance input to drive any external load.
(3) Measured at fCLK = 400 MSPS and fOUT = 70 MHz
5
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
AC Electrical Characteristics
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA, differential
transformer-coupled output, 50-Ω doubly-terminated load (unless otherwise noted)
PARAMETER
Analog Output
TEST CONDITIONS
MIN TYP MAX
UNIT
fCLK
Output update rate
400 MSPS
ts(DAC)
tPD
tr(IOUT)
tf(IOUT)
Output setting time to 0.1%
Output propagation delay
Output rise time, 10% to 90%
Output fall time, 90% to 10%
Transition: code x2000 to x23FF
12
1
ns
ns
ns
ns
2
2
IOUTFS = 20 mA
IOUTFS = 2 mA
55
30
Output noise
pA/√Hz
AC Linearity
fCLK = 100 MSPS,
fCLK = 160 MSPS,
fCLK = 200 MSPS,
fOUT = 19.9 MHz
fOUT = 41 MHz
fOUT = 70 MHz
fOUT = 20.1 MHz
fOUT = 70 MHz
fOUT = 140 MHz
fOUT = 19.9 MHz
fOUT = 41 MHz
fOUT = 70 MHz
fOUT = 20.1 MHz
fOUT = 70 MHz
fOUT = 140 MHz
fOUT = 19.9 MHz
fOUT = 41 MHz
fOUT = 70 MHz
fOUT = 20.1 MHz
fOUT = 70 MHz
fOUT = 140 MHz
73
72
68
72
71
58
73
73
70
73
74
60
88
87
82
87
82
75
73
71
65
73
THD
Total harmonic distortion
dBc
fCLK = 400 MSPS
fCLK = 100 MSPS,
fCLK = 160 MSPS,
fCLK = 200 MSPS,
Spurious-free dynamic range
to Nyquist
SFDR
SFDR
dBc
dBc
fCLK = 400 MSPS
fCLK = 100 MSPS,
fCLK = 160 MSPS,
fCLK = 200 MSPS,
Spurious-free dynamic range
within a window, 5-MHz span
fCLK = 400 MSPS
fCLK = 122.88 MSPS, IF = 30.72 MHz, See Figure 9
Adjacent channel power ratio
ACPR
IMD
WCDM A with 3.84 MHz BW, fCLK = 245.76 MSPS, IF = 61.44 MHz, See Figure 10
dB
5-MHz channel spacing
fCLK = 399.32 MSPS, IF = 153.36 MHz, See Figure 12
Two-tone intermodulation
to Nyquist (each tone at
–6 dBfs)
fCLK = 400 MSPS, fOUT1 = 70 MHz, fOUT2 = 71 MHz
fCLK = 400 MSPS, fOUT1 = 140 MHz, fOUT2 = 141 MHz
fCLK = 156 MSPS, fOUT = 15.6, 15.8, 16.2, 16.4 MHz
fCLK = 400 MSPS, fOUT = 68.1, 69.3, 71.2, 72 MHz
62
82
74
dBc
Four-tone intermodulation,
15-MHz span, missing center
tone (each tone at –16 dBfs)
6
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
Digital Specifications
over operating free-air temperature range, typical values at 25°C, AVDD = 3.3 V, DVDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
LVDS Interface: Nodes D[13:0]A, D[13:0]B
Positive-going differential input
voltage threshold
VITH+
100
mV
mV
See LVDS Min/Max Threshold
Voltages table
Negative-going differential input
voltage threshold
VITH–
–100
ZT
CI
Internal termination impedance
Input capacitance
90
2
110 132
2
Ω
pF
CMOS Interface (SLEEP)
VIH
VIL
IIH
High-level input voltage
3.3
V
Low-level input voltage
High-level input current
Low-level input current
Input capacitance
0
2
0.8
100
10
V
–100
–10
µA
µA
pF
IIL
Clock Interface (CLK, CLKC)
|CLK-CLKC|
tw(H)
Clock differential input voltage
0.4
0.8
VPP
ns
Clock pulse width high
Clock pulse width low
Clock duty cycle
1.25
1.25
tw(L)
ns
40%
60%
VCM
Common-mode voltage range
Input resistance
2 ± 20%
V
Node CLK, CLKC
Node CLK, CLKC
Differential
670
2
Ω
Input capacitance
pF
kΩ
pF
Input resistance
1.3
1
Input capacitance
Differential
Timing
tSU
Input setup time
1.5
0.25
2
ns
ns
ns
clk
tH
Input hold time
tLPH
tDD
Input latch pulse high time
Digital delay time
DLL disabled, DLLOFF = 1
3
7
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
Timing Information
D[13:0]A
Valid Data
D[13:0]B
tH
tSU
tDD
CLK
50%
tW (LPH)
50%
CLKC
tS(DAC)
tPD
0.1%
50%
DAC Output
90%
10%
IOUT1/IOUT
2
0.1%
tr(IOUT)
Figure 1. Timing Diagram
Electrical Characteristics(1)
over operating free-air temperature range, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA (unless otherwise noted)
RESULTING
DIFFERENTIAL
INPUT VOLTAGE
RESULTING
COMMON-MODE
INPUT VOLTAGE
LOGICAL BIT
BINARY
EQUIVALENT
APPLIED
VOLTAGES
COMMENT
VA (V)
VB (V)
VA,B (mV)
100
VCOM (V)
1.2
1.25
1.15
2.4
2.3
0.1
0
1.15
1.25
2.3
2.4
0
1
0
1
0
1
0
1
0
1
0
1
0
–100
100
1.2
Operation with minimum differential voltage
(±100 mV) applied to the complementary inputs
versus common-mode range
2.35
2.35
0.05
0.05
1.2
–100
100
0.1
0.9
1.5
1.8
2.4
0
–100
600
1.5
0.9
2.4
1.8
0.6
0
–600
600
1.2
Operation with maximum differential voltage
(±600 mV) applied to the complementary inputs
versus common-mode range
2.1
–600
600
2.1
0.3
0.6
–600
0.3
(1) Specifications subject to change.
DVDD
VA
1.4 V
DAC5675-EP
VB
1 V
VA, B
0.4 V
0 V
VA, B
−0.4 V
1
VA
Logical Bit
Equivalent
VA + VB
VCOM =
0
2
DGND
VB
Figure 2. LVDS Timing Test Circuit and Input Test Levels
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
DEVICE INFORMATION
PHP PACKAGE
(TOP VIEW)
DAC5675
A. Thermal pad size: 4,5mm × 4,5mm (min), 5,5mm × 5,5mm (max)
9
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
NAME
AGND
I/O
DESCRIPTION
NO.
19, 41, 46, 47
I
I
Analog negative supply voltage (ground). Pin 47 is internally connected to the heat slug.
Analog positive supply voltage
AVDD
BIASJ
CLK
20, 42, 45, 48
39
22
21
O
I
Full-scale output current bias
External clock input
CLKC
I
Complementary external clock
1, 3, 5, 7, 9,
11, 13, 23, 25,
27, 29, 31, 33,
35
LVDS positive input, data bits 13–0.
D13A is the most significant data bit (MSB).
D0A is the least significant data bit (LSB).
D[13:0]A
D[13:0]B
I
I
2, 4, 6, 8, 10,
12, 14, 24, 26,
28, 30, 32, 34,
36
LVDS negative input, data bits 13–0..
D13B is the most significant data bit (MSB).
D0B is the least significant data bit (LSB).
DGND
DVDD
16, 18
15, 17
I
I
Digital negative supply voltage (ground)
Digital positive supply voltage
Internal reference output or external reference input. Requires a 0.1-µF decoupling capacitor to
AGND when used as reference output.
EXTIO
IOUT1
IOUT2
40
43
44
I/O
O
DAC current output. Full-scale when all input bits are set 1. Connect the reference side of the
DAC load resistors to AVDD
DAC complementary current output. Full-scale when all input bits are 0. Connect the reference
side of the DAC load resistors to AVDD
.
O
.
NC
38
37
Not connected in chip. Can be high or low.
SLEEP
I
Asynchronous hardware power-down input. Active high. Internal pulldown.
10
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY (DNL) vs INPUT CODE
INTEGRAL NONLINEARITY (INL) vs INPUT CODE
1.0
0.8
0.6
0.4
0.2
0
1.5
1.0
0.5
0
−
0.2
−
0.5
1.0
1.5
−
0.4
−
0.6
−
−
−
0.8
−
1.0
0
2000 4000 6000 8000 10000 12000 14000 16000
Input Code
0
2000 4000 6000 8000 10000 12000 14000 16000
Input Code
Figure 3.
Figure 4.
TWO-TONE IMD (POWER) vs FREQUENCY
TWO-TONE IMD3 vs FREQUENCY
0
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
f
= 69.5 MHz, −6 dBFS
= 70.5 MHz, −6 dBFS
1
−
−
−
−
−
−
−
−
−
10
20
30
40
50
60
70
80
90
f
2
IMD3 = 77.41 dBc
V
= V = 3.3 V
AA
CC
f
= 200 MHz
CLK
−
f2 f1 = 1 MHz (–6 dBFS each)
CC = VAA = 3.3 V
CLK = 200 MHz
V
f
−
100
65
67
69
71
73
75
5
15
25
35
45
55
65
75
85
Frequency (MHz)
Center Frequency (MHz)
Figure 5.
Figure 6.
SINGLE-TONE SPECTRUM
POWER vs FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE vs FREQUENCY
0
90
VCC = VAA = 3.3 V
CLK = 400 MHz
VCC = VAA = 3.3 V
fCLK = 400 MHz
86
82
78
74
70
66
62
58
54
50
20.1 MHz
−
10
20
30
40
50
60
70
80
90
f
−
3 dBFS
fOUT = 20.1 MHz, 0 dBFS
SFDR = 74.75 dBc
−
−
−
−
−
−
−
−
−
6 dBFS
0 dBFS
40.06 MHz
60.25 MHz
0
20
40
60
80 100 120 140 160 180 200
Frequency (MHz)
10 20 30 40 50 60 70 80 90 100 110 120
Output Frequency (MHz)
Figure 7.
Figure 8.
11
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TYPICAL CHARACTERISTICS (continued)
W-CDMA TM1 SINGLE CARRIER
POWER vs FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE vs FREQUENCY
−
−
−
−
−
−
−
−
90
25
35
45
55
65
75
85
95
VCC = VAA = 3.3 V
CLK = 200 MHz
VCC = VAA = 3.3 V
fCLK = 122.88 MHz
CENTER = 30.72 MHz
ACLR = 72.29 dB
86
82
78
74
70
66
62
58
54
50
f
−
3 dBFS
f
−
6 dBFS
0 dBFS
−
−
105
115
10 20 30 40 50 60 70 80 90 100 110 120
Output Frequency (MHz)
18
23
28
33
38
43
Frequency
Figure 9.
Figure 10.
W-CDMA TM1 DUAL CARRIER
POWER vs FREQUENCY
W-CDMA TM1 SINGLE CARRIER
ACLR vs OUTPUT FREQUENCY
−
30
80
78
76
74
72
70
68
66
64
62
60
V
f
= V = 3.3 V
AA
f
= 368.64 MHz
VCC = VAA = 3.3 V
CC
CLK
ACLR = 65 dBc
=
−
40
−
50
−
60
−
70
−
80
−
90
fCLK = 399.36 MHz
Single Channel
CENTER
92.16 MHz
−
−
100
110
82.2
87.2
92.2
97.2
10.2
10
30
50
70
90
110
130
150
Frequency
Output Frequency (MHz)
Figure 11.
Figure 12.
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APPLICATION INFORMATION
Detailed Description
Figure 13 shows a simplified block diagram of the current steering DAC5675. The DAC5675 consists of a
segmented array of NPN-transistor current sources, capable of delivering a full-scale output current up to
20 mA. Differential current switches direct the current of each current source to either one of the complementary
output nodes IOUT1 or IOUT2. The complementary current output enables differential operation, canceling out
common-mode noise sources (digital feedthrough, on-chip, and PCB noise), dc offsets, and even-order
distortion components, and doubling signal output power.
The full-scale output current is set using an external resistor (RBIAS) in combination with an on-chip bandgap
voltage reference source (1.2 V) and control amplifier. The current (IBIAS) through resistor RBIAS is mirrored
internally to provide a full-scale output current equal to 16 times IBIAS. The full-scale current is adjustable from
20 mA down to 2 mA by using the appropriate bias resistor value.
SLEEP
3.3 V
(AVDD
)
DAC5675-EP
Bandgap
Reference
1.2 V
Ω
50
IOUT
Output
1:1
EXTIO
BIASJ
Current
Source
Array
Output
Current
Switches
RLOAD
Ω
100
Ω
50
CEXT
Control Amp
0.1 mF
IOUT
3.3 V
(AVDD
)
RBIAS
Ω
Ω
50
1 k
14
14
D[13:0]A
D[13:0]B
DAC
Latch
+
3.3 V
LVDS
Input
Input
Decoder
(AVDD
)
Latches
Interface
Drivers
CLK
1:4
Clock
Input
RT
Ω
Clock Distribution
DVDD(2x)
200
CLKC
AVDD(4x)
AGND(4x)
DGND(2x)
Figure 13. Application Schematic
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
Digital Inputs
The DAC5675 uses a low-voltage differential signaling (LVDS) bus input interface. The LVDS features a low
differential voltage swing with low constant power consumption (4 mA per complementary data input) across
frequency. The differential characteristic of LVDS allows for high-speed data transmission with low
electromagnetic interference (EMI) levels. The LVDS input minimum and maximum input threshold table lists the
LVDS input levels. Figure 14 shows the equivalent complementary digital input interface for the DAC5675, valid
for pins D[13:0]A and D[13:0]B. Note that the LVDS interface features internal 110-Ω resistors for proper
termination. Figure 2 shows the LVDS input timing measurement circuit and waveforms. A common-mode level
of 1.2 V and a differential input swing of 0.8 VPP is applied to the inputs.
Figure 15 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5675, valid for
the SLEEP pin.
DVDD
DAC5675-EP
DAC5675-EP
D[13..0]A
D[13..0]B
Ω
110-
Internal
Termination
Resistor
Digital In
D[13:0]A
D[13:0]B
Internal
Digital In
DGND
Figure 14. LVDS Digital Equivalent Input
DVDD
DAC5675-EP
Internal
Digital Input
Digital In
DGND
Figure 15. CMOS/TTL Digital Equivalent Input
Clock Input
The DAC5675 features differential LVPECL-compatible clock inputs (CLK, CLKC). Figure 16 shows the
equivalent schematic of the clock input buffer. The internal biasing resistors set the input common-mode voltage
to approximately 2 V, while the input resistance is typically 670 Ω. A variety of clock sources can be ac-coupled
to the device, including a sine-wave source (see Figure 17).
14
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
AVDD
DAC5675-EP
R
1
R
1
1 kΩ
1 kΩ
Internal
Clock
CLK
CLKC
R
2
R
2
2 kΩ
2 kΩ
AGND
Figure 16. Clock Equivalent Input
Optional, may be
bypassed for sine-
wave input
Swing Limitation
C
AC
0.1 mF
1:4
CLK
RT
Ω
DAC5675-EP
200
CLKC
Termination
Resistor
Figure 17. Driving the DAC5675 With a Single-Ended Clock Source Using a Transformer
To obtain best ac performance, the DAC5675 clock input should be driven with a differential LVPECL or
sine-wave source as shown in Figure 18 and Figure 19. Here, the potential of VTT should be set to the
termination voltage required by the driver along with the proper termination resistors (RT). The DAC5675 clock
input can also be driven single ended; this is shown in Figure 20.
CAC
ECL/PECL
Gate
0.01 mF
CLK
Single-Ended
ECL
CAC
DAC5675-EP
or
0.01 mF
(LV)PECL
Source
CLKC
RT
Ω
RT
Ω
50
50
VTT
Figure 18. Driving the DAC5675 With a Single-Ended ECL/PECL Clock Source
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
CAC
0.01 mF
CLK
+
−
Differential
ECL
CAC
DAC5675-EP
CLKC
or
0.01mF
(LV)PECL
Source
RT
Ω
RT
Ω
50
50
VTT
Figure 19. Driving the DAC5675 With a Differential ECL/PECL Clock Source
TTL/CMOS
CLK
Source
ROPT
DAC5675-EP
Ω
22
CLKC
0.01mF
Node CLKC
Internally Biased to
AVDD/2
Figure 20. Driving the DAC5675 With a Single-Ended TTL/CMOS Clock Source
Supply Inputs
The DAC5675 comprises separate analog and digital supplies, that is AVDD and DVDD, respectively. These
supply inputs can be set independently from 3.6 V down to 3.15 V.
DAC Transfer Function
The DAC5675 delivers complementary output currents IOUT1 and IOUT2. The DAC supports straight binary
coding, with D13 being the MSB and D0 the LSB. (For ease of notation, we denote D13–D0 as the logical bit
equivalent of the complementary LVDS inputs D[13:0]A and D[13:0]B). Output current IOUT1 equals the
approximate full-scale output current when all input bits are set high, when the binary input word has the decimal
representation 16383. Full-scale output current flows through terminal IOUT2 when all input bits are set low
(mode 0, straight binary input). The relation between IOUT1 and IOUT2 can thus be expressed as:
IOUT1 + IO( )*IOUT2
FS
(1)
where IO(FS) is the full-scale output current. The output currents can be expressed as:
IO( CODE
)
FS
IOUT1 +
IOUT2 +
16384
(2)
(3)
(
)
IO( 16383*CODE
)
FS
16384
where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drive
a load RL. RL is the combined impedance for the termination resistance and/or transformer load resistance,
RLOAD (see Figure 22 and Figure 23). This would translate into single-ended voltages VOUT1 and VOUT2 at
terminal IOUT1 and IOUT2, respectively, of Equation 4 and Equation 5:
16
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
ǒCODE I R Ǔ
(
)
L
O FS
VOUT1 + IOUT1 RL +
VOUT2 + IOUT2 RL +
16384
(4)
(5)
(
)
16383*CODE IO FS R
(
)
L
16384
Thus, the differential output voltage VOUT(DIFF) can be expressed as:
(
)
2CODE * 16383 IO FS R
(
)
L
VOUT( ) + VOUT1*VOUT2 +
DIFF
16384
(6)
Equation 6 shows that applying the differential output results in doubling the signal power delivered to the load.
Since the output currents IOUT1 and IOUT2 are complementary, they become additive when processed
differentially. Care should be taken not to exceed the compliance voltages at nodes IOUT1 and IOUT2, which
leads to increased signal distortion.
Reference Operation
The DAC5675 has a bandgap reference and control amplifier for biasing the full-scale output current. The
full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor RBIAS
is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current equals
16 times this bias current. The full-scale output current IO(FS) is thus expressed as Equation 7:
16 VEXTIO
IO FS) + 16 I
(
+
BIAS
RBIAS
(7)
where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers a stable voltage of 1.2 V.
This reference can be overridden by applying an external voltage to terminal EXTIO. The bandgap reference
can additionally be used for external reference operation. In such a case, an external buffer amplifier with high
impedance input should be selected in order to limit the bandgap load current to less than 100 nA. The capacitor
CEXT may be omitted. Terminal EXTIO serves as either an input or output node. The full-scale output current is
adjustable from 20 mA down to 2 mA by varying resistor RBIAS
.
Analog Current Outputs
Figure 21 shows a simplified schematic of the current source array output with corresponding switches.
Differential NPN switches direct the current of each individual NPN current source to either the positive output
node IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the
stack of the current sources and differential switches and is >300 kΩ in parallel with an output capacitance
of 5 pF.
The external output resistors are referred to the positive supply AVDD
.
17
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
3.3 V
AVDD
RLOAD
RLOAD
IOUT2
IOUT1
DAC5675-EP
S(1)
S(1)C S(2)
S(2)C S(N)
S(N)C
Current Sink Array
AGND
Figure 21. Equivalent Analog Current Output
The DAC5675 can easily be configured to drive a doubly-terminated 50-Ω cable using a properly selected
transformer. Figure 22 and Figure 23 show the 1:1 and 4:1 impedance ratio configuration, respectively. These
configurations provide maximum rejection of common-mode noise sources and even-order distortion
components, thereby doubling the power of the DAC to the output. The center tap on the primary side of the
transformer is terminated to AVDD, enabling a dc-current flow for both IOUT1 and IOUT2. Note that the ac
performance of the DAC5675 is optimum and specified using a 1:1 differential transformer-coupled output.
3.3 V
AVDD
Ω
50
100
50
1:1
IOUT1
DAC5675-EP
RLOAD
Ω
Ω
50
IOUT2
Ω
3.3 V
AVDD
Figure 22. Driving a Doubly-Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer
18
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
3.3 V
AVDD
Ω
100
4:1
IOUT1
DAC5675-EP
RLOAD
Ω
50
IOUT2
15 Ω
Ω
100
3.3 V
AVDD
Figure 23. Driving a Doubly-Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer
Figure 24(a) shows the typical differential output configuration with two external matched resistor loads. The
nominal resistor load of 25 Ω gives a differential output swing of 1 VPP (0.5 VPP single ended) when applying a
20-mA full-scale output current. The output impedance of the DAC5675 slightly depends on the output voltage at
nodes IOUT1 and IOUT2. Consequently, for optimum dc-integral nonlinearity, the configuration of Figure 24(b)
should be chosen. In this current/voltage (I-V) configuration, terminal IOUT1 is kept at AVDD by the inverting
operational amplifier. The complementary output should be connected to AVDD to provide a dc-current path for
the current sources switched to IOUT1. The amplifier maximum output swing and the full-scale output current of
the DAC determine the value of the feedback resistor RFB. The capacitor CFB filters the steep edges of the
DAC5675 current output, thereby reducing the operational amplifier slew-rate requirements. In this configuration,
the operational amplifier should operate at a supply voltage higher than the resistor output reference voltage
AVDD as a result of its positive and negative output swing around AVDD. Node IOUT1 should be selected if a
single-ended unipolar output is desired.
3.3 V
CFB
AVDD
Ω
200
(RFB)
DAC5675-EP
IOUT1
Ω
25
25
DAC5675-EP
IOUT1
VOUT
1
2
V
OUT
IOUT2
VOUT
Ω
IOUT2
Optional, for single-
ended output
3.3 V
AVDD
referred to AVDD
3.3 V
AVDD
(a)
(b)
Figure 24. Output Configurations
Sleep Mode
The DAC5675 features a power-down mode that turns off the output current and reduces the supply current to
approximately 6 mA. The power-down mode is activated by applying a logic level one to the SLEEP pin, pulled
down internally.
19
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SGLS381A–OCTOBER 2006–REVISED OCTOBER 2006
DEFINITIONS
Definitions of Specifications and Terminology
Gain error is defined as the percentage error in the ratio between the measured full-scale output current and
the value of 16 × V(EXTIO)/RBIAS. A V(EXTIO) of 1.25 V is used to measure the gain error with an external reference
voltage applied. With an internal reference, this error includes the deviation of V(EXTIO) (internal bandgap
reference voltage) from the typical value of 1.25 V.
Offset error is defined as the percentage error in the ratio of the differential output current (IOUT1-IOUT2) and
the half of the full-scale output current for input code 8192.
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental output
signal.
SNR is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral
components below the Nyquist frequency, including noise, but excluding the first six harmonics and dc.
SINAD is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectral
components below the Nyquist frequency, including noise and harmonics, but excluding dc.
ACPR or adjacent channel power ratio is defined for a 3.84-Mcps 3GPP W-CDMA input signal measured in a
3.84-MHz bandwidth at a 5-MHz offset from the carrier with a 12-dB peak-to-average ratio.
APSSR or analog power supply ratio is the percentage variation of full-scale output current versus a 5%
variation of the analog power supply AVDD from the nominal. This is a dc measurement.
DPSSR or digital power supply ratio is the percentage variation of full-scale output current versus a 5% variation
of the digital power supply DVDD from the nominal. This is a dc measurement.
20
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
DAC5675MPHPEP
DAC5675MPHPREP
V62/05619-01XE
V62/05619-02XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTQFP
PHP
48
48
48
48
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
HTQFP
HTQFP
HTQFP
PHP
PHP
PHP
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC5675-EP :
Catalog: DAC5675
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC5675MPHPREP
HTQFP
PHP
48
1000
330.0
16.4
9.6
9.6
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PHP 48
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
DAC5675MPHPREP
1000
Pack Materials-Page 2
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