V62/05615-02XE [TI]
增强型产品 Memorystick™ 内部互联扩展器芯片组 | PW | 20 | -40 to 125;
| 型号： | V62/05615-02XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品 Memorystick™ 内部互联扩展器芯片组 | PW | 20 | -40 to 125 |
| 文件： | 总21页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
Memory Stick™ INTERCONNECT EXTENDER CHIPSET WITH LVDS
SN65LVDT14 – ONE DRIVER PLUS FOUR RECEIVERS
SN65LVDT41 – FOUR DRIVERS PLUS ONE RECEIVER
FEATURES
APPLICATIONS
•
Memory Stick™ Interface Extensions With
Long Interconnects Between Host and
Memory Stick
•
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
•
Serial Peripheral Interface™ (SPI™) Interface
Extension to Allow Long Interconnects
Between Master and Slave
•
Enhanced Diminishing Manufacturing
Sources (DMS) Support
•
•
•
Enhanced Product-Change Notification
•
•
MultiMediaCard™ (MMC) Interface in SPI
Mode
General-Purpose Asymmetric Bidirectional
Communication
(1)
Qualification Pedigree
Integrated 110-Ω Nominal Receiver Line
Termination Resistor
•
•
•
•
•
•
Operate From a Single 3.3-V Supply
Greater Than 125-Mbps Data Rate
Flow-Through Pinout
DESCRIPTION
The SN65LVDT14 combines one LVDS line driver
with four terminated LVDS line receivers in one
package. It is designed to be used at the Memory
Stick™ end of an LVDS-based Memory Stick
interface extension.
LVTTL-Compatible Logic I/Os
ESD Protection on Bus Pins Exceeds 12 kV
Meet or Exceed Requirements of
ANSI/TIA/EIA-644A Standard for LVDS
The SN65LVDT41 combines four LVDS line drivers
with a single terminated LVDS line receiver in one
package. It is designed to be used at the host end of
an LVDS-based Memory Stick interface extension.
•
20-Pin Thin Shrink Small-Outline
Package (PW) With 26-Mil Terminal Pitch
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
brk
brk
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Serial Peripheral Interface, SPI are trademarks of Motorola.
MultiMediaCard is a trademark of MultiMediaCard Association.
Memory Stick is a trademark of Sony.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
SN65LVDT41 LOGIC DIAGRAM
(POSITIVE LOGIC)
SN65LVDT14 LOGIC DIAGRAM
(POSITIVE LOGIC)
1A
1R
1B
1Y
1D
1Z
2A
2R
2B
2Y
2D
2Z
3A
3R
3B
3Y
3D
3Z
4Y
4A
4R
4B
4D
4Z
5Y
5D
5Z
5A
5R
5B
TYPICAL MEMORY STICK INTERFACE EXTENSION
SN65LVDT41
SN65LVDT14
1Y
1A
1D
2D
3D
4D
SCLK
1R
1Z
2Y
1B
2A
SCLK
SCLK
Memory
Stick
Host
Memory
Stick
BS
SDIO
DIR
BS
DIR
SD1
2R
3R
4R
BS
2Z
3Y
2B
3A
SDIO
Controller
3Z
4Y
3B
4A
CBT
4Z
5A
4B
5Y
CBT
SD2
5R
5D
5B
5Z
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
SN65LVDT14,
SN65LVDT41
UNIT
MIN
–0.5
–0.5
–0.5
MAX
VCC Supply voltage range(2)
4
6
V
V
D or R
Input voltage range
A, B, Y, or Z
4
A, B, Y, Z, and GND
All pins
±12
±8
Human-Body Model(3)
Electrostatic discharge
KV
V
Charged-Device Model(4)
All pins
±500
Continuous total power dissipation
See Dissipation Rating Table
Storage temperature range
–65
150
260
°C
°C
Lead temperature 1,6 mm (1/16 in) from case for 10 s
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with JEDEC Standard 22, Test Method A114-A
(4) Tested in accordance with JEDEC Standard 22, Test Method C101
2
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
Package Dissipation Ratings
TA < 25°C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
PACKAGE
PW
774 mW
6.2 mW/°C
402 mW
154 mW
Recommended Operating Conditions
MIN NOM
MAX
UNIT
VCC
VIH
VIL
Supply voltage range
3
2
3.3
3.6
V
V
V
V
High-level input voltage
Low-level input voltage
0.8
0.6
|VID
VIC
TA
|
Magnitude of differential input voltage
0.1
|VID
|VID
|
|
2.4 *
2
2
Common-mode input voltage (see Figure 1)
Operating free-air temperature
V
VCC – 0.8
125
–40
°C
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
2.5
Max at V > 3.15 V
CC
Max at V = 3 V
CC
2
1.5
1
0.5
0
Minimum
0.4
0
0.1
0.2
0.3
0.5
0.6
|V | − Differential Input Voltage − V
ID
Figure 1. VIC vs VID and VCC
3
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
Receiver Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX
100
UNIT
mV
VITH+
VITH–
VOH
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
High-level output voltage
See Figure 2 and Table 1
See Figure 2 and Table 1
IOH = –8 mA
–100
2.4
mV
V
VOL
Low-level output voltage
IOL = 8 mA
0.4
±40
±40
V
VI = 0 V and VI = 2.4 V,
Other input open
II
Input current (A or B inputs)
µA
II(OFF)
Ci
Power-off input current (A or B inputs)
Input capacitance, A or B input to GND
Termination impedance
VCC = 0 V, VI = 2.4 V
VI = A sin 2πft + CV
VID = 0.4 sin2.5E09 t V
µA
pF
Ω
5
Zt
88
132
(1) All typical values are at 25°C and with a 3.3-V supply.
Driver Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RL = 100 Ω,
See Figure 3 and Figure 5
MIN TYP(1)
MAX UNIT
|VOD
|
Differential output voltage magnitude
247
340
454
mV
Change in differential output voltage magnitude
between logic states
RL = 100 Ω,
See Figure 3 and Figure 5
∆|VOD
|
–50
1.125
–50
50
1.375
50
mV
V
VOC(SS)
Steady-state common-mode output voltage
See Figure 6
Change in steady-state common-mode output voltage
between logic states
∆VOC(SS)
See Figure 6
mV
VOC(PP)
IIH
Peak-to-peak common-mode output voltage
High-level input current
See Figure 6
50
mV
µA
µA
VIH = 2 V
20
10
IIL
Low-level input current
VIL = 0.8 V
VOY or VOZ = 0 V
VOD = 0 V(2)
±24
±12
±1
IOS
Short-circuit output current
Power-off output current
mA
IO(OFF)
VCC = 1.5 V, VO = 2.4 V
µA
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) This parameter is GBD over industrial temperature range.
Device Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
SN65LVDT14
SN65LVDT41
TEST CONDITIONS
MIN
MAX
25
UNIT
Driver RL = 100 Ω, Driver VI = 0.8 V or 2 V,
Receiver VI = ±0.4 V
ICC
Supply current
mA
35
4
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
Receiver Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Output signal rise time
TEST CONDITIONS
MIN
1
NOM
2.6
MAX UNIT
tPLH
tPHL
tr
4.8
4.8
1.4
1.4
750
550
1
ns
ns
ns
ns
ps
ps
ns
1
2.6
0.15
0.15
tf
Output signal fall time
CL = 10 pF, See Figure 4
tsk(p)
tsk(o)
tsk(pp)
Pulse skew (|tPHL – tPLH |)
Output skew(1)
Part-to-part skew(2)
150
100
(1) tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all the receivers of a single device with all of their inputs
connected together.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Driver Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Differential output signal rise time
Differential output signal fall time
Pulse skew (|tPHL – tPLH|)
TEST CONDITIONS
MIN
0.9
NOM
1.7
MAX UNIT
tPLH
tPHL
tr
3.9
3.9
1.2
1.2
750
400
1.5
ns
ns
ns
ns
ps
ps
ns
0.9
1.6
0.26
0.26
RL = 100 Ω, CL = 10 pF,
See Figure 7
tf
tsk(p)
tsk(o)
tsk(pp)
150
80
Output skew(1)
Part-to-part skew(2)
(1) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
PARAMETER MEASUREMENT INFORMATION
A
V
) V
R
IA
IB
V
ID
2
V
IA
B
V
O
V
IC
V
IB
Figure 2. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
RESULTING
DIFFERENTIAL
INPUT VOLTAGE
RESULTING
COMMON-MODE
INPUT VOLTAGE
APPLIED VOLTAGE
VIA
1.25 V
1.15 V
2.4 V
2.3 V
0.1 V
0 V
VIB
1.15 V
1.25 V
2.3 V
2.4 V
0 V
VID
VIC
100 mV
–100 mV
100 mV
–100 mV
100 mV
–100 mV
600 mV
–600 mV
600 mV
–600 mV
600 mV
–600 mV
1.2 V
1.2 V
2.35 V
2.35 V
0.05 V
0.05 V
1.2 V
1.2 V
2.1 V
2.1 V
0.3 V
0.3 V
0.1 V
0.9 V
1.5 V
1.8 V
2.4 V
0 V
1.5 V
0.9 V
2.4 V
1.8 V
0.6 V
0 V
0.6 V
I
OY
Y
Z
I
I
D
V
OD
V
) V
OY
OZ
I
OZ
V
OY
2
V
I
V
OC
V
OZ
Figure 3. Driver Voltage and Current Definitions
6
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
PARAMETER MEASUREMENT INFORMATION
V
ID
V
IA
C
L
V
O
10 pF
V
IB
V
V
1.4 V
1 V
IA
IB
0.4 V
0 V
V
ID
−0.4 V
t
t
PHL
PLH
V
V
O
OH
80%
20%
V
V
/2
CC
OL
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 1 Mpps, pulse width = 0.5 ± 0.05 µs. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 4. Receiver Timing Test Circuit and Waveforms
7
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
PARAMETER MEASUREMENT INFORMATION
3.75 kΩ
Y
+
0 V ≤ V
≤ 2.4 V
V
OD
100 Ω
test
Input
_
Z
3.75 kΩ
Figure 5. Driver VDO Test Circuit
49.9 Ω, ±1% (2 Places)
3 V
0 V
Y
Z
D
Input
V
IA
2 pF
V
OC
V
OC(PP)
V
OC(SS)
V
OC
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 µs. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 1 GHz.
Figure 6. Test Circuit and Definitions for Driver Common-Mode Output Voltage
Y
100 Ω
±1%
V
OD
Input
Z
C
L
(2 Places)
2 V
Input
1.4 V
0.8 V
t
PHL
t
PLH
100%
80%
V
OD(H)
Output
0 V
V
OD(L)
20%
0%
t
f
t
r
A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 1 Mpps, pulse width = 0.5 ± 0.05 µs. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 7. Test Circuit, Timing, and Voltage Definitions for Differential Output Signal
8
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
SN65LVDT41 (Marked as LVDT41)
SN65LVDT14 (Marked as LVDT14)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1D
GND
2D
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
5A
5B
1A
1B
2A
2B
3A
3B
4A
4B
5Y
5Z
1R
GND
2R
V
CC
3R
GND
4R
V
CC
5D
GND
V
CC
3D
GND
4D
V
CC
5R
GND
FUNCTION TABLES
RECEIVER(1)
INPUTS
VID = VA – VB
ID ≥ 100 mV
–100 mV < VID < 100 mV
OUTPUT
R
V
H
?
VID ≤ – 100 mV
L
Open
H
(1) H = high level, L = low level,
? = indeterminate
DRIVER(1)
OUTPUTS
INPUT
D
Y
H
L
Z
L
H
L
H
H
Open
L
(1) H = high level, L = low level
9
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
RECEIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
110 Ω
A
B
300 kΩ
300 kΩ
5 Ω
R Output
A Input
B Input
7 V
7 V
7 V
DRIVER EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
V
CC
V
CC
50 Ω
D Input
5 Ω
Y or Z
Output
10 kΩ
7 V
300 kΩ
7 V
10
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
TYPICAL CHARACTERISTICS
Receiver
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4
3.5
3
5
4.5
4
T = 25°C,
T = 25°C,
A
A
V
CC
= 3.3 V
V
CC
= 3.3 V
3.5
3
2.5
2.5
2
1.5
1
2
1.5
1
0.5
0
0.5
0
−70 −60
0
10
20
30
40
50
60
70
80
−50
−40
−30
−20
−10
0
I
− High-Level Output Current − mA
I
− Low-Level Output Current − mA
OH
OL
Figure 8.
Figure 9.
LOW-TO-HIGH PROPAGATION DELAY TIME
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
3
2.9
2.8
2.7
2.6
2.5
2.4
3
2.9
2.8
2.7
2.6
2.5
2.4
V
= 3 V
V
= 3 V
CC
CC
V
CC
= 3.3 V
V
CC
= 3.3 V
V
= 3.6 V
V
= 3.6 V
CC
CC
2.3
2.2
2.3
2.2
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 10.
Figure 11.
11
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
TYPICAL CHARACTERISTICS
Driver
LOW-TO-HIGH PROPAGATION DELAY TIME
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2.1
2
2.2
2.1
V
CC
= 3 V
V
CC
= 3 V
2
1.9
1.8
1.7
1.6
1.5
V
CC
= 3.3 V
1.9
1.8
1.7
V
CC
= 3.6 V
V
CC
= 3.6 V
1.6
1.5
V
= 3.3 V
0
CC
−50
−25
0
25
50
75
100
−50
−25
25
50
75
100
Ta − Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 12.
Figure 13.
12
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
APPLICATION INFORMATION
bbbbrk
Extending the Memory Stick Interface Using LVDS Signaling
Over Differential Transmission Cables
SN65LVDT41
SN65LVDT14
1Y
1A
1D
2D
3D
4D
SCLK
1R
1Z
2Y
1B
2A
SCLK
SCLK
Memory
Stick
Host
Memory
Stick
BS
SDIO
DIR
BS
DIR
SD1
BS
2R
3R
4R
2Z
3Y
2B
3A
SDIO
Controller
3Z
4Y
3B
4A
CBT
4B
5Y
4Z
5A
SD2
CBT
5R
5D
5B
5Z
Figure 14. System-Level Block Diagram
LVDS, as specified by the TIA/EIA-644-A standard,
provides several benefits when compared to
alternative long-distance signaling technologies: low
radiated emissions, high noise immunity, low power
consumption, and inexpensive interconnect cables.
The Memory Stick signaling interface operates in a
master-slave architecture, with three active signal
lines. The host (master) supplies a clock (SCLK) and
bus-state (BS) signal to control the operation of the
system. The SCLK and BS signals are unidirectional
(simplex) from the host to the Memory Stick. The
serial data input/output (SDIO) signal is a bidirectional
(half-duplex) signal used to communicate both control
and data information between the host and the
Memory Stick. The direction of data control is
managed by the host through a combination of BS
line states and control information delivered to the
Memory Stick.
This device pair provides the necessary LVDS drivers
and receivers specifically targeted at implementing a
Memory Stick interconnect extension. It utilizes
simplex links for the SCLK and BS signals and two
simplex links for the SDIO data. The half-duplex
SDIO data is split into two simplex streams under
control of the host processor by means of the
direction (DIR) signal. The DIR signal also is carried
from the host to the Memory Stick on a simplex LVDS
link.
The basic Memory Stick interface is capable of
operating only over short distances due to the
single-ended nature of the digital I/O signals. Such a
configuration is entirely suitable for compact and
portable devices where there is little if any separation
between the host and the Memory Stick. In
applications where a greater distance is needed
between the host controller and the Memory Stick, it
is necessary to utilize a different signaling method,
such as low-voltage differential signaling, or LVDS.
The switching of the SDIO signal-flow direction in the
single-ended interfaces is managed by electronic
switch devices, identified by the CBT symbol in
Figure 7. A suggested CBT device for this application
is the TI SN74CBTLV1G125. These devices are
available in space-saving SOT-23 or SC-70
packages.
13
SN65LVDT14-EP, SN65LVDT41-EP
www.ti.com
SCES633–JUNE 2005
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°−ā8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
14
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LVDT14QPWREP TSSOP
SN65LVDT41QPWREP TSSOP
PW
PW
20
20
2000
2000
330.0
330.0
16.4
16.4
6.95
6.95
7.1
7.1
1.6
1.6
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65LVDT14QPWREP
SN65LVDT41QPWREP
TSSOP
TSSOP
PW
PW
20
20
2000
2000
356.0
356.0
356.0
356.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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