V62/05620-05XE [TI]
3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTâ¢); 3 V至6 V的输入， 6 -A输出同步降压PWM具有集成FET SWITCHER （ SWIFTâ ?? ¢ ）
| 型号： | V62/05620-05XE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFTâ¢) |
| 文件： | 总21页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
Typical Size
6,6 mm X 9,8 mm
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
3-V TO 6-V INPUT, 6-A OUTPUT SYNCHRONOUS BUCK PWM
SWITCHER WITH INTEGRATED FETs (SWIFT™)
FEATURES
APPLICATIONS
•
Low-Voltage, High-Density Systems With
Power Distributed at 5 V or 3.3 V
•
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
•
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
•
•
Extended Temperature Performance of –55°C
to 125°C
•
•
Broadband, Networking and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
Enhanced Diminishing Manufacturing
Sources (DMS) Support
•
•
•
Enhanced Product-Change Notification
(1)
DESCRIPTION
Qualification Pedigree
30-mΩ, 12-A Peak MOSFET Switches for High
Efficiency at 6-A Continuous Output Source
and Sink
The SWIFT™ family of dc/dc regulators, the
TPS54611, TPS54612, TPS54613, TPS54614,
TPS54615, and TPS54616 low-input voltage
high-output
current
synchronous-buck
PWM
•
•
0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V
Fixed Output Voltage Devices With 1% Initial
Accuracy
converters integrate all required active components.
Included on the substrate are true, high-performance,
voltage error amplifiers that provide high performance
under transient conditions; an under-voltage lockout
circuit to prevent start-up until the input voltage
Internally Compensated for Easy Use and
Minimal Component Count
reaches
3 V; an internally and externally set
•
•
Fast Transient Response
slow-start circuit to limit in-rush currents; and a power
good output useful for processor/logic reset, fault
signaling, and supply sequencing.
Wide PWM Frequency - Fixed 350 kHz,
550 kHz or Adjustable 280 kHz to 700 kHz
•
•
Load Protected by Peak Current Limit and
Thermal Shutdown
The TPS54611-6 devices are available in a thermally
enhanced 28-pin TSSOP (PWP) PowerPAD™
package, which eliminates bulky heatsinks. Texas
Instruments provides evaluation modules and the
SWIFT™ designer software tool to aid in quickly
achieving high-performance power supply designs to
meet aggressive equipment development cycles.
Integrated Solution Reduces Board Area and
Total Cost
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
EFFICIENCY AT 350 kHz
100
95
90
85
80
SIMPLIFIED SCHEMATIC
Input
Output
VIN
PH
TPS54614
BOOT
PGND
75
70
65
VSENSE
VBIAS
AGND
60
55
50
0
1
2
3
4
5
6
Load Current − A
PWP PACKAGE
(TOP VIEW)
1
28
AGND
RT
2
27
26
25
24
23
22
21
20
19
18
17
16
15
VSENSE
NC
PWRGD
BOOT
PH
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
3
4
5
6
7
PH
PH
PH
PH
PH
PH
PH
PH
THERMAL
PAD
8
VIN
VIN
9
10
11
12
13
14
PGND
PGND
PGND
PGND
PGND
AVAILABLE OPTIONS
PACKAGED DEVICES
TJ
OUTPUT VOLTAGE
PLASTIC HTSSOP
(PWP)(1)
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
TPS54611MPWPREP(2)
TPS54612MPWPREP(2)
TPS54613MPWPREP
TPS54614MPWPREP(2)
TPS54615MPWPREP
TPS54616MPWPREP(2)
–55°C to 125°C
(1) The PWP package is taped and reeled as denoted by the R suffix on the device type (i.e., TPS54616MPWPREP). See the application
section of this data sheet for the PowerPAD drawing and layout information.
(2) Product Preview
2
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
Analog ground. Return for slow-start capacitor, VBIAS capacitor, RT resistor FSEL. Make PowerPAD connection to
AGND.
AGND
1
Bootstrap input. A 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates a floating drive for
the high-set FET driver.
BOOT
NC
5
3
No connection
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns and negative terminals of the input and output capacitors.
PGND
PH
15–19
6–14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
Power good open drain output. High-Z when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or internal shutdown signal active.
PWRGD
RT
4
28
26
27
25
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SS/ENA
FSEL
VBIAS
Frequency select input. Provides logic input to select between two internally set switching frequencies.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low-ESR 0.1-µF to 1-µF ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low-ESR 1-µF to 10-µF ceramic capacitor.
VIN
20–24
2
VSENSE
Error amplifier inverting input. Connect directly to output voltage sense point.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE / UNIT
–0.3 V to 7 V
–0.3 V to 6 V
–0.3 V to 4 V
–0.3 V to 17 V
–0.3 V to 7 V
–0.6 V to 10 V
Internally Limited
6 mA
VIN, SS/ENA, FSEL
RT
VI
Input voltage range
VSENSE
BOOT
VBIAS, PWRGD
PH
VO
Output voltage range
Source current
PH
IO
VBIAS
PH
12 A
IS
Sink current
SS/ENA, PWRGD
AGND to PGND
10 mA
Voltage differential
±0.3 V
Continuous power dissipation
See Power Dissipation Rating Table
–55°C to 150°C
–65°C to 150°C
300°C
TJ
Operating virtual junction temperature range
Storage temperature
Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
DISSIPATION RATINGS(1)(2)
PACKAGE
THERMAL IMPEDANCE
TA = 25°C
TA = 70°C
TA = 85°C
JUNCTION-TO-AMBIENT
POWER RATING POWER RATING
POWER RATING
28-pin PWP with solder
18.2°C/W
5.49 W(3)
2.48 W
3.02 W
1.36 W
2.2 W
28-pin PWP without solder
40.5°C/W
0.99 W
(1) For more information on the PWP package, see the Texas Instruments technical brief SLMA002.
(2) Test board conditions:
a. 3 inch x 3 inch, 4 layers, thickness: 0.062 inch
b. 1.5 oz. copper traces located on the top of the PCB
c. 1.5 oz. copper ground plane on the bottom of the PCB
d. 0.5 oz. copper ground planes on the 2 internal layers
e. 12 thermal vias (see the Recommended Land Pattern section in the applications section of this data sheet)
(3) Maximum power dissipation may be limited by overcurrent protection.
ADDITIONAL 6A SWIFT™ DEVICES
DEVICE
TPS54610
TPS54672
TPS54680
TPS54673
OUTPUT VOLTAGE
0.9 V to 3.3 V
DDR memory adjustable
Sequencing adjustable
Prebias adjustable
RELATED DC/DC PRODUCTS
•
•
•
TPS40000—Low-input, voltage-mode synchronous buck controller
TPS759xx—7.5-A low dropout regulator
PT6440 series—6-A plugin modules
4
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS
TJ = –55°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY VOLTAGE, VIN
VIN
Input voltage range
Quiescent current
3
6
15.8
23.5
1.4
V
fs = 350 kHz, FSEL ≤ 0.8 V, RT open, phase pin open
fs = 550 kHz, FSEL ≥ 2.5 V, RT open, phase pin open
Shutdown, SS/ENA = 0 V
9.8
14
1
I(Q)
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
Hysteresis voltage, UVLO
Rising and falling edge deglitch, UVLO(1)
BIAS VOLTAGE
2.95
2.8
3
V
V
2.7
2.7
0.16
2.5
V
µs
Output voltage, VBIAS
I(VBIAS) = 0
2.8
3
V
Output current, VBIAS(1)
100
µA
OUTPUT VOLTAGE
TJ = 25°C, VIN = 5 V
0.9
1.2
1.5
1.8
2.5
3.3
V
V
V
V
V
V
TPS54611
3 V ≤ VIN≤ 6 V, 0 ≤ IL≤ 6 A, –55°C ≤ TJ≤ 125°C
TJ = 25°C, VIN = 5 V
–4%
–4%
–4%
–4%
–4%
–4%
3%
3%
3%
3%
3%
3%
TPS54612
TPS54613
TPS54614
TPS54615
TPS54616
3 V ≤ VIN≤ 6 V, 0 ≤ IL≤ 6 A, –55°C ≤ TJ≤ 125°C
TJ = 25°C, VIN = 5 V
3 V ≤ VIN≤ 6 V, 0 ≤ IL≤ 6 A, –55°C ≤ TJ≤ 125°C
TJ = 25°C, VIN = 5 V
VO
Output voltage
3 V ≤ VIN≤ 6 V, 0 ≤ IL≤ 6 A, –55°C ≤ TJ≤ 125°C
TJ = 25°C, VIN = 5 V
3 V ≤ VIN≤ 6 V, 0 ≤ IL≤ 6 A, –55°C ≤ TJ≤ 125°C
TJ = 25°C, VIN = 5 V
3 V ≤ VIN≤ 6 V, 0 ≤ IL≤ 6 A, –55°C ≤ TJ≤ 125°C
REGULATION
Line regulation(1)(2)
Load regulation(1)(2)
IL = 3 A, 350 ≤ fs≤ 550 kHz, TJ = 85°C
0.088
%/V
%/A
IL = 0 A to 6 A, 350 ≤ fs≤ 550 kHz, TJ = 85°C
0.091
7
OSCILLATOR
FSEL ≤ 0.8 V, RT open
265
415
350
550
280
312
700
440
680
Internally set – free running frequency
kHz
kHz
FSEL ≥ 2.5 V, RT open
RT = 180 kΩ (1% resistor to AGND)(1)
RT = 160 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND)(1)
Externally set – free running frequency range
290
2.5
390
High level threshold, FSEL
Low level threshold, FSEL
Pulse duration, FSEL(1)
V
V
0.8
50
ns
kHz
V
Frequency range, FSEL(1)(3)
Ramp valley(1)
330
700
0.75
1
Ramp amplitude (peak-to-peak)(1)
Minimum controllable on time(1)
Maximum duty cycle(1)
V
200
ns
90%
(1) Specified by design
(2) Tested using circuit in Figure 10.
(3) To ensure proper operation when the RC filter is used between the external clock and the FSEL pin, the recommended values are R ≤ 1
kΩ and C ≤ 120 pF.
5
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
ELECTRICAL CHARACTERISTICS (continued)
TJ = –55°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ERROR AMPLIFIER
(4)
Error amplifier open loop voltage gain
26
5
dB
Error amplifier unity gain bandwidth(4)
3
0
MHz
Error amplifier common mode input voltage range Powered by internal LDO(4)
SLOW-START/ENABLE
VBIAS
1.4
V
Enable threshold voltage, SS/ENA
Enable hysteresis voltage, SS/ENA
Falling edge deglitch, SS/ENA(4)
0.82
1.2
0.03
2.5
3.3
4.5
5.6
3.3
4.7
6.1
5
V
V
(4)
µs
TPS54611
TPS54612
TPS54613
TPS54614
TPS54615
TPS54616
2.6
3.5
4.4
2.6
3.6
4.7
2.5
1.5
4.1
5.4
6.7
4.1
5.6
7.6
8
Internal slow-start time(4)
ms
Charge current, SS/ENA
SS/ENA = 0 V
µA
Discharge current, SS/ENA
SS/ENA = 0.2 V, VI = 2.7 V
2.3
4
mA
POWER GOOD
Power good threshold voltage
Power good hysteresis voltage
Power good falling edge deglitch
VSENSE falling
90
3
%VO
%VO
µs
(4)
See
(4)
See
35
Output saturation voltage, PWRGD
Leakage current, PWRGD
I(sink) = 2.5 mA
VI = 5.5 V
0.18
100
0.3
V
nA
CURRENT LIMIT
VI = 3 V
VI = 6 V
10
12
Current limit(4)
A
Current limit leading edge blanking time(4)
Current limit total response time(4)
100
200
ns
ns
THERMAL SHUTDOWN
Thermal shutdown trip point(4)
Thermal shutdown hysteresis(4)
135
150
10
165
°C
OUTPUT POWER MOSFETs
VI = 6 V(5)
VI = 3 V(5)
26
36
47
65
rDS(on) Power MOSFET switches
mΩ
(4) Specified by design
(5) Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design.
6
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VIN
Enable
Comparator
5 µA
SS/ENA
REG
VBIAS
ILIM
Falling
Edge
Deglitch
SHUTDOWN
VIN
1.8 V
VIN
Comparator
Thermal
Shutdown
145°C
Hysteresis: 0.03
V
Leading
Edge
2.5 µs
Blanking
VIN UVLO
Comparator
Falling
and
100 ns
VIN
BOOT
Rising
Edge
2.94 V
Sensefet
Deglitch
Hysteresis: 0.16
V
30 mΩ
2.5 µs
SS_DIS
SHUTDOWN
L
OUT
V
O
PH
Internal/External
Slow-Start
(Internal Slow-Start Time
=
+
−
C
O
Adaptive Dead-Time
and
Control Logic
R
S
Q
2 kΩ
3.3 ms to 6.6 ms)
PWM
Comparator
40 kΩ
Error
Amplifier
VIN
25 ns Adaptive
Deadtime
V
I
30 mΩ
Feed-Forward
Compensation
V
I
OSC
PGND
Power good
Comparator
Reference/
DAC
Falling
Edge
PWRGD
VSENSE
0.90 V
ref
Deglitch
TPS5461x
Hysteresis: 0.03 Vref
SHUTDOWN
35 µs
FSEL
VSENSE
RT
7
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
TYPICAL CHARACTERISTICS
DRAIN-SOURCE ON-STATE
RESISTANCE
DRAIN-SOURCE ON-STATE
RESISTANCE
INTERNALLY SET OSCILLATOR
FREQUENCY
vs
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
120
100
750
650
550
450
V = 3.3 V
I
V = 5 V
I
100
80
I
= 3 A
O
I
= 3 A
O
80
60
40
20
0
FSEL ≥ 2.5 V
60
FSEL ≤ 0.8 V
40
350
250
20
0
−40
0
25
85
125
−40
0
25
85
125
−40
0
25
85
125
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 1.
Figure 2.
Figure 3.
EXTERNALLY SET OSCILLATOR
FREQUENCY
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
OUTPUT VOLTAGE REGULATION
vs
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
0.895
0.8950
0.8930
0.8910
0.8890
800
RT = 68 k
T
A
= 85°C
700
600
500
400
0.893
0.891
RT = 100 k
0.889
f = 350 kHz
RT = 180 k
0.8870
0.8850
0.887
0.885
300
200
−40
0
25
85
125
−40
0
25
85
125
3
4
5
6
T
J
− Junction Temperature − °C
V − Input Voltage − V
I
T
J
− Junction Temperature − °C
Figure 4.
Figure 5.
Figure 6.
ERROR AMPLIFIER
OPEN LOOP RESPONSE
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
DEVICE POWER LOSSES
vs
LOAD CURRENT
0
5
3.80
3.65
3.50
3.35
3.20
3.05
140
120
100
80
R = 10 kΩ,
L
T
F
= 125°C
= 700 kHz
−20
J
4.5
C
T
= 160 pF,
= 25°C
L
S
−40
−60
−80
A
4
V = 3.3 V
I
3.5
3
Phase
−100
−120
60
2.5
40
20
Gain
2
1.5
1
−140
−160
V = 5.0 V
I
0
−180
−200
2.90
2.75
0.5
−20
0
10
100 1 k 10 k 100 k 1 M 10 M
0
0
−40
0
25
85
125
1
2
3
4
5
6
7
8
f − Frequency − Hz
T
J
− Junction Temperature − °C
I
− Load Current − A
L
Figure 7.
Figure 8.
Figure 9.
8
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical TPS54614 application. The TPS54614 (U1) can provide
greater than 6 A of output current at a nominal output voltage of 1.8 V. For proper operation, the exposed
thermal PowerPAD underneath the integrated circuit package needs to be soldered to the printed-circuit board.
V
20
21
5
6
I
VIN
VIN
VIN
VIN
VIN
BOOT
PH
3 V − 6 V
220 µF
10 µF
0.047 µF
7.2 µH
22
23
24
7
8
PH
PH
V
O
9
PH
1.8 V
10
11
10 kΩ
680 µF
PH
27
28
FSEL
RT
PH
PwrGood
Enable
12
13
PH
26
25
4
PH
SS/ENA
VBIAS
PWRGD
NC
14
15
PH
PGND
PGND
16
17
18
3
2
0.1 µF
VSENSE
PGND
PGND
PGND
C
SS
1
19
AGND
PwrPad
Figure 10. Application Circuit
COMPONENT SELECTION
The values for the components used in this design example were selected using the SWIFT designer software
tool. SWIFT designer provides a complete design environment for developing dc-dc converters using the
TPS54614, or other devices in the SWIFT product family. Additional design information is available at
www.ti.com.
INPUT FILTER
The input to the circuit is a nominal 3.3 VDC or 5 VDC. The input filter is a 220-µF POSCAP capacitor, with a
maximum allowable ripple current of 3 A. A 10-µF ceramic capacitor for the TPS54614 is required, and must be
located as close as possible to the device.
FEEDBACK CIRCUIT
The output voltage of the converter is fed directly into the VSENSE pin of the TPS54614. The TPS54614 is
internally compensated to provide stability of the output under varying line and load conditions.
OPERATING FREQUENCY
In the application circuit, 350 kHz operation is selected by leaving FSEL open. Different operating frequencies
can be selected by connecting a resistor between RT pin and AGND. Choose the value of R using Equation 1 for
the desired operating frequency:
500 kHz
SwitchingFrequency
R +
100 kW
(1)
Alternately, a preset operating frequency of 550 kHz can be selected by leaving RT open and connecting the
FSEL pin to VI.
9
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
APPLICATION INFORMATION (continued)
OUTPUT FILTER
The output filter is composed of a 5.2-µH inductor and a 470-µF capacitor. The inductor is low dc resistance
(16-mΩ) type, Sumida CDRH104R-5R2. The capacitor used is a 4-V POSCAP with a maximum ESR of 40 mΩ.
The output filter components work with the internal compensation network to provide a stable closed loop
response for the converter.
GROUNDING AND POWERPAD LAYOUT
The TPS54611-16 have two internal grounds (analog and power). Inside the TPS54611-16, the analog ground
ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD
is tied internally to the analog ground. Noise injected between the two grounds can degrade the performance of
the TPS54611-16, particularly at higher output currents. However, ground noise on an analog ground plane can
also cause problems with some of the control and bias signals. For these reasons, separate analog and power
ground planes are recommended. These two planes should tie together directly at the IC to reduce noise
between the two grounds. The only components that should tie directly to the power ground plane are the input
capacitor, the output capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54611-16.
The layout of the TPS54614 evaluation module is representative of a recommended layout for a 4-layer board.
Documentation for the TPS54614 evaluation module can be found on the Texas Instruments web site
(www.ti.com) under the TPS54614 product folder. See the TPS54614-185 User's Guide (SLVU053) and the
application note (SLVA105).
LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE
For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A
3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient
temperature and airflow. Most applications have larger areas of internal ground plane available, and the
PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also
help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection
from the exposes area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch
diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four
additional vias located under the device package. The size of the vias under the package, but not in the exposed
thermal pad area, can be increased to 0.018. Additional vias beyond the 10 recommended that enhance thermal
performance should be included in areas not under the device package.
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
Ø0.0130
8 PL
4 PL Ø0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.0150
0.06
0.0339
0.0650
0.0500
0.3820 0.3478
0.2090
0.0256
0.0500
0.0500
0.0650
0.0339
Minimum Recommended Exposed
Copper Area for Powerpad. 5mm
Stencils May Require 10 Percent
0.1700
Larger Area
0.1340
0.0630
Minimum Recommended Top
Side Analog Ground Area
0.0400
Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD
10
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
PERFORMANCE GRAPHS
EFFICIENCY
vs
LOAD CURRENT
OUTPUT VOLTAGE
vs
LOAD CURRENT
LOOP RESPONSE
180
100
1.03
1.02
1.01
60
50
90
80
135
90
40
30
Phase
V = 5 V
I
V = 5 V
I
V
= 3.3V
I
20
10
1
V
= 3.3V
Gain
I
70
0.99
45
0
0
60
50
0.98
0.97
−10
−20
10
100
1 k
10 k
100 k
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
f − Frequency − Hz
I
− Load Current − A
I
− Load Current − A
L
L
Figure 12.
Figure 13.
Figure 14.
TRANSIENT RESPONSE
START-UP WAVEFORMS
OUTPUT RIPPLE VOLTAGE
16
8
7
6
80
70
60
400
350
300
14
12
10
250
200
150
100
5
4
3
2
50
40
30
20
8
6
4
2
0
50
0
1
0
10
0
0
20 40 60 80 100 120 140 160 180 200
0
2
4
6
8
10 12 14 16 18 20
0
20 40 60 80 100 120 140 160 180 200
t − Time − µs
t − Time − µs
t − Time − µs
Figure 15.
Figure 16.
Figure 17.
AMBIENT TEMPERATURE
vs
LOAD CURRENT
125
T
F
= 125°C
= 700 kHz
J
115
105
S
V = 5 V
I
95
85
75
65
55
45
V = 3.3 V
I
Safe Operating Area
35
25
0
1
2
3
4
5
6
7
8
I
− Load Current − A
L
Figure 18.
11
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
The TPS5461x incorporates an under voltage lockout circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator and
a 2.5-µs rising and falling edge deglitch circuit reduces the likelihood of shutting the device down due to noise on
VIN.
Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduces the chance of
triggering the enable due to noise. See the Table 1 for startup times for each device.
Table 1. Startup Times for the Devices
DEVICE
OUTPUT VOLTAGE
SLOW-START
3.3 ms
TPS54611
TPS54612
TPS54613
TPS54614
TPS54615
TPS54616
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
4.5 ms
5.6 ms
3.3 ms
4.7 ms
6.1 ms
The second function of the SS/ENA pin provides an external means for extending the slow-start time with a
ceramic capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two effects
on start-up. First, a delay occurs between release of the SS/ENA pin and start-up of the output. The delay is
proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
1.2 V
t
+ C
d
(SS)
5 mA
(2)
Second, as the output becomes active, a brief ramp up at the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.
The slow-start time set by the capacitor is approximately:
0.7 V
t
+ C
(SS)
(SS)
5 mA
(3)
The actual slow-start time is likely to be less than the above approximation due to the brief ramp up at the
internal rate.
VBIAS Regulator
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V,
and external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits.
12
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
Voltage Reference
The voltage reference system produces a precise, temperature-stable voltage from a bandgap circuit. A scaling
amplifier and DAC are then used to produce the reference voltages for each of the fixed output devices.
Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the FSEL pin as a
static digital input. If a different frequency of operation is required for the application, the oscillator frequency can
be externally adjusted from 280 kHz to 700 kHz by connecting a resistor from the RT pin to AGND and floating
the FSEL pin. The switching frequency is approximated by the following equation, where R is the resistance from
RT to AGND:
100 kW
Switching Frequency +
500 [kHz]
R
(4)
The following table summarizes the frequency selection configurations:
SWITCHING FREQUENCY
350 kHz, internally set
FSEL PIN
Float or AGND
RT PIN
Float
550 kHz, internally set
≥2.5 V
Float
Externally set 280 kHz to 700 kHz
Externally synchronized frequency(1)
Float
R = 180 kΩ to 68 kΩ
Synchronization signal
R = RT value for 80% external synchronization fre-
quency
(1) To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R ≤ 1 kΩ and C
≤ 120 pF.
Error Amplifier
The high performance, wide bandwidth, voltage error amplifier is gain-limited to provide internal compensation of
the control loop. The user is given limited flexibility in choosing output L and C filter components. Inductance
values of 4.7 µH to 10 µH are typical and available from several vendors. The resulting designs exhibit good
noise and ripple characteristics, but with exceptional transient response. Transient recovery times are typically in
the range of 10 µs to 20 µs.
PWM Control
Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.
Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator pulse train alternately set and reset the PWM latch.
Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse
width. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp.
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM latch is never reset, and the high-side FET remains on
until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET on. The
device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting
VSENSE to approximately the same voltage as Vref. If the error amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS54611-TPS54616
devices are capable of sinking current continuously until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns, the PWM latch resets before the PWM ramp exceeds
the error amplifier output. The high-side FET turns off and the low-side FET turns on to decrease the energy in
the output inductor and consequently decrease the output current. This process is repeated each cycle in which
the current limit comparator is tripped.
13
TPS54611-EP, TPS54612-EP
TPS54613-EP, TPS54614-EP
TPS54615-EP, TPS54616-EP
www.ti.com
SGLS293A–FEBRUARY 2005–REVISED AUGUST 2005
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turnon times of the MOSFET drivers. The high-side
driver does not turn on until the voltage at the gate of the low-side FET is below 2 V. The high-side and low-side
drivers are designed with 300 mA source and sink capability to quickly drive the power MOSFETs gates. The
low-side driver is supplied from VIN, while the high-side drive is supplied from the BOOT pin. A bootstrap circuit
uses an external BOOT capacitor and internal 2.5-Ω bootstrap switch connected between the VIN and BOOT
pins. The integrated bootstrap switch improves drive efficiency and reduces external component count.
Overcurrent Protection
Cycle-by-cycle current limiting is achieved by sensing the current flow through the high-side MOSFET and a
differential amplifier with preset overcurrent threshold. The high-side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100-ns leading edge blanking circuit prevents false tripping of current limit.
Current limit detection occurs only when current flows from VIN to PH when sourcing current to the output filter.
Load protection during current sink operation is provided by thermal shutdown.
Thermal Shutdown
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown when the junction temperature decreases to
10°C below the thermal shutdown trip point, and starts up under control of the slow-start circuit. Thermal
shutdown provides protection when an overload condition is sustained for several milliseconds. With a persistent
fault condition, the device cycles continuously: starting up by control of the slow-start circuit, heating up due to
the fault, and then shutting down upon reaching the thermal shutdown trip point.
Power Good (PWRGD)
The power good circuit monitors for under voltage conditions on VSENSE. If the voltage on VSENSE falls 10%
below the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold, or SS/ENA is low, or thermal shutdown is asserted. When VIN = UVLO threshold,
SS/ENA = enable threshold, and VSENSE > 90% of Vref, the open drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35-µs falling edge deglitch circuit prevent tripping of the power good
comparator due to high-frequency noise.
14
PACKAGE OPTION ADDENDUM
www.ti.com
10-Feb-2010
PACKAGING INFORMATION
Orderable Device
TPS54613MPWPREP
TPS54615MPWPREP
V62/05620-03XE
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
PWP
28
28
28
28
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
V62/05620-05XE
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54611-EP, TPS54612-EP, TPS54613-EP, TPS54614-EP, TPS54615-EP, TPS54616-EP :
Catalog: TPS54611, TPS54612, TPS54613, TPS54614, TPS54615, TPS54616
Automotive: TPS54612-Q1, TPS54613-Q1, TPS54614-Q1, TPS54615-Q1, TPS54616-Q1
•
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
•
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54613MPWPREP HTSSOP PWP
TPS54615MPWPREP HTSSOP PWP
28
28
2000
2000
330.0
330.0
16.4
16.4
6.9
6.9
10.2
10.2
1.8
1.8
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS54613MPWPREP
TPS54615MPWPREP
HTSSOP
HTSSOP
PWP
PWP
28
28
2000
2000
367.0
367.0
367.0
367.0
38.0
38.0
Pack Materials-Page 2
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相关型号：
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