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V62/06603-01XE [TI]

PARALLEL-LOAD 8-BIT SHIFT REGISTER; 并联负载8位移位寄存器
V62/06603-01XE
型号： V62/06603-01XE
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

PARALLEL-LOAD 8-BIT SHIFT REGISTER
并联负载8位移位寄存器

移位寄存器 触发器 逻辑集成电路 光电二极管
文件： 总13页 (文件大小：512K)
中文：  中文翻译
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SN74LV165A-EP  
PARALLEL-LOAD 8-BIT SHIFT REGISTER  
www.ti.com  
SCLS694–JANUARY 2006  
FEATURES  
•
Controlled Baseline  
•
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– One Assembly/Test Site, One Fabrication  
Site  
•
•
Extended Temperature Performance of –55°C  
to 125°C  
– 1000-V Charged-Device Model (C101)  
PW PACKAGE  
(TOP VIEW)  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
•
•
•
•
•
Enhanced Product-Change Notification  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
SH/LD  
CLK  
E
V
CC  
(1)  
Qualification Pedigree  
CLK INH  
D
C
B
A
2-V to 5.5-V VCC Operation  
Max tpd of 10.5 ns at 5 V  
F
G
H
Supports Mixed-Mode Voltage Operation on  
All Ports  
Q
H
SER  
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
GND  
Q
H
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION  
The SN74LV165A-EP is a parallel-load, 8-bit shift register designed for 2-V to 5.5-V VCC operation.  
When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is  
provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The  
SN74LV165A-EP features a clock-inhibit function and a complemented serial output, QH.  
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock  
inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a  
low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while  
CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are enabled  
while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the devices when they are powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
LV165EP  
–55°C to 125°C  
TSSOP – PW  
Reel of 2000  
SN74LV165AMPWREP  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN74LV165A-EP  
PARALLEL-LOAD 8-BIT SHIFT REGISTER  
www.ti.com  
SCLS694–JANUARY 2006  
FUNCTION TABLE  
INPUTS  
OPERATION  
SH/LD  
CLK  
X
CLK INH  
L
H
H
H
H
X
X
H
↑
Parallel load  
H
Q0  
Q0  
X
L
Shift  
Shift  
↑
L
LOGIC DIAGRAM (POSITIVE LOGIC)  
A
B
C
D
E
F
G
H
11  
12  
13  
14  
3
4
5
6
1
SH/LD  
15  
CLK INH  
2
CLK  
SER  
9
S
S
S
S
S
S
S
S
Q
H
H
C1  
C1  
C1  
C1  
C1  
C1  
C1  
C1  
7
10  
1D  
R
1D  
R
1D  
R
1D  
R
1D  
R
1D  
R
1D  
R
1D  
R
Q
2
SN74LV165A-EP  
PARALLEL-LOAD 8-BIT SHIFT REGISTER  
www.ti.com  
SCLS694–JANUARY 2006  
TYPICAL SHIFT, LOAD, AND INHIBIT SEQUENCES  
CLK  
CLK INH  
SER  
L
SH/LD  
A
H
L
B
C
H
Data  
Inputs  
L
D
E
F
H
L
H
H
G
H
L
L
L
Q
H
H
L
H
L
H
L
H
L
H
L
Q
H
H
H
H
Inhibit  
Serial Shift  
Load  
3
SN74LV165A-EP  
PARALLEL-LOAD 8-BIT SHIFT REGISTER  
www.ti.com  
SCLS694–JANUARY 2006  
Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
–0.5  
–0.5  
MAX  
UNIT  
VCC Supply voltage range  
7
V
VI  
Input voltage range(2)  
7
7
V
V
VO  
VO  
IIK  
Voltage range applied to any output in the high-impedance or power-off state(2)  
Output voltage range(2)(3)  
VCC + 0.5  
–20  
V
Input clamp current  
VI < 0  
mA  
mA  
mA  
mA  
°C/W  
°C  
IOK  
IO  
Output clamp current  
VO < 0  
–50  
Continuous output current  
Continuous current through VCC or GND  
Package thermal impedance(4)  
Storage temperature range  
VO = 0 to VCC  
±25  
±50  
θJA  
108  
Tstg  
–65  
150  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.  
(3) This value is limited to 5.5 V maximum.  
(4) The package thermal impedance is calculated in accordance with JESD 51-7.  
Recommended Operating Conditions(1)  
MIN  
2
MAX  
UNIT  
VCC  
Supply voltage  
5.5  
V
VCC = 2 V  
1.5  
VCC = 2.3 V to 2.7 V  
VCC = 3 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VCC = 2 V  
V
V
V
CC × 0.7  
CC × 0.7  
CC × 0.7  
VIH  
High-level input voltage  
V
V
0.5  
CC × 0.3  
CC × 0.3  
CC × 0.3  
5.5  
VCC = 2.3 V to 2.7 V  
VCC = 3 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
V
V
V
VIL  
Low-level input voltage  
VI  
Input voltage  
0
0
V
V
VO  
Output voltage  
VCC  
–50  
–2  
VCC = 2 V  
µA  
VCC = 2.3 V to 2.7 V  
VCC = 3 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VCC = 2 V  
IOH  
High-level output current  
Low-level output current  
–6  
mA  
µA  
–12  
50  
VCC = 2.3 V to 2.7 V  
VCC = 3 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
VCC = 2.3 V to 2.7 V  
VCC = 3 V to 3.6 V  
VCC = 4.5 V to 5.5 V  
2
IOL  
6
mA  
12  
200  
100  
20  
∆t/∆v  
Input transition rise or fall rate  
Operating free-air temperature  
ns/V  
TA  
–55  
125  
°C  
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
4
SN74LV165A-EP  
PARALLEL-LOAD 8-BIT SHIFT REGISTER  
www.ti.com  
SCLS694–JANUARY 2006  
Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
IOH = –50 µA  
VCC  
2 V to 5.5 V  
2.3 V  
MIN  
VCC – 0.1  
2
TYP  
MAX  
UNIT  
IOH = –2 mA  
VOH  
V
IOH = –6 mA  
3 V  
2.48  
IOH = –12 mA  
IOL = 50 µA  
4.5 V  
3.8  
2 V to 5.5 V  
2.3 V  
0.1  
0.4  
0.44  
0.55  
±1  
IOL = 2 mA  
VOL  
V
IOL = 6 mA  
3 V  
IOL = 12 mA  
4.5 V  
II  
VI = 5.5 V or GND  
VI = VCC or GND,  
VI or VO = 0 to 5.5 V  
VI = VCC or GND  
0 to 5.5 V  
5.5 V  
µA  
µA  
µA  
pF  
ICC  
Ioff  
Ci  
IO = 0  
20  
0
5
3.3 V  
1.7  
Timing Requirements  
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)  
TA = 25°C  
MIN  
MAX  
UNIT  
MIN  
8.5  
11  
7
MAX  
CLK high or low  
9
13  
8.5  
9.5  
7
tw  
Pulse duration  
Setup time  
ns  
SH/LD low  
SH/LD high before CLK↑  
SER before CLK↑  
8.5  
7
tsu  
ns  
ns  
CLK INH before CLK↑  
Data before SH/LD↑  
SER data after CLK↑  
Parallel data after SH/LD↑  
SH/LD high after CLK↑  
11.5  
–1  
0
12  
0
th  
Hold time  
0.5  
0
0
Timing Requirements  
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)  
TA = 25°C  
MIN  
MAX  
UNIT  
MIN  
6
MAX  
CLK high or low  
7
9
tw  
Pulse duration  
Setup time  
ns  
SH/LD low  
7.5  
5
SH/LD high before CLK↑  
SER before CLK↑  
6
5
6
tsu  
ns  
ns  
CLK INH before CLK↑  
Data before SH/LD↑  
SER data after CLK↑  
Parallel data after SH/LD↑  
SH/LD high after CLK↑  
5
5
7.5  
0
8.5  
0
th  
Hold time  
0.5  
0
0.5  
0
5
SN74LV165A-EP  
PARALLEL-LOAD 8-BIT SHIFT REGISTER  
www.ti.com  
SCLS694–JANUARY 2006  
Timing Requirements  
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)  
TA = 25°C  
MIN  
MAX  
UNIT  
MIN  
4
MAX  
CLK high or low  
6.5  
6.5  
4
tw  
Pulse duration  
Setup time  
ns  
SH/LD low  
5
SH/LD high before CLK↑  
SER before CLK↑  
4
4
4
tsu  
ns  
ns  
CLK INH before CLK↑  
Data before SH/LD↑  
SER data after CLK↑  
Parallel data after SH/LD↑  
SH/LD high after CLK↑  
3.5  
5
4.5  
5
0.5  
1
0.5  
1
th  
Hold time  
0.5  
0.5  
Switching Characteristics  
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)  
TA = 25°C  
TYP  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
MIN  
MAX UNIT  
MIN  
MAX  
fmax  
CL = 50 pF  
CL = 50 pF  
40  
65  
35  
1
MHz  
26  
CLK  
SH/LD  
H
15.3  
23.3  
25.1  
25.3  
tpd  
QH or QH  
16.1  
1
28  
28  
ns  
15.9  
1
Switching Characteristics  
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)  
TA = 25°C  
TYP  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
MIN  
MAX UNIT  
MIN  
MAX  
fmax  
CL = 50 pF  
CL = 50 pF  
60  
90  
50  
1
MHz  
16.9  
CLK  
SH/LD  
H
10.9  
14.9  
19.3  
17.6  
tpd  
QH or QH  
11.3  
1
22  
20  
ns  
11.1  
1
Switching Characteristics  
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)  
TA = 25°C  
TYP  
85  
FROM  
(INPUT)  
TO  
(OUTPUT)  
LOAD  
CAPACITANCE  
PARAMETER  
MIN  
MAX UNIT  
MIN  
MAX  
fmax  
CL = 50 pF  
CL = 50 pF  
75  
75  
1
MHz  
13.5  
CLK  
SH/LD  
H
7.7  
11.9  
11.9  
11  
tpd  
QH or QH  
7.7  
1
13.5  
12.5  
ns  
7.6  
1
Operating Characteristics  
TA = 25°C  
PARAMETER  
Power dissipation capacitance  
TEST CONDITIONS  
CL = 50 pF, f = 10 MHz  
VCC  
3.3 V  
5 V  
TYP  
UNIT  
36.1  
37.5  
Cpd  
pF  
6
SN74LV165A-EP  
PARALLEL-LOAD 8-BIT SHIFT REGISTER  
www.ti.com  
SCLS694–JANUARY 2006  
PARAMETER MEASUREMENT INFORMATION  
V
CC  
S1  
Open  
R
L
= 1 kΩ  
TEST  
/t  
S1  
From Output  
Under Test  
Test  
Point  
From Output  
Under Test  
GND  
t
t
Open  
PLH PHL  
C
L
C
L
t
/t  
V
CC  
PLZ PZL  
(see Note A)  
(see Note A)  
/t  
GND  
PHZ PZH  
Open Drain  
V
CC  
LOAD CIRCUIT FOR  
LOAD CIRCUIT FOR  
TOTEM-POLE OUTPUTS  
3-STATE AND OPEN-DRAIN OUTPUTS  
V
CC  
50% V  
CC  
Timing Input  
0 V  
t
w
t
h
t
su  
V
CC  
V
CC  
50% V  
50% V  
CC  
Input  
Input  
CC  
50% V  
50% V  
CC  
Data Input  
0 V  
CC  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
V
CC  
CC  
Output  
Control  
50% V  
50% V  
50% V  
50% V  
CC  
CC  
CC  
CC  
0 V  
0 V  
t
t
t
t
t
PLH  
PHL  
PZL  
PLZ  
Output  
Waveform 1  
≈V  
V
CC  
OH  
In-Phase  
Output  
50% V  
50% V  
CC  
50% V  
CC  
CC  
V
V
+ 0.3 V  
OL  
S1 at V  
CC  
V
OL  
V
OL  
(see Note B)  
t
t
t
PZH  
PHZ  
PHL  
PLH  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
OH  
Out-of-Phase  
Output  
− 0.3 V  
OH  
50% V  
50% V  
50% V  
CC  
CC  
CC  
OL  
V
≈0 V  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.  
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PHL  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PLH pd  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuits and Voltage Waveforms  
7
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Sep-2008  
PACKAGING INFORMATION  
Orderable Device  
SN74LV165AMPWREP  
V62/06603-01XE  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TSSOP  
PW  
16  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
PW  
16  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF SN74LV165A-EP :  
Catalog: SN74LV165A  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
SN74LV165AMPWREP TSSOP  
PW  
16  
2000  
330.0  
12.4  
6.9  
5.6  
1.6  
8.0  
12.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
TSSOP PW 16  
SPQ  
Length (mm) Width (mm) Height (mm)  
367.0 367.0 35.0  
SN74LV165AMPWREP  
2000  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should  
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All  
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time  
of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
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