V62/08606-01XE_技术文档

Typ ical Si ze

(6 ,3 mm x 6, 4 mm)

TPS54310-EP

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3-V TO 6-V INPUT, 3-A OUTPUT, SYNCHRONOUS BUCK PWM

SWITCHER WITH INTEGRATED FETs (SWIFT™)

1

FEATURES

2

•

Controlled Baseline

•

Adjustable Output Voltage Down to 0.9 V With

1% Accuracy

–

One Assembly Site

One Test Site

•

Externally Compensated for Design Flexibility

Fast Transient Response

One Fabrication Site

Wide PWM Frequency: Fixed 350 kHz, 550

kHz, or Adjustable 280 kHz to 700 kHz

•

Extended Temperature Performance of

–55°C to 125°C

•

Load Protected by Peak Current Limit and

Thermal Shutdown

Enhanced Diminishing Manufacturing Sources

(DMS) Support

Integrated Solution Reduces Board Area and

Total Cost

•

Enhanced Product-Change Notification

(1)

Qualification Pedigree

60-mΩ MOSFET Switches for High Efficiency

at 3-A Continuous Output Source or Sink

Current

APPLICATIONS

•

Low-Voltage High-Density Systems With

Power Distributed at 5 V or 3.3 V

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

•

Point of Load Regulation for

High-Performance DSPs, FPGAs, ASICs, and

Microprocessors

Broadband, Networking, and Optical

Communications Infrastructure

•

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

Portable Computing/Notebook PCs

DESCRIPTION/ORDERING INFORMATION

As members of the SWIFT™ family of dc/dc regulators, the TPS54310 low input voltage high output current

synchronous buck PWM converter integrates all required active components. Included on the substrate with the

listed features are a true, high performance, voltage error amplifier that provides high performance under

transient conditions; an undervoltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; an

internally and externally set slow-start circuit to limit in-rush currents; and a power good output useful for

processor/logic reset, fault signaling, and supply sequencing.

The TPS54310 device is available in a thermally enhanced 20-pin TSSOP (PWP) PowerPAD™ package, which

eliminates bulky heatsinks. TI provides evaluation modules and the SWIFT designer software tool to aid in

quickly achieving high-performance power supply designs to meet aggressive equipment development cycles.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS54310-EP

SLVS818–APRIL 2008 ..................................................................................................................................................................................................... www.ti.com

EFFICIENCY

vs

Simplified Schematic

LOAD CURRENT

96

94

92

90

88

86

84

82

80

Input

Output

VIN

PH

TPS54310

BOOT

PGND

VSENSE

VBIAS

AGND COMP

T

= 25°C

A

V = 5 V

V

I

= 3.3 V

O

0

0.5

1

1.5

2

2.5

3

Load Current − A

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

PACKAGED DEVICES

TOPSIDE MARKING

T_J

OUTPUT VOLTAGE

PLASTIC HTSSOP (PWP)⁽²⁾⁽³⁾

–55°C to 125°C

Adjustable Down to 0.9 V

TPS54310MPWPREP

54310EP

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) The PWP package is shipped taped and reeled with 2000 units per reel. See the application section of this data sheet for PowerPAD

drawing and layout information.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

TPS54310

UNIT

V

VIN, SS/ENA, SYNC

–0.3 to 7

RT

–0.3 to 6

V

V_I

Input voltage range

VSENSE

–0.3 to 4

V

BOOT

–0.3 to 17

V

VBIAS, PWRGD, COMP

–0.3 to 7

V

V_O

Output voltage range

PH

–0.6 to 10

V

PH

Internally Limited

I_O

COMP, VBIAS

PH

6

mA

A

6

Sink current

COMP

6

mA

V

SS/ENA, PWRGD

AGND to PGND

10

±0.3

Voltage differential

Continuous power dissipation

See Package Dissipation Rating

–55 to 150

T_J

Operating virtual-junction temperature range

Storage temperature

°C

T_stg

–65 to 150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2

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RECOMMENDED OPERATING CONDITIONS

MIN

3

MAX

6

UNIT

V

V_I

Input voltage

T_J

Operating virtual-junction temperature

–55

125

°C

PACKAGE DISSIPATION RATINGS^{(1) (2)}

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

T_A= 25°C

POWER RATING

T_A= 70°C

POWER RATING

T_A= 85°C

POWER RATING

PACKAGE

20-Pin PWP with solder

26°C/W

3.85 W⁽³⁾

2.12 W

1.54 W

0.69 W

20-Pin PWP without solder

57.5°C/W

1.73 W

0.96 W

(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.

(2) Test board conditions:

a. 3 inch × 3 inch, 2 layers, Thickness: 0.062 inch

b. 1.5 oz copper traces located on the top of the PCB

c. 1.5 oz copper ground plane on the bottom of the PCB

d. Ten thermal vias (see recommended land pattern in application section of this data sheet)

(3) Maximum power dissipation may be limited by overcurrent protection.

ELECTRICAL CHARACTERISTICS

T_J= –55°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)

PARAMETER

SUPPLY VOLTAGE, VIN

VIN input voltage range

TEST CONDITIONS

MIN

TYP

MAX UNIT

3

6

9.6

V

f_s= 350 kHz, SYNC = 0.8 V, RT open

f_s= 550 kHz, SYNC ≥ 2.5 V, RT open, phase pin open

Shutdown, SS/ENA = 0 V

6.2

8.4

1

Quiescent current

12.8

1.4

mA

UNDERVOLTAGE LOCKOUT

Start threshold voltage, UVLO

Stop threshold voltage, UVLO

Hysteresis voltage, UVLO

2.95

2.80

0.16

2.5

3

V

2.70

0.10

V

Rising and falling edge deglitch, UVLO⁽¹⁾

µs

BIAS VOLTAGE

Output voltage, VBIAS

V_O

I_(VBIAS)= 0

2.70

2.80

2.95

100

V

Output current, VBIAS⁽²⁾

µA

CUMULATIVE REFERENCE

V_ref

Accuracy

0.880

0.891

0.900

V

REGULATION

I_L= 1.5 A, f_s= 350 kHz, T_J= 85°C

I_L= 1.5 A, f_s= 550 kHz, T_J= 85°C

I_L= 0 A to 3 A, f_s= 350 kHz, T_J= 85°C

I_L= 0 A to 3 A, f_s= 550 kHz, T_J= 85°C

0.07

0.03

(3)

Line regulation⁽¹⁾

Load regulation⁽¹⁾

%/V

%/A

(3)

(1) Specified by design

(2) Static resistive loads only

(3) Specified by the circuit used in Figure 10.

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ELECTRICAL CHARACTERISTICS (continued)

T_J= –55°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

OSCILLATOR

SYNC ≤ 0.8 V, RT open

255

400

245

450

650

2.5

350

550

280

500

700

450

kHz

700

Internally set free-running frequency range

Externally set free-running frequency range

SYNC ≥ 2.5 V, RT open

RT = 180 kΩ (1% resistor to AGND)⁽⁴⁾

RT = 100 kΩ (1% resistor to AGND)

RT = 68 kΩ (1% resistor to AGND)

313

550

775

kHz

High-level threshold voltage, SYNC

Low-level threshold voltage, SYNC

Pulse duration, SYNC⁽⁵⁾

V

0.8

50

Frequency range, SYNC⁽⁵⁾

Ramp valley⁽⁴⁾

Ramp amplitude (peak-to-peak)⁽⁴⁾

Minimum controllable on time

Maximum duty cycle

330

700

kHz

V

0.75

1

V

200

ns

90%

ERROR AMPLIFIER

Error amplifier open loop voltage gain

Error amplifier unity gain bandwidth

1 kΩ COMP to AGND⁽⁵⁾

90

3

110

5

dB

MHz

V

Parallel 10 kΩ, 160 pF COMP to AGND⁽⁵⁾

Powered by internal LDO⁽⁵⁾

VSENSE = V_ref

Error amplifier common-mode input voltage range

Input bias current, VSENSE

0

VBIAS

250

I_IB

60

nA

V_O

Output voltage slew rate (symmetric), COMP

1.4

V/µs

PWM COMPARATOR

PWM comparator propagation delay time, PWM

10 mV overdrive⁽⁵⁾

70

85

ns

comparator input to PH pin (excluding dead time)

SLOW-START/ENABLE

Enable threshold voltage, SS/ENA

Enable hysteresis voltage, SS/ENA⁽⁴⁾

Falling edge deglitch, SS/ENA⁽⁴⁾

Internal slow-start time

0.82

1.20

0.03

2.5

3.35

5

1.45

V

µs

ms

µA

mA

2.2

2.5

1.2

4.1

8

Charge current, SS/ENA

SS/ENA = 0 V

Discharge current, SS/ENA

SS/ENA = 0.2 V, V_I= 2.7 V

2.3

4

POWER GOOD

Power good threshold voltage

Power good hysteresis voltage⁽⁴⁾

Power good falling edge deglitch⁽⁴⁾

Output saturation voltage, PWRGD

Leakage current, PWRGD

VSENSE falling

90

3

%V_ref

µs

35

I_(sink)= 2.5 mA

V_I= 5.0 V

0.18

0.30

1

V

µA

CURRENT LIMIT

V_I= 3 V, output shorted⁽⁵⁾

V_I= 6 V, output shorted⁽⁵⁾

4

6.5

7.5

Current limit trip point

A

4.5

Current limit leading edge blanking time⁽⁴⁾

Current limit total response time⁽⁴⁾

100

200

ns

THERMAL SHUTDOWN

Thermal shutdown trip point⁽⁴⁾

Thermal shutdown hysteresis⁽⁴⁾

135

150

10

165

°C

OUTPUT POWER MOSFETS

I_O= 0.5 A, VI = 6 V⁽⁶⁾

I_O= 0.5 A, VI = 3 V⁽⁶⁾

59

85

88

r_DS(on)Power MOSFET switches

mΩ

136

(4) Specified by design

(5) Specified by design for T_J= -40°C to 125°C

(6) Matched MOSFETs, low side r_DS(on)production tested, high side r_DS(on)specified by design.

4

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PIN ASSIGNMENTS

PWP PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

AGND

VSENSE

COMP

PWRGD

BOOT

PH

RT

SYNC

SS/ENA

VBIAS

VIN

PGND

PH

TERMINAL FUNCTIONS

TERMINAL

DESCRIPTION

NAME

NO.

Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor

and SYNC pin. Make PowerPAD connection to AGND.

AGND

1

Bootstrap input. 0.022 µF to 0.1 µF low-ESR capacitor connected from BOOT to PH generates floating drive for the

high-side FET driver.

BOOT

COMP

PGND

PH

5

3

Error amplifier output. Connect compensation network from COMP to VSENSE.

Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper

areas to the input and output supply returns, and negative terminals of the input and output capacitors.

11–13

6–10

4

Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.

Power good open drain output. High when VSENSE ≥ 90% V_ref, otherwise PWRGD is low. Note that output is low

when SS/ENA is low or internal shutdown signal active.

PWRGD

RT

20

Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, f_s.

Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and

capacitor input to externally set the start-up time.

SS/ENA

18

Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin

select between two internally set switching frequencies. When used to synchronize to an external signal, a resistor

must be connected to the RT pin.

SYNC

VBIAS

19

17

Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a

high quality, low ESR 0.1 µF to 1.0 µF ceramic capacitor.

Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to

device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.

VIN

14–16

2

VSENSE

Error amplifier inverting input.

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FUNCTIONAL BLOCK DIAGRAM

VBIAS

AGND

VIN

Enable

Comparator

SS/ENA

REG

VBIAS

Falling

Edge

Deglitch

SHUTDOWN

VIN

ILIM

Comparator

1.2 V

3 − 6 V

Thermal

Shutdown

150°C

Hysteresis: 0.03

V

Leading

Edge

2.5 µs

Blanking

VIN UVLO

Comparator

Falling

and

100 ns

VIN

BOOT

Rising

Edge

2.95 V

Deglitch

Hysteresis: 0.16

V

30 mΩ

2.5 µs

SS_DIS

SHUTDOWN

L

OUT

V

O

PH

Internal/External

Slow-start

(Internal Slow-start Time = 3.35 ms

+

−

C

O

Adaptive Dead-Time

and

Control Logic

R

S

Q

Error

Amplifier

PWM

Comparator

Reference

VIN

VREF = 0.891 V

30 mΩ

OSC

PGND

Powergood

Comparator

PWRGD

VSENSE

0.90 V

Falling

Edge

ref

Deglitch

TPS54610

Hysteresis: 0.03 Vref

SHUTDOWN

35 µs

SYNC

VSENSE

COMP

RT

ADDITIONAL 3-A SWIFT DEVICES

DEVICE

OUTPUT VOLTAGE

DEVICE

TPS54314

TPS54315

TPS54316

OUTPUT VOLTAGE

DEVICE

OUTPUT VOLTAGE

DDR/Adjustable

TPS54311

TPS54312

TPS54313

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

TPS54372

TPS54373

TPS54380

Prebias/Adjustable

Sequencing/Adjustable

RELATED DC/DC PRODUCTS

•

TPS40000 — dc/dc controller

PT5500 series — 3-A plug-in modules

TPS757xx — 3-A low dropout regulator

6

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TYPICAL CHARACTERISTICS

DRAIN-SOURCE ON-STATE

RESISTANCE

DRAIN-SOURCE ON-STATE

RESISTANCE

INTERNALLY SET OSCILLATOR

FREQUENCY

vs

JUNCTION TEMPERATURE

120

100

80

100

80

60

40

20

0

750

650

550

450

V = 3.3 V

I

V = 5 V

I

= 3 A

O

I

= 3 A

O

SYNC ≥ 2.5 V

60

SYNC ≤ 0.8 V

40

350

250

20

0

−40

0

25

85

125

−40

0

25

85

125

−40

0

25

85

125

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

T

J

− Junction Temperature − °C

Figure 1.

Figure 2.

Figure 3.

EXTERNALLY SET OSCILLATOR

FREQUENCY

VOLTAGE REFERENCE

vs

OUTPUT VOLTAGE REGULATION

vs

JUNCTION TEMPERATURE

INPUT VOLTAGE

0.895

0.8950

0.8930

0.8910

0.8890

800

T

A

= 85°C

RT = 68 k

RT = 100 k

RT = 180 k

700

600

500

400

0.893

0.891

0.889

f = 350 kHz

0.8870

0.8850

0.887

0.885

300

200

−40

0

25

85

125

−40

0

25

85

125

3

4

5

6

T

J

− Junction Temperature − °C

V − Input Voltage − V

I

T

J

− Junction Temperature − °C

Figure 4.

Figure 5.

Figure 6.

INTERNAL SLOW-START TIME

vs

JUNCTION TEMPERATURE

DEVICE POWER LOSSES

vs

ERROR AMPLIFIER

OPEN LOOP RESPONSE

LOAD CURRENT

0

2.25

2

3.80

3.65

3.50

3.35

3.20

3.05

140

120

100

80

R = 10 kΩ,

L

T

− 125°C

J

−20

−40

−60

−80

C

T

= 160 pF,

= 25°C

L

f

= 700 kHz

s

A

1.75

1.5

V = 3.3 V

I

Phase

1.25

−100

−120

60

1

40

20

V = 5 V

I

Gain

0.75

−140

−160

0.5

0

2.90

2.75

−180

−200

0.25

−20

0

10

100 1 k 10 k 100 k 1 M 10 M

−40

0

25

85

125

1

2

3

4

f − Frequency − Hz

T

J

− Junction Temperature − °C

I

− Load Current − A

L

Figure 7.

Figure 8.

Figure 9.

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APPLICATION INFORMATION

Figure 10 shows the schematic diagram for a typical TPS54310 application. The TPS54310 (U1) can provide up

to 3 A of output current at a nominal output voltage of 3.3 V. For proper thermal performance, the thermal pad

under the TPS54310 integrated circuit needs to be soldered well to the printed-circuit board.

VIN

J1

2

V

I

+

U1

1

C2

1

C8

10 µF

GND

TPS54310PWP

R3

20

16

15

14

RT

VIN

PH

71.5 kΩ

R1

10 kΩ

19

18

17

4

L1

1.2 µH

SYNC

J3

SS/ENA

VBIAS

PWRGD

1

2

10

9

V

O

+

PH

GND

PWRGD

8

C3

0.1 µF

PH

C11

1000 pF

C9

180 µF

4 V

3

COMP

7

PH

6

PH

C7

0.047 µF

2

VSENSE

AGND

5

BOOT

13

12

11

PGND

1

C5

3900 pF

C4

PwrPAD

100 pF

R2

3.74 kΩ

C6

R6

R7

732 Ω

49.9 Ω

2700 pF

R4

R5

3.74 kΩ

10 kΩ

1

Optional

Figure 10. TPS54310 Schematic

INPUT VOLTAGE

SETTING THE OUTPUT VOLTAGE

The input to the circuit is a nominal 5 VDC, applied at

J1. The optional input filter (C2) is a 220-µF POSCAP

capacitor, with a maximum allowable ripple current of

3 A. C8 is the decoupling capacitor for the TPS54310

and must be located as close to the device as

possible.

The output voltage of the TPS54310 can be set by

feeding back a portion of the output to the VSENSE

pin using a resistor divider network. In the application

circuit of Figure 10, this divider network is comprised

of resistors R5 and R4. To calculate the resistor

values to generate the required output voltage use

Equation 1.

FEEDBACK CIRCUIT

R5 x 0.891

R4 =

V

- 0.891

The resistor divider network of R5 and R4 sets the

output voltage for the circuit at 3.3 V. R5, along with

R2, R6, C4, C5, and C6 forms the loop compensation

network for the circuit. For this design, a Type 3

topology is used.

O

(1)

Start with a fixed value of R5 and calculate the

required R4 value. Assuming a fixed value of 10 kΩ

for R5, the following table gives the appropriate R4

value for several common output voltages:

OUTPUT VOLTAGE (V)

R4 VALUE (KΩ)

1.2

1.5

1.8

2.5

3.3

28.7

14.7

9.76

5.49

3.74

8

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There should be an area of ground one the top layer

directly under the IC, with an exposed area for

connection to the PowerPAD. Use vias to connect

this ground area to any internal ground planes. Use

additional vias at the ground side of the input and

output filter capacitors as well. The AGND and PGND

pins should be tied to the PCB ground by connecting

them to the ground area under the device as shown.

The only components that should tie directly to the

power ground plane are the input capacitors, the

output capacitors, the input voltage decoupling

capacitor, and the PGND pins of the TPS54310. Use

a separate wide trace for the analog ground signal

path. This analog ground should be used for the

voltage set point divider, timing resistor RT, slow start

capacitor and bias capacitor grounds. Connect this

trace directly to AGND (pin 1).

OPERATING FREQUENCY

In the application circuit, the 350-kHz operation is

selected by leaving RT and SYNC open. Connecting

a 68-kΩ to 180-kΩ resistor between RT (pin 20) and

analog ground can be used to set the switching

frequency from 280 kHz to 700 kHz. To calculate the

RT resistor, use the Equation 2:

100 kW

R +

500 kHz

ƒ

SW

(2)

OUTPUT FILTER

The output filter is composed of a 1.2-µH inductor

and 180-µF capacitor. The inductor is a low dc

resistance (0.017 Ω) type, Coilcraft DO1813P-122HC.

The capacitor used is a 4-V special polymer type with

a maximum ESR of 0.015 Ω. The feedback loop is

compensated so that the unity gain frequency is

approximately 75 kHz.

The PH pins should be tied together and routed to

the output inductor. Since the PH connection is the

switching node, inductor should be located very close

to the PH pins and the area of the PCB conductor

minimized to prevent excessive capacitive coupling.

PCB LAYOUT

Connect the boot capacitor between the phase node

and the BOOT pin as shown. Keep the boot capacitor

close to the IC and minimize the conductor trace

lengths.

Figure 11 shows a generalized PCB layout guide for

the TPS54310.

The VIN pins should be connected together on the

printed circuit board (PCB) and bypassed with a low

ESR ceramic bypass capacitor. Care should be taken

to minimize the loop area formed by the bypass

capacitor connections, the VIN pins, and the

TPS54X10 ground pins. The minimum recommended

bypass capacitance is 10-µF ceramic with a X5R or

X7R dielectric and the optimum placement is closest

to the VIN pins and the PGND pins.

Connect the output filter capacitor(s) as shown

between the VOUT trace and PGND. It is important to

keep the loop formed by the PH pins, Lout, Cout and

PGND as small as practical.

Place the compensation components from the VOUT

trace to the VSENSE and COMP pins. Do not place

these components too close to the PH trace. Due to

the size of the IC package and the device pinout,

they will have to be routed somewhat close, but

maintain as much separation as possible while still

keeping the layout compact.

The TPS54310 has two internal grounds (analog and

power). Inside the TPS54310, the analog ground ties

to all of the noise sensitive signals, while the power

ground ties to the noisier power signals. Noise

injected between the two grounds can degrade the

performance of the TPS54310, particularly at higher

output currents. Ground noise on an analog ground

plane can also cause problems with some of the

control and bias signals. For these reasons, separate

analog and power ground traces are recommended.

Connect the bias capacitor from the VBIAS pin to

analog ground using the isolated analog ground

trace. If a slow-start capacitor or RT resistor is used,

or if the SYNC pin is used to select 350-kHz

operating frequency, connect them to this trace as

well.

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ANALOG GROUND TRACE

FREQUENCY SET RESISTOR

AGND

RT

SYNC

SS/ENA

VBIAS

VIN

SLOW START

CAPACITOR

VSENSE

COMP

COMPENSATION

NETWORK

PWRGD

BOOT

BIAS CAPACITOR

EXPOSED

POWERPAD

AREA

BOOT

CAPACITOR

Vin

VIN

PH

VOUT

VIN

PGND

OUTPUT INDUCTOR

PH

INPUT

BYPASS

INPUT

BULK

CAPACITOR

FILTER

OUTPUT

FILTER

CAPACITOR

TOPSIDE GROUND AREA

VIA to Ground Plane

Figure 11. TPS54310 PCB Layout

LAYOUT CONSIDERATIONS FOR THERMAL

PERFORMANCE

For operation at full rated load current, the analog

ground plane must provide adequate heat dissipating

area. A 3 inch by 3 inch plane of 1 ounce copper is

recommended, though not mandatory, depending on

ambient temperature and airflow. Most applications

have larger areas of internal ground plane available,

and the PowerPAD should be connected to the

largest area available. Additional areas on the top or

bottom layers also help dissipate heat, and any area

available should be used when 3 A or greater

operation is desired. Connection from the exposed

area of the PowerPAD to the analog ground plane

layer should be made using 0.013 inch diameter vias

to avoid solder wicking through the vias. Six vias

should be in the PowerPAD area with four additional

vias located under the device package. The size of

the vias under the package, but not in the exposed

thermal pad area, can be increased to 0.018.

Additional vias beyond the ten recommended that

enhance thermal performance should be included in

areas not under the device package.

10

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6 PL

4 PL

0.0130

0.0180

Minimum Recommended Thermal Vias: 6 × .013 dia.

Inside Powerpad Area 4 × .018 dia. Under Device as Shown.

Additional .018 dia. Vias May be Used if Top Side Analog

Ground Area is Extended.

Connect Pin 1 to Analog Ground Plane

in This Area for Optimum Performance

0.0150

0.06

0.0227

0.0600

0.0400

0.2560

0.2454

0.1010

0.0400

0.0600

0.0256

0.1700

0.1340

0.0620

0.0400

Minimum Recommended Exposed

Copper Area For Powerpad. 5mm

Stencils may Require 10 Percent

Larger Area

Minimum Recommended Top

Side Analog Ground Area

Figure 12. Recommended Land Pattern for 20-Pin PWP PowerPAD

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PERFORMANCE GRAPHS

EFFICIENCY

vs

OUTPUT CURRENT

OUTPUT VOLTAGE

vs

LOAD CURRENT

LOOP RESPONSE

100

95

135

90

3.4

3.38

3.36

3.34

60

40

20

V = 5 V

I

V = 4 V

I

T

= 25°C

A

V = 5 V

I

Phase

90

85

V = 6 V

I

45

Gain

3.32

3.3

80

75

0

T

A

= 25°C

3.28

3.26

3.24

−45

−20

70

65

−90

1 M

−40

0

1

2

3

4

5

100

1 k

10 k

100 k

0

1

2

3

4

5

I

− Output Current − A

I

− Load Current − A

f − Frequency − Hz

O

L

Figure 13.

Figure 14.

Figure 15.

OUTPUT RIPPLE VOLTAGE

LOAD TRANSIENT RESPONSE

SLOW-START TIMING

V = 5 V

40 µs/div

V (AC)

O

50 mV/div

I

V

(AC)

O

V 2 V/div

I

10 mV/div

V

O

2 V/div

V

5 V/div

PWRGD

I

O

V = 5 V

I

2 A/div

I

O

= 3 A

400 ns/div

1 ms/div

Figure 16.

Figure 17.

Figure 18.

AMBIENT TEMPERATURE

vs

LOAD CURRENT

125

115

105

95

V

= 5 V

I

85

V

= 3.3 V

†

I

75

65

Safe Operating Area

55

45

35

25

0

1

2

3

4

I

− Load Current − A

L

†

Safe operating area is applicable to the test board conditions

listed in the dissipation rating table section of this data sheet.

Figure 19.

12

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VBIAS Regulator (VBIAS)

DETAILED DESCRIPTION

The VBIAS regulator provides internal analog and

digital blocks with a stable supply voltage over

variations in junction temperature and input voltage. A

high quality, low-ESR, ceramic bypass capacitor is

required on the VBIAS pin. X7R or X5R grade

dielectrics are recommended because their values

are more stable over temperature. The bypass

capacitor should be placed close to the BVIAS pin

and returned to AGND. External loading on VBIAS is

allowed, with the caution that internal circuits require

a minimum BVIAS of 2.7 V, and external loads on

VBIAS with ac or digital switching noise may degrade

performance. The VBIAS pin may be useful as a

reference voltage for external circuits.

Under Voltage Lock Out (UVLO)

The TPS54310 incorporates an under voltage lockout

circuit to keep the device disabled when the input

voltage (VIN) is insufficient. During power up, internal

circuits are held inactive until VIN exceeds the

nominal UVLO threshold voltage of 2.95 V. Once the

UVLO start threshold is reached, device start-up

begins. The device operates until VIN falls below the

nominal UVLO stop threshold of 2.8 V. Hysteresis in

the UVLO comparator, and a 2.5-µs rising and falling

edge deglitch circuit reduce the likelihood of shutting

the device down due to noise on VIN.

Slow-Start/Enable (SS/ENA)

Voltage Reference

The slow-start/enable pin provides two functions; first,

the pin acts as an enable (shutdown) control by

keeping the device turned off until the voltage

exceeds the start threshold voltage of approximately

1.2 V. When SS/ENA exceeds the enable threshold,

device start up begins. The reference voltage fed to

the error amplifier is linearly ramped up from 0 V to

0.891 V in 3.35 ms. Similarly, the converter output

voltage reaches regulation in approximately 3.35 ms.

Voltage hysteresis and a 2.5-µs falling edge deglitch

circuit reduce the likelihood of triggering the enable

due to noise.

The voltage reference system produces a precise V_ref

signal by scaling the output of a temperature stable

bandgap circuit. During manufacture, the bandgap

and scaling circuits are trimmed to produce 0.891 V

at the output of the error amplifier, with the amplifier

connected as a voltage follower. The trim procedure

adds to the high precision regulation of the

TPS54310, since it cancels offset errors in the scale

and error amplifier circuits

Oscillator and PWM Ramp

The oscillator frequency can be set to internally fixed

values of 350 kHz or 550 kHz using the SYNC pin as

a static digital input. If a different frequency of

operation is required for the application, the oscillator

frequency can be externally adjusted from 280 kHz to

700 kHz by connecting a resistor to the RT pin to

ground and floating the SYNC pin. The switching

frequency is approximated by the following equation,

where R is the resistance from RT to AGND:

The second function of the SS/ENA pin provides an

external means of extending the slow-start time with

a low-value capacitor connected between SS/ENA

and AGND. Adding a capacitor to the SS/ENA pin

has two effects on start-up. First, a delay occurs

between release of the SS/ENA pin and start up of

the output. The delay is proportional to the slow-start

capacitor value and lasts until the SS/ENA pin

reaches the enable threshold. The start-up delay is

approximately:

100 kW

SWITCHING FREQUENCY +

500 kHz

R

(5)

1.2 V

5 mA

t

+ C

d

(SS)

(3)

External synchronization of the PWM ramp is

possible over the frequency range of 330 kHz to

700 kHz by driving a synchronization signal into

SYNC and connecting a resistor from RT to AGND.

Choose an RT resistor that sets the free-running

frequency to 80% of the synchronization signal.

Second, as the output becomes active, a brief

ramp-up at the internal slow-start rate may be

observed before the externally set slow-start rate

takes control and the output rises at

a rate

proportional to the slow-start capacitor. The slow-start

time set by the capacitor is approximately:

Table

1

summarizes the frequency selection

configurations.

0.7 V

5 mA

t

+ C

(SS)

(4)

The actual slow-start is likely to be less than the

above approximation due to the brief ramp-up at the

internal rate.

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Table 1. Summary of the Frequency Selection Configurations

SWITCHING FREQUENCY

350 kHz, internally set

SYNC PIN

Float or AGND

RT PIN

Float

550 kHz, internally set

≥ 2.5 V

Float

Externally set 280 kHz to 700 kHz

Externally synchronized frequency

Float

R = 68 k to 180 k

Synchronization signal

R = RT value for 80% of external synchronization frequency

Error Amplifier

The high performance, wide bandwidth, voltage error

amplifier sets the TPS54310 apart from most dc/dc

converters. The user is given the flexibility to use a

wide range of output L and C filter components to suit

the particular needs of the application. Type 2 or type

3 compensation can be employed using external

compensation components.

low-side FET remains on until the VSENSE voltage

decreases to

a

range that allows the PWM

comparator to change states. The TPS54310 is

capable of sinking current continuously until the

output reaches the regulation set-point.

If the current limit comparator trips for longer than

100 ns, the PWM latch resets before the PWM ramp

exceeds the error amplifier output. The high-side FET

turns off and low-side FET turns on to decrease the

energy in the output inductor and consequently the

output current. This process is repeated each cycle in

which the current limit comparator is tripped.

PWM Control

Signals from the error amplifier output, oscillator, and

current limit circuit are processed by the PWM control

logic. Referring to the internal block diagram, the

control logic includes the PWM comparator, OR gate,

PWM latch, and portions of the adaptive dead-time

and control logic block. During steady-state operation

below the current limit threshold, the PWM

comparator output and oscillator pulse train

alternately reset and set the PWM latch. Once the

PWM latch is set, the low-side FET remains on for a

minimum duration set by the oscillator pulse duration.

During this period, the PWM ramp discharges rapidly

to its valley voltage. When the ramp begins to charge

back up, the low-side FET turns off and high-side

FET turns on. As the PWM ramp voltage exceeds the

error amplifier output voltage, the PWM comparator

resets the latch, thus turning off the high-side FET

and turning on the low-side FET. The low-side FET

remains on until the next oscillator pulse discharges

the PWM ramp.

Dead-Time Control and MOSFET Drivers

Adaptive dead-time control prevents shoot-through

current from flowing in both N-channel power

MOSFETs during the switching transitions by actively

controlling the turn-on times of the MOSFET drivers.

The high-side driver does not turn on until the gate

drive voltage to the low-side FET is below 2 V. The

low-side driver does not turn on until the voltage at

the gate of the high-side MOSFETs is below 2 V. The

high-side and low-side drivers are designed with

300-mA source and sink capability to quickly drive the

power MOSFETs gates. The low-side driver is

supplied from VIN, while the high-side drive is

supplied from the BOOT pin. A bootstrap circuit uses

an external BOOT capacitor and an internal 2.5-Ω

bootstrap switch connected between the VIN and

BOOT pins. The integrated bootstrap switch improves

drive efficiency and reduces external component

count.

During transient conditions, the error amplifier output

could be below the PWM ramp valley voltage or

above the PWM peak voltage. If the error amplifier is

high, the PWM latch is never reset and the high-side

FET remains on until the oscillator pulse signals the

control logic to turn the high-side FET off and the

low-side FET on. The device operates at its

maximum duty cycle until the output voltage rises to

the regulation set-point, setting VSENSE to

approximately the same voltage as V_ref. If the error

amplifier output is low, the PWM latch is continually

reset and the high-side FET does not turn on. The

Overcurrent Protection

The cycle by cycle current limiting is achieved by

sensing the current flowing through the high-side

MOSFET and differential amplifier and comparing it to

the preset overcurrent threshold. The high-side

MOSFET is turned off within 200 ns of reaching the

current limit threshold.

A 100-ns leading edge

blanking circuit prevents false tripping of the current

limit. Current limit detection occurs only when current

flows from VIN to PH when sourcing current to the

output filter. Load protection during current sink

operation is provided by thermal shutdown.

14

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Thermal Shutdown

Power Good (PWRGD)

The device uses the thermal shutdown to turn off the

power MOSFETs and disable the controller if the

junction temperature exceeds 150°C. The device is

released from shutdown when the junction

temperature decreases to 10°C below the thermal

shutdown trip point and starts up under control of the

slow-start circuit. Thermal shutdown provides

protection when an overload condition is sustained for

several milliseconds. With a persistent fault condition,

the device cycles continuously; starting up by control

of the soft-start circuit, heating up due to the fault,

and then shutting down upon reaching the thermal

shutdown point.

The power good circuit monitors for under voltage

conditions on VSENSE. If the voltage on VSENSE is

10% below the reference voltage, the open-drain

PWRGD output is pulled low. PWRGD is also pulled

low if VIN is less than the UVLO threshold, or

SS/ENA is low, or thermal shutdown is asserted.

When VIN = UVLO threshold, SS/ENA = enable

threshold, and VSENSE > 90% of V_ref, the open drain

output of the PWRGD pin is high. A hysteresis

voltage equal to 3% of V_refand a 35-µs falling edge

deglitch circuit prevent tripping of the power good

comparator due to high frequency noise.

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PACKAGE MATERIALS INFORMATION

www.ti.com

8-May-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

TPS54310MPWPREP HTSSOP PWP

20

2000

330.0

16.4

6.95

7.1

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-May-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 20

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 33.0

TPS54310MPWPREP

2000

Pack Materials-Page 2

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型号：	V62/08606-01XE
厂家：	TEXAS INSTRUMENTS
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