V62/08624-01XE_技术文档

UC2625-EP

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BRUSHLESS DC MOTOR CONTROLLER

1

FEATURES

•

Controlled Baseline

•

Drives Power MOSFETs or Power Darlingtons

Directly

–

One Assembly Site

One Test Site

•

50-V Open Collector High-Side Drivers

Latched Soft Start

One Fabrication Site

High-speed Current-Sense Amplifier with Ideal

Diode

•

Extended Temperature Performance of –55°C

to 125°C

•

Pulse-by-Pulse and Average Current Sensing

Over-Voltage and Under-Voltage Protection

Direction Latch for Safe Direction Reversal

Tachometer

Enhanced Diminishing Manufacturing Sources

(DMS) Support

•

Enhanced Product-Change Notification

(1)

Qualification Pedigree

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an

extended temperature range. This includes, but is not limited

to, Highly Accelerated Stress Test (HAST) or biased 85/85,

temperature cycle, autoclave or unbiased HAST,

Trimmed Reference Sources 30 mA

Programmable Cross-Conduction Protection

Two-Quadrant and Four-Quadrant Operation

electromigration, bond intermetallic life, and mold compound

life. Such qualification testing should not be viewed as

justifying use of this component beyond specified

performance and environmental limits.

DESCRIPTION/ORDERING INFORMATION

The UC2625 motor controller integrates most of the functions required for high-performance brushless dc motor

control into one package. When coupled with external power MOSFETs or Darlingtons, this device performs

fixed-frequency PWM motor control in either voltage or current mode while implementing closed loop speed

control and braking with smart noise rejection, safe direction reversal, and cross-conduction protection.

Although specified for operation from power supplies between 10 V and 18 V, the UC2625 can control higher

voltage power devices with external level-shifting components. The UC2625 contains fast, high-current push-pull

drivers for low-side power devices and 50-V open-collector outputs for high-side power devices or level shifting

circuitry.

The UC2625 is characterized for operation over the military temperature range of –55°C to 125°C.

ORDERING INFORMATION⁽¹⁾

ORDERABLE PART

NUMBER

TOP-SIDE

MARKING

T_A

PACKAGE⁽²⁾

PDIP – N

UC2625MNEP

UC2625EP

–55°C to 125°C

SOIC – DW

UC2625MDWREP

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI website at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

UC2625-EP

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Typical Application

+5 VTOHALL

+15 V

VMOTOR

VREF

SENSORS

+

3 kW

100 nF

100 F

+

2N3904

20

F

20

F

10 W

10 kW

3 kW

R

2

19

11

OSC

33 kW

QUAD

DIR

2N3906

IRF9350

22

6

3 kW

16

17

18

14

13

TO

MOTOR

1 k

TOOTHER

CHANNELS

1

100 nF

28

27

25

UC3625

4 kW

REQUIRED

FORBRAKE

ANDFAST

REVERSE

TOOTHER

CHANNELS

10 W

IRF532

2200 pF

12

20

C

OSC

15

10 kW

BRAKE

21

26

3

24

23

8

9

10

4

5

7

100 nF

5 nF

3 nF

68 kW

REQUIRED

FOR

C

240 W

R

T

FROMHALL

SENSORS

100 nF

AVERAGE

CURRENT

SENSING

0.02 W

2 nF

5 nF

240 W

R

S

51 kW

2 nF

0.02 W

R

D

VREF

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

VCC

20

Supply voltage

PWR VCC

PWM IN

–0.3 to 6

–0.3 to 12

–1.3 to 6

E/A IN(+), E/A IN(–)

V

ISENSE1, ISENSE2

OV-COAST, DIR, SPEED-IN, SSTART, QUAD SEL

–0.3 to 8

H1, H2, H3

–0.3 to 12

–0.3 to 50

+200 continuous

±200 continuous

±10

PU Output Voltage

PU

PD

E/A

Output current

I_SENSE

mA

–10

TACH OUT

VREF

±10

–50 continuous

–55 to 125

T_J

Operating temperature range

°C

(1) Currents are positive into and negative out of the specified terminal.

2

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CONNECTION DIAGRAM

E/A IN(+)

VREF

1

2

3

4

5

6

7

8

9

28 E/A IN(-)

27 E/A OUT

26 PWM IN

25 RC-OSC

24 SSTART

23 OV-COAST

22 QUAD SEL

21 RC-BRAKE

20 TACH-OUT

19 VCC

ISENSE

ISENSE1

ISENSE2

DIR

SPEED-IN

H1

H2

H3 10

PWR VCC 11

PDC 12

18 PUA

17 PUB

PDB 13

16 PUC

PDA 14

15 GND

A. This pinout applies to the SOIC (DW) package.

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ELECTRICAL CHARACTERISTICS

Unless otherwise stated, these specifications apply for: T_A= 25°C; Pwr V_CC= V_CC= 12 V; R_OSC= 20 kΩ to V_REF; C_OSC= 2 nF;

R_TACH= 33 kΩ; C_TACH= 10 nF; and all outputs unloaded. T_A= T_J.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Overall

Supply current

14.5

8.95

8.05

30.0

9.55

8.55

mA

V

VCC turn-on threshold

VCC turn-off threshold

-55°C to 125°C

8.65

7.75

Overvoltage/Coast

OV-COAST inhibit threshold

1.65

1.535

0.05

1.75

1.65

0.10

–1

1.85

1.75

0.155

10

OV-COAST restart threshold

OV-COAST hysteresis

V

-55°C to 125°C

OV-COAST input current

–10

µA

Logic Inputs

H1, H2, H3 low threshold

H1, H2, H3 high threshold

H1, H2, H3 input current

QUAD SEL, dir thresholds

QUAD SEL hysteresis

DIR hysteresis

0.8

1.6

1.0

1.9

–250

1.4

70

1.25

2.0

V

-55°C to 125°C, to 0 V

-55°C to 125°C

–400

0.8

–120

3.0

µA

V

mV

V

0.6

50

QUAD SEL input current

DIR input current

–30

150

30

µA

–1

PWM Amp/Comparator

E/A IN(+), E/A IN(–) input current

PWM IN input current

Error amp input offset

Error amp voltage gain

E/A OUT range

To 2.5 V

–5.0

0

–0.1

3

5.0

30

10

µA

To 2.5 V

0 V < V_COMMON-MODE< 3 V

–10

70

mV

dB

90

0.25

-16

3.50

4.55

–5

V

-55°C to 125°C

To 0 V

Pullup current

–10

µA

To 0 V , -55°C to 125°C

To 2.5 V

–17.5

0.1

-5

S_START

Discharge current

Restart threshold

0.4

0.2

3.0

0.3

mA

V

0.1

Current Amp

Gain

I_SENSE1= 0.3 V, I_SENSE2= 0.5 V to 0.7 V

I_SENSE1= 0.3 V, I_SENSE2= 0.3 V

1.75

2.4

1.95

2.5

2.15

2.65

0.26

0.36

0

V/V

V

Level shift

Peak current threshold

Over current threshold

I_SENSE1, I_SENSE2input current

I_SENSE1, I_SENSE2offset current

Range I_SENSE1, I_SENSE2

0.14

0.26

–850

0.20

0.30

–320

±2

I_SENSE1= 0 V, force I_SENSE2

To 0 V

µA

±12

2

–1

4.7

V

Tachometer/Brake

TACH-OUT high level

TACH-OUT low level

On time

5

5.3

0.2

-55°C to 125°C, 10 kΩ to 2.5 V

V

170

220

0.1%

–1.9

1.0

280

µs

On time change with temp

RC-BRAKE input current

Threshold to brake, RC-brake

Brake hysteresis, RC-brake

-55°C to 125°C

To 0 V

–4.0

0.8

mA

V

-55°C to 125°C

1.2

0.09

4

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ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated, these specifications apply for: T_A= 25°C; Pwr V_CC= V_CC= 12 V; R_OSC= 20 kΩ to V_REF; C_OSC= 2 nF;

R_TACH= 33 kΩ; C_TACH= 10 nF; and all outputs unloaded. T_A= T_J.

PARAMETER

TEST CONDITIONS

-55°C to 125°C

MIN

220

–30

TYP

257

–5

MAX

290

30

UNIT

mV

SPEED-IN threshold

SPEED-IN input current

µA

Low-Side Drivers

Voh, –1 mA, down from V_CC

Voh, –50 mA, down from V_CC

Vol, 1 mA

1.60

1.75

0.05

0.36

50

2.50

2.45

0.4

-55°C to 125°C

V

ns

V

Vol, 50 mA

0.8

Rise/fall time

10% to 90% slew time, into 1 nF

-55°C to 125°C

High-Side Drivers

Vol, 1 mA

0.1

1.0

0.4

1.8

30

Vol, 50 mA

Leakage current

Fall time

Output voltage = 50 V

µA

10% to 90% slew time, 50 mA load

50

ns

Oscillator

Reference

40

35

30

60

65

80

Frequency

-40°C to 105°C

-55°C to 125°C

kHz

Iref = 0 mA

4.9

4.7

–40

–10

50

5.0

–5

5.1

5.3

Output voltage

V

-55°C to 125°C

0 mA to –20 mA load

10 V to 18 V V_CC

-55°C to 125°C

Load regulation

Line regulation

mV

mA

–1

10

Short circuit current

100

150

Miscellaneous

Output turn-on delay

1

µs

Output turn-off delay

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Block Diagram

QUADSEL 22

5 V

REFERENCE

2

VREF

S

R

Q

RC-OSC 25

PWMIN 26

E/AOUT 27

OSC

PWMCLOCK

E/AIN(+)

1

2.9 V

E/AIN(–) 28

SSTART 24

10µA

ISENSE

ISENSE1

ISENSE2

3

4

5

Q1

R

S

Q

0.2 V

ABSVALUE

2.5 V

250 Ω

2X

3.1 V

VCC 19

9 V

PWM

CLOCK

OV-COAST 23

18 PUA

17 PUB

16 PUC

1.75 V

DIR

6

7

DIRECTION

LATCH

SPEED-IN

0.25 V

+5 V

PWMCLOCK

DIR

H1

COAST

CHOP

QUAD

11 PWRVCC

14 PDA

H1

H2

8

9

CROSS

D

L

Q

CONDUCTION

PROTECTION

LATCHES

+5 V

H2

H3

DECODER

D

L

13 PDB

H3 10

D

L

BRAKE

12 PDC

15 GND

EDGE

DETECT

+5 V

2k

RC-BRAKE 21

ONE

SHOT

20 TACH-OUT

1 V

6

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DEVICE INFORMATION

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

The position decoder logic translates the Hall signals and the DIR signal to the

correct driver signals (PUs and PDs). To prevent output stage damage, the signal

on DIR is first loaded into a direction latch, then shifted through a two-bit register.

As long as SPEED-IN is less than 250 mV, the direction latch is transparent. When

SPEED-IN is higher than 250 mV, the direction latch inhibits all changes

indirection. SPEED-IN can be connected to TACH-OUT through a filter, so that the

direction latch is only transparent when the motor is spinning slowly, and has too

little stored energy to damage power devices.

Additional circuitry detects when the input and output of the direction latch are

different, or when the input and output of the shift register are different, and inhibits

all output drives during that time. This can be used to allow the motor to coast to a

safe speed before reversing.

DIR, SPEED-IN

6, 7

The shift register ensures that direction can not be changed instantaneously. The

register is clocked by the PWM oscillator, so the delay between direction changes

is always going to be between one and two oscillator periods. At 40 kHz, this

corresponds to a delay of between 25 µs and 50 µs. Regardless of output stage,

25 µs deadtime should be adequate to ensure no overlap cross-conduction.

Toggling DIR causes an output pulse on TACH-OUT regardless of motor speed.

E/A IN(+) and E/A IN(–) are not internally committed to allow for a wide variety of

uses. They can be connected to the ISENSE, to TACH-OUT through a filter, to an

external command voltage, to a D/A converter for computer control, or to another

op amp for more elegant feedback loops. The error amplifier is compensated for

unity gain stability, so E/A OUT can be tied to E/A IN(–) for feedback and major

loop compensation.

E/A OUT and PWM In drive the PWM comparator. For voltage-mode PWM

systems, PWM In can be connected to RC-OSC. The PWM comparator clears the

PWM latch, commanding the outputs to chop.

E/A IN(+), E/A IN(–), E/A

OUT, PWM IN

1, 28, 27,

26

The error amplifier can be biased off by connecting E/A IN(–) to a higher voltage

than /EA IN(+). When biased off, E/A OUT appears to the application as a resistor

to ground. E/A OUT can then be driven by an external amplifier.

All thresholds and outputs are referred to the GND pin except for the PD and PU

outputs.

GND

15

The three shaft position sensor inputs consist of hysteresis comparators with input

pullup resistors. Logic thresholds meet TTL specifications and can be driven by

5-V CMOS, 12-V CMOS, NMOS, or open-collectors.

Connect these inputs to motor shaft position sensors that are positioned 120

electrical degrees apart. If noisy signals are expected, zener clamp and filter these

inputs with 6-V zeners and an RC filter. Suggested filtering components are 1 kΩ

and 2 nF. Edge skew in the filter is not a problem, because sensors normally

generate modified gray code with only one output changing at a time, but rise and

fall times must be shorter than 20 µs for correct tachometer operation. Motors with

60 electrical degree position sensor coding can be used if one or two of the

position sensor signals is inverted.

H1, H2, H3

8, 9, 10

The current sense amplifier has a fixed gain of approximately two. It also has a

built-in level shift of approximately 2.5 V. The signal appearing on ISENSE is:

I_SENSE= 2.5 V + (2 × ABS ( I_SENSE1– I_SENSE2) )

I_SENSE1and I_SENSE2are interchangeable and can be used as differential inputs.

The differential signal applied can be as high as ±0.5 V before saturation.

If spikes are expected on ISENSE1 or ISENSE2, they are best filtered by a

capacitor from ISENSE to ground. Filtering this way allows fast signal inversions to

be correctly processed by the absolute value circuit. The peak-current comparator

allows the PWM to enter a current-limit mode with current in the windings never

exceeding approximately 0.2 V / R_SENSE. The overcurrent comparator provides a

fail-safe shutdown in the unlikely case of current exceeding 0.3 V / R_SENSE. Then,

softstart is commanded, and all outputs are turned off until the high current

condition is removed. It is often essential to use some filter driving ISENSE1 and

ISENSE2 to reject extreme spikes and to control slew rate. Reasonable starting

values for filter components might be 250-Ω series resistors and a 5-nF capacitor

between ISENSE1 and ISENSE2. Input resistors should be kept small and

matched to maintain gain accuracy.

ISENSE1, ISENSE2,

ISENSE

3, 4, 5

This input can be used as an over-voltage shut-down input, as a coast input, or

both. This input can be driven by TTL, 5-V CMOS, or 12-V CMOS.

OV-COAST

23

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Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

These outputs can drive the gates of N-channel power MOSFETs directly or they

can drive the bases of power Darlingtons if some form of current limiting is used.

They are meant to drive low-side power devices in high-current output stages.

Current available from these pins can peak as high as 0.5 A. These outputs feature

a true totem-pole output stage. Beware of exceeding device power dissipation

limits when using these outputs for high continuous currents. These outputs pull

high to turn a “low-side” device on (active high).

PDA, PDB, PDC

12, 13, 14

These outputs are open-collector, high-voltage drivers that are meant to drive

high-side power devices in high-current output stages. These are active low

outputs, meaning that these outputs pull low to command a high-side device on.

These outputs can drive low-voltage PNP Darlingtons and P-channel MOSFETs

directly, and can drive any high-voltage device using external charge pump

techniques, transformer signal coupling, cascode level-shift transistors, or

opto-isolated drive (high-speed opto devices are recommended). (See

applications).

PUA, PUB, PUC

PWR VCC

16, 17, 18

This supply pin carries the current sourced by the PD outputs. When connecting

PD outputs directly to the bases of power Darlingtons, the PWR VCC pin can be

current limited with a resistor. Darlington outputs can also be "Baker Clamped" with

diodes from collectors back to PWR VCC. (See Applications)

11

The device can chop power devices in either of two modes, referred to as

“two-quadrant” (Quad Sellow) and “four quadrant” (Quad Sel high). When

two-quadrant chopping, the pulldown power devices are chopped by the output of

the PWM latch while the pullup drivers remain on. The load chops into one

commutation diode, and except for back-EMF, will exhibit slow discharge current

and faster charge current. Two-quadrant chopping can be more efficient than

four-quadrant.

QUAD SEL

22

When four-quadrant chopping, all power drivers are chopped by the PWM latch,

causing the load current to flow into two diodes during chopping. This mode

exhibits better control of load current when current is low, and is preferred in servo

systems for equal control over acceleration and deceleration. The QUAD SEL input

has no effect on operation during braking.

Each time the TACH-OUT pulses, the capacitor tied to RC-BRAKE discharges

from approximately 3.33 V down to 1.67 V through a resistor. The tachometer

pulse width is approximately T = 0.67 R_TC_T, where R_Tand C_Tare a resistor and

capacitor from RC-BRAKE to ground. Recommended values for R_Tare 10 kΩ to

500 kΩ, and recommended values for C_Tare 1 nF to 100 nF, allowing times

between 5 µs and 10 ms. Best accuracy and stability are achieved with values in

the centers of those ranges.

RC-BRAKE also has another function. If RC-BRAKE pin is pulled below the brake

threshold, the device enters brake mode. This mode consists of turning off all three

high-side devices, enabling all three low-side devices, and disabling the

tachometer. The only things that inhibit low-side device operation in braking are

low-supply, exceeding peak current, OV-COAST command, and the PWM

comparator signal. The last of these means that if current sense is implemented

such that the signal in the current sense amplifier is proportional to braking current,

the low-side devices will brake the motor with current control. (See applications)

Simpler current sense connections results in uncontrolled braking and potential

damage to the power devices.

RC-BRAKE

21

The UC3625 can regulate motor current using fixed-frequency pulse width

modulation (PWM). The RC-OSC pin sets oscillator frequency by means of timing

resistor R_OSCfrom the RC-OSC pin to VREF and capacitor COSC from RC-OSC

to Gnd. Resistors 10 kΩ to 100 kΩ and capacitors 1 nF to 100 nF works the best,

but frequency should always be below 500 kHz. Oscillator frequency is

approximately:

RC-OSC

25

F = 2/(R_OSCx C_OSC)

Additional components can be added to this device to cause it to operate as a

fixed off-time PWM rather than a fixed frequency PWM, using the RC-OSC pin to

select the monostable time constant.

The voltage on the RC-OSC pin is normally a ramp of about 1.2 V peak-to-peak,

centered at approximately 1.6 V. This ramp can be used for voltage-mode PWM

control, or can be used for slope compensation in current-mode control.

8

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Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Any time that VCC drops below threshold or the sensed current exceeds the

over-current threshold, the soft-start latch is set. When set, it turns on a transistor

that pulls down on SSTART. Normally, a capacitor is connected to this pin, and the

transistor will completely discharge the capacitor. A comparator senses when the

NPN transistor has completely discharged the capacitor, and allows the soft-start

latch to clear when the fault is removed. When the fault is removed, the soft-start

capacitor charges from the on-chip current source.

SSTART clamps the output of the error amplifier, not allowing the error amplifier

output voltage to exceed SSTART regardless of input. The ramp on RC-OSC can

be applied to PWM In and compared to E/A OUT. With SSTART discharged below

0.2 V and the ramp minimum being approximately 1.0 V, the PWM comparator

keeps the PWM latch cleared and the outputs off. As SSTART rises, the PWM

comparator begins to duty-cycle modulate the PWM latch until the error amplifier

inputs overcome the clamp. This provides for a safe and orderly motor start-up

from an off or fault condition. A 51-kΩ resister is added between VREF and

SSTART to ensure switching.

SSTART

24

Any change in the H1, H2, or H3 inputs loads data from these inputs into the

position sensor latches. At the same time data is loaded, a fixed-width 5-V pulse is

triggered on TACH-OUT. The average value of the voltage on TACH-OUT is

directly proportional to speed, so this output can be used as a true tachometer for

speed feedback with an external filter or averaging circuit which usually consists of

a resistor and capacitor.

TACH-OUT

20

Whenever TACH-OUT is high, the position latches are inhibited, such that during

the noisiest part of the commutation cycle, additional commutations are not

possible. Although this effectively sets a maximum rotational speed, the maximum

speed can be set above the highest expected speed, preventing false commutation

and chatter.

This device operates with supplies between 10 V and 18 V. Under-voltage lockout

keeps all outputs off below 7.5 V, insuring that the output transistors never turn on

until full drive capability is available. Bypass VCC to ground with an 0.1-µF ceramic

capacitor. Using a 10-µF electrolytic bypass capacitor as well can be beneficial in

applications with high supply impedance.

VCC

19

2

This pin provides regulated 5 V for driving Hall-effect devices and speed control

circuitry. VREF reaches 5 V before VCC enables, ensuring that Hall-effect devices

powered from VREF becomes active before the UC3625 drives any output. For

proper performance VREF should be bypassed with at least a 0.1-µF capacitor to

ground.

VREF

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TYPICAL CHARACTERISTICS

Oscillator Frequency

vs

Tachometer on Time

vs

C_OSCand R_OSC

RT and CT

100 ms

10 ms

1 MHz

R

T

– 500 k

R

T

– 100 k

R

OSC

– 10 k

100 kHz

R

OSC

– 10 k

1 ms

100 ms

10 ms

1 ms

R

OSC

– 100 k

10 kHz

1 kHz

R

T

– 10 k

R

T

– 30 k

0.001

0.01

– mF

0.1

100 Hz

0.001

0.01

(mF)

0.1

C

T

C

OSC

Figure 1.

Figure 2.

Supply Current

vs

Temperature

Soft-Start Pullup Current

vs

Temperature

20

18

16

-5

-6

-7

14

12

10

-8

-9

-10

8

6

-11

-12

4

2

-13

-14

0

-75

-15

-75

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature – 5C

Figure 3.

Figure 4.

10

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www.ti.com .................................................................................................................................................................................................. SLUS802–MARCH 2008

TYPICAL CHARACTERISTICS (continued)

Soft-Start Discharge Current

Current Sense Amplifier Transfer Function

vs

Temperature

I_SENSE2– I_SENSE1

1.25

1.00

3.5

.75

.50

.25

0

3

2.5

-0.5

-75

-50

-25

0

25

50

75

100

125

0.0

0.5

Temperature – 5C

I

– I

SENSE1

– V

SENSE2

Figure 5.

Figure 6.

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UC2625-EP

SLUS802–MARCH 2008 .................................................................................................................................................................................................. www.ti.com

APPLICATION INFORMATION

Cross Conduction Prevention

The UC2625 inserts delays to prevent cross conduction due to overlapping drive signals. However, some thought

must always be given to cross conduction in output stage design because no amount of dead time can prevent

fast slewing signals from coupling drive to a power device through a parasitic capacitance.

The UC2625 contains input latches that serve as noise blanking filters. These latches remain transparent through

any phase of a motor rotation and latch immediately after an input transition is detected. They remain latched for

two cycles of the PWM oscillator. At a PWM oscillator speed of 20 kHz, this corresponds to 50 µs to 100 µs of

blank time which limits maximum rotational speed to 100 kRPM for a motor with six transitions per rotation or 50

kRPM for a motor with 12 transitions per rotation.

This prevents noise generated in the first 50 µs of a transition from propagating to the output transistors and

causing cross-conduction or chatter.

The UC2625 also contains six flip flops corresponding to the six output drive signals. One of these flip flops is set

every time that an output drive signal is turned on, and cleared two PWM oscillator cycles after that drive signal

is turned off. The output of each flip flop is used to inhibit drive to the opposing output (Figure 7). In this way, it is

impossible to turn on driver PUA and PDA at the same time. It is also impossible for one of these drivers to turn

on without the other driver having been off for at least two PWM oscillator clocks.

EDGE

FINDER

SHIFT

REG

S

R

Q

PUA

PWM

CLK

PULL UP

S

R

Q

FROM

DECODER

PULL

PDA

DOWN

Figure 7. Cross Conduction Prevention

12

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UC2625-EP

www.ti.com .................................................................................................................................................................................................. SLUS802–MARCH 2008

Power Stage Design

The UC2625 is useful in a wide variety of applications, including high-power in robotics and machinery. The

power output stages used in such equipment can take a number of forms, according to the intended performance

and purpose of the system. Figure 8 show four different power stages with the advantages and disadvantages of

each.

For high-frequency chopping, fast recovery circulating diodes are essential. Six are required to clamp the

windings. These diodes should have a continuous current rating at least equal to the operating motor current,

since diode conduction duty-cycle can be high. For low-voltage systems, Schottky diodes are preferred. In higher

voltage systems, diodes such as Microsemi UHVP high voltage platinum rectifiers are recommended.

In a pulse-by-pulse current control arrangement, current sensing is done by resistor R_S, through which the

transistor's currents are passed (Fig. A, B, and C). In these cases, R_Dis not needed. The low-side circulating

diodes go to ground and the current sense terminals of the UC2625 (I_SENSE1and I_SENSE2) are connected to R_S

through a differential RC filter. The input bias current of the current sense amplifier causes a common mode

offset voltage to appear at both inputs, so for best accuracy, keep the filter resistors below 2 kΩ and matched.

The current that flows through R_Sis discontinuous because of chopping. It flows during the on time of the power

stage and is zero during the off time. Consequently, the voltage across R_Sconsists of a series of pulses,

occurring at the PWM frequency, with a peak value indicative of the peak motor current.

To sense average motor current instead of peak current, add another current sense resistor (R_Din Fig. D) to

measure current in the low-side circulating diodes, and operate in four quadrant mode (pin 22 high). The

negative voltage across R_Dis corrected by the absolute value current sense amplifier. Within the limitations

imposed by Table 1, the circuit of Fig. B can also sense average current.

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UC2625-EP

SLUS802–MARCH 2008 .................................................................................................................................................................................................. www.ti.com

FIGURE A

FIGURE B

TO

MOTOR

TO

MOTOR

R_S

FIGURE C

FIGURE D

TO

MOTOR

R_S

R_D

R_S

Figure 8. Four Power Stage Designs

Table 1. Imposed Limitations for Figure 8

CURRENT SENSE

SAFE

BRAKING

2 QUADRANT 4 QUADRANT

POWER REVERSE

Pulse-by-Pulse

Average

No

Figure A

Figure B

Figure C

Figure D

Yes

No

N0

Yes

In 4-quad mode only

Yes

No

Yes

14

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UC2625-EP

www.ti.com .................................................................................................................................................................................................. SLUS802–MARCH 2008

For drives where speed is critical, P-channel MOSFETs can be driven by emitter followers as shown in Figure 9.

Here, both the level shift NPN and the PNP must withstand high voltages. A zener diode is used to limit

gate-source voltage on the MOSFET. A series gate resistor is not necessary, but always advisable to control

overshoot and ringing.

High-voltage optocouplers can quickly drive high-voltage MOSFETs if a boost supply of at least 10 V greater

than the motor supply is provided (See Figure 10) To protect the MOSFET, the boost supply should not be

higher than 18 V above the motor supply.

For under 200-V 2-quadrant applications, a power NPN driven by a small P-Channel MOSFET performs well as

a high-side driver as in Figure 11. A high voltage small-signal NPN is used as a level shift and a high voltage

low-current MOSFET provides drive. Although the NPN does not saturate if used within its limitations, the

base-emitter resistor on the NPN is still the speed-limiting component.

Figure 12 shows a power NPN Darlington drive technique using a clamp to prevent deep saturation. By limiting

saturation of the power device, excessive base drive is minimized and turn-off time is kept fairly short. Lack of

base series resistance also adds to the speed of this approach.

Figure 9. Fast High-Side P-Channel Driver

Figure 10. Optocoupled N-Channel High-Side Driver

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SLUS802–MARCH 2008 .................................................................................................................................................................................................. www.ti.com

Figure 11. Power NPN High-Side Driver

Figure 12. Power NPN Low-Side Driver

16

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Product Folder Link(s) :UC2625-EP

UC2625-EP

www.ti.com .................................................................................................................................................................................................. SLUS802–MARCH 2008

Fast High-Side N-Channel Driver with Transformer Isolation

A small pulse transformer can provide excellent isolation between the UC2625 and a high-voltage N-Channel

MOSFET while also coupling gate drive power. In this circuit (shown in Figure 13), a UC3724 is used as a

transformer driver/encoder that duty-cycle modulates the transformer with a 150-kHz pulse train. The UC3725

rectifies this pulse train for gate drive power, demodulates the signal, and drives the gate with over 2-A peak

current.

+12V

VMOTOR

3

33kW

6

4

7

8

PUA

2

4

7

UC3724N

UC3725N

1:2

8

1

2

5

1

6

3

5kW

1nF

100nF

TO MOTOR

Figure 13. Fast High-Side N-Channel Driver with Transformer Isolation

Both the UC3724 and the UC3725 can operate up to 500 kHz if the pulse transformer is selected appropriately.

To raise the operating frequency, either lower the timing resistor of the UC3724 (1 kΩ min), lower the timing

capacitor of the UC3724 (500 pF min) or both.

If there is significant capacitance between transformer primary and secondary, together with very high output

slew rate, then it may be necessary to add clamp diodes from the transformer primary to 12 V and ground.

General purpose small signal switching diodes such as 1N4148 are normally adequate.

The UC3725 also has provisions for MOSFET current limiting. See the UC3725 data sheet for more information

on implementing this.

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Product Folder Link(s) :UC2625-EP

UC2625-EP

SLUS802–MARCH 2008 .................................................................................................................................................................................................. www.ti.com

Computational Truth Table

Table 2 shows the outputs of the gate drive and open collector outputs for given hall input codes and direction

signals. Numbers at the top of the columns are pin numbers.

These devices operate with position sensor encoding that has either one or two signals high at a time, never all

low or all high. This coding is sometimes referred to as "120° Coding" because the coding is the same as coding

with position sensors spaced 120 magnetic degrees about the rotor. In response to these position sense signals,

only one low-side driver turns on (go high) and one high-side driver turns on (pull low) at any time.

Table 2. Computational Truth Table

INPUTS

OUTPUTS

DIR

6

H1

8

0

1

0

1

0

H2

9

0

1

0

1

0

1

0

H3

10

1

Low-Side

High-Side

12

L

13

H

L

14

L

16

L

17

H

L

18

H

L

1

L

H

L

1

0

L

H

L

1

0

H

L

1

0

L

H

L

1

H

L

0

1

L

H

L

H

L

0

L

H

L

0

L

H

L

0

L

H

0

1

H

L

0

1

L

H

X

1

L

H

0

L

18

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UC2625-EP

www.ti.com .................................................................................................................................................................................................. SLUS802–MARCH 2008

+15V

VMOTOR

+5V TO HALL

SENSORS

VREF

+

3kW

100nF

100mF

+

2N3904

10W

20mF

10kW

3kW

R_OSC

33kW

2

19

11

QUAD

DIR

2N3906

IRF9350

22

6

3kW

16

17

18

14

13

TO

MOTOR

1k

TO OTHER

CHANNELS

1

28

27

25

UC3625

4kW

REQUIRED

FOR BRAKE

AND FAST

REVERSE

100nF

TO OTHER

CHANNELS

10W

IRF532

2200pF

C_OSC

12

20

15

10kW

BRAKE

21

26

3

24

23

8

9

10

4

5

7

100nF

5nF

3nF

C_T

68kW

R_T

REQUIRED

FOR

240W

FROM

HALL

SENSORS

100nF

AVERAGE

CURRENT

SENSING

0.02

W

2nF

5nF

240W

51kW

2nF

R_S

0.02

W

R_D

VREF

Figure 14. 45-V/8-A Brushless DC Motor Drive Circuit

N-Channel power MOSFETs are used for low-side drivers, while P-Channel power MOSFETs are shown for

high-side drivers. Resistors are used to level shift the UC2625 open-collector outputs, driving emitter followers

into the MOSFET gate. A 12-V zener clamp insures that the MOSFET gate-source voltage never exceeds 12 V.

Series 10-Ω gate resistors tame gate reactance, preventing oscillations and minimizing ringing.

The oscillator timing capacitor should be placed close to pins 15 and 25, to keep ground current out of the

capacitor. Ground current in the timing capacitor causes oscillator distortion and slaving to the commutation

signal.

The potentiometer connected to pin 1 controls PWM duty cycle directly, implementing a crude form of speed

control. This control is often referred to as "voltage mode" because the potentiometer position sets the average

motor voltage. This controls speed because steady-state motor speed is closely related to applied voltage.

Pin 20 (Tach-Out) is connected to pin 7 (SPEED IN) through an RC filter, preventing direction reversal while the

motor is spinning quickly. In two-quadrant operation, this reversal can cause kinetic energy from the motor to be

forced into the power MOSFETs.

A diode in series with the low-side MOSFETs facilitates PWM current control during braking by insuring that

braking current will not flow backwards through low-side MOSFETs. Dual current-sense resistors give continuous

current sense, whether braking or running in four-quadrant operation, an unnecessary luxury for two-quadrant

operation.

The 68-kΩ and 3-nF tachometer components set maximum commutation time at 140 µs. This permits smooth

operation up to 35,000 RPM for four-pole motors, yet gives 140 µs of noise blanking after commutation.

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Product Folder Link(s) :UC2625-EP

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2008

PACKAGING INFORMATION

Orderable Device

UC2625MDWREP

UC2625MNEP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

DW

28

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

PDIP

SOIC

N

13 Green (RoHS & CU NIPDAU N / A for Pkg Type

no Sb/Br)

V62/08624-01XE

V62/08624-01YE

13 Green (RoHS & CU NIPDAU N / A for Pkg Type

no Sb/Br)

DW

1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UC2625-EP :

Catalog: UC2625

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

UC2625MDWREP

SOIC

DW

28

1000

330.0

32.4

11.35

18.67

3.1

16.0

32.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC DW 28

SPQ

Length (mm) Width (mm) Height (mm)

346.0 346.0 49.0

UC2625MDWREP

1000

Pack Materials-Page 2

IMPORTANT NOTICE

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型号：	V62/08624-01XE
厂家：	TEXAS INSTRUMENTS
描述：	BRUSHLESS DC MOTOR CONTROLLER 直流无刷电机控制器运动控制电子器件信号电路光电二极管电动机控制电机控制器
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