bq24130RHLT [TI]

600-kHz Synchronous Switch-Mode Host-Controlled Battery/Supercapacitor Charger With 4-A Integrated MOSFETs; 600 - kHz的同步开关模式主机控制的电池/超级电容器充电器, 4 -A集成的MOSFET
bq24130RHLT
型号: bq24130RHLT
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

600-kHz Synchronous Switch-Mode Host-Controlled Battery/Supercapacitor Charger With 4-A Integrated MOSFETs
600 - kHz的同步开关模式主机控制的电池/超级电容器充电器, 4 -A集成的MOSFET

电池 开关 电容器
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bq24130  
www.ti.com  
SLUSAN2C JULY 2011REVISED JUNE 2012  
600-kHz Synchronous Switch-Mode Host-Controlled  
Battery/Supercapacitor Charger With 4-A Integrated MOSFETs  
Check for Samples: bq24130  
1
FEATURES  
2
600kHz Synchronous Switch-mode Charger  
with 4 A Integrated N-MOSFETs  
Small QFN Package  
3.5 mm x 4.5 mm QFN-20 pin  
Up to 96% Efficiency  
APPLICATIONS  
30 V Input Rating with 18V Overvoltage  
Protection  
Tablet PC  
4.5 V to 17 V Input Operating Range  
Battery Charge Voltage  
1, 2,or 3-Cell With 4.2V/Cell  
Netbook and Ultra-Mobile Computers  
Portable Data Capture Terminals  
Portable Printers  
Constant Current Super Capacitor Charging  
High Integration  
Medical Diagnostics Equipment  
Battery Bay Chargers  
Integrated 20-V Switching MOSFETs  
Integrated Bootstrap Diode  
Internal Loop Compensation  
Internal Digital Soft Start  
Back-Up Systems  
Li-Ion/Li-Polymer Battery and Super Capacitor  
Applications  
SW  
SW  
Safety  
PVCC  
PVCC  
AVCC  
STAT  
TS  
PGND  
PGND  
BTST  
REGN  
ISET2  
SRP  
Thermal Regulation Loop Throttles Back  
Current to Limit TJ = 120°C  
bq24130  
Thermal Shutdown  
Battery Thermistor Sense Hot/Cold Charge  
Suspend  
CMOD  
VREF  
AGND  
Input Overvoltage Protection  
Cycle by Cycle Current Limit  
SRN  
BAT  
Accuracy  
±0.5% Charge Voltage Regulation  
±4% Charge Current Regulation  
ISET1  
CELL  
Less than 15 µA Battery Current with Adapter  
Removed  
DESCRIPTION  
The bq24130 is an integrated host-controlled Li-ion and Li-polymer switch-mode battery charge controllers with  
two integrated N-channel power MOSFETs. It offers a constant-frequency synchronous PWM controller with high  
accuracy regulation of charge current and voltage. The fast charge and precharge current can be either  
hardwired with resistors or programmed by system power management microcontroller using a DAC or GPIOs.  
Battery remote sensing provides accurate charge voltage regulation.  
The bq24130 monitors the battery pack temperature to allow charger only in a preset temperature window. The  
thermal regulation loop reduces the charge current to maintain the junction temperature of 120ºC during  
operation.  
The bq24130 automatically enters a low-quiescent current sleep mode when the input voltage falls below the  
battery voltage. The bq24130 charges one, two or three cell (selected by CELL pin), supporting up to 4 A charge  
current. The bq24130 is available in a 20-pin, 3.5 x 4.5 mm2 thin QFN package.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
PowerPAD is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2011–2012, Texas Instruments Incorporated  
 
 
bq24130  
SLUSAN2C JULY 2011REVISED JUNE 2012  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
PIN FUNCTIONS  
PIN  
NAME  
TYPE  
FUNCTION DESCRIPTION  
Switching node, charge current output inductor connection. Connect the 0.47-µF bootstrap capacitor from  
SW to BTST.  
1, 20  
SW  
P
Charger input voltage. Connect at least 10-µF ceramic capacitor from PVCC to PGND and place it as  
close as possible to IC.  
2, 3  
4
PVCC  
AVCC  
P
P
IC power positive supply. Place a 1-µF ceramic capacitor from AVCC to AGND and place it as close as  
possible to IC. Place a 10 ohm resistor from input side to AVCC pin to filter the noise. For 5 V input, a 5-Ω  
resistor is recommended.  
Open-drain charge status pin with 10-kΩ pull up to power rail. The STAT pin can be used to drive LED or  
communicate with the host processor. It indicates various charger operations: LOW when charge in  
process, HIGH when charge complete or SLEEP mode. Blinking when fault occurs, such as charge  
suspend, and input overvoltage.  
5
STAT  
O
Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program  
the hot and cold temperature window with a resistor divider from VREF to TS to AGND. The temperature  
qualification window can be set to 5-40ºC or wider. The 103AT thermister is recommended.  
6
7
TS  
I
I
Charge mode selection: low (pull down to AGND) for pre-charge current as set by ISET2 pin and high (pull  
up to VREF) for fast charge current as set by ISET1 pin. If the battery voltage reaches the voltage  
regulation set point, IC changes to voltage regulation mode regardless of CMOD pin input.  
CMOD  
3.3 V reference voltage output. Place a 1-µF ceramic capacitor from VREF to AGND pin close to the IC.  
This voltage could be used for programming charge current regulation on ISET1 and ISET2 pins,  
programming the threshold of TS pin, and the pull-up rail of STAT pin and CELL pin.  
8
9
VREF  
AGND  
P
P
Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout,  
connect to the analog ground plane, and only connect to PGND through the PowerPad underneath the IC.  
Fast charge current set point. Use a voltage divider from VREF to AGND to set this value.  
V
ISET1  
(
)
I
=
(CHG)  
10  
ISET1  
I
20 ´ R(SR)  
The charger is disabled when ISET1 pin voltage is below 50mV and is enabled when ISET1 pin voltage is  
above 100mV.  
11  
12  
CELL  
BAT  
I
I
Cell selection pin. Set CELL pin LO for 1-cell, Float for 2-cell, and HI for 3-cell with a fixed 4.2 V per cell.  
Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal  
to the BAT pin to accurately sense the battery pack voltage. Place a 0.1-µF capacitor from BAT to AGND  
close to the IC to filter high frequency noise.  
Charge current sense resistor, negative input. A 0.1-µF ceramic capacitor is placed from SRN to SRP to  
provide differential-mode filtering. A 0.1-µF ceramic capacitor is placed from SRN pin to AGND for  
common-mode filtering.  
13  
14  
SRN  
SRP  
I
Charge current sense resistor, positive input. A 0.1-µF ceramic capacitor is placed from SRN to SRP to  
provide differential-mode filtering. A 0.1-µF ceramic capacitor is placed from SRP pin to AGND for  
common-mode filtering.  
P/I  
Pre-charge current set point. Use a voltage divider from VREF to AGND to set this value.  
V
ISET2  
(
)
15  
ISET2  
I
I
=
(PRECHG)  
100 ´ R(SR)  
PWM low side driver positive 6V supply output. Connect a 1-µF ceramic capacitor from REGN to PGND  
pin, close to the IC. Use for low side driver and high-side driver bootstrap voltage by integrated diode from  
REGN to BTST.  
16  
REGN  
BTST  
PGND  
P
P
17  
PWM high side driver positive supply. Connect the 47 nF bootstrap capacitor from SW to BTST.  
Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly  
to source of low-side power MOSFET, to ground connection of in put and output capacitors of the charger.  
Only connect to AGND through the PowerPAD underneath the IC.  
18, 19  
Exposed pad beneath the IC. Always solder PowerPAD to the board, and have vias on the PowerPAD  
plane star-connecting to AGND and ground plane for high-current power converter. It also serves as a  
thermal pad to dissipate the heat.  
PowerPAD™  
Pad  
Pad  
ORDERING INFORMATION(1)  
PART NUMBER  
MARKING  
PACKAGE  
ORDERING NUMBER  
QUANTITY  
3000  
bq24130RHLR  
bq24130  
bq24130  
20-pin 3.5 x 4.5mm2 QFN  
bq24130RHLT  
250  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
2
Submit Documentation Feedback  
Copyright © 2011–2012, Texas Instruments Incorporated  
Product Folder Link(s): bq24130  
 
bq24130  
www.ti.com  
SLUSAN2C JULY 2011REVISED JUNE 2012  
ABSOLUTE MAXIMUM RATINGS(1) (2)  
over operating free-air temperature range (unless otherwise noted)  
VALUE  
UNIT  
MIN  
–0.3  
–0.3  
–0.3  
–2  
MAX  
20  
PVCC  
V
V
AVCC, STAT  
30  
SRP, SRN, BAT  
Voltage  
20  
V
(with respect to AGND and  
PGND)  
SW  
20  
V
REGN, TS, CELL, CMOD  
BTST  
–0.3  
–0.3  
–0.3  
–0.5  
–40  
–55  
7
V
26  
V
VREF, ISET1, ISET2  
3.6  
0.5  
155  
155  
V
Maximum difference voltage SRP–SRN  
Junction temperature, TJ  
V
°C  
°C  
Storage temperature, Tstg  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage  
values are with respect to the network ground terminal unless otherwise noted.  
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal, if not specified.  
Consult Packaging Section of the data sheet for thermal limitations and considerations of packages.  
THERMAL INFORMATION  
bq24130  
THERMAL METRIC(1)(2)  
UNITS  
RHL (20 PIN)  
θJA  
Junction-to-ambient thermal resistance  
35  
N/A  
N/A  
0.4  
9.1  
2.1  
θJCtop  
θJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
ψJB  
θJCbot  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.  
RECOMMENDED OPERATING CONDITIONS  
MIN  
MAX  
17  
UNIT  
V
Input voltage  
VIN  
4.5  
Output voltage  
BAT  
13.5  
4
V
Output current  
IOUT  
0.6  
–200  
–40  
A
Maximum difference voltage  
Operating junction temperature range  
SRP-SRN  
TJ  
200  
125  
mV  
°C  
Copyright © 2011–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): bq24130  
 
 
 
bq24130  
SLUSAN2C JULY 2011REVISED JUNE 2012  
www.ti.com  
ELECTRICAL CHARACTERISTICS  
4.5 V V(PVCC, AVCC) 17 V, -40°C < TJ < 125°C (unless otherwise noted)  
PARAMETER  
OPERATING CONDITIONS  
V(AVCC) AVCC Input Voltage Operating Range  
QUIESCENT CURRENTS  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
4.5  
17  
V
V(AVCC) < V(UVLO), 0°C - 85°C  
15  
15  
V(AVCC) > V(UVLO)  
V(SRN) > V(AVCC) (SLEEP)  
Battery Discharge Current  
I(BAT)  
(sum of currents into AVCC, BTST, SW,  
SRP, SRN, BAT)  
µA  
V(AVCC) > V(UVLO), V(AVCC) > V(SRN)  
ISET1 < 40 mV (Charge disabled)  
25  
25  
1.5  
5
V(AVCC) > V(UVLO), V(AVCC) > V(SRN)  
ISET1 > 120 mV (Charge enabled), Charge done  
V(AVCC) > V(UVLO), V(AVCC) > V(BAT)  
ISET1 < 40 mV (Charge disabled)  
1
2
Adapter Supply Current (sum of currents  
into AVCC)  
V(AVCC) > V(UVLO), V(AVCC) > V(BAT)  
ISET1 > 120 mV (Charge enabled), no switching  
I(AC)  
mA  
V(AVCC) > V(UVLO), V(AVCC) > V(BAT)  
ISET1 > 120 mV (Charge enabled), switching  
15  
CHARGE VOLTAGE REGULATION  
bq24130, CELL to AGND  
bq24130, CELL floating  
bq24130, CELL to VREF  
TJ = 0 to 85°C  
4.2  
8.4  
V(BAT_REG)  
BAT Regulation Voltage  
V
12.6  
–0.5%  
–0.7%  
614  
0.5%  
0.7%  
820  
Charge Voltage Regulation Accuracy  
BAT pin resistance(1)  
TJ = -40 to 125°C  
R(BAT)  
717  
5
kΩ  
CURRENT REGULATION (FAST CHARGE)  
V(ISET1)  
K(ISET1)  
ISET1 Voltage Range  
0.12  
0.8  
V
Charge Current Set Factor (Amps of Charge  
Current per Volt on ISET1 pin)  
RSENSE = 10 mΩ  
A/V  
V(IREG_CHG) = 40 mV  
V(IREG_CHG) = 20 mV  
V(IREG) = 5 mV  
ISET1 rising  
–4%  
-7%  
4%  
7%  
Charge Current Regulation Accuracy (With  
Schottky Diode on SW)  
–25%  
25%  
120  
ISET1 Rising Threshold to Enable Charge  
ISET1 Falling to Disable Charge  
Leakage Current into ISET1 pin  
100  
50  
mV  
mV  
nA  
V(ISET1_CE)  
lLkg  
ISET1 falling  
40  
V(ISET1) = 2 V  
100  
CURRENT REGULATION – PRECHARGE  
V(ISET2)  
ISET2 Voltage Range  
0
2
2
V
A
I(IREG_PRECHG)  
Precharge current range  
RSENSE = 10 mΩ  
RSENSE = 10 mΩ  
0.125  
Precharge Current Set Factor (Amps of  
precharge Current per Volt on ISET2 pin)  
K(ISET2)  
1
A/V  
V(IREG_CHG) = 10 mV, V(SRP) = 4 V  
V(IREG_CHG) = 10 mV, V(SRP) = 2.6 V  
V(IREG_CHG) = 4 mV  
–10%  
–15%  
–25%  
-40%  
10%  
15%  
25%  
40%  
Precharge Current Regulation Accuracy  
V(IREG_CHG) = 2 mV  
lLkg  
Leakage Current into ISET2 pin  
V(ISET2) = 2V  
100  
nA  
INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)  
AC Undervoltage Rising Threshold  
UVLO  
Measure on AVCC  
3.4  
50  
3.6  
3.8  
V
AC Undervoltage Hysteresis, falling  
340  
mV  
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)  
SLEEP Falling Threshold  
SLEEP Hysteresis  
V(AVCC) – V(SRN) to enter SLEEP  
90  
200  
100  
30  
150  
mV  
mV  
ms  
ms  
V(SLEEP)  
SLEEP Rising Shutdown Deglitch  
SLEEP Falling Power-up Deglitch  
AVCC falling below SRN  
AVCC rising above SRN  
(1) Specified by Design  
4
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Copyright © 2011–2012, Texas Instruments Incorporated  
Product Folder Link(s): bq24130  
 
bq24130  
www.ti.com  
SLUSAN2C JULY 2011REVISED JUNE 2012  
ELECTRICAL CHARACTERISTICS (continued)  
4.5 V V(PVCC, AVCC) 17 V, -40°C < TJ < 125°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
BAT OVERVOLTAGE COMPARATOR  
V(OV_RISE)  
V(OV_FALL)  
Overvoltage Rising Threshold  
As percentage of VBAT  
As percentage of VBAT  
104%  
102%  
Overvoltage Falling Threshold  
Overvoltage Deglitch Time to Disable  
Charge  
tOV  
30  
ms  
INPUT OVERVOLTAGE COMPARATOR (ACOV)  
AC Overvoltage Rising Threshold  
Measure on AVCC  
Measured on AVCC  
17  
18  
540  
1
19  
V
AC Overvoltage Falling Hysteresis  
V(ACOV)  
mV  
ms  
ms  
AC Overvoltage Rising Deglitch  
AC Overvoltage Falling Deglitch  
1
THERMAL REGULATION  
TJ  
THERMAL SHUTDOWN COMPARATOR  
T(SHUT) Thermal Shutdown Rising Temperature  
Junction Temperature Regulation Accuracy ISET1 > 120 mV, Charging  
120  
°C  
Temperature Increasing  
150  
20  
°C  
°C  
µs  
Thermal Shutdown Hysteresis  
Thermal Shutdown Rising Deglitch  
Thermal Shutdown Falling Deglitch  
Temperature Increasing Delay  
Temperature Decreasing Delay  
100  
10  
ms  
THERMISTOR COMPARATOR  
Cold Temperature Threshold, TS pin  
Voltage Rising Threshold  
V(LTF)  
Charger suspends charge as Percentage to VREF  
As Percentage to VREF  
73% 73.5%  
0.2% 0.4%  
74%  
Cold Temperature Hysteresis, TS pin  
Voltage Falling  
V(LTF_HYS)  
V(HTF)  
0.6%  
Hot Temperature TS pin voltage falling  
Threshold  
As Percentage to VREF  
46.6% 47.2% 47.8%  
Cut-off Temperature TS pin voltage falling  
Threshold  
V(TCO)  
As Percentage to VREF  
44.2% 44.7% 45.2%  
Deglitch time for Temperature Out of Range  
Detection  
V(TS) > V(LTF), or V(TS) < V(TCO), or V(TS) < V(HTF)  
400  
20  
ms  
ms  
Deglitch time for Temperature in Valid  
Range Detection  
V(TS) < V(LTF) – V(LTF_HYS) or V(TS) > V(TCO), or V(TS)  
V(HTF)  
>
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)  
Charge Overvurrent Rising Threshold,  
V(SRP) > 2.2V  
V(OC)  
Current as percentage of V(IREG_CHG)  
160%  
45  
Charge Overvurrent Rising Threshold,  
V(SRP) < 2.2V  
mV  
mV  
A
Charge Overvurrent Limit Range,  
V(SRP) > 2.2V  
75  
I(OCP)  
Charge OCP using high side sense FET  
8
1
11.5  
5
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE)  
Switch from Sync mode to Non-Sync mode, measure  
on V(SRP-SRN)  
V(UCP)  
Charge Undercurrent Falling Threshold  
9
mV  
BAT SHORT COMPARATOR (BATSHORT)  
Battery Short Falling Threshold  
Measure on BAT  
2
200  
1
V
V(BATSHT)  
Battery Short Rising Hysteresis  
Deglitch on Both Edge  
mV  
µs  
LOW CHARGE CURRENT COMPARATOR  
Low Charge Current Falling Threshold  
Measure on V(SRP-SRN)  
1.25  
1.25  
1
mV  
mV  
µs  
V(LC)  
Low Charge Current Rising Hysteresis  
Deglitch on Both Edge  
VREF REGULATOR  
V(VREF_REG) VREF Regulator Voltage  
I(VREF_LIM) VREF Current Limit  
V(AVCC) > UVLO  
3.267  
35  
3.3  
3.333  
120  
V
V(VREF) = 0V, V(AVCC) > UVLO  
mA  
Copyright © 2011–2012, Texas Instruments Incorporated  
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5
Product Folder Link(s): bq24130  
bq24130  
SLUSAN2C JULY 2011REVISED JUNE 2012  
www.ti.com  
ELECTRICAL CHARACTERISTICS (continued)  
4.5 V V(PVCC, AVCC) 17 V, -40°C < TJ < 125°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
REGN REGULATOR  
V(REGN_REG)  
REGN Regulator Voltage  
REGN Current Limit  
V(AVCC) > 10 V, 0mA - 40 mA, ISET1 > 100 mV  
V(REGN) = 0 V, V(AVCC) > UVLO  
5.7  
40  
6
6.3  
V
I(REGN_LIM)  
120  
mA  
INTERNAL PWM  
PWM Switching Frequency  
Driver Dead Time  
500  
600  
30  
700  
kHz  
ns  
Dead time when switching between LSD and HSD,  
no load  
R(DS_HI)  
R(DS_LO)  
High Side MOSFET On Resistance  
Low Side MOSFET On Resistance  
V(BTST) – V(SW) = 5.5 V  
25  
60  
45  
mΩ  
mΩ  
110  
V(BTST) – V(SW) when low side refresh pulse is  
requested, V(VCC) = 4.5 V  
3
4
V
V
Bootstrap Refresh Comparator Threshold  
Voltage  
V(BTST)  
V(BTST) – V(SW) when low side refresh pulse is  
requested, V(VCC) > 6 V  
INTERNAL SOFT START (8 steps to regulation current I(CHG)  
)
Soft Start Steps  
8
step  
ms  
Soft Start Step Time  
1.6  
3
5
CHARGER SECTION POWER-UP SEQUENCING  
Delay from ISET1 above 120 mV to start charging the  
battery  
(2)  
Charge-Enable Delay after Power-up  
2
ms  
INTEGRATED BTST DIODE  
VF  
VR  
Forward Bias Voltage  
IF = 120 mA at 25°C  
IR = 2 µA at 25°C  
0.85  
V
V
Reverse breakdown voltage  
20  
LOGIC IO PIN CHARACTERISTICS  
V(OUT_LO)  
V(CELL_LO)  
V(CELL_MID)  
V(CELL_HI)  
STAT Output Low Saturation Voltage  
Sink Current = 5 mA  
0.5  
0.5  
1.8  
V
V
V
V
CELL pin input low threshold, 1 cell  
CELL pin input mid threshold, 2 cells  
CELL pin input high threshold, 3 cells  
CELL pin voltage falling edge  
CELL pin voltage rising for MIN, falling for MAX  
CELL pin voltage rising edge  
0.8  
2.5  
Resistance between CELL to ground to  
keep CELL LOW [1]  
R(CELL_GND)  
120  
0.8  
kΩ  
VIL  
VIH  
CMOD Low-level input voltage threshold  
CMOD High-level input voltage threshold  
IIL = 5 µA  
V
V
IIL = 20 µA  
2.1  
(2) Specified by Design  
6
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Copyright © 2011–2012, Texas Instruments Incorporated  
Product Folder Link(s): bq24130  
bq24130  
www.ti.com  
SLUSAN2C JULY 2011REVISED JUNE 2012  
BLOCK DIAGRAM  
bq24130  
ACOV  
VACOV  
VUVLO  
UVLO  
AVCC  
VSRN+VSLEEP_FALL  
SLEEP  
EN_VREF  
VREF  
LDO  
VBAT_SHT  
BAT_SHT  
VREF  
AGND  
REGN  
LDO  
BAT_OVP  
REGN  
BTST  
EN_CHRG  
VOV_RISE  
BAT  
FBO  
EAI  
CELL  
PVCC  
PVCC  
2.1V  
EAO  
LEVEL  
SHIFTER  
1V  
SW  
SW  
PWM  
IC TJ  
REGN  
TJ_REG  
20μA  
PWM  
CONTROL  
LOGIC  
SYNC  
V(SRP-SRN)  
VUCP  
EN_CHRG  
PGND  
PGND  
120mV  
OCP  
V(SRP-SRN)  
VOC  
REFRESH  
VSW+VBTST_REFRESH  
VBTST  
STAT  
ISET1  
ISET2  
ISET1  
IBAT_REG  
/STAT  
ISET2  
Selection  
VLC  
V(SRP-SRN)  
LC  
CHARGE  
20μA  
CMOD  
SRP  
VREF  
CMOD  
LTF  
V(SRP-SRN)  
TS  
20X  
IC TJ  
TSHUT  
TSHUT  
STATE  
SRN  
MACHINE  
LOGIC  
EN_CHRG  
SUSPEND  
HTF  
TCO  
ACOV  
UVLO  
SLEEP  
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TYPICAL APPLICATION  
ADAPTER  
SYSTEM  
C4  
10µ  
Q3  
Q4  
PVCC  
AVCC  
Q6  
C1  
1µ  
R1  
10  
AGND  
VREF  
Q1  
L: 4.7?H  
R9:10m  
VBAT  
SW  
D2  
(optional)  
C2: 1µ  
R2  
R4  
154k  
C5  
47n  
C8  
0.1?  
ISET2  
ISET1  
BTST  
R5  
10k  
100k  
Q2  
ISET1<40mV  
Charge Diable  
C9, C10  
2 x 10?  
C7  
0.1?  
R3  
REGN  
PGND  
22.2k  
VREF  
C6  
1?  
CMOD  
CELL  
CMOD  
High: Fast charge ISET1  
Low: Pre-charge ISET2  
SRP  
SRN  
STAT  
TS  
R6  
5.23k  
R8  
1.5k  
D1  
BAT  
RT  
103AT  
bq24130  
R7  
30.1k  
12 V input, 1 Cell, 3 A Charge Current, 0.2 A Pre-charge Current, 0’C - 45ºC TS  
Figure 1. Typical Battery Charging Application Schematic  
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TYPICAL APPLICATION (continued)  
ADAPTER  
C4  
10µ  
PVCC  
AVCC  
C1  
1µ  
R1  
10  
AGND  
VREF  
Q1  
L: 4.7?H  
R9:10m  
VCAP  
SW  
C2: 1µ  
R4  
65k  
C8  
0.1?  
C5  
47n  
ISET2  
ISET1  
R2  
232k  
BTST  
R5  
100k  
Q2  
ISET1<40mV  
Charge Diable  
C9, C10  
2 x 10?  
C7  
0.1?  
R3  
32.4k  
REGN  
PGND  
C6  
1?  
CMOD  
CELL  
SRP  
SRN  
VREF  
STAT  
TS  
R12  
60k  
R6  
2.98k  
R8  
1.5k  
D1  
BAT  
RT  
103AT  
R11  
300k  
bq24130  
R7  
11.84k  
12 V input, 5.4 V Output, 2 A Charge Current, 0°C - 60°C TS  
Figure 2. Typical Super Capacitor Charging Application Schematic  
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TYPICAL CHARACTERISTICS  
AVCC  
AVCC  
10 V/div  
10 V/div  
REGN  
REGN  
5 V/div  
5 V/div  
PH 10 V/div  
BAT  
5 V/div  
STAT  
ICHG  
10 V/div  
2 A/div  
t - Time - 10 ms/div  
t - Time - 10 ms/div  
Figure 3. Power Up (BAT, STAT)  
Figure 4. Power Up (PH, ICHG)  
ISET1  
500 mV/div  
PH  
10 V/div  
STAT  
10 V/div  
PH  
10 V/div  
ICHG  
I(IND)  
2 A/div  
2 A/div  
t - Time - 10 ms/div  
t - Time - 4 ms/div  
Figure 5. Current Soft Start  
Figure 6. ISET1 Enable and Disable Charge  
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TYPICAL CHARACTERISTICS (continued)  
ISET1  
500 mV/div  
ISET1  
500 mV/div  
STAT  
10 V/div  
STAT  
10 V/div  
PH  
10 V/div  
PH 10 V/div  
ICHG  
2 A/div  
I(IND)  
2 A/div  
t - Time - 4 ms/div  
t - Time - 2 ms/div  
Figure 7. Charge Enable  
Figure 8. Charge Disable  
CMOD  
5 V/div  
PH  
10 V/div  
ICHG  
2 A/div  
ICHG  
1 A/div  
t - Time - 10 ms/div  
t - Time - 400 ns/div  
Figure 9. CMOD Select Charge Current  
(ISET1 2A, ISET2 0.4A)  
Figure 10. Switching (CCM)  
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TYPICAL CHARACTERISTICS (continued)  
BAT  
5 V/div  
PH  
10 V/div  
PH 10 V/div  
I(IND)  
500 mA/div  
I(IND)  
2 A/div  
t - Time - 400 ns/div  
t - Time - 400 ns/div  
Figure 11. Switching (DCM)  
Figure 12. Short Battery  
VBAT  
5 V/div  
VCAP 5 V/div  
AVCC  
5 V/div  
PH 10 V/div  
PH 10 V/div  
IOUT  
I(IND)  
2 A/div  
1 A/div  
t - Time - 200 ms/div  
Figure 14. SuperCap Charge Cycle  
t - Time - 4 ms/div  
Figure 13. Short Battery (zoom-in)  
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TYPICAL CHARACTERISTICS (continued)  
100  
95  
90  
85  
80  
V = 12 V  
I
VBAT 7.5 V  
V = 5 V  
I
VBAT 3.6 V  
V = 12 V  
I
VBAT 3.6 V  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
Charge Current - A  
Figure 15. Efficiency  
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DETAILED DESCRIPTION  
Battery Voltage Regulation  
Internally, the BAT pin has 717 kΩ to AGND. For output voltage above 4.2 V, but not 8.4 V or 12 V, the user can  
use an external resistor divider from output to VBAT pin to AGND.  
The bq24130 offers a high accuracy voltage regulation on charge voltage. The bq24130 uses CELL pin to select  
number of cells with a fixed 4.2 V/cell. CELL pin adjusts internal resistor voltage divider from BAT pin to AGND  
pin for voltage feedback and regulate to internal 2.1 V voltage reference.  
Table 1.  
CELL Pin  
AGND  
Voltage Regulation  
4.2V  
8.4V  
Floating  
VREF  
12.6V  
Internally, the BAT pin has 717 kΩ to AGND. For output voltage above 4.2 V, but not 8.4 V or 12 V, the user can  
use an external resistor divider from output to the VBAT pin to AGND.  
Battery Current Regulation  
The bq24130 has two current setting inputs, ISET1 and ISET2.  
A low-level signal on the CMOD pin forces the IC to charge at the pre-charge rate set on the ISET2 pin. A high-  
level signal forces charge at fast-charge rate as set by the ISET1 pin. The CMOD pin cannot float.  
The ISET1 input sets the maximum charging current. Battery current is sensed by current sensing resistor RSR  
connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 40 mV max. The  
equation for charge current is:  
V
(ISET1)  
I(CHARGE)  
=
20´R(SR)  
(1)  
The valid input voltage range of ISET1 is up to 0.8 V. With 10 mΩ sense resistor, the maximum output current is  
4 A. With 20 mΩ sense resistor, the maximum output current is 2 A.  
The ISET2 input sets the pre-charge current up to 2 A on a 10 mΩ sense resistor.  
V
(ISET2)  
I(PRECHARGE)  
=
100´R(SR)  
(2)  
The charger is disabled when ISET1 pin voltage is below 40 mV and is enabled when ISET1 pin voltage is above  
120 mV. For 10 mΩ current sensing resistor, the minimum fast charge current must higher than 600 mA.  
Under high ambient temperature, the charge current will fold back to keep IC temperature not exceeding 120°C  
Power Up  
The charger uses a SLEEP comparator to determine the source of power on the AVCC pin, since AVCC can be  
supplied either from the battery or the adapter. If the AVCC voltage is greater than the SRN voltage, charger  
exits SLEEP mode. If all conditions are met for charging, charger will then attempt to charge the battery (See the  
Enable and Disable Charging section). If the SRN voltage is greater than AVCC, charger enters a low quiescent  
current 15 µA) SLEEP mode to minimize current drain from the battery. During the SLEEP mode, the VREF  
output turns off and the STAT pin goes to high impedance.  
If AVCC is below the UVLO threshold, the device is disabled.  
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Enable and Disable Charging  
The following conditions have to be valid before charge is enabled:  
ISET1 pin above 120 mV  
The device is not in Under Voltage Lockout (UVLO) mode (i.e. V(AVCC) > UVLO)  
The device is not in SLEEP mode (i.e. V(AVCC) > V(SRN)  
The AVCC voltage is lower than the AC over-voltage threshold (i.e. V(AVCC) < V(ACOV)  
50 ms delay is complete after initial power-up  
The REGN and VREF LDO voltages are at the correct levels  
Thermal Shut down (TSHUT) is not valid  
No TS fault is detected  
)
)
One of the following conditions will stop on-going charging:  
ISET1 pin voltage is below 40mV;  
The device is in UVLO mode;  
Adapter is removed, causing the device to enter SLEEP mode;  
AVCC voltage is over voltage  
The REGN or VREF LDO voltage is overloaded;  
TSHUT temperature threshold is reached.  
TS voltage goes out of range indicating the battery temperature is too hot or too cold  
Automatic Internal Soft-Start Charger Current  
The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge  
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists  
of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.  
Each step lasts around 1.6 ms, for a typical rise time of 12.8 ms. No external components are needed for this  
function.  
Converter Operation  
The bq24130 employs a 600kHz constant-frequency step-down switching regulator. The fixed frequency  
oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage,  
charge current and temperature, simplifying output filter design and keeping it out of the audible noise region.  
A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-  
tooth ramp is compared to the internal error control signals to vary the duty-cycle of the converter. The ramp  
height is proportional to the AVCC voltage to cancel out any loop gain variation due to a change in input voltage,  
and simplifies loop compensation. Internal gate drive logic allows achieving 97% duty cycle before pulse skipping  
starts.  
Charge Undercurrent Protection  
When the voltage between BTST and SW falls below 4 V, the low-side FET turns on to provide refresh charge  
up the bootstrap capacitor. After the recharge, if the SRP-SRN voltage decreases below 5 mV, the low side FET  
will be turned off for the remainder of the switching cycle (i.e. non-synchronous operation). This is important to  
prevent negative inductor current from causing any boost effect in which the input voltage increases as power is  
transferred from the battery to the input capacitors. This can lead to an overvoltage on the AVCC node and  
potentially cause damage to the system.  
When the IC senses SRP-SRN average voltage drops below 1.25 mV (0.125 A of inductor current for a 10 mΩ  
sense resistor) or the battery voltage is less than 2 V, the charger will enter non-synchronous mode and the low-  
side n-channel power MOSFET will stay off and rely on the body diode to make converter as a standard buck.  
This prevents the battery discharge current when battery is almost fully charged and current tapers down to a  
lower level. The low-side n-channel power MOSFET will turn on when a bootstrap capacitor refresh pulse is  
needed.  
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Charge Overcurrent Protection  
The charger monitors top side MOSFET current by high side sense FET. When peak current is higher than over-  
current threshold, it will turn off the top side MOSFET and keep it off until the next cycle. The charger has a  
secondary cycle-to-cycle over-current protection. It monitors the charge current, and prevents the current from  
exceeding 160% of the programmed charge current. The high-side gate drive turns off when the overcurrent is  
detected, and automatically resumes when the current falls below the over-current threshold.  
Battery Overvoltage Protection  
The converter will not allow the high-side FET to turn-on until the battery voltage goes below 102% of the  
regulation voltage. This allows one-cycle response to an over-voltage condition – such as occurs when the load  
is removed or the battery is disconnected. An 8 mA current sink from SRP/SRN to AGND is on only during  
charge and allows discharging the stored output inductor energy that is transferred to the output capacitors. If  
battery overvoltage condition lasts for more than 30 ms, charge is disabled.  
Battery Short Protection  
When SRN pin voltage is lower than 2 V it is considered as battery short condition during charging period. The  
charger will shut down immediately, then soft start back to the charging current 1.25 A max. This prevents high  
current may build in output inductor and cause inductor saturation when battery terminal is shorted during  
charging. The converter works in non-synchronous mode during battery short.  
Input Overvoltage Protection (ACOV)  
ACOV provides protection to prevent system damage due to high input voltage. In bq24130, once the voltage on  
AVCC reaches the 18 V ACOV threshold, charge is disabled.  
Input Under Voltage Lock Out (UVLO)  
The system must have a minimum 3.85 V AVCC voltage to allow proper operation. This AVCC voltage could  
come from either input adapter or battery, since a conduction path exists from the battery to AVCC through the  
high side NMOS body diode. When AVCC is below the 3.85 V UVLO threshold, all circuits on the IC are  
disabled.  
Thermal Regulation and Shutdown Protection  
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the  
ambient, to keep junctions temperatures low. The internal thermal regulation loop will adjust the charge current to  
maintain the junction temperature around 120°C.  
As added level of protection, the charger converter turns off and self-protects whenever the junction temperature  
exceeds the TSHUT threshold of 150°C. The charger stays off until the junction temperature falls below 130°C.  
Temperature Qualification  
The controller continuously monitors battery temperature by measuring the voltage between the TS pin and  
AGND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this  
voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.  
To initiate a charge cycle, the battery temperature must be within the V(LTF) to V(HTF) thresholds. If battery  
temperature is outside of this range, the controller suspends charge and waits until the battery temperature is  
within the V(LTF) to V(HTF) range. During the charge cycle the battery temperature must be within the V(LTF) to  
V(TCO) thresholds. If battery temperature is outside of this range, the controller suspends charge and waits until  
the battery temperature is within the V(LTF) to V(HTF) range. The controller suspends charge by turning off the  
PWM charge MOSFETs. Figure 16 summarizes the operation.  
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TEMPERATURE RANGE  
TEMPERATURE RANGE  
TO INITIATE CHARGE  
DURING A CHARGE CYCLE  
VREF  
VREF  
CHARGE SUSPENDED  
CHARGE SUSPENDED  
V
V
(LTF)  
(LTF)  
V
V
(LTFH)  
(LTFH)  
CHARGE at full C  
CHARGE at full C  
V
V
(HTF)  
(TCO)  
CHARGE SUSPENDED  
CHARGE SUSPENDED  
AGND  
AGND  
Figure 16. TS pin, Thermistor Sense Thresholds  
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 1, the value RT1 and RT2 can be  
determined by using Equation 4 and Equation 4:  
æ
ç
ç
ç
ö
÷
÷
÷
1
1
V(VREF) ´RTH(COLD) ´RTH(HOT)  
´
-
÷
÷
çV  
V
è
(TCO) ø  
(LTF)  
RT2 =  
æ
ç
ç
ç
ö
æ
ç
ç
ç
ö
V
V
(VREF)  
÷
÷
(VREF)  
÷
÷
-1  
÷
RTH(HOT)  
´
-1 -RTH  
´
÷
(COLD)  
÷
÷
÷
÷
ç V  
ç V  
è
ø
è
ø
(TCO)  
(LTF)  
(3)  
(4)  
SPACER  
V
(VREF)  
-1  
V
(LTF)  
RT1=  
1
1
+
RT2 RTH(COLD)  
Select 0°C to 45°C range for Li-ion or Li-polymer battery.  
RTH(COLD) = 27.28 KΩ  
RTH(HOT) = 4.911 KΩ  
RT1 = 5.253 kΩ, Select Resistor 5.23k  
RT2 = 31.318 kΩ, Select Resistor 30.9k  
After select closest standard resistor value, by calculating the thermistor resistance at temperature threshold, the  
final temperature range can be determined from thermistor data sheet temperature-resistance.  
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VREF  
RT1  
RT2  
bq24130  
TS  
RTH  
103AT  
Figure 17. TS Resistor Network  
Inductor, Capacitor, and Sense Resistor Selection Guidelines  
The IC provides internal loop compensation. With this scheme, best stability occurs when the LC resonant  
frequency, fo, is approximately 12 kHz – 17 kHz for IC per Equation 5:  
1
f =  
o
2p LC  
(5)  
Charge Status Outputs  
The open-drain STAT outputs indicate various charger operations as shown in . These status pins can be used  
to drive LED or communicate with the host processor. Note that OFF indicates that the open-drain transistor is  
turned off.  
Table 2. STAT Pin Defination  
Charge State  
STAT  
On  
Charge in progress  
Sleep mode, Charge Disabled  
OFF  
Chagre suspended. Input overvoltage, Battery overvoltage  
BLINK  
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APPLICATION INFORMATION  
Inductor Selection  
The bq24130 has 600 kHz switching frequency to allow the use of small inductor and capacitor values. The  
Inductor saturation current should be higher than the charging current (I(CHG)) plus half the ripple current  
(I(RIPPLE)):  
I(SAT) I(CHG) + (1/2) I(RIPPLE)  
(6)  
The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fs)  
and inductance (L):  
V ´D´(1-D)  
=
f s´L  
IN  
I(RIPPLE)  
(7)  
Input Capacitor  
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case  
RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at  
50% duty cycle, then the worst case capacitor RMS current I(CIN) occurs where the duty cycle is closest to 50%  
and can be estimated by Equation 8:  
I(CIN) = I(CHG) ´ D´(1-D)  
(8)  
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be  
placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage  
rating of the capacitor must be higher than normal input voltage level. 25 V rating or higher capacitor is preferred  
for 15 V input voltage. 20 μF capacitance is suggested for typical of 3 A - 4 A charging current.  
Output Capacitor  
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The  
output capacitor RMS current I(COUT) is given:  
I(RIPPLE)  
I(COUT)  
=
» 0.29´I(RIPPLE)  
2´ 3  
(9)  
The output capacitor voltage ripple can be calculated as follows:  
æ
ö
VOUT  
8LCf s2  
VOUT  
÷
÷
÷
÷
ø
ç
DVO =  
1-  
ç
ç
ç
V
è
IN  
(10)  
At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the  
output filter LC.  
The bq24130 has internal loop compensator. To get good loop stability, the resonant frequency of the output  
inductor and output capacitor should be designed between 12 kHz and 17 kHz. The preferred ceramic capacitor  
is 25 V or higher rating, X7R or X5R  
Input Filter Design  
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second  
order system. The voltage spike at AVCC/PVCC pin may be beyond IC maximum voltage rating and damage IC.  
The input filter must be carefully designed and tested to prevent overvoltage event on AVCC/PVCC pin.  
There are several methods to damping or limit the overvoltage spike during adapter hot plug-in. An electrolytic  
capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC maximum pin  
voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level.  
However, these two solutions may not have low cost or small size.  
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A cost effective and small size solution is shown in Figure 18. The R1 and C1 are composed of a damping RC  
network to damp the hot plug-in oscillation. As a result the overvoltage spike is limited to a safe level. D1 is used  
for reverse voltage protection for AVCC pin. C2 is AVCC pin decoupling capacitor and it should be place to  
AVCC pin as close as possible. The R2 and C2 form a damping RC network to further protect the IC from high  
dv/dt and high voltage spike. C2 value should be less than C1 value so R1 can dominant the equivalent ESR  
value to get enough damping effect for hot plug-in. R1 and R2 package must be sized enough to handle inrush  
current power loss according to resistor manufacturer’s data sheet. The filter components value always need to  
be verified with real application and minor adjustments may need to fit in the real application circuit.  
If the input is 5 V (USB host or USB adapter), the D1 can be saved. R2 has to be 5 Ω or higher to limit the  
current if the input is reversely inserted.  
D1  
R2 (1206)  
4.7 - 30W  
R1 (2010)  
2W  
Adapter  
Connector  
VCC pin  
C1  
2.2mF  
C2  
0.1 - 1mF  
Figure 18. Input Filter  
PCB LAYOUT  
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the  
components to minimize high frequency current path loop (see Figure 19) is important to prevent electrical and  
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper  
layout. Layout PCB according to this specific order is essential  
1. Place input capacitor as close as possible to PVCC supply and ground connections and use shortest copper  
trace connection. These parts should be placed on the same layer of PCB instead of on different layers and  
using vias to make this connection.  
2. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower  
electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not  
use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other  
trace or plane.  
3. The charging current sensing resistor should be placed right next to the inductor output. Route the sense  
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop  
area) and do not route the sense leads through a high-current path (see Figure 20 for Kelvin connection for  
best current accuracy). Place decoupling capacitor on these traces next to the IC.  
4. Place output capacitor next to the sensing resistor output and ground.  
5. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor  
ground before connecting to system ground.  
6. Route analog ground separately from power ground and use single ground connection to tie charger power  
ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins  
to reduce inductive and capacitive noise coupling. Use thermal pad as the single ground connection point to  
connect analog ground and power ground together. Or using a 0 Ω resistor to tie analog ground to power  
ground (thermal pad should tie to analog ground). A star-connection under thermal pad is highly  
recommended.  
7. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground.  
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the  
other layers.  
8. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.  
20  
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Product Folder Link(s): bq24130  
 
bq24130  
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SLUSAN2C JULY 2011REVISED JUNE 2012  
9. All via size and number should be enough for a given current path.  
Figure 19. High Frequency Current Path  
Current Direction  
R(SNS)  
Current Sensing Direction  
To SRP/SRN pins  
Figure 20. Sensing Resistor PCB Layout  
Copyright © 2011–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
21  
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bq24130  
SLUSAN2C JULY 2011REVISED JUNE 2012  
www.ti.com  
REVISION HISTORY  
Changes from Original (July 2011) to Revision A  
Page  
Added the Li-Ion/Li-Polymer battery Application ................................................................................................................... 1  
Changed pin BTST Description From: Connect the 0.1 µF bootstrap capacitor. To: Connect the 47 nF bootstrap  
capacitor ............................................................................................................................................................................... 2  
Changed the Min and Max values for Voltage in the ABS Max Ratings Table .................................................................... 3  
Changed the RECOMMENDED OPERATING CONDITIONS table .................................................................................... 3  
Changed the ELECT CHARACTERISTICS conditions statement From: 4.5 V V(PVCC, AVCC) 18 V To: 4.5 V ≤  
V(PVCC, AVCC) 17 V ............................................................................................................................................................... 4  
Changed the Electrical Characteristics table ........................................................................................................................ 4  
Added Figure 2 ..................................................................................................................................................................... 9  
Added the TYPICAL CHARACTERISTICS section ............................................................................................................ 10  
Changed the Battery Voltage Regulation section ............................................................................................................... 14  
Changed the Charge Overcurrent Protection section ......................................................................................................... 16  
Changes from Revision A (August 2011) to Revision B  
Page  
Added Features Bullet: Constant Current Super Capacitor Charging .................................................................................. 1  
Changed the Thermal Information Table .............................................................................................................................. 3  
Changed Figure 1 ................................................................................................................................................................. 8  
Changed Figure 2 ................................................................................................................................................................. 9  
Changed Figure 14 ............................................................................................................................................................. 12  
Changes from Revision B (August 2011) to Revision C  
Page  
Changed the value of RT1 From: RT1 = 31.23 KΩ To: RT1 = 5.253 kΩ, Select Resistor 5.23k ....................................... 17  
Changed the value of RT2 From: RT2 = 5.25 KΩ To: RT2 = 31.318 kΩ, Select Resistor 30.9k ....................................... 17  
22  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
26-Jun-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
BQ24130RHLR  
BQ24130RHLT  
ACTIVE  
ACTIVE  
QFN  
QFN  
RHL  
RHL  
20  
20  
3000  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
BQ24130RHLR  
BQ24130RHLT  
QFN  
QFN  
RHL  
RHL  
20  
20  
3000  
250  
330.0  
180.0  
12.4  
12.4  
3.8  
3.8  
4.8  
4.8  
1.6  
1.6  
8.0  
8.0  
12.0  
12.0  
Q1  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
BQ24130RHLR  
BQ24130RHLT  
QFN  
QFN  
RHL  
RHL  
20  
20  
3000  
250  
367.0  
210.0  
367.0  
185.0  
35.0  
35.0  
Pack Materials-Page 2  
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