T6L79 [TOSHIBA]
IC LIQUID CRYSTAL DISPLAY DRIVER, UUC443, TCP-443, Display Driver;
| 型号： | T6L79 |
| 厂家： | 
TOSHIBA |
| 描述： | IC LIQUID CRYSTAL DISPLAY DRIVER, UUC443, TCP-443, Display Driver 驱动 接口集成电路 |
| 文件： | 总18页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T6L79
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6L79
Source Driver for TFT LCD Panels
The T6L79 is a 64-grayscale-level and 384-channel output
source driver for TFT LCD panels. The device accepts 8-bit ×
6-dot digital CMOS-level inputs, for which the direction of data
transfer can be selected by the U/D pin. The 10 (5 × 2) external
power supply and the internal DA converter realize display of
260,000 colors, on which reference analog voltage inputs is made.
The DA converter supports one side dot line inversion,
achieving high picture quality. The output dynamic range is a
generous 7.3 to 9.8 Vp-p.
Unit: mm
User Pitch Area
IN OUT
T6L79
For the latest TCP specifications and
product line-up, contact Toshiba or your
local sales office.
Base on high-speed CMOS, the T6L79 offers both low power
consumption and high-speed operation. To configure an SXGA or
XGA-compatible TFT-LCD module, it allows a maximum
operating frequency 45 MHz.
TCP (Tape Carrier Package)
Features
•
Grayscale data
: Digital CMOS-level 36-bit (6-bit × 6-input) parallel transfer method, selectable transfer
direction
•
Panel drive outputs
: 384 outputs, 64 grayscale levels, R-DAC system, reference analog voltage inputs,
10 external power supplies (5 × 2), one side dot line inversion drive
•
•
High-speed operation : 45 MHz max
Power supply voltage : Digital power supply voltage . . . 3.0 to 3.6 V
Analog power supply voltage . . . 7.5 to 10.0 V
Operating temperature: −20 to 75°C
Package: Tape carrier package (TCP)
Cascading of multiple devices
•
•
•
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T6L79
Block Diagram
DI/O
CPH
U/D
DO/I
Data control unit
DINV
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
Sampling register (REG1)
LOAD
Load register (REG2)
POL
DA converter
V0 to V9
TEST
TESTP
Output circuit
AV
DV
DD
DD
AV
DV
SS
SS
OUT1
OUT3
OUT382
OUT384
OUT2
OUT383
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2002-04-03
T6L79
Pin Assignment
OUT1 60
OUT2 61
OUT3 62
OUT4 63
OUT5 64
OUT6 65
OUT7 66
OUT8 67
OUT9 68
OUT10 69
59 DI/O
58 D00
53 D05
52 D10
47 D15
46 D20
41 D25
40 DINV
39 POL
38 LOAD
37 CPH
36
TESTP
35 DV
34 V0
33 V1
32 V2
31 V3
30 V4
29 AV
28 AV
27 V5
26 V6
25 V7
24 V8
23 V9
SS
T6L79
(chip top view)
SS
DD
22 U/D
21 TEST
20 DV
DD
19 D30
14 D35
13 D40
OUT375 434
OUT376 435
OUT377 436
OUT378 437
OUT379 438
OUT380 439
OUT381 440
OUT382 441
OUT383 442
OUT384 443
8
7
D45
D55
2
1
D55
DO/I
The figure above shows an example of the pin assignment in the TCP. It does not specify the pad layout on the
chip. For the latest TCP specifications, contact Toshiba or your local sales office.
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2002-04-03
T6L79
Pin Functions
Pin Name
I/O
Function
Data transfer enable pins
These pins are used to input/output grayscale data.
Input and output are switched as shown below according to the setting of the U/D pin.
U/D
DI/O
Input
DO/I
Output
Input
H
L
Output
DI/O
DO/I
I/O
When DI/O or DO/I is set to input
High level input to the pin is latched into the internal logic in sync with the rising edge of CPH.
If the internal logic is in standby state, the device is ready for data transfer. Grayscale data are
sequentially latched starting from the next rising edge of CPH.
When DI/O or DO/I is set to output
Sends enable signal to the T6L79 at the next stage of the LCD driver. After outputting High
level, the pin enters standby state.
Transfer direction select pin
Controls the transfer direction of grayscale data. The data are transferred in the following order
in sync with the rising edge of CPH:
When U/D = High: OUT1 to OUT6, OUT7 to OUT12 . . . OUT379 to OUT384
When U/D = Low: OUT379 to OUT384, OUT373 to OUT378 . . . OUT1 to OUT6
The voltage applied to this pin must be DC level, High or Low.
U/D
I
I
I
Data transfer clock pin
CPH
Transfers grayscale data. Sequentially latches grayscale data into REG1 in sync with the rising
edge of CPH. Input clocks at least three cycles after High level of the LOAD pin.
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
Grayscale data bus pins
Inputs output data consisting of 6 bits for six channels in one transfer. The relationship between
grayscale data and output pins is as follows:
Grayscale data = 32 × Dn5 + 16 × Dn4 + 8 × Dn3 + 4 × Dn2 + 2 × Dn1 + Dn0
(*) n = 0, 1, . . . , 5
Data load input pin
High level input to the pin is latched into the internal logic in sync with the rising edge of CPH.
Then, the REG1 data are transferred to REG2. The voltage changes to that corresponding to
grayscale data in sync with the falling edge of LOAD.
LOAD
DINV
I
I
Data polarity inverting pin
Selects inversion or non-inversion of grayscale data bus at the rising edge of CPH.
DINV = Low: Data bus not inverted
DINV = High: Data bus inverted
”H” or “L” level is discriminated at the rising edge of CPH same as gray data bus.
Polarity inverting pin
Latches the input signal into the internal logic in sync with the rising edge of LOAD.
POL = Low: The reference voltage for odd-numbered outputs is input from V0 to V4;
for even-numbered outputs, V5 to V9.
POL
I
POL = High: The reference voltage for odd-numbered outputs is input from V5 to V9;
for even-numbered outputs, V0 to V4.
Reference analog voltage input pins
Externally input reference analog voltage inputs voltage.
Hold the input voltage during output of the voltage corresponding to grayscale data.
V0 to V9
TEST
I
I
AV
− 0.1 > V0 > V1 > V2 > V3 > V4 > 0.5 × AV
SS
> V5 > V6 > V7 > V8 >
DD
DD
V9 > AV + 0.1
Test pin
Leave the pin open or set to DV level.
SS
Test pin
Controlling the output amp constant current supply reduces current dissipation.
In Low Power Mode ( TESTP = Low), current dissipation is reduced to 2/3 of the value in
TESTP
I
Normal Current Dissipation Mode. The pin is internally pulled up to DV
.
DD
TESTP = High or the pin left open: Normal Current Dissipation Mode
TESTP = Low: Low-Current-Dissipation Mode
OUT1 to OUT384
O
LCD panel drive pins
AV
AV
DV
DV
Analog power supply pin
DD
SS
DD
SS
Analog GND pin
Apply the same voltage as that of digital GND pin.
Digital power supply pin
Digital GND pin
Apply the same voltage as that of analog GND pin.
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2002-04-03
T6L79
Device Operation
(1) Starting data transfer
High level input to the data transfer enable pin (DI/O or DO/I) is latched into the internal logic in sync with
the rising edge of CPH, setting the device to ready for transfer.
Set the period for High level input to the data transfer enable pin to one clock.
(2) Data transfer method
Grayscale data are transferred from the data bus to the sampling register (REG1) in sync with the rising edge
of CPH. Grayscale data for six channels are simultaneously written in one transfer. Transfer completes after 64
times and the device enters standby state. Data to be written to REG1 are the result of operations between the
grayscale data bus and DINV.
Note 1: Do not input High level to LOAD during data transfer.
(3) Ending data transfer
High level is output from the data transfer enable pin (DO/I or DI/O) from the rising edge of CPH, one cycle
before the last data are latched, to the next rising edge of CPH.
(4) LCD panel drive output
Inputting High level to LOAD in sync with the rising edge of CPH following High level output from DO/I
(DI/O) transfers data from the sampling register (REG1) to the load register (REG2) and outputs a voltage
corresponding to the grayscale data in sync with the falling edge of LOAD.
Note 2: Input High level to LOAD at least three clock cycles.
The T6L79 has a capacity for polarity inverting corresponding to dot-inverting operation. By POL signal to
the pin which is latched into the internal logic in sync with the rising edge of LOAD, the polarity of
odd-numbered outputs and even-numbered outputs are inverted.
By changing the cycle of POL signal, n-line inverting operation is available to correspond.
The reference voltage for odd-numbered outputs is input
POL = “L”
from V0 to V4, for even-numbered outputs, V5 to V9
The reference voltage for odd-numbered outputs is input
from V5 to V9, for even-numbered outputs, V0 to V4
POL = “H”
(5)
(Low power control function)
TESTP
Output amp bias current can be switched between two values using the TESTP pin. The current dissipation
in Low Current Dissipation Mode can be reduced to 2/3 of that in Normal Current Dissipation mode.
Note 3: Input the stabilized DC voltage (DV , DV ) to the TESTP pin.
DD
SS
TESTP = “H”
TESTP = “L”
Normal current dissipation mode
Low current dissipation mode
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2002-04-03
T6L79
(6) Reference analog voltage inputs power supply circuit
The DA converter consists of ladder resistors and switches. Resistors are serially connected between the
supply voltage input pins for reference analog voltage inputs.
V0
R0 to R15
V1
V2
V3
V4
R16 to R31
R32 to R47
R48 to R62
V5
V6
V7
V8
V9
R62 to R48
R47 to R32
R31 to R16
R15 to R0
• Resistors between power supply pins for reference analog voltage inputs (typical)
Unit: Ω
Resistor Resistance Resistor Resistance Resistor Resistance Resistor Resistance
Name
Values
648.0
607.5
567.0
Name
Values
243.0
202.5
202.5
Name
Values
Name
Values
R
0
R
16
R
32
R
48
81.0
81.0
R
1
R
17
R
33
R
49
81.0
81.0
R
2
R
18
R
34
R
50
81.0
81.0
R
3
R
R
R
526.5
486.0
445.5
445.5
405.0
405.0
324.0
324.0
283.5
283.5
283.5
243.0
243.0
202.5
162.0
162.0
162.0
121.5
121.5
121.5
121.5
81.0
81.0
81.0
81.0
81.0
81.0
81.0
81.0
81.0
81.0
81.0
81.0
81.0
81.0
81.0
81.0
19
35
51
R
4
R
20
R
36
R
52
R
5
R
21
R
37
R
53
121.5
121.5
121.5
162.0
162.0
202.5
202.5
243.0
405.0
648.0
R
6
R
22
R
38
R
54
R
7
R
23
R
39
R
55
R
8
R
24
R
40
R
56
R
9
R
25
R
41
R
57
R
10
R
26
R
42
R
58
R
11
R
27
R
43
R
59
R
12
R
28
R
44
R
60
81.0
R
13
R
29
R
45
R
61
81.0
R
14
R
30
R
46
R
62
81.0
R
15
R
31
R
47
81.0
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2002-04-03
T6L79
(7) Relationship between grayscale data and output voltage
The output voltage is determined according to the grayscale data values and the ten power supply voltages for
reference analog voltage inputs. When U/D is High or Low, the grayscale data and the output pins correspond as
shown in the table below.
Output
Grayscale Data
U/D = “H”
U/D = “L”
OUT (6p − 5)
OUT (6 p − 4)
OUT (6p − 3)
OUT (6p − 2)
OUT (6p − 1)
OUT (6p)
D00 to D05
D10 to D15
D20 to D25
D30 to D35
D40 to D45
D50 to D55
OUT (6m − 5)
OUT (6m − 4)
OUT (6m − 3)
OUT (6m − 2)
OUT (6m − 1)
OUT (6m)
(*) m = 1, 2, 3, • • • , 62, 63, 64
p = 64, 63, 62, • • • , 3, 2, 1
• Schematic of reference analog voltage inputs
Number of reference analog
resistance divisions
AV
DD
V0
16
V1
V2
V3
16
16
15
V4
V5
15
V6
V7
V8
16
16
16
V9
Number of reference analog
AV
SS
resistance divisions
“3F”
“00”
“10”
“20”
“30”
Input grayscale data (HEX)
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2002-04-03
T6L79
• Relationship 1 between grayscale data and output voltage
(grayscale data: 00H to 1FH)
(*) n = 0, 1, • • •, 5
Output Voltage (reference value)
Grayscale
Data
Dn5 Dn4 Dn3 Dn2 Dn1 Dn0
V5 < V4 < V3 < V2 < V1 < V0 < AV
DINV = L
,
AV < V9 < V8 < V7 < V6 < V5 < V4,
DD
SS
DINV = L
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V00H V0
V00H’ V9
V01H V1 + (V0 − V1) × 5872.5/6520.5 V01H’ V9 + (V8－V9) × 648.0/6520.5
V02H V1 + (V0 − V1) × 5265.0/6520.5 V02H’ V9 + (V8－V9) × 1255.5/6520.5
V03H V1 + (V0 − V1) × 4698.0/6520.5 V03H’ V9 + (V8－V9) × 1822.5/6520.5
V04H V1 + (V0 − V1) × 4171.5/6520.5 V04H’ V9 + (V8－V9) × 2349.0/6520.5
V05H V1 + (V0 − V1) × 3685.5/6520.5 V05H’ V9 + (V8－V9) × 2835.0/6520.5
V06H V1 + (V0 − V1) × 3240.0/6520.5 V06H’ V9 + (V8－V9) × 3280.5/6520.5
V07H V1 + (V0 − V1) × 2794.5/6520.5 V07H’ V9 + (V8－V9) × 3726.0/6520.5
V08H V1 + (V0 − V1) × 2389.5/6520.5 V08H’ V9 + (V8－V9) × 4131.0/6520.5
V09H V1 + (V0 − V1) × 1984.5/6520.5 V09H’ V9 + (V8－V9) × 4536.0/6520.5
V0AH V1 + (V0 − V1) × 1660.5/6520.5 V0AH’ V9 + (V8 − V9) × 4860.0/6520.5
V0BH V1 + (V0 − V1) × 1336.5/6520.5 V0BH’ V9 + (V8 − V9) × 5184.0/6520.5
V0CH V1 + (V0 − V1) × 1053.0/6520.5 V0CH’ V9 + (V8 − V9) × 5467.5/6520.5
V0DH V1 + (V0 − V1) × 769.5/6520.5
V0EH V1 + (V0 − V1) × 486.0/6520.5
V0FH V1 + (V0 − V1) × 243.0/6520.5
V10H V1
V0DH’ V9 + (V8 − V9) × 5751.0/6520.5
V0EH’ V9 + (V8 − V9) × 6034.5/6520.5
V0FH’ V9 + (V8 − V9) × 6277.5/6520.5
V10H’ V8
V11H V2 + (V1 − V2) × 1984.5/2227.5 V11H’ V8 + (V7 − V8) × 243.0/2227.5
V12H V2 + (V1 − V2) × 1782.0/2227.5 V12H’ V8 + (V7 − V8) × 445.5/2227.5
V13H V2 + (V1 − V2) × 1579.5/2227.5 V13H’ V8 + (V7 − V8) × 648.0/2227.5
V14H V2 + (V1 − V2) × 1377.0/2227.5 V14H’ V8 + (V7 − V8) × 850.5/2227.5
V15H V2 + (V1 − V2) × 1215.0/2227.5 V15H’ V8 + (V7 − V8) × 1012.5/2227.5
V16H V2 + (V1 − V2) × 1053.0/2227.5 V16H’ V8 + (V7 − V8) × 1174.5/2227.5
V17H V2 + (V1 − V2) × 891.0/2227.5
V18H V2 + (V1 − V2) × 769.5/2227.5
V19H V2 + (V1 − V2) × 648.0/2227.5
V1AH V2 + (V1 − V2) × 526.5/2227.5
V1BH V2 + (V1 − V2) × 405.0/2227.5
V1CH V2 + (V1 − V2) × 324.0/2227.5
V1DH V2 + (V1 − V2) × 243.0/2227.5
V1EH V2 + (V1 − V2) × 162.0/2227.5
V1FH V2 + (V1 − V2) × 81.0/2227.5
V17H’ V8 + (V7 − V8) × 1336.5/2227.5
V18H’ V8 + (V7 − V8) × 1458.0/2227.5
V19H’ V8 + (V7 − V8) × 1579.5/2227.5
V1AH’ V8 + (V7 − V8) × 1701.0/2227.5
V1BH’ V8 + (V7 − V8) × 1822.5/2227.5
V1CH’ V8 + (V7 − V8) × 1903.5/2227.5
V1DH’ V8 + (V7 − V8) × 1984.5/2227.5
V1EH’ V8 + (V7 − V8) × 2065.5/2227.5
V1FH’ V8 + (V7 − V8) × 2146.5/2227.5
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2002-04-03
T6L79
• Relationship 2 between grayscale data and output voltage
(grayscale data: 20H to 3FH)
(*) n = 0, 1, • • •, 5
Output Voltage (reference value)
Grayscale
Data
Dn5 Dn4 Dn3 Dn2 Dn1 Dn0
V5 < V4 < V3 < V2 < V1 < V0 < AV
DINV = L
,
AV < V9 < V8 < V7 < V6 < V5 < V4,
DD
SS
DINV = L
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
20H V2
20H’ V7
21H V3 + (V2 − V3) × 1215.0/1296.0 21H’ V7 + (V6 − V7) × 81.0/1296.0
22H V3 + (V2 − V3) × 1134.0/1296.0 22H’ V7 + (V6 − V7) × 162.0/1296.0
23H V3 + (V2 − V3) × 1053.0/1296.0 23H’ V7 + (V6 − V7) × 243.0/1296.0
24H V3 + (V2 − V3) × 972.0/1296.0
25H V3 + (V2 − V3) × 891.0/1296.0
26H V3 + (V2 − V3) × 810.0/1296.0
27H V3 + (V2 − V3) × 729.0/1296.0
28H V3 + (V2 − V3) × 648.0/1296.0
29H V3 + (V2 − V3) × 567.0/1296.0
2AH V3 + (V2 − V3) × 486.0/1296.0
2BH V3 + (V2 − V3) × 405.0/1296.0
2CH V3 + (V2 − V3) × 324.0/1296.0
2DH V3 + (V2 − V3) × 243.0/1296.0
2EH V3 + (V2 − V3) × 162.0/1296.0
2FH V3 + (V2 − V3) × 81.0/1296.0
30H V3
24H’ V7 + (V6 − V7) × 324.0/1296.0
25H’ V7 + (V6 − V7) × 405.0/1296.0
26H’ V7 + (V6 − V7) × 486.0/1296.0
27H’ V7 + (V6 − V7) × 567.0/1296.0
28H’ V7 + (V6 − V7) × 648.0/1296.0
29H’ V7 + (V6 − V7) × 729.0/1296.0
2AH’ V7 + (V6 − V7) × 810.0/1296.0
2BH’ V7 + (V6 − V7) × 891.0/1296.0
2CH’ V7 + (V6 − V7) × 972.0/1296.0
2DH’ V7 + (V6 − V7) × 1053.0/1296.0
2EH’ V7 + (V6 − V7) × 1134.0/1296.0
2FH’ V7 + (V6 − V7) × 1215.0/1296.0
30H’ V6
31H V4 + (V3 − V4) × 2713.5/2794.5 31H’ V6 + (V5－V6) × 81.0/2794.5
32H V4 + (V3 − V4) × 2632.5/2794.5 32H’ V6 + (V5－V6) × 162.0/2794.5
33H V4 + (V3 − V4) × 2551.5/2794.5 33H’ V6 + (V5－V6) × 243.0/2794.5
34H V4 + (V3 − V4) × 2470.5/2794.5 34H’ V6 + (V5－V6) × 324.0/2794.5
35H V4 + (V3 − V4) × 2389.5/2794.5 35H’ V6 + (V5－V6) × 405.0/2794.5
36H V4 + (V3 − V4) × 2268.0/2794.5 36H’ V6 + (V5－V6) × 526.5/2794.5
37H V4 + (V3 − V4) × 2146.5/2794.5 37H’ V6 + (V5－V6) × 648.0/2794.5
38H V4 + (V3 − V4) × 2025.0/2794.5 38H’ V6 + (V5－V6) × 769.5/2794.5
39H V4 + (V3 − V4) × 1863.0/2794.5 39H’ V6 + (V5－V6) × 931.5/2794.5
3AH V4 + (V3 − V4) × 1701.0/2794.5 3AH’ V6 + (V5－V6) × 1093.5/2794.5
3BH V4 + (V3 − V4) × 1498.5/2794.5 3BH’ V6 + (V5－V6) × 1296.0/2794.5
3CH V4 + (V3 − V4) × 1296.0/2794.5 3CH’ V6 + (V5－V6) × 1498.5/2794.5
3DH V4 + (V3 − V4) × 1053.0/2794.5 3DH’ V7 + (V5－V6) × 1741.5/2794.5
3EH V4 + (V3 − V4) × 648.0/2794.5
3EH’ V7 + (V5－V6) × 2146.5/2794.5
3FH V4
3FH’ V5
9
2002-04-03
T6L79
• Relationship between LOAD and POL output waveforms
LOAD
POL
OUT
2N-1
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
OUT
2N
POL
OUT
OUT
2N
2N-1
L
V0 to V4
V5 to V9
V5 to V9
V0 to V4
H
(*) OUT
2N-1
(odd-numbered outputs)
OUT (even-numbered outputs)
2N
10
2002-04-03
T6L79
Timing Chart
• Start pulse and data sequence
DI/O, DO/I
(Input)
0
1
2
3
62
63
64
CPH
(*)
OUT1/
D00 to D05
XOR DINV
OUT7/
OUT13/
OUT367/ OUT373/ OUT379/
OUT13 OUT7 OUT1
OUT379 OUT373 OUT367
D10 to D15
XOR DINV
OUT2/
OUT8/
OUT14/
OUT368/ OUT374/ OUT380/
OUT14 OUT8 OUT2
OUT380 OUT374 OUT368
D20 to D25
XOR DINV
OUT3/
OUT9/
OUT15/
OUT369/ OUT375/ OUT381/
OUT15 OUT9 OUT3
OUT381 OUT375 OUT369
D30 to D35
XOR DINV
OUT4/
OUT10/ OUT16/
OUT370/ OUT376/ OUT382/
OUT16 OUT10 OUT4
OUT382 OUT376 OUT370
D40 to D45
XOR DINV
OUT5/
OUT11/ OUT17/
OUT371/ OUT377/ OUT383/
OUT17 OUT11 OUT5
OUT383 OUT377 OUT371
D50 to D55
XOR DINV
OUT6/
OUT12/ OUT18/
OUT372/ OUT378/ OUT384/
OUT18 OUT12 OUT6
OUT384 OUT378 OUT372
DO/I, DI/O
(Output)
(*) Upper: OUT1 → U/D = High level
Lower: OUT379 → U/D = Low level
11
2002-04-03
T6L79
• Loading and cascading operation
0
1
63
64
64n
0
1
CPH
(∗) First input
DI/O
(∗) First output
DO/I
(∗) nth output
DO/I
Grayscale
data bus
First DATA
Last DATA
First DATA at
next stage
LOAD
POL
Hi-z
OUT1~
OUT384
1
2
3
4
n
(*) First input
DI/O
First output
DO/I
nth output
DO/I
· · ·
Panel
12
2002-04-03
T6L79
Maximum Ratings (DV = AV = 0 V)
SS
SS
Characteristics
Digital supply voltage
Symbol
Rating
Unit
Applicable Pin
V0 to V9
DV
AV
−0.3 to 4.0
V
V
DD
Analog supply voltage
Gamma correction voltage
Digital input voltage
−0.3 to 11.0
DD
V (0:9)
−0.3 to AV
+ 0.3
V
DD
DD
V
−0.3 to DV
+ 0.3
V
IN
Storage temperature
T
−55 to 125
°C
stg
Operating Range (DV = AV = 0 V)
SS
SS
Characteristics
Digital supply voltage
Symbol
Rating
Unit
Applicable Pin
DV
AV
3.0 to 3.6
V
V
DD
Analog supply voltage
Gamma correction voltage
Operating temperature
Operating frequency
7.5 to 10.0
DD
V (0:9)
0.1 to AV
− 0.1
V
V0 to V9
CPH
DD
T
−20 to 75
°C
MHz
opr
f
40 (max)
75
CPH
OUT1 to
OUT384
Output load capacitance
C
L
pF/PIN
8 (max)
5 (max)
DI/O, DO/I
Input capacitance
C
IN
pF
Input pins
except DI/O, DO/I
13
2002-04-03
T6L79
Electrical Characteristics
DC Characteristics
(DV = 3.0 to 3.6 V, AV = 7.5 to 10.0 V, DV = AV = 0 V, Ta = −20 to 75°C)
DD
DD
SS
SS
Test
Circuit
Applicable
Pin
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
V
0.3 ×
Low level
V
0
IL
DV
DD
Input voltage
Logic input
0.7 ×
High level
Low level
High level
V
DV
IH
OL
OH
DD
DV
DD
V
I
I
=1 mA
0
0.5
OL
Logic
output
Output voltage
V
DV
DD
V
= −1 mA
OH
− 0.5
AV
AV
− 0.1
OUT1 to
OUT384
SS
DD
Output voltage range
VDO
V
+ 0.1
(Note 4) −20
(Note 5) −30
(Note 6) −10
(Note 7) −20
(Note 8) −30
20
OUT1 to
OUT384
Output voltage deviation
∆V
mV
O
30
10
mV
mV
mV
Output amplitude voltage
deviation
OUT1 to
OUT384
∆Vp-p
Rγ
20
30
V0 to V4
V5 to V9
Gamma resistance fluctuation
7.7
12.8
18
kΩ
Leakage current
Standby current
I
−1
1
1
µA
µA
Logic input
IN
ID
STB
DV
DV
DD
DD
DI
5
DD
(Note 9)
AI
AI
AI
AI
6
DD1
DD2
DD3
DD4
Current dissipation
Output current
mA
4
AV
DD
16
16
(Note 10)
Vout = 8.9 V, AV
Vx = 4 V
= 9 V
(Note 11)
DD
I
−20
chg
OUT1 to
OUT384
µA
Vout = 0.1 V, AV
Vx = 1 V
= 9 V
(Note 11)
DD
I
30
dis
Note4: AV
= 9V, AV = 0 V, AV + 1.5 V ≤ VOUT ≤ AV
− 1.5 V
DD
SS SS DD
∆VO is the numerical different the anticipated value of LCD panel drive output voltage (refer for (7)
relationship between grayscale data and output voltage) from each LCD panel drive output voltage, These
relationship shows as following formula.
∆VO = [each LCD panel drive pin output voltage] − [anticipated value of LCD panel drive output voltage]
Note 5: AV
DD
= 9 V, AV = 0 V, AV + 0.1 V ≤ VOUT < AV + 1.5 V、AV
− 1.5 V < VOUT ≤ AV − 0.1 V
DD
SS
SS
SS
DD
The formula for ∆VO is same as Note 4.
Note 6: AV = 9 V, AV = 0 V, AV + 1.5 V < VOUT < AV
− 1.5 V
DD SS SS
DD
∆Vpp is the numerical different the remainder of the average of all LCD panel drive output voltage at positive
electrode and negative electrode from each LCD panel drive output voltage
∆Vpp = {[the remainder of each LCD panel drive output voltage at positive electrode (V0 to V4) and negative
electrode (V5 to V9)]− [all LCD panel drive output voltage at positive electrode (V0 to V4) and negative
electrode (V5 to V9) of LCD panel drive output voltage]} in the same grayscale
Note 7: AV
DD
= 9 V, AV = 0 V, AV + 0.8 V < VOUT ≤ AV + 1.5 V, AV
SS SS SS
− 1.5 V ≤ VOUT < AV
− 0.8 V
DD
DD
The formula for ∆Vpp is same as Note 6.
Note 8: AV = 9 V, AV = 0 V, AV + 0.1 V ≤ VOUT ≤ AV + 0.8 V, AV
− 0.8 V ≤ VOUT ≤ AV
− 0.1 V
DD SS SS SS
DD
DD
The formula for ∆Vpp is same as Note 6.
14
2002-04-03
T6L79
Note 9: LOAD cycle = 20 µs, f
= 32.5 MHz
CPH
DI : dot-checkered input pattern, no loaded
DD
AI 1: V0 to V4 = V5 to V9 = 4.5 V, AV
= 9 V, LCD panel drive load = 200 Ω + 80 pF, TESTP = “H”
DD
DD
AI 2: V0 to V4 = V5 to V9 = 4.5 V, AV
= 9 V, LCD panel drive load = 200 Ω + 80 pF, TESTP = “L”
DD
DD
Note 10: LOAD cycle = 20 µs, f
= 32.5 MHz
CPH
AI 3: V0 = 8.9 V, V4 = V5, V9 = 0.1 V, AV
= 9 V, LCD panel drive load = 200 Ω + 80 pF, TESTP = “H”
= 9 V, LCD panel drive load = 200 Ω + 80 pF, TESTP = “L”
DD
DD
DD
AI 4: V0 = 8.9 V, V4 = V5, V9 = 0.1 V, AV
DD
Note 11: Voltage applied to LCD panel drive
I
I
dis
chg
A
A
Vout
Vout
Vx
Vx
AC Characteristics
(DV = 3.0 to 3.6 V, AV = 7.5 to 10.0 V, DV = AV = 0 V, Ta = −20 to 75°C)
DD
DD
SS
SS
Test
Characteristics
Symbol
Test Condition
Min
Typ.
Max
Unit
Circuit
CPH pulse width H
CPH pulse width L
Enable setup time
Enable hold time
t
4
4
4
0
4
0
ns
ns
ns
ns
ns
ns
CWH
t
CWL
t
t
sDI
hDI
Data DINV setup time
Data DINV hold time
t
sDD
hDD
t
CPH
cycle
LOAD high period
t
3
2
1
LWH
CPH
cycle
LOAD enable input period
LOAD enable output period
t
t
LOAD-D1
LD-LOAD
CPH
cycle
LOAD setup time
POL setup time
t
6
4
15
ns
ns
ns
ns
sLD
sDP
hDP
t
t
POL hold time
6
Enable output delay time
t
C
C
= 15 pF
pdDO
L
= 75 pF
L
R = 5 kΩ
Target output voltage × 0.9
Output delay time 1
Output delay time 2
t
t
6
µs
µs
pdDE
pdDX
(Note 12)
C
L
= 75 pF
R = 5 kΩ
Target output voltage ± ∆V
11
O
(Note 12)
Note 12: Output load condition
LCD drive output pin
(Measured here)
R = 1 kΩ
C = 15 pF
R
R
R
R
R
C
C
C
C
C
15
2002-04-03
T6L79
t
t
CWL
CWH
CPH
0.7 × DV
0.3 × DV
DD
DD
DI/O
0.7 × DV
0.7 × DV
DD
DD
(入力)
t
t
hDI
sDI
t
LOAD-DI
0.7 × DV
DD
LOAD
0.7 × DV
DD
CPH
t
t
hDD
sDD
Dn0~Dn5
XOR DINV
(n = 0, 1, ･･･4, 5)
0.7 × DV /0.3 × DV
DD
DD
(*)
0.7 × DV
CPH
0.7 × DV
DD
DD
t
t
pdDO
pdDO
DO/I
(出力)
0.7 × DV
0.7 × DV
DD
DD
Note: Timing for loading OUT379 to OUT384
Timing for loading OUT1 to OUT6
0.7 × DV
0.7 × DV
DD
DD
CPH
Dn0~Dn5
XOR DINV
(n = 0, 1, ･･･4, 5)
Last data
t
LD-LOAD
t
SLD
0.7 × DV
0.7 × DV
DD
DD
LOAD
t
LWH
16
2002-04-03
T6L79
0.7 × DV
0.7 × DV
DD
DD
LOAD
POL
t
t
hDP
sDP
0.7 × DV /0.3 × DV
DD
DD
t
pdDX
t
pdDE
90%
10%
OUT1 to OUT384
Power-On Sequence
At power ON, the sequence is: DV
→ LOGOC input signal → AV , reference analog voltage
DD
DD
At power OFF, the sequence is the reverse of that for power ON.
Turn ON/OFF power supplies for AV
and reference analog voltage inputs simultaneously.
DD
DD
As long as the voltage condition, AV
simultaneously.
> DV , is satisfied, all power supplies can be turned OFF
DD
AV , reference analog voltage
DD
(2)
(1)
(2)
(1)
(1) DV , (2) LOGOC input signal
DD
DV , AV
SS
SS
17
2002-04-03
T6L79
RESTRICTIONS ON PRODUCT USE
000707EBE
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with
the film. Try to design and manufacture products so that there is no chance of users touching the film after
assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to
ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as
industrial waste.
• Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases
this can cause the device to malfunction.
This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing
circuits, make sure that devices are protected against incident light from external sources. Exposure to light both
during regular operation and during inspection must be taken into account.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other
rights of the third parties which may result from its use. No license is granted by implication or otherwise under
any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
18
2002-04-03
相关型号：
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