TXC-03701-BIPL [TRANSWITCH]
Framer, PQCC68, PLASTIC, LCC-68;
| 型号： | TXC-03701-BIPL |
| 厂家： | 
TRANSWITCH CORPORATION |
| 描述： | Framer, PQCC68, PLASTIC, LCC-68 电信 电信集成电路 |
| 文件： | 总44页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E2/E3F Device
8-, 34-Mbit/s Framer
TXC-03701B
DATA SHEET
FEATURES
DESCRIPTION
• Framer for ITU-TSS Recommendations:
- G.742 (8448 kbit/s)
The E2/E3 Framer (E2/E3F) is a CMOS VLSI device
that provides the functions needed to frame a wideband
payload to one of four ITU-TSS Recommendations:
G.742, G.745, G.751, or G.753. The E2/E3F interfaces
to line circuitry with either rail or NRZ signals. On the
terminal side, the interface can be either nibble-parallel
or bit-serial. The nibble interface clocks are gapped for
the service bits, framing bits and the BIP-4 option, if
selected. For the serial interface, a transmit reference
generator is provided.
- G.745 (8448 kbit/s)
- G.751 (34368 kbit/s)
- G.753 (34368 kbit/s)
• Line side interface:
- Rail or NRZ
• HDB3 codec for rail I/O
The E2/E3F can be operated with or without a micropro-
cessor. When interfaced with a microprocessor, the E2/
E3F provides an 8-byte memory map for control, perfor-
mance counters and alarm status. The E2/E3F provides
a transmit and receive interface port for accessing the
overhead bits from each of the four recommendations.
The overhead bits can also be accessed by the micro-
processor via the memory map.
• Terminal side interface:
- Nibble-parallel
- Bit-serial
• Transmit reference generator for serial I/O
• Microprocessor or control leads
• Service bit I/O port
APPLICATIONS
• Pin-selectable transmit line clock polarity
• 68-pin plastic leaded chip carrier
• Line terminals
• Wideband data or video transport
• Test equipment
• Multiplexer systems
+5V
TERMINAL
SIDE
LINE
SIDE
Receive
bit-serial/nibble-parallel
E2/E3F
NRZ
or
Rail
I/O
Transmit reference
generator
8-, 34-Mbit/s Framer
TXC-03701B
Transmit
bit-serial/nibble-parallel
Control
leads
Microprocessor Service bits
Alarms
I/O
bus
Document Number:
TXC-03701B-MB
Ed. 1, August 1995
Copyright
1995 TranSwitch Corporation
TXC and TranSwitch are registered trademarks of TranSwitch Corporation
TranSwitch Corporation
8 Progress Drive
Shelton, CT 06484
USA
Tel: 203-929-8810 Fax: 203-926-9453
•
•
•
•
•
E2/E3F
TXC-03701B
TABLE OF CONTENTS
SECTION
PAGE
Block Diagram ............................................................................................................ 3
Block Diagram Description ......................................................................................... 3
Pin Diagram ................................................................................................................ 6
Pin Descriptions .......................................................................................................... 6
Absolute Maximum Ratings ...................................................................................... 14
Thermal Characteristics ............................................................................................ 14
Power Requirements ................................................................................................ 14
Throughput Delays ................................................................................................... 14
Input, Output and I/O Parameters ............................................................................ 15
Timing Characteristics .............................................................................................. 17
Operation .................................................................................................................. 33
Power Supply Connections ............................................................................... 33
Memory Map ............................................................................................................. 33
Memory Map Descriptions ........................................................................................ 34
Package Information ................................................................................................. 37
Ordering Information ................................................................................................. 38
Related Products ...................................................................................................... 38
Standards Documentation Sources .......................................................................... 39
Documentation Update Registration Form .......................................................... 43
LIST OF FIGURES
Figure 1. E2/E3F TXC-03701B Block Diagram ...................................................... 3
Figure 2. G.7XX Frame Contents Summary ........................................................... 4
Figure 3. G.745 BIP-4 Location .............................................................................. 5
Figure 4. E2/E3F TXC-03701B Pin Diagram .......................................................... 6
Figure 5. Line Side Receive NRZ Timing ............................................................. 17
Figure 6. Line Side Transmit NRZ Timing ............................................................ 18
Figure 7. Line Side Receive Rail Timing .............................................................. 19
Figure 8. Line Side Transmit Rail Timing ............................................................. 20
Figure 9. Transmit Reference Generator Timing .................................................. 21
Figure 10. Terminal Side Receive Nibble Timing ................................................... 22
Figure 11. Terminal Side Transmit Nibble Timing .................................................. 23
Figure 12. Terminal Side Receive Serial Timing .................................................... 24
Figure 13. Terminal Side Transmit Serial Timing ................................................... 25
Figure 14. G.742/G.751 Service Bit Receive Timing .............................................. 26
Figure 15. G.745/G.753 Service Bit Receive Timing .............................................. 27
Figure 16. G.742/G.751 Service Bit Transmit Timing ............................................. 28
Figure 17. G.745/G.753 Service Bit Transmit Timing ............................................. 29
Figure 18. BIP-4 Error Timing ................................................................................. 30
Figure 19. Microprocessor Read Cycle .................................................................. 31
Figure 20. Microprocessor Write Cycle .................................................................. 32
Figure 21. Power Supply Connections ................................................................... 33
Figure 22. E2/E3F TXC-03701B 68-Pin Plastic Leaded Chip Carrier .................... 37
TXC-03701B-MB
Ed. 1, August 1995
- 2 -
E2/E3F
TXC-03701B
BLOCK DIAGRAM
RDL
RCKL
SERIAL
PARALLEL
Receive
Data
RSD
TDOUT
TCG
TFOUT
RSC
RSF
RNIB3
RNIB2
RNIB1
RNIB0
RNC
Data
Clock
Frame
Data
RP/RDL
RN
Line
Decoder
Clock
Frame
Frame
Alignment
Interpreter
Clock
Output
RCK/RCKL
CV
RAIS
RNF
RCG
N.C.
RLOC
BIP-4E
RLOF
ROD
ROC
ROF
FE
NRZLINE
BIP-4
M0
M1
MICRO
SER
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
SEL
ALE
RD
Micro-
processor
I/O
Control
DAIS
TLBK
PLBK
WR
RDY
TAIS
TLCINV
LPT
Transmit
Reference
Generator
TLOC
FORCEFE
TOD
XNIB3
XNIB2
XNIB1
XNIB0
XCK
XSF
N.C.
TCIN
XSD
XCK
TOC
TOF
RESET
Input
TCKL
TDL
Clock
TP/TDL
TCK/TCKL
XNF
XNC
N.C.
TCOUT
G.7XX
Send
Data
Framing
Data
Line
Encoder
Clock
TN
Transmit
TLCINV
Line Side
Terminal Side
Figure 1. E2/E3F TXC-03701B Block Diagram
BLOCK DIAGRAM DESCRIPTION
The block diagram for the E2/E3F is shown in Figure 1. The E2/E3F receives a line side NRZ data signal
(RDL) and clock signal (RCKL), or a positive (RP) and negative (RN) rail signal and clock signal (RCK), from a
TranSwitch MRT, or from another line interface circuit. The selection of the line interface, rail or NRZ, is con-
trolled by the external lead labeled NRZLINE. Indications of HDB3 coding violation errors are detected in the
Line Decoder Block and are provided on an external signal lead (CV) as pulses. Coding violation errors are
also counted in an 8-bit saturating counter accessed by the microprocessor through the memory map. A cod-
ing violation is not part of the standard HDB3 zero-substitution code, and occurs because of noise or other
impairments on the line.
The selection of one of the four G.7XX framing formats (G.742, G.745, G.751, and G.753), which are sup-
ported by the E2/E3F, is determined by external control leads (M1 and M0), or states written into the memory
map by the microprocessor. The Frame Alignment Block performs frame alignment and alarm detection. It
detects Loss of Frame (RLOF), Loss of Clock (RLOC), and performs AIS detection (RAIS) and BIP-4 (Bit Inter-
leaved Parity-4) detection (BIP-4E) when this feature is enabled in the nibble-parallel mode. Loss of clock is
detected whether the clock is stuck high or low. A framing error (FE) output is also provided to indicate when
any of the framing bits in the G. 7XX frame are in error. Loss of the receive clock or framing normally causes
AIS to be inserted into the terminal side data stream. However, for some applications, receive data is required
on the terminal side regardless of frame alignment. The disable AIS (DAIS) control lead permits the E2/E3F to
provide receive data in the presence of loss of frame. The external alarm indications (latched and unlatched
states) are provided in the memory map, and unlatched alarm indications are provided at signal leads.
TXC-03701B-MB
Ed. 1, August 1995
- 3 -
E2/E3F
TXC-03701B
The service bits are defined as bits 11 and 12 for G.742 and G.751, as listed in Figure 2. The service bits for
G.745 and G.753 are defined as bits 5 through 8 in sets II and III. The receive service bit interface consists of
the following signals: data output signal (ROD), clock output signal (ROC), and framing pulse (ROF). The clock
signal (ROC) is gapped and is provided for clocking out the service bits. The service bit states are also written
by the Interpreter Block into E2/E3F memory locations, which can be read by the microprocessor if the signal-
ing rate is low.
G.742
1
11 12
212(Set I)
DATA
424(II)
636(III)
844
848(IV)
1111010000
s
s
DATA
DATA
DATA
DATA
DATA
BIP-4 if selected
G.745
1
264(I) 268 272
528(II) 532 536
792(III)
DATA
1052
1056(IV)
11100110
DATA
jc
s
jc
s
DATA
BIP-4 if selected
G.751
1
11 12
384(Set I)
768(II)
1152(III)
1532
1536(IV)
1111010000
s
s
DATA
DATA
DATA
DATA
BIP-4 if selected
G.753
1
716(I) 720 724
jc
1432(II) 1436 1440
jc
2144
BIP-4 if selected
2148(III)
111110100000
DATA
s
DATA
s
Note:
1. The leading segment of the frame (starting at bit 1) is the frame alignment signal pattern.
2. s indicates the service bits.
3. jc indicates four justification control bits. In sets where DATA is not preceded by service bits,
the first 4 or 8 bits of DATA may be associated with justification.
No. of Bits in
Frame
Frame Alignment
Signal Pattern
Bit Rate
(kbit/s)
Specifications
Service Bits
G.742
G.745
11,12
848
1111010000
11100110
8448
8448
5-8 Set II (269-272)
5-8 Set III (533-536)
1056
G.751
G.753
11,12
1536
2148
1111010000
34368
34368
5-8 Set II (721-724)
111110100000
5-8 Set III (1437-1440)
Figure 2. G.7XX Frame Contents Summary
The E2/E3F terminal side Output Block provides either a bit-serial or a nibble-parallel interface. The interface
is selected by an external control lead (SER) or by setting a control bit in the memory map. The bit-serial inter-
face consists of the following signals: a data output signal (RSD), a clock output signal (RSC), a receive clock
gapped output signal (RCG), and a framing pulse (RSF). The receive clock gapped signal (RCG) is active low
during the framing and service bit times. The nibble-parallel interface consists of the following signals: a data
output signal having a nibble format (RNIB3 through RNIB0), a clock output signal (RNC), and a framing pulse
(RNF). Signal leads are shared for the two interfaces (RSD and RNIB3, RSC and RNC, RSF and RNF) and
with the transmit reference generator, which is used in the serial mode only. The RNIB3 bit corresponds to the
first bit received in a four-bit bit-serial stream segment. In the nibble mode, the framing pattern, service bits and
BIP-4 nibble are not provided at the interface. The receive nibble clock (RNC) is gapped during framing pat-
tern, service bit and BIP-4 times.
TXC-03701B-MB
Ed. 1, August 1995
- 4 -
E2/E3F
TXC-03701B
The transmitter operates independently of the receiver, unless the loop timing feature is selected. When the
loop timing feature is selected, the receive clock becomes the transmitted clock. In the transmit direction, the
terminal side bit-serial interface consists of the following signals: a data input signal (XSD), a clock input signal
(XCK), and a framing pulse (XSF). The nibble-parallel interface consists of the following signals: a data input
signal having a nibble format (XNIB3 - XNIB0), a clock input signal (XCK), a framing output pulse (XNF), and a
nibble output clock signal (XNC). The leads are shared between the two interfaces and with the E2/E3F trans-
mit reference generator in order to minimize the pin count. The XNIB3 bit corresponds to the first bit transmit-
ted in a four-bit bit-serial stream segment. The transmit nibble clock (XNC) is stretched to accommodate the
framing pattern, service bit and BIP-4 times. The E2/E3F also detects loss of clock (TLOC) whether the input
clock is stuck high or low.
The transmitter has control leads for BIP-4 generation (BIP-4) and inserting AIS (TAIS). When the E2/E3F is
operating with a microprocessor, the BIP-4 and AIS functions are controlled by the microprocessor. When the
BIP-4 option is selected, the BIP-4 is transmitted as the last nibble in the frame format, as shown in Figures 2
and 3.
Bit 1
G.745 Frame
1053
1056
SET III
SERVICE
BITS
SET II
SERVICE
BITS
1 1 1 0 0 1 1 0
DATA
DATA
DATA
BIP-4
When BIP-4 feature
is selected
Figure 3. G.745 BIP-4 Location
The transmitted service bits are inserted into the frame format from either an external interface or from mem-
ory map locations. The transmit service bit interface consists of the following signals: a data in signal (TOD), a
clock output signal (TOC), and a framing pulse (TOF).
To facilitate transmit side multiplexing while operating in the bit-serial mode, the E2/E3F provides a transmit
frame reference generator. The transmit frame reference generator accepts an external 8.448 or 34.368 MHz
clock signal (TCIN) and produces a clock out signal (TCOUT), a framing pulse (TFOUT), a clock gap signal
(TCG), and a data signal (TDOUT). The data signal consists of G.7XX framing bits and zeros elsewhere. The
purpose of the transmit reference signals is to fix the transmit time-base for the terminal payload multiplexer
circuitry.
The selection of the transmit line interface, rail or NRZ, is controlled by the state present on the NRZLINE con-
trol lead, which also controls the receive interface selection. When the internal HDB3 Encoder Block is
bypassed, the transmit line interface consists of a data signal (TDL) and a clock signal (TCKL). When the
HDB3 encoder is enabled, the transmit line interface consists of positive (TP) and negative (TN) rail signals
and a clock signal (TCK). The TCK/TCKL clock may be inverted by setting TLCINV low.
Input pins are provided for activating terminal loopback (TLBK) and payload loopback (PLBK).
A high placed on the microprocessor control lead (MICRO) selects the microprocessor interface. All the exter-
nal control leads, except the loop timing (LPT), receive AIS disable (DAIS), and the line interface (NRZLINE)
control leads are disabled when the microprocessor interface is selected. The E2/E3F provides pull-up resis-
tors for the active low control leads.
The microprocessor interface consists of eight bidirectional data and address leads (AD7 - AD0), along with
four microprocessor control input leads and a ready (RDY) output signal.
TXC-03701B-MB
Ed. 1, August 1995
- 5 -
E2/E3F
TXC-03701B
PIN DIAGRAM
ROC
ROF
FE
BIP-4E
XNC/TCOUT
XNF
60
59
11
12
13
14
15
16
17
18
19
20
21
22
23
24
58
57
56
55
54
53
52
51
50
49
48
47
46
45
NRZLINE
BIP-4
M0
XCK
XNIB0/XSD
XNIB1/TCIN
XNIB2
XNIB3/XSF
GND
M1
E2/E3F
VDD
TXC-03701B
Pin Diagram
(Top View)
GND
VDD
MICRO
SER
TLCINV
DAIS
TLBK
PLBK
TAIS
RDY
WR
RD
LPT
ALE
TLOC
FORCEFE
25
26
SEL
Figure 4. E2/E3F TXC-03701B Pin Diagram
PIN DESCRIPTIONS
POWER SUPPLY AND GROUND
Symbol
Pin No.
I/O/P*
Type
Name/Function
VDD
GND
1,17,35,51
P
P
VDD: +5-volt supply voltage, +/- 5%
Ground: 0 volts reference.
18,34,52,68
*Note: I = Input; O = Output; P = Power
TXC-03701B-MB
Ed. 1, August 1995
- 6 -
E2/E3F
TXC-03701B
LINE SIDE RECEIVE SIGNALS
Symbol
Pin No.
I/O/P
Type *
Name/Function
RP/RDL
2
I
TTLp
Receive Positive Rail/Receive NRZ Data: Positive
rail input data is clocked into the E2/E3F on negative
transitions of the clock signal RCK/RCKL. The HDB3
codec for rail operation is enabled by applying a low to
the NRZLINE signal lead. Receive NRZ data is
clocked into the E2/E3F on positive transitions of the
clock signal RCK/RCKL. The NRZ mode is enabled by
applying a high to the NRZLINE signal lead.
RN
3
4
I
I
TTLp
TTLp
Receive Negative Rail Data: Negative rail input data
is clocked into the E2/E3F on negative transitions of
the clock signal RCK/RCKL. The HDB3 codec for rail
operation is enabled by applying a low to the NRZ-
LINE signal lead.
RCK/RCKL
Receive Clock Rail/NRZ: The receive clock is used
for clocking in the rail/NRZ data signals and is used as
the time base for receiver operation.
LINE SIDE TRANSMIT SIGNALS
Symbol
Pin No.
I/O/P
Type
Name/Function
TP/TDL
31
O
TTL8mA
Transmit Positive Rail/Transmit NRZ Data: Positive
rail data is clocked out of the E2/E3F on positive tran-
sitions of the clock signal TCK/TCKL when pin 50 is
high and on negative transitions of the clock when pin
50 is low. The HDB3 codec for rail operation is
enabled by applying a low to the NRZLINE signal lead.
Transmit NRZ data is clocked out of the E2/E3F on
negative transitions of the clock signal TCK/TCKL.
The NRZ mode is enabled by applying a high to the
NRZLINE signal lead.
TCK/TCKL
32
O
TTL8mA
Transmit Clock Rail/NRZ: The transmit clock is used
for clocking out the rail/NRZ data signals. The TCK/
TCKL clock signal is derived from the XCK clock.
Note: When XCK is removed, the framer then uses
TCIN to generate TCK/TCKL (in serial mode only). If
both XCK and TCIN are removed, TCK/TCKL is
derived from RCK/RCKL. This clock may be inverted
by using control pin 50 (TLCINV).
TN
33
O
TTL8mA
Transmit Negative Rail Data: Negative rail output
data is clocked out of the E2/E3F on positive transi-
tions of the clock signal TCK/TCKL when pin 50 is
high and on negative transitions of the clock when pin
50 is low. The HDB3 codec for rail operation is
enabled by applying a low to the NRZLINE signal lead.
* Note: See Input, Output and I/O Parameters section for Type definitions.
TXC-03701B-MB
Ed. 1, August 1995
- 7 -
E2/E3F
TXC-03701B
TERMINAL INTERFACE SIGNALS
Symbol
Pin No.
I/O/P
Type
Name/Function
RCG
61
O
TTL4mA
Receive Clock Gapped: An active low signal which
indicates the receive framing and service bit locations.
The RCG signal is provided in the serial mode only.
RNF/RSF
62
63
O
O
TTL4mA
TTL4mA
Receive Framing Pulse: This active low framing
pulse is synchronous with the last data nibble
RNIB(3-0) for the terminal side nibble-parallel inter-
face, and with the first bit in the frame for the bit-serial
interface.
RNIB3/RSD
Receive Nibble Bit 3/Receive Serial Data: Bit 3 is the
most significant bit in the nibble and corresponds to
the first bit received in the nibble. The framing pattern,
service bits, and BIP-4 nibble are not provided as par-
allel data. In the serial mode, all bits, including the
framing pattern and service bits, are provided.
RNIB2/
TDOUT
64
65
66
67
O
O
O
O
TTL4mA
TTL4mA
TTL4mA
TTL4mA
Receive Nibble Bit 2/Transmit Reference Generator
Data Output: Bit 2 in nibble mode. The reference gen-
erator is enabled in the serial mode. The output data
signal consists of all ones in place of the framing bits
and zeros elsewhere in the frame. The TDOUT signal
is generated from the input clock (TCIN).
RNIB1/TCG
Receive Nibble Bit 1/Transmit Reference Generator
Clock Gap Signal: Bit 1 in nibble mode. The refer-
ence generator is enabled in the serial mode. The
active low TCG signal indicates the location of the
framing pattern and the service bits in the frame. The
TCG signal is generated from the input clock (TCIN).
RNIB0/
TFOUT
Receive Nibble Bit 0/Transmit Reference Generator
Framing Pulse: Bit 0 is the least significant bit in the
nibble and is the last bit received. The reference gen-
erator is enabled in the serial mode. The active low
TFOUT signal is one clock cycle (TCOUT) wide, and is
synchronous with the first bit in the frame.
RNC/RSC
Receive Nibble Clock/Receive Serial Clock: The
nibble and serial clocks are derived from the line side
rail/NRZ clock signal (RCK/RCKL). A received nibble
is clocked out on positive transitions of RNC. RNC is
gapped during framing pattern, service bit and BIP-4
bit times. Serial data is clocked out on positive transi-
tions of RSC.
TXC-03701B-MB
Ed. 1, August 1995
- 8 -
E2/E3F
TXC-03701B
Symbol
Pin No.
I/O/P
Type
Name/Function
XNIB3/XSF
53
I
TTLp
Transmit Nibble Bit 3/Transmit Serial Framing
Pulse: For the terminal side parallel interface, bit 3 in
the transmitted nibble is the most significant bit and
corresponds to the first bit transmitted in the nibble.
When the terminal interface is serial, the negative
framing pulse is synchronous with the first bit in the
frame. It is recommended that the framing pulse
(TFOUT) and other signals generated by the transmit
reference generator be used as the transmit framing
pulse, and for multiplexing the data into the frame.
XNIB2
54
55
I
I
TTLp
TTLp
Transmit Nibble Bit 2: Bit 2 in the transmit nibble.
XNIB1/TCIN
Transmit Nibble Bit 1/Transmit Reference Genera-
tor Clock In: Bit 1 in the transmit nibble. For a serial
interface, the reference clock (TCIN) is used to derive
the clock out (TCOUT), data signal (TDOUT), framing
pulse (TFOUT), and gapped clock signal (TCG). The
reference generator signals are provided for multiplex-
ing the external payload data into the serial frame. The
E2/E3F requires a transmit clock having a frequency of
8448 kHz with a stability of +/- 30 ppm to meet the
clock tolerance specified in ITU-TSS Recommenda-
tions G.742 and G.745. For Recommendations G.751
and G.753, the required clock frequency is 34368 kHz
with a stability of +/- 20 ppm.
XNIB0/XSD
56
I
TTLp
Transmit Nibble Bit 0/Transmit Serial Data: For the
terminal side parallel interface, bit 0 is the least signifi-
cant bit in the nibble and the last bit from the nibble
that is transmitted. For a serial interface, the input
must consist of all the bits in the frame. The E2/E3F
inserts a new framing pattern and the service bits
(from the external interface or the memory map) into
the transmit data stream determined by the location of
the framing pulse (XSF).
XCK
57
I
TTLp
Transmit Clock: For the terminal side parallel inter-
face, the transmit clock is used for all transmit timing
functions, including deriving the nibble output clock
(XNC) and framing pulse (XNF). The E2/E3F requires
a transmit clock having a frequency of 8448 kHz with a
stability of +/- 30 ppm to meet the clock tolerance
specified in ITU-TSS Recommendations G.742 and
G.745. For Recommendations G.751 and G.753, the
required clock frequency is 34368 kHz with a stability
of +/- 20 ppm. For the serial interface, this clock may
be derived from the transmit reference generator clock
output (TCOUT). The duty cycle must be 50 ± 5%.
TXC-03701B-MB
Ed. 1, August 1995
- 9 -
E2/E3F
TXC-03701B
Symbol
Pin No.
I/O/P
Type
Name/Function
XNF
58
O
TTL4mA
Transmit Nibble Framing Pulse: The nibble framing
pulse and clock signal (XNC) are provided for multi-
plexing nibble data into the E2/E3F from external cir-
cuitry. The negative framing pulse identifies the first bit
in the frame.
XNC/TCOUT
59
O
TTL8mA
Transmit Nibble Clock/Transmit Reference Genera-
tor Clock Out: The nibble clock is derived from the
transmit clock (XCK) and is used as a time base for
clocking data out of the external multiplexer and into
the E2/E3F. XNC is gapped during the framing pattern,
service bit and BIP-4 bit times. Data is clocked in on
positive transitions. TCOUT is derived from the input
clock (TCIN), and has the same duty cycle.
SERVICE BIT INTERFACE SIGNALS
Symbol
Pin No.
I/O/P
Type
Name/Function
ROD
9
O
TTL8mA
Receive Service Data Bits: The service bits for the
G.742 and G.751 recommendations are defined as
bits 11 and 12. For the G.745 and G.753 recommen-
dations, the service bits are defined as 5 through 8 in
Sets II and III.
ROC
ROF
10
11
O
O
TTL8mA
TTL8mA
Receive Service Bits Clock: A gapped clock that
clocks out the service bits on positive transitions.
Receive Service Bits Framing Pulse: A positive
framing pulse that is synchronous with the first bit in
the frame.
TOD
27
I
TTLp
Transmit Service Data Bits: The service bits for
G.742 and G.751 are bits 11 and 12. For G.745 and
G.753, the service bits are 5 through 8 in Sets II and
III. When the E2/E3F is configured to work with a
microprocessor, bit 0 (OHI/O) in location 00H must be
written with a one to enable TOD.
TOC
TOF
28
29
O
O
TTL8mA
TTL8mA
Transmit Service Bits Clock: A gapped clock that
clocks in the service bits on positive transitions. The
clock is active only for clocking in the transmit service
data bits (TOD).
Transmit Service Bits Framing Pulse: A positive
framing pulse that is synchronous with the first bit in
the frame.
TXC-03701B-MB
Ed. 1, August 1995
- 10 -
E2/E3F
TXC-03701B
MICROPROCESSOR INTERFACE SIGNALS
Symbol
Pin No.
I/O/P
Type
Name/Function
AD(7-0)
36-43
I/O
TTL I/O
Address/Data Bus: These leads constitute the time-
multiplexed address and data bus for accessing the
registers which reside in the E2/E3F. Only AD(2-0)
are required for address input.
SEL
ALE
44
45
I
I
TTLp
TTLp
Select: A low enables the microprocessor to access
the E2/E3F memory map for control, status, and
alarm information (Note 1).
Address Latch Enable: An active high signal gener-
ated by the microprocessor. Used by the micropro-
cessor to hold an address stable during a read/write
bus cycle (Note 1).
RD
WR
46
47
48
I
I
TTLp
TTLp
TTL
Read: An active low signal generated by the micro-
processor for reading the registers which reside in the
memory map. The E2/E3F memory map is selected
by placing a low on the select lead (Note 1).
Write: An active low signal generated by the micro-
processor for writing to the registers which reside in
the memory map. The E2/E3F memory map is
selected by placing a low on the select lead (Note 1).
RDY
O
Ready: An active high is an E2/E3F acknowledgment
Open Drain to the microprocessor that the addressed memory
map location can complete the data transfer.
*Note 1: When MICRO (pin 19) is tied low, the microprocessor interface is disabled. This microprocessor interface input
pin has an internal pull-up resistor and can be left open.
CONTROL SIGNALS
Symbol
Pin No.
I/O/P
Type
Name/Function
NRZLINE
13
I
TTLp
Non-Return to Zero Line Selection: A high enables
an NRZ line interface (RP/TP), and causes the HDB3
decoder/encoder to be bypassed. An active low
enables the rail interface (RP/RN, and TP/TN) and the
HDB3 decoder/encoder.
BIP-4
14
I
TTLp
Bit Interleaved Parity - 4: A high enables the BIP-4
function. In the transmit direction, the BIP-4 is calcu-
lated for data nibbles only, and is sent as the last nibble
in the frame format. In the receive direction, the BIP-4 is
calculated for the data bits only and compared against
the received value which is present in the last four bits
of the frame. An output indication (BIP-4E) occurs when
one or more columns do not match. A BIP-4 error mask
is provided in the memory map which permits up to four
errors to be transmitted. At the terminal interface, the
transmit and receive nibble clocks are gapped to
accommodate the time that corresponds to the BIP-4
nibble.
TXC-03701B-MB
Ed. 1, August 1995
- 11 -
E2/E3F
TXC-03701B
Symbol
Pin No.
I/O/P
Type
Name/Function
M1
M0
16
15
I
TTLp
Mode Control: The two controls select the operating
rate of the E2/E3F according to the table shown below:
M1
M0
Recommendation Rate (kbit/s)
low
low
G.745
G.742
G.753
G.751
8448
8448
low high
high low
high high
34368
34368
MICRO
19
20
I
I
TTLp
TTLp
Microprocessor Mode: A high enables the micropro-
cessor interface. When the microprocessor is enabled,
the following hardware control leads are disabled: BIP-
4, Mode (M0 and M1), Serial I/O (SER), and transmit
AIS (TAIS). Bits are provided in Address 00H of the
memory map for controlling these functions. These bits
are inactive when MICRO is low.
SER
Serial Interface: A high selects the bit-serial interface
for the terminal side interface. A low selects the nibble-
parallel interface.
TLBK
PLBK
21
22
I
I
TTLp
TTLp
Terminal Loopback: A low enables a transmit-to-
receive loopback at the line side.
Payload Loopback: A low enables a receive-to-trans-
mit loopback at the terminal side in the serial mode of
operation only.
TAIS
LPT
23
24
26
30
I
I
I
I
TTLp
TTLp
TTLp
TTLp
Transmit Alarm Indication Signal: A low causes an all
ones signal (AIS) to be sent in place of a G.7XX frame
format.
Loop Timing: A low enables the loop timing feature.
Loop timing disables the transmit clock and enables the
receive clock to be used as the transmit clock.
FORCEFE
RESET
Force Framing Error: An errored framing bit is
inserted into the transmit framing pattern upon a high to
low transition.
Reset: A positive pulse having a duration of at least 10
transmit clock cycles (XCK) applied to this pin resets
the internal counters, logic circuits, and the perfor-
mance counters and control bits in the memory map to
zero. The reset pulse is applied after the power
becomes stable.
DAIS
49
50
I
I
TTLp
TTLp
Disable AIS: A low disables the automatic insertion of
AIS into the terminal side receive nibble/serial bit
stream.
TLCINV
Transmit Line Clock Invert: A low inverts the output
clock TCK/TCKL when operating in the P and N rail
mode.
TXC-03701B-MB
Ed. 1, August 1995
- 12 -
E2/E3F
TXC-03701B
STATUS AND ALARM SIGNALS
Symbol
Pin No.
I/O/P
Type
Name/Function
CV
5
O
TTL8mA
Coding Violation: A positive pulse, one clock cycle
wide, is generated when an illegal coding violation is
detected. A coding violation is not part of the HDB3
zero-substitution code. A CV occurs because of noise
or other impairments occurring on the line. This out-
put is only valid in the P and N rail mode of operation.
RAIS
6
O
TTL8mA
Receive Alarm Indication Signal: An active low
alarm occurs within one millisecond after the E2/E3F
detects an all ones condition, including in the pres-
-5
ence of a 10 bit error rate. An incoming signal with a
framing pattern and all ones in the data field is not
mistaken as an AIS.
RLOC
RLOF
7
8
O
O
TTL8mA
TTL8mA
Receive Loss of Clock: An active low alarm occurs
when there are no transitions in the received clock
(RCK/RCKL) for 10 clock cycles. Recovery occurs on
the first clock transition.
Receive Loss of Frame: An active low alarm occurs
when frame cannot be detected in the following
modes and conditions:
G.742: Four consecutive frames lost. Recovery
occurs when three consecutive frames are detected.
The framing pattern is 1111010000 (10-bit pattern).
G.745: Five consecutive frames lost. Recovery
occurs when two consecutive frames are detected.
The framing pattern is 11100110 (8-bit pattern).
G.751: Four consecutive frames lost. Recovery
occurs when three consecutive frames are detected.
The framing pattern is 1111010000 (10-bit pattern).
G.753: Three consecutive frames lost. Recovery
occurs when three consecutive frames are detected.
The framing pattern is 111110100000 (12-bit pattern).
FE
12
O
TTL8mA
Framing Error: An active high alarm occurs when
one or more framing bits are in error. The framing
error alarm occurs at the end of the framing pattern
and remains high until an error-free framing pattern is
received or a loss of frame occurs.
TLOC
25
60
O
O
TTL8mA
TTL8mA
Transmit Loss of Clock: An active low alarm occurs
when there are no transitions in the transmit clock
(TCK) for 10 clock cycles. Recovery occurs on the
first clock transition.
BIP-4E
BIP-4E: A positive pulse occurs when the comparison
between the received BIP-4 value and the calculated
value does not match in a column.
TXC-03701B-MB
Ed. 1, August 1995
- 13 -
E2/E3F
TXC-03701B
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Min *
Max *
Unit
Supply voltage
V
-0.3
-0.5
+7.0
V
V
DD
DC input voltage
V
V
+ 0.5
DD
IN
Continuous power dissipation
Ambient operating temperature
Operating junction temperature
Storage temperature range
P
1
Watts
C
o
T
-40
+85
150
150
C
A
o
T
C
J
o
T
-55
C
S
*Note: Operating conditions exceeding those listed in Absolute Maximum Ratings may cause permanent failure. Expo-
sure to absolute maximum ratings for extended periods may impair device reliability.
THERMAL CHARACTERISTICS
Parameter
Min
Typ
Max
Unit
Test Conditions
Thermal resistance -
o
junction to ambient
46
48
12
C/W
0 ft/min linear airflow
0 ft/min linear airflow
Thermal resistance -
junction to case
o
C/W
POWER REQUIREMENTS
Parameter
Min
Typ
Max
Unit
Test Conditions
V
4.75
5.0
5.25
125
675
V
DD
DD
I
mA
mW
DD
P
Inputs switching
THROUGHPUT DELAYS
E2
Path
Delay (bit times)
Rx line input to Rx terminal output
Tx terminal input to Tx line output
TBD
TBD
E3
Path
Delay (bit times)
Rx line input to Rx terminal output
Tx terminal input to Tx line output
TBD
TBD
TXC-03701B-MB
Ed. 1, August 1995
- 14 -
E2/E3F
TXC-03701B
INPUT, OUTPUT AND I/O PARAMETERS
INPUT PARAMETERS FOR TTLp
Parameter
Min
Typ
Max
Unit
Test Conditions
4.75 <V < 5.25
V
V
2.0
V
V
IH
IL
DD
0.8
4.75 <V < 5.25
DD
Input leakage current
Input capacitance
-70.0
4.0
µA
pF
Note: Input has a 72k (nominal) internal pull-up resistor.
OUTPUT PARAMETERS FOR TTL4mA
Parameter
Min
Typ
Max
Unit
Test Conditions
= 4.75; I = 4.0
V
V
2.4
V
V
V
V
OH
OL
DD
DD
OH
0.5
-4.0
4.0
= 4.75; I = -4.0
OL
I
I
t
t
mA
mA
ns
ns
OL
OH
1.2
1.7
C
C
= 15 pF
= 15 pF
RISE
FALL
LOAD
LOAD
OUTPUT PARAMETERS FOR TTL8mA
Parameter
Min
Typ
Max
Unit
Test Conditions
V
V
2.4
V
V
V
V
= 4.75; I = 8.0
OH
OH
OL
DD
DD
0.5
-8.0
8.0
= 4.75; I = -8.0
OL
I
I
t
t
mA
mA
ns
ns
OL
OH
2.0
1.9
C
C
= 15 pF
= 15 pF
RISE
FALL
LOAD
LOAD
OUTPUT PARAMETERS FOR TTL OPEN DRAIN
Parameter
Min
Typ
Max
Unit
Test Conditions
V
0.5
V
V
= 4.75; I = -8.0
DD OL
OL
I
t
-8.0
mA
ns
OL
FALL
11.0
C
= 15 pF
LOAD
Note: VOH, IOH and tRISE will depend on external resistance and capacitance.
TXC-03701B-MB
Ed. 1, August 1995
- 15 -
E2/E3F
TXC-03701B
INPUT/OUTPUT PARAMETERS FOR TTL I/O
Parameter
Min
Typ
Max
Unit
Test Conditions
4.75 <V < 5.25
V
V
2.0
V
V
IH
IL
DD
0.8
4.75 <V < 5.25
DD
Input leakage current
Input capacitance
-70.0
7.1
--
µA
pF
V
V
V
2.4
V
= 4.75; I = 8.0
DD OH
OH
OL
0.5
-8.0
8.0
V
V
= 4.75; I = -8.0
DD OL
I
I
t
t
mA
mA
ns
ns
OL
--
OH
3.3
7.9
C
C
= 15 pF
= 15 pF
RISE
FALL
LOAD
LOAD
TXC-03701B-MB
Ed. 1, August 1995
- 16 -
E2/E3F
TXC-03701B
TIMING CHARACTERISTICS
Detailed timing diagrams for the E2/E3F are illustrated in Figures 5 through 20, with values of the timing inter-
vals tabulated below the diagrams. All output times are measured with a maximum 75 pF load capacitance.
Timing parameters are measured at voltage levels of (V + V )/2 for input signals or (V + V )/2 for output
IH
IL
OH
OL
signals.
Figure 5. Line Side Receive NRZ Timing
t
CYC
t
t
PWH
PWL
RCKL
(Input)
t
SU
t
H
RDL
(Input)
E3
Parameter
Symbol
Min
Typ
Max
Unit
RCKL clock period
t
29.0
12.1
12.1
4.0
ns
ns
ns
ns
ns
CYC
RCKL high time
t
14.6
14.6
PWH
RCKL low time
t
PWL
RDL set-up time to RCKL↑
RDL hold time after RCKL↑
t
SU
t
4.0
H
E2
Parameter
Symbol
Min
Typ
Max
Unit
RCKL clock period
t
116.0
46.0
46.0
4.0
ns
ns
ns
ns
ns
CYC
RCKL high time
t
59.2
59.2
PWH
RCKL low time
t
PWL
RDL set-up time to RCKL↑
RDL hold time after RCKL↑
t
SU
t
4.0
H
TXC-03701B-MB
Ed. 1, August 1995
- 17 -
E2/E3F
TXC-03701B
Figure 6. Line Side Transmit NRZ Timing
t
CYC
t
t
PWL
PWH
TCK/TCKL
(Output)
Pin 50 high
or floating
t
D
TDL
(Output)
E3
Parameter
Symbol
Min
Typ
Max
Unit
TCKL clock period
TCKL high time
t
29.1
13.1
13.1
29.1
ns
ns
ns
ns
CYC
t
PWH
TCKL low time
t
PWL
TDL delay after TCKL↓
t
7.0
D
E2
Parameter
Symbol
Min
Typ
Max
Unit
TCKL clock period
TCKL high time
t
118.4
53.3
53.3
118.4
ns
ns
ns
ns
CYC
t
PWH
TCKL low time
t
PWL
TDL delay after TCKL↓
t
7.0
D
TXC-03701B-MB
Ed. 1, August 1995
- 18 -
E2/E3F
TXC-03701B
Figure 7. Line Side Receive Rail Timing
t
CYC
t
t
PWH
PWL
RCK
(Input)
t
t
SU
H
RP
RN
(Inputs)
E3
Parameter
Symbol
Min
Typ
Max
Unit
RCK clock period
t
29.0
12.1
12.1
4.0
ns
ns
ns
ns
ns
CYC
RCK high time
t
14.6
14.6
PWH
RCK low time
t
PWL
RP/RN set-up time to RCK↓
RP/RN hold time after RCK↓
t
SU
t
4.0
H
E2
Parameter
Symbol
Min
Typ
Max
Unit
RCK clock period
t
116.0
46.0
46.0
4.0
ns
ns
ns
ns
ns
CYC
RCK high time
t
59.2
59.2
PWH
RCK low time
t
PWL
RP/RN set-up time to RCK↓
RP/RN hold time after RCK↓
t
SU
t
4.0
H
TXC-03701B-MB
Ed. 1, August 1995
- 19 -
E2/E3F
TXC-03701B
Figure 8. Line Side Transmit Rail Timing
t
CYC
t
t
PWH
PWL
TCK
(Output)
Pin 50 low
t
t
PWL
PWH
TCK
(Output)
Pin 50 high
or floating
t
D
TP
TN
(Outputs)
E3
Parameter
Symbol
Min
Typ
Max
Unit
TCK clock period
TCK high time
TCK low time
t
29.1
13.1
13.1
29.1
ns
ns
ns
ns
CYC
t
16.0
16.0
7.0
PWH
t
PWL
TP/TN delay after TCK active edge
t
D
E2
Parameter
Symbol
Min
Typ
Max
Unit
TCK clock period
t
118.4
53.3
53.3
118.4
ns
ns
ns
ns
CYC
TCK high time
t
65.1
65.1
7.0
PWH
TCK low time
t
PWL
TP/TN delay after TCK active edge
t
D
TXC-03701B-MB
Ed. 1, August 1995
- 20 -
E2/E3F
TXC-03701B
Figure 9. Transmit Reference Generator Timing
t
CYC(1)
t
t
PWH(1)
PWL(1)
TCIN
(Input)
t
t
CYC(2)
D(1)
t
PWH(2)
TCOUT
(Output)
t
D(2)
TDOUT
(Output)
FRAMING PATTERN
TFOUT
(Output)
t
PW
TCG
(Output)
FRAMING PATTERN & SERVICE BITS
E3
Parameter
Symbol
Min
Typ
Max
Unit
TCIN clock period
TCIN high time
tCYC(1)
tPWH(1)
tPWL(1)
tCYC(2)
tPWH(2)
tD(1)
29.1
13.1
13.1
29.1
13.1
ns
ns
ns
ns
ns
ns
ns
ns
TCIN low time
TCOUT clock period
TCOUT high time
TCOUT↑ delay after TCIN↓
15.0
7.0
TDOUT, TFOUT, TCG delay after TCOUT↑
tD(2)
TFOUT pulse width
tPW
1 tCYC(1)
E2
Parameter
Symbol
Min
Typ
Max
Unit
TCIN clock period
tCYC(1)
tPWH(1)
tPWL(1)
tCYC(2)
tPWH(2)
tD(1)
118.4
53.3
53.3
118.4
53.3
118.4
ns
ns
ns
ns
ns
ns
ns
ns
TCIN high time
TCIN low time
TCOUT clock period
TCOUT high time
TCOUT↑ delay after TCIN↓
TDOUT, TFOUT, TCG delay after TCOUT↑
TFOUT pulse width
15.0
7.0
tD(2)
tPW
1 tCYC(1)
TXC-03701B-MB
Ed. 1, August 1995
- 21 -
E2/E3F
TXC-03701B
Figure 10. Terminal Side Receive Nibble Timing
t
CYC
t
t
PWH
PWL
RNC
(Output)
t
D(1)
RNIB(3-0)
(Output)
N260
N259
N258
N1
t
D(2)
t
PW
RNF
(Output)
This waveform diagram shows a G.745 frame with the BIP-4 feature off. The gapped clock period corresponds
to the 8-bit (two nibbles) framing pattern.
E2
Parameter
Symbol
Min
Typ
Max
Unit
RNC clock period
RNC high time
RNC low time
tCYC
tPWH
tPWL
tD(1)
tD(2)
tPW
473.0
213.0
213.0
ns
ns
ns
ns
ns
ns
ns
RNIB delay after RNC↑
RNF delay after RNC↑
RNF pulse width (G.745)
RNF pulse width (G.742)
7.0
7.0
947.0
tPW
1184.0
BIP-4 On
Number of Nibbles
Bip-4 Off
Number of Nibbles
Nibble Rate
k nibbles/s
Recommendation
G.742
G.745
G.751
G.753
208
259
380
531
209
260
381
532
2112
2112
8592
8592
E3
Parameter
Symbol
Min
Typ
Max
Unit
RNC clock period
tCYC
tPWH
tPWL
tD(1)
tD(2)
tPW
116.4
52.4
52.4
ns
ns
ns
ns
ns
ns
ns
RNC high time
RNC low time
RNIB delay after RNC↑
RNF delay after RNC↑
RNF pulse width (G.753)
RNF pulse width (G.751)
7.0
7.0
349.0
291.0
tPW
TXC-03701B-MB
Ed. 1, August 1995
- 22 -
E2/E3F
TXC-03701B
Figure 11. Terminal Side Transmit Nibble Timing
t
CYC
XNC
(Output)
(BIP-4 on)
t
t
PWH
PWL
XNC
(Output)
(BIP-4 off)
t
SU
t
H
XNIB(3-0)
(Input)
N260
N1
N2
t
OD
XNF
(Output)
(BIP-4 on)
t
+ t
CYC
PW
t
OD
XNF
(Output)
(BIP-4 off)
t
PW
This waveform diagram shows a G.745 frame with the BIP-4 feature on and off. The gapped clock period cor-
responds to the 8-bit (two nibbles) framing pattern.
E2
Parameter
Symbol
Min
Typ
Max
Unit
XNC clock period
XNC high time
XNC low time
tCYC
tPWH
tPWL
tSU
473.0
213.0
213.0
4.0
ns
ns
ns
ns
ns
ns
ns
ns
XNIB set-up time to XNC↑
XNIB hold time after XNC↑
tH
4.0
XNF output delay after XNC↑
XNF pulse width (BIP-4 off, G.745)
XNF pulse width (BIP-4 off, G.742)
tOD
4.0
tPW
tPW
947.0
1184.0
E3
Parameter
Symbol
Min
Typ
Max
Unit
XNC clock period
tCYC
tPWH
tPWL
tSU
116.4
52.4
52.4
4.0
ns
ns
ns
ns
ns
ns
ns
ns
XNC high time
XNC low time
XNIB set-up time to XNC↑
XNIB hold time after XNC↑
XNF output delay after XNC↑
XNF pulse width (BIP-4 off, G.753)
XNF pulse width (BIP-4 off, G.751)
tH
4.0
tOD
4.0
tPW
tPW
349.0
291.0
TXC-03701B-MB
Ed. 1, August 1995
- 23 -
E2/E3F
TXC-03701B
Figure 12. Terminal Side Receive Serial Timing
BIT 1056
Set III
One G.745 Frame
Set II
Framing Pattern
RSD
(Output)
1
2
3
4
5
6
7
8
5
6
7
8
5
6
7
8
1
2
3
RSC
(Output)
RCG
(Output)
RSF
(Output)
t
CYC
t
t
PWH
PWL
RSC
t
D
RSD
RCG
RSF
E3
Parameter
Symbol
Min
Typ
Max
Unit
RSC clock period
RSC high time
RSC low time
t
29.0
11.5
11.5
29.1
ns
ns
ns
ns
CYC
t
PWH
t
PWL
RSD, RCG, RSF delay after RSC↑
t
7.0
D
E2
Parameter
Symbol
Min
Typ
Max
Unit
RSC clock period
t
116.0
46.0
46.0
118.4
ns
ns
ns
ns
CYC
RSC high time
t
PWH
RSC low time
t
PWL
RSD, RCG, RSF delay after RSC↑
t
7.0
D
TXC-03701B-MB
Ed. 1, August 1995
- 24 -
E2/E3F
TXC-03701B
Figure 13. Terminal Side Transmit Serial Timing
One G.745 Frame
BIT 1056
XSD
(Input)
3
1
2
3
1
2
XCK
(Input)
XSF
(Input)
t
CYC
t
t
PWH
PWL
XCK
t
SU
t
H
XSD
XSF
E3
Parameter
Symbol
Min
Typ
Max
Unit
XCK clock period
t
29.1
13.1
13.1
4.0
ns
ns
ns
ns
ns
CYC
XCK high time
t
PWH
XCK low time
t
PWL
XSD, XSF set-up time to XCK↓
XSD, XSF hold time after XCK↓
t
SU
t
4.0
H
E2
Parameter
Symbol
Min
Typ
Max
Unit
XCK clock period
t
118.4
53.3
53.3
4.0
ns
ns
ns
ns
ns
CYC
XCK high time
t
PWH
XCK low time
t
PWL
XSD, XSF set-up time to XCK↓
XSD, XSF hold time after XCK↓
t
SU
t
4.0
H
TXC-03701B-MB
Ed. 1, August 1995
- 25 -
E2/E3F
TXC-03701B
Figure 14. G.742/G.751 Service Bit Receive Timing
ROD
(Output)
11
12
t
D
t
t
PWH
t
ROC
(Output)
CYC
t
PWL
PW
ROF
(Output)
First bit in frame
G.751 (E3)
Parameter
Symbol
Min
Typ
Max
Unit
ROC clock period
ROC high time
t
29.0
11.0
11.0
11.0
29.1
ns
ns
ns
ns
ns
CYC
t
PWH
ROC low time
t
PWL
ROF pulse width
ROD delay after ROC↑
t
PW
t
7.0
D
G.742 (E2)
Parameter
Symbol
Min
Typ
Max
Unit
ROC clock period
ROC high time
t
116.0
46.0
46.0
46.0
118.4
ns
ns
ns
ns
ns
CYC
t
PWH
ROC low time
t
PWL
ROF pulse width
ROD delay after ROC↑
t
PW
t
7.0
D
TXC-03701B-MB
Ed. 1, August 1995
- 26 -
E2/E3F
TXC-03701B
Figure 15. G.745/G.753 Service Bit Receive Timing
SET II
SET III
ROD
(Output)
8
5
6
7
5
6
7
8
t
CYC
t
D
t
PWH
ROC
(Output)
t
PWL
t
PW
ROF
(Output)
First bit in frame
G.753 (E3)
Parameter
Symbol
Min
Typ
Max
Unit
ROC clock period
ROC high time
t
29.0
11.0
11.0
11.0
29.1
ns
ns
ns
ns
ns
CYC
t
PWH
ROC low time
t
PWL
ROF pulse width
ROD delay after ROC↑
t
PW
t
7.0
D
G.745 (E2)
Parameter
Symbol
Min
Typ
Max
Unit
ROC clock period
ROC high time
t
116.0
46.0
46.0
46.0
118.4
ns
ns
ns
ns
ns
CYC
t
PWH
ROC low time
t
PWL
ROF pulse width
ROD delay after ROC↑
t
PW
t
7.0
D
TXC-03701B-MB
Ed. 1, August 1995
- 27 -
E2/E3F
TXC-03701B
Figure 16. G.742/G.751 Service Bit Transmit Timing
TOD
(Input)
11
12
t
t
SU
CYC
t
H
TOC
(Output)
t
PWH
t
PWL
t
PW
TOF
(Output)
First bit in frame
G.751 (E3)
Parameter
Symbol
Min
Typ
Max
Unit
TOC clock period
TOC high time
t
29.1
13.1
13.1
11.0
4.0
ns
ns
ns
ns
ns
ns
CYC
t
PWH
TOC low time
t
PWL
TOF pulse width
t
PW
TOD set-up time to TOC↑
TOD hold time after TOC↑
t
SU
t
4.0
H
G.742 (E2)
Parameter
Symbol
Min
Typ
Max
Unit
TOC clock period
TOC high time
t
118.4
53.3
53.3
46.0
4.0
ns
ns
ns
ns
ns
ns
CYC
t
PWH
TOC low time
t
PWL
TOF pulse width
t
PW
TOD set-up time to TOC↑
TOD hold time after TOC↑
t
SU
t
4.0
H
TXC-03701B-MB
Ed. 1, August 1995
- 28 -
E2/E3F
TXC-03701B
Figure 17. G.745/G.753 Service Bit Transmit Timing
SET III
SET II
t
H
t
SU
TOD
(Input)
5
6
7
8
5
6
7
8
t
CYC
TOC
(Output)
t
PWH
t
t
PWL
PW
TOF
(Output)
First bit in frame
G.753 (E3)
Parameter
Symbol
Min
Typ
Max
Unit
TOC clock period
TOC high time
TOC low time
t
29.1
13.1
13.1
11.0
4.0
ns
ns
ns
ns
ns
ns
CYC
t
PWH
t
PWL
TOF pulse width
t
PW
TOD set-up time after TOC↑
TOD hold time to TOC↑
t
SU
t
4.0
H
G.745 (E2)
Parameter
Symbol
Min
Typ
Max
Unit
TOC clock period
TOC high time
t
118.4
53.3
53.3
46.0
4.0
ns
ns
ns
ns
ns
ns
CYC
t
PWH
TOC low time
t
PWL
TOF pulse width
t
PW
TOD set-up time after TOC↑
TOD hold time to TOC↑
t
SU
t
4.0
H
TXC-03701B-MB
Ed. 1, August 1995
- 29 -
E2/E3F
TXC-03701B
Figure 18. BIP-4 Error Timing
t
PWL(1)
t
PWH(1)
RCK/RCKL
(Input)
t
D
t
PWH(2)
BIP-4E
(Output)
Column one in BIP-4 calculation/comparison is in error when it is high
E3
Parameter
Symbol
Min
Typ
Max
Unit
RCK/RCKL high time
RCK/RCKL low time
t
12.1
12.1
14.6
14.6
ns
ns
ns
ns
PWH(1)
t
PWL(1)
BIP-4E delay after RCK/RCKL↓
t
7.0
D
BIP-4E high time
t
11.0
PWH(2)
E2
Parameter
Symbol
Min
Typ
Max
Unit
RCK/RCKL high time
RCK/RCKL low time
t
46.0
46.0
59.2
59.2
ns
ns
ns
ns
PWH(1)
t
PWL(1)
BIP-4E delay after RCK/RCKL↓
BIP-4E high time
t
7.0
D
t
46.0
PWH(2)
TXC-03701B-MB
Ed. 1, August 1995
- 30 -
E2/E3F
TXC-03701B
Figure 19. Microprocessor Read Cycle
tPW(1)
tW(1)
ALE
tH(2)
tSU(1)
tOD(1)
tH(1)
ADDESS
VALID
DATA
VALID
AD (7-0)
tW(5)
tOD(2)
tW(3)
tSU(2)
SEL
RD
tW(2)
tPW(2)
tW(4)
tD
tPW(3)
RDY
-t/RC
VDD (1-e
) (Note 1)
Parameter
Symbol
Min
Typ
Max
Unit
ALE pulse width
t
20.0
25.0
10.0
10.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PW(1)
ALE wait time after RD↑
Address set-up time to ALE↓
Address hold time after ALE↓
Address hold time after RD↓
t
W(1)
t
SU(1)
t
t
H(1)
H(2)
Data output delay (to tristate) after RD↑
Data output delay after RD↓ (Notes 2, 4)
SEL set-up time to RD↓
t
t
10.0
90.0
OD(1)
OD(2)
2
t
+ 20.0
CYC
t
20.0
SU(2)
RD pulse width (Notes 2, 3)
RD wait time after ALE↓
t
2
t
+ 3.0
CYC
PW(2)
t
t
20.0
W(2)
W(3)
SEL wait time after RD↑
5.0
3.0
RDY delay after RD↓ (Note 2)
RDY pulse width (Notes 2, 4)
RD wait time after RDY↑
t
t
+12
CYC
D
t
2
t
3
t
CYC
PW(3)
CYC
t
t
0.0
W(4)
W(5)
SEL wait time after ALE↓
10.0
Note 1: Open drain rise time is dependent upon external load resistance (R) and capacitance (C).
Note 2: tCYC is the period of the line interface clock used (E2 or E3).
Note 3: At least 10 clock cycles of XCK must occur after reset before a read cycle is valid.
Note 4: Output data is valid when RDY is released from low level at end of tPW(3)
.
TXC-03701B-MB
Ed. 1, August 1995
- 31 -
E2/E3F
TXC-03701B
Figure 20. Microprocessor Write Cycle
tPW(1)
tW(1)
ALE
tH(1)
tH(2)
tSU(2)
tSU(1)
ADDESS
VALID
DATA
VALID
AD (7-0)
SEL
tW(5)
tSU(3)
tW(3)
tW(2)
WR
tPW(2)
tW(4)
tD
RDY
tPW(3)
-t/RC
VDD (1-e
) (Note 1)
Parameter
Symbol
Min
Typ
Max
Unit
ALE pulse width
t
20.0
25.0
10.0
10.0
10.0
10.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PW(1)
ALE wait time after WR↑
t
W(1)
Address set-up time to ALE↓
Address hold time after ALE↓
Data set-up time to WR↑
Data hold time after WR↑
WR pulse width (Notes 2, 3)
WR wait time after ALE↓
SEL set-up time to WR↓
SEL wait time after WR↑
t
SU(1)
t
H(1)
t
SU(2)
t
H(2)
t
2
t
+ 3.0
PW(2)
CYC
t
20.0
W(2)
t
20.00
5.0
SU(3)
t
W(3)
RDY delay time after WR↓ (Note 2)
RDY pulse width (Note 2)
WR wait time after RDY↑
t
3.0
t
+12
CYC
D
t
2
t
3
t
CYC
PW(3)
CYC
t
t
0.0
W(4)
SEL wait time after ALE↓
10.0
W(5)
Note 1: Open drain rise time is dependent upon external load resistance (R) and capacitance (C).
Note 2: tCYC is the period of the line interface clock used (E2 or E3).
Note 3: At least 10 clock cycles of XCK must occur after reset before a write cycle is valid.
TXC-03701B-MB
Ed. 1, August 1995
- 32 -
E2/E3F
TXC-03701B
OPERATION
POWER SUPPLY CONNECTIONS
The E2/E3F has four supply pins that provide
internal power distribution. A VDD pin must be
connected to a single +5 volt power supply, as
shown in Figure 21. It is recommended that 0.1
microfarad ceramic disk capacitors be used for
decoupling each of the supply pins, and that the
decoupling capacitors be connected in close
proximity to the E2/E3F. In addition, a 10 micro-
farad 6.3v tantalum capacitor should be con-
nected between +5 volt and ground.
1
+5V
18
GND
GND
GND
GND
VDD
VDD
VDD
VDD
+
0.1
0.1
0.1
0.1
10/6.3v
34
17
35
52
68
51
Figure 21. Power Supply Connections
MEMORY MAP
Address
(Hex)
Mode*
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
2
3
4
5
6
7
R/W
R
M1
M0
SER
TAIS
BIP-4
TLBK
PLBK
OHI/O
CODING VIOLATION COUNTER
RAIS TLOC --
R
RLOF
RLOC
--
--
--
R
BIP-4 ERROR COUNTER
--
R/W
R
BIP-4 ERROR MASK
--
--
FRSRCH
ROH8
TOH8
--
ROH5/11 ROH6/12
ROH7
TOH7
RAIS
ROH8
TOH8
TLOC
ROH5
TOH5
--
ROH6
TOH6
--
ROH7
TOH7
--
R/W
R(L)
TOH5/11
RLOF
TOH6/12
RLOC
*R/W: Read/write; R: Read only; R(L): Read only - latched register. Unused bit positions in R/W addresses should be writ-
ten to 0.
TXC-03701B-MB
Ed. 1, August 1995
- 33 -
E2/E3F
TXC-03701B
MEMORY MAP DESCRIPTIONS
CONTROL REGISTERS
Address* Bit Symbol
Description
0
7
6
M1
M0
Mode Control: The two controls select the operating rate of the E2/E3F according
to the table given below:
M1
0
M0
0
Recommendation
G.745
Rate (kbit/s)
8448
0
1
G.742
8448
1
0
G.753
34368
1
1
G.751
34368
5
4
3
SER Serial Interface: A one written into this bit location selects the bit-serial interface
for the terminal side I/O. A zero selects the nibble-parallel interface.
TAIS Transmit Alarm Indication Signal: A one written into this bit location causes an
all ones signal (AIS) to be sent in place of a G.7XX frame format.
BIP-4 Bit Interleaved Parity-4 Alarm: A one written into this location enables the BIP-4
function. In the transmit direction, the BIP-4 is calculated for data nibbles only, and
is sent as the last four bits in the transmitted frame format. In the receive direction,
the BIP-4 is calculated for the data bits only and compared against the last four
bits of the frame (BIP-4). An output indication (BIP-4E) occurs when one or more
columns do not match. At the terminal interface, the transmit and receive nibble
clocks are gapped during the BIP-4 time.
2
TLBK Terminal Loopback: A one written into this location disables the receive line side
input and causes the transmit line output to be looped back as the receive line
input. To avoid contention between the loopback control lead, which is not dis-
abled in the microprocessor mode, and the memory map control bit, the following
truth table is used.
TLBK
Control Lead
low
TLBK
Control Bit
Don’t Care
Terminal
Loopback
On
high
high
1
0
On
Off
1
PLBK Payload Loopback: PLBK is valid only in the serial mode. A one written into this
location disables the terminal side transmit data input, and causes the terminal
receive data output to be looped back as the transmit terminal data input in the
serial mode only. To avoid contention between the loopback control lead, which is
not disabled in the microprocessor mode, and the memory map control bit, the fol-
lowing truth table is used. A payload loopback is also known as a line loopback.
PLBK
Control Lead
low
PLBK
Control Bit
Don’t Care
Payload
Loopback
On
high
high
1
0
On
Off
0
OHI/O Service (Overhead) Bit I/O Selection: A one written into this location enables the
external service bit interface (TOD). A zero written into this location disables the
external service bit interface (TOD), and enables service bits written into Address
6H as the transmitted service bits.
* All Addresses are hexadecimal.
TXC-03701B-MB
Ed. 1, August 1995
- 34 -
E2/E3F
TXC-03701B
COUNTERS, STATUS BITS AND SERVICE BITS
Address Bit
Symbol
Description
1
7-0
Coding Violation Counter: This saturating counter counts the number of
illegal coding violations. Its count is valid only when operating in the P and N
rail mode. Bit 7 is the most significant bit. The counter resets to zero upon
completion of a microprocessor read cycle.
2
7
RLOF
Receive Loss of Frame (Unlatched): For G.742, RLOF occurs when four
consecutive frames are lost. Recovery occurs when three consecutive
frames are detected. The framing pattern is: 1111010000. For G.745, RLOF
occurs when five consecutive frames are lost. Recovery occurs when two
consecutive frames are detected. The framing pattern is 11100110. For
G.751, RLOF occurs when four consecutive frames are lost. Recovery
occurs when three consecutive frames are detected. The framing pattern is
1111010000. For G.753, RLOF occurs when three consecutive frames are
lost. Recovery occurs when three consecutive frames are detected. The
framing pattern is: 111110100000.
6
5
RLOC
RAIS
Receive Loss of Clock (Unlatched): An alarm occurs when no transitions
are detected in the received clock (RCK/RCKL) for 10 clock cycles. Recovery
occurs on the first clock transition.
Receive Alarm Indication Signal (Unlatched): An alarm occurs when an all
ones condition is detected in the receive data, including in the presence of a
-5
10 error rate.
4
TLOC
Transmit Loss of Clock (Unlatched): An alarm occurs when no transitions
are detected in the transmit clock (XCK) for 10 clock cycles. Recovery occurs
on the first clock transition.
3
4
7-0
BIP-4 Error Counter: This saturating counter counts the number of BIP-4
errors that have occurred in the comparison between the received BIP-4
value and the calculated value. Bit 7 is the most significant bit. The counter
resets to zero upon completion of a microprocessor read cycle.
7-4
BIP-4 Error Mask: A one written to one or more bits causes those BIP-4 val-
ues to be inverted from their calculated value, and transmitted continuously.
Bit 7 represents the first BIP-4 value transmitted in the frame, while bit 4 rep-
resents the last BIP-4 value transmitted in the frame. To stop the transmis-
sion of errors, the microprocessor must write zeros to the appropriate mask
positions again.
0
FRSRCH Frame Search: A one written to this control bit causes one clock slip in the
framer detection circuit, which forces the framer out of frame intentionally and
forces the framer to search for a new valid frame. A zero must be written to
this location before a subsequent frame search is issued.
5
7-0
ROHn
Receive Overhead (Service Bits): ROH5/11 and ROH6/12 in bits 7 and 6
are the received bits which correspond to bits 11 and 12 in received G.742
and G.751 frame formats. ROH5/11 - ROH8 in bits 7-4 correspond to bits 5-8
in Set II in the G.745 and G.753 frame formats. ROH5-ROH8 in bits 3-0 cor-
respond to bits 5-8 in Set III in the G.745 and G.753 frame formats.
TXC-03701B-MB
Ed. 1, August 1995
- 35 -
E2/E3F
TXC-03701B
Address Bit
Symbol
Description
6
7-0
TOHn
Transmit Overhead (Service) Bits: TOH5/11 and TOH6/12 in bits 7 and 6
correspond to bits 11 and 12 in the G.742 and G.751 frame formats. TOH5/
11-TOH8 in bits 7-4 correspond to bits 5-8 in Set II in the G.745 and G.753
frame formats. TOH5-TOH8 in bits 3-0 correspond to bits 5-8 in Set III in the
G.745 and G.753 frame formats. The transmission of the service bits in this
location is enabled by writing a zero to bit 0 (OHI/O) in Address 0H.
7
7-4
Latched Alarm Bits: The bits in this location correspond to the bits in loca-
tion 02H, except that the bits are latched on with an alarm. A microprocessor
read cycle clears the latched bit positions. If an alarm remains active during a
read cycle, the bit re-latches.
TXC-03701B-MB
Ed. 1, August 1995
- 36 -
E2/E3F
TXC-03701B
PACKAGE INFORMATION
The E2/E3F is available in a 68-pin plastic leaded chip carrier suitable for surface or socket mounting, as
shown in Figure 22.
.990 SQ.
.953 SQ.
.800 SQ.
.170
.149
.075
0.050
typ.
61
1
9
9
1
61
60
10
60
10
TRANSWITCH
0.017
typ.
44
26
26
44
27
43
27
43
TOP VIEW
BOTTOM VIEW
Note: All dimensions are in inches and are nominal unless otherwise indicated.
Figure 22. E2/E3F TXC-03701B 68-Pin Plastic Leaded Chip Carrier
TXC-03701B-MB
Ed. 1, August 1995
- 37 -
E2/E3F
TXC-03701B
ORDERING INFORMATION
Part Number: TXC-03701-BIPL
68-pin plastic leaded chip carrier
RELATED PRODUCTS
TXC-02050, MRT Multi-Rate Line Interface device. The MRT directly interfaces with the
E2/E3F and provides the functions for terminating ITU-TSS-specified 8448 kbit/s (E2) and
34368 kbit/s (E3) line rate signals, or 6312 kbit/s (JT2) line signals specified in the Japanese
NTT Technical Reference for High Speed Digital Leased Circuits. An optional HDB3 codec is
provided for the two ITU-TSS line rates.
TXC-05101C, HDLC VLSI Device (HDLC Controller). Provides an interface to packet.
Performs flag generation/detection, zero insertion/deletion, abort detection and byte framing.
TXC-05501, SARA-S VLSI Device (ATM/SMDS Segmentation Controller). Simultaneously
segments up to 8000 packets into ATM/SMDS cells using AAL3/4/5.
TXC-05601, SARA-R VLSI Device (ATM/SMDS Reassembly Controller). Simultaneously
reassembles ATM/SMDS cells back into up to 8000 packets using AAL3/4/5.
TXC-06125, XBERT VLSI Device (Bit Error Rate Generator Receiver). Programmable multi-
rate test pattern generator and receiver in a single chip with serial, nibble, or byte interface
capability.
TXC-21037, E2/E3F-MRT Evaluation Board. A complete ready-to-use single board that
demonstrates the functions and features of the E2/E3F and MRT Line Interface VLSI devices.
Includes on-board microprocessor, RS-232 interface, and MS-DOS compatible PC software.
The PC software provides full access to the E2/E3F VLSI device for control and monitoring.
TXC-03701B-MB
Ed. 1, August 1995
- 38 -
E2/E3F
TXC-03701B
STANDARDS DOCUMENTATION SOURCES
Telecommunication technical standards and reference documentation may be obtained
from the following organizations:
ANSI (U.S.A.):
American National Standards Institute (ANSI)
11 West 42nd Street
New York, New York 10036
Tel: 212-642-4900
Fax: 212-302-1286
Bellcore (U.S.A.):
Bellcore
Attention - Customer Service
8 Corporate Place
Piscataway, NJ 08854
Tel: 800-521-CORE (In U.S.A.)
Tel: 908-699-5800
Fax: 908-336-2559
IEEE (U.S.A.)
The Institute of Electrical and Electronics Engineers, Inc.
Customer Service Department
445 Hoes Lane
P. O. Box 1331
Piscataway, NJ 08855-1331
Tel: 800-701-4333 (In U.S.A.)
Tel: 908-981-0060
Fax: 908-981-9667
ITU-TSS (International):
Publication Services of International Telecommunication Union (ITU)
Telecommunication Standardization Sector (TSS)
Place des Nations
CH 1211
Geneve 20, Switzerland
Tel: 41-22-730-5285
Fax: 41-22-730-5991
TTC (Japan):
TTC Standard Publishing Group of the
Telecommunications Technology Committee
2nd Floor, Hamamatsucho - Suzuki Building,
1 2-11, Hamamatsu-cho, Minato-ku, Tokyo
Tel: 81-3-3432-1551
Fax: 81-3-3432-1553
TXC-03701B-MB
Ed. 1, August 1995
- 39 -
E2/E3F
TXC-03701B
- NOTES -
TXC-03701B-MB
Ed. 1, August 1995
- 40 -
E2/E3F
TXC-03701B
- NOTES -
TranSwitch reserves the right to make changes to the product(s) or
circuit(s) described herein without notice. No liability is assumed as a
result of their use or application. TranSwitch assumes no liability for
TranSwitch applications assistance, customer product design, soft-
ware performance, or infringement of patents or services described
herein. Nor does TranSwitch warrant or represent that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TranSwitch cov-
ering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
TXC-03701B-MB
Ed. 1, August 1995
- 41 -
TranSwitch VLSI:
Powering Communication Innovation
TranSwitch Corporation 8 Progress Drive Shelton, CT 06484 USA Tel: 203-929-8810 Fax: 203-926-9453
•
•
•
•
•
- 42 -
E2/E3F
TXC-03701B
DOCUMENTATION UPDATE REGISTRATION FORM
If you would like be added to our database of customers who have registered to receive updated documenta-
tion for this device as it becomes available, please provide your name and address below, and fax or mail this
page to Mary Koch at TranSwitch. Mary will ensure that relevant Product Information Sheets, Data Sheets,
Application Notes and Technical Bulletins are sent to you.
Please print or type the information requested below, or attach a business card.
Name: ________________________________________________________________________
Title: _________________________________________________________________________
Company: _____________________________________________________________________
Dept./Mailstop: ________________________________________________________________
Street: _______________________________________________________________________
City/State/Zip: _________________________________________________________________
If located outside U.S.A., please add - Postal Code: ___________ Country: ______________
Telephone:______________________________________________ Ext.: _________________
Fax: __________________________________ E-Mail: _______________________________
Purchasing Dept. Location: _______________________________________________________
Please describe briefly your intended application for this device, and indicate whether you would
care to have a TranSwitch applications engineer contact you to provide assistance:
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
If you are also interested in receiving updated documentation for other TranSwitch device types,
please list them below rather than submitting separate registration forms:
__________
__________
__________
__________
__________
__________
Please fax this page to Mary Koch at (203) 926-9453 or fold, tape and mail it (see other side)
TXC-03701B-MB
Ed. 1, August 1995
- 43 -
TranSwitch VLSI:
Powering Communication Innovation
(Fold back on this line second, then tape closed, stamp and mail.)
First
Class
Postage
Required
TranSwitch Corporation
Attention: Mary Koch
8 Progress Drive
Shelton, CT 06484
U.S.A.
(Fold back on this line first.)
Please complete the registration form on this back cover sheet, and fax or mail it, if you
wish to receive updated documentation on this TranSwitch product as it becomes avail-
able.
TranSwitch Corporation 8 Progress Drive Shelton, CT 06484 USA Tel: 203-929-8810 Fax: 203-926-9453
•
•
•
•
•
相关型号：
©2020 ICPDF网 联系我们和版权申明