SI2392ADS-T1-GE3 [VISHAY]
Small Signal Field-Effect Transistor, 3.1A I(D), 100V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-236AB, HALOGEN FREE AND ROHS COMPLIANT, TO-236, 3 PIN;
| 型号： | SI2392ADS-T1-GE3 |
| 厂家： | 
VISHAY |
| 描述： | Small Signal Field-Effect Transistor, 3.1A I(D), 100V, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-236AB, HALOGEN FREE AND ROHS COMPLIANT, TO-236, 3 PIN 开关 光电二极管 晶体管 |
| 文件： | 总10页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si2392ADS
Vishay Siliconix
www.vishay.com
N-Channel 100 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
• TrenchFET® power MOSFET
• 100 % Rg and UIS tested
• Material categorization:
For definitions of compliance please see
www.vishay.com/doc?99912
ID (A) a
3.1
VDS (V)
RDS(on) (Ω) MAX.
Qg (TYP.)
0.126 at VGS = 10 V
0.144 at VGS = 6 V
0.189 at VGS = 4.5 V
100
2.9
2.9 nC
2.6
SOT-23 (TO-236)
D
APPLICATIONS
• DC/DC converters / boost converters
• Load switch
D
3
• LED backlighting in LCD TVs
G
• Power management for mobile
2
S
computing
S
1
G
N-Channel MOSFET
Top View
Marking Code: G2
Ordering Information:
Si2392ADS-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
100
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
V
VGS
20
T
T
C = 25 °C
C = 70 °C
3.1
2.5
Continuous Drain Current (TJ = 150 °C)
ID
TA = 25 °C
TA = 70 °C
2.2 b, c
1.8 b, c
8
A
Pulsed Drain Current (t = 300 μs)
IDM
IS
T
C = 25 °C
2.1
1 b, c
Continuous Source-Drain Diode Current
TA = 25 °C
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
IAS
3
L = 0.1 mH
EAS
0.45
2.5
mJ
W
T
T
C = 25 °C
C = 70 °C
1.6
Maximum Power Dissipation
PD
TA = 25 °C
TA = 70 °C
1.25 b, c
0.8 b, c
-55 to 150
Operating Junction and Storage Temperature Range
TJ, Tstg
°C
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient b, d
SYMBOL
RthJA
TYPICAL
MAXIMUM
UNIT
t ≤ 5 s
Steady State
75
40
100
50
°C/W
Maximum Junction-to-Foot (Drain)
RthJF
Notes
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 166 °C/W.
S14-0909-Rev. A, 28-Apr-14
Document Number: 62960
1
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2392ADS
Vishay Siliconix
www.vishay.com
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
VDS
ΔVDS/TJ
ΔVGS(th)/TJ
VGS(th)
VGS = 0 V, ID = 250 μA
ID = 250 μA
Drain-Source Breakdown Voltage
100
-
-
V
VDS Temperature Coefficient
-
-
59
-
mV/°C
VGS(th) Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
-4.8
-
3
VDS = VGS, ID = 250 μA
1.2
-
-
V
IGSS
VDS = 0 V, VGS
=
20 V
-
100
1
nA
VDS = 100 V, VGS = 0 V
VDS = 100 V, VGS = 0 V, TJ = 55 °C
VDS ≥ 5 V, VGS = 10 V
-
-
-
IDSS
Zero Gate Voltage Drain Current
On-State Drain Current a
μA
A
-
10
ID(on)
5
-
-
-
VGS = 10 V, ID = 2 A
0.102
0.120
0.135
5
0.126
0.144
0.189
-
Drain-Source On-State Resistance a
RDS(on)
VGS = 6 V, ID = 1 A
-
Ω
V
GS = 4.5 V, ID = 1 A
-
Forward Transconductance a
Dynamic b
gfs
VDS = 20 V, ID = 2 A
-
S
Ciss
Coss
Crss
Input Capacitance
-
-
196
67
14
5.2
2.9
1
-
-
VDS = 50 V, VGS = 0 V, f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
pF
-
-
V
DS = 50 V, VGS = 10 V, ID = 2.2 A
VDS = 50 V, VGS = 4.5 V, ID = 2.2 A
f = 1 MHz
-
10.4
5.8
-
Qg
Total Gate Charge
-
nC
Qgs
Qgd
Rg
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
-
-
1.4
4.3
40
68
14
20
8
-
0.9
-
8.6
60
102
21
30
16
20
20
14
Ω
td(on)
tr
td(off)
tf
td(on)
tr
td(off)
tf
-
VDD = 50 V, RL = 27.7 Ω
ID = 1.8 A, VGEN = 4.5 V, Rg = 1 Ω
Turn-Off Delay Time
Fall Time
-
-
ns
Turn-On Delay Time
Rise Time
-
-
10
10
7
VDD = 50 V, RL = 27.7 Ω
ID = 1.8 A, VGEN = 10 V, Rg = 1 Ω
Turn-Off Delay Time
Fall Time
-
-
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulse Diode Forward Current a
Body Diode Voltage
IS
ISM
VSD
trr
TC = 25 °C
IS = 1.8 A
-
-
-
-
-
-
-
-
-
2.1
8
A
0.8
23
21
17
6
1.2
35
32
-
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Reverse Recovery Fall Time
ns
nC
Qrr
ta
IF = 1.8 A, dI/dt = 100 A/μs,
TJ = 25 °C
ns
tb
Reverse Recovery Rise Time
-
Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S14-0909-Rev. A, 28-Apr-14
Document Number: 62960
2
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2392ADS
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1
8
6
4
2
0
VGS = 10 V thru 5 V
VGS = 4.5 V
0.8
0.6
0.4
0.2
0
VGS = 4 V
TC = 25 °C
TC = 125 °C
VGS = 3 V
TC = - 55 °C
0
0.5
1
1.5
2
0
1
2
3
4
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
280
210
140
70
0.21
0.17
0.13
0.09
0.05
Ciss
VGS = 4.5 V
VGS = 6 V
VGS = 10 V
Coss
Crss
0
0
2
4
6
8
0
20
40
60
80
100
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current and Gate Voltage
Capacitance
2
1.7
1.4
1.1
0.8
0.5
10
VGS = 10 V, 2 A
ID = 2.2 A
8
6
4
2
0
VDS = 25 V
VGS = 4.5 V, 1 A
VDS = 80 V
VGS = 6 V, 1 A
0
1.5
3
4.5
6
- 50 - 25
0
25
50
75
100 125 150
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 62960
S14-0909-Rev. A, 28-Apr-14
3
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2392ADS
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.35
100
10
1
ID = 2 A
0.28
0.21
0.14
0.07
0
TJ = 125 °C
TJ = 150 °C
TJ = 25°C
TJ = 25 °C
0.1
2
4
6
8
10
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VSD - Source-to-Drain Voltage (V)
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
2.8
2.5
2.2
1.9
1.6
10
8
6
ID = 250 μA
4
2
T = 25 °C
A
0
- 50 - 25
0
25
50
75
100 125 150
0.01
0.1
1
10
100
1000
TJ - Temperature (°C)
Time (s)
Single Pulse Power
Threshold Voltage
100
Limited by RDS(on)
*
Limited by IDM
10
1
100 μs
1 ms
10 ms
0.1
100 ms
10 s, 1s
DC
0.01
0.001
BVDSS Limited
TA = 25 °C
Single Pulse
0.1
1
10
100
1000
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
S14-0909-Rev. A, 28-Apr-14
Document Number: 62960
4
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2392ADS
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3.5
2.8
2.1
1.4
0.7
0
0
25
50
75
100
125
150
TC - Case Temperature (°C)
Current Derating*
3
2.4
1.8
1.2
0.6
0
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
TA - Ambient Temperature (°C)
TC - Case Temperature (°C)
Power, Junction-to-Foot
Power, Junction-to-Ambient
* The power dissipation PD is based on TJ (max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the
package limit.
S14-0909-Rev. A, 28-Apr-14
Document Number: 62960
5
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si2392ADS
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1
Duty Cycle = 0.5
0.2
0.1
0.1
Notes:
P
DM
0.05
t
1
0.02
t
2
t
t
1
2
1. Duty Cycle, D =
2. Per Unit Base = R
= 166 °C/W
thJA
(t)
= P
Z
3. T - T
A
DM thJA
JM
4. Surface Mounted
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
100
1000
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62960.
S14-0909-Rev. A, 28-Apr-14
Document Number: 62960
6
For technical questions, contact: pmostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
SOT-23 (TO-236): 3-LEAD
b
3
E
1
E
1
2
e
S
e
1
D
0.10 mm
0.004"
C
C
0.25 mm
q
A
2
A
Gauge Plane
Seating Plane
Seating Plane
C
A
1
L
L
1
MILLIMETERS
INCHES
Dim
Min
0.89
0.01
Max
1.12
0.10
Min
0.035
0.0004
Max
0.044
0.004
A
A1
A2
0.88
0.35
0.085
2.80
2.10
1.20
1.02
0.50
0.18
3.04
2.64
1.40
0.0346
0.014
0.003
0.110
0.083
0.047
0.040
0.020
0.007
0.120
0.104
0.055
b
c
D
E
E1
e
0.95 BSC
1.90 BSC
0.0374 Ref
e1
0.0748 Ref
L
0.40
0.60
8°
0.016
0.024
8°
L1
0.64 Ref
0.50 Ref
0.025 Ref
0.020 Ref
S
q
3°
3°
ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479
Document Number: 71196
09-Jul-01
www.vishay.com
1
AN807
Vishay Siliconix
Mounting LITTLE FOOTR SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
ambient air. This pattern uses all the available area underneath the
body for this purpose.
0.114
2.9
0.081
2.05
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
0.150
3.8
0.059
1.5
0.0394
1.0
0.037
0.95
FIGURE 1. Footprint With Copper Spreading
The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
Document Number: 70739
26-Nov-03
www.vishay.com
1
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SOT-23
0.037
0.022
(0.950)
(0.559)
0.053
(1.341)
0.097
(2.459)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 72609
Revision: 21-Jan-08
www.vishay.com
25
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Revision: 08-Feb-17
Document Number: 91000
1
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