SI4276DY [VISHAY]
Dual N-Channel 30 V (D-S) MOSFET; 双N沟道30 V （D -S ）的MOSFET
| 型号： | SI4276DY |
| 厂家： | 
VISHAY |
| 描述： | Dual N-Channel 30 V (D-S) MOSFET |
| 文件： | 总15页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si4276DY
Vishay Siliconix
Dual N-Channel 30 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
•
Halogen-free According to IEC 61249-2-21
VDS (V)
RDS(on) (Ω)
ID (A)a Qg (Typ.)
Definition
TrenchFET® Power MOSFET
100 % Rg Tested
0.0153 at VGS = 10 V
0.0184 at VGS = 4.5 V
0.0280 at VGS = 10 V
0.0340 at VGS = 4.5 V
8e
8e
•
•
•
Channel 1
Channel 2
30
8.4
100 % UIS Tested
8
30
3.6
7.1
• Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
•
DC/DC for Notebook PC
D
1
D
2
SO-8
S
1
D
1
D
1
D
2
D
2
1
2
3
4
8
7
6
5
G
1
G
G
2
1
S
2
G
2
Top View
Ordering Information: Si4276DY-T1-GE3 (Lead (Pb)-free and Halogen-free)
S
S
2
1
N-Channel MOSFET
N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted
A
Parameter
Symbol
Channel 1
Channel 2
Unit
Drain-Source Voltage
Gate-Source Voltage
VDS
30
20
V
VGS
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
8e
8e
8b, c, e
7.6b, c
50
8
6.4
Continuous Drain Current (TJ = 150 °C)
ID
6.8b, c
5.5b, c
30
A
Pulsed Drain Current (10 µs Pulse Width)
Source-Drain Current Diode Current
IDM
IS
TC = 25 °C
TA = 25 °C
3.0
1.7b, c
2.3
1.7b, c
Single Pulse Avalanche Current
Avalanche Energy
IAS
20
10
L = 0.1 mH
EAS
20
5
mJ
W
TC = 25 °C
TC = 70 °C
TA = 25 °C
TA = 70 °C
3.6
2.8
2.3
1.8
Maximum Power Dissipation
PD
2.1b, c
1.3b, c
2.0b, c
1.3b, c
Operating Junction and Storage Temperature Range
TJ, Tstg
- 55 to 150
°C
THERMAL RESISTANCE RATINGS
Channel 1
Channel 2
Typical
Maximum
Typical
58
Maximum
62.5
Parameter
Symbol
Unit
Maximum Junction-to-Ambientb, d
t ≤ 10 s
Steady
RthJA
47
30
60
35
°C/W
Maximum Junction-to-Foot (Drain)
RthJF
38
45
Notes:
a. Based on TC = 25 °C.
b. Surface mounted on 1" x 1" FR4 board.
c. t = 10 s.
d. Maximum under steady state conditions is 107 °C/W (Ch 1) and 110 °C/W (Ch 2).
e. Package limited.
Document Number: 66599
S10-1289-Rev. A, 31-May-10
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1
Si4276DY
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Symbol
Test Conditions
Min.
Typ.a
Max.
Unit
Static
VGS = 0 V, ID = 250 µA
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
30
30
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
VGS(th) Temperature Coefficient
Gate Threshold Voltage
VDS
ΔVDS/TJ
ΔVGS(th)/TJ
VGS(th)
V
V
GS = 0 V, ID = 250 µA
ID = 250 µA
29
30
ID = 250 µA
mV/°C
ID = 250 µA
- 5.2
- 4.4
ID = 250 µA
VDS = VGS, ID = 250 µA
DS = VGS, ID = 250 µA
1.2
1.2
2.5
2.5
100
100
1
V
V
Gate-Body Leakage
IGSS
VDS = 0 V, VGS
=
20 V
nA
VDS = 30 V, VGS = 0 V
VDS = 30 V, VGS = 0 V
1
Zero Gate Voltage Drain Current
On-State Drain Currentb
IDSS
ID(on)
RDS(on)
gfs
µA
A
VDS = 30 V, VGS = 0 V, TJ = 55 °C
VDS = 30 V, VGS = 0 V, TJ = 55 °C
VDS = 5 V, VGS = 10 V
10
10
10
10
V
DS = 5 V, VGS = 10 V
VGS = 10 V, ID = 9.5 A
VGS = 10 V, ID = 6.8 A
VGS = 4.5 V, ID = 8.7 A
VGS = 4.5 V, ID = 6.1 A
VDS = 15 V, ID = 9.5 A
0.0127
0.0230
0.0146
0.0280
43
0.0153
0.0280
0.0184
0.0340
Drain-Source On-State
Resistanceb
Ω
S
Forward Transconductanceb
Dynamica
V
DS = 15 V, ID = 6.8 A
17
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
1000
366
215
82
Input Capacitance
Ciss
Coss
Crss
Channel 1
VDS = 15 V, VGS = 0 V, f = 1 MHz
Output Capacitance
pF
Channel 2
VDS = 15 V, VGS = 0 V, f = 1 MHz
85
Reverse Transfer Capacitance
45
V
DS = 15 V, VGS = 10 V, ID = 9.5 A
DS = 15 V, VGS = 10 V, ID = 6.8 A
17.2
7.3
8.4
3.6
3
26
15
17
8
V
Total Gate Charge
Qg
Channel 1
VDS = 15 V, VGS = 4.5 V, ID = 9.5 A
nC
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Qgs
Qgd
Rg
1.1
2.6
1.3
3.1
2.6
Channel 2
VDS = 15 V, VGS = 4.5 V, ID = 6.8 A
0.6
0.5
6.2
5.2
f = 1 MHz
Ω
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Document Number: 66599
S10-1289-Rev. A, 31-May-10
Si4276DY
Vishay Siliconix
SPECIFICATIONS T = 25 °C, unless otherwise noted
J
Parameter
Dynamica
Symbol
Test Conditions
Min.
Typ.a
Max.
Unit
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
8
4
16
8
Turn-On Delay Time
Rise Time
td(on)
Channel 1
DD = 15 V, RL = 2 Ω
ID ≅ 7.6 A, VGEN = 10 V, Rg = 1 Ω
10
8
20
16
30
20
14
14
21
16
20
20
27
20
14
14
V
tr
20
11
7
Channel 2
VDD = 15 V, RL = 2.7 Ω
ID ≅ 5.5 A, VGEN = 10 V, Rg = 1 Ω
Turn-Off DelayTime
Fall Time
td(off)
tf
7
ns
14
8
Turn-On Delay Time
Rise Time
td(on)
Channel 1
DD = 15 V, RL = 2 Ω
ID ≅ 7.6 A, VGEN = 4.5 V, Rg = 1 Ω
11
10
18
10
7
V
tr
Channel 2
VDD = 15 V, RL = 2.7 Ω
ID ≅ 5.5 A, VGEN = 4.5 V, Rg = 1 Ω
Turn-Off Delay Time
Fall Time
td(off)
tf
7
Drain-Source Body Diode Characteristics
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
Ch 1
Ch 2
3
Continous Source-Drain Diode
Current
IS
TC = 25 °C
IS = 7.6 A
2.3
50
30
1.2
1.2
30
20
20
12
A
Pulse Diode Forward Currenta
Body Diode Voltage
ISM
VSD
trr
0.82
0.85
20
13
12
6
V
I
S = 5.5 A
Body Diode Reverse Recovery
Time
ns
nC
Channel 1
IF = 7.7 A, dI/dt = 100 A/µs, TJ = 25 °C
Body Diode Reverse Recovery
Charge
Qrr
ta
11
7
Channel 2
IF = 5.5 A, dI/dt = 100 A/µs, TJ = 25 °C
Reverse Recovery Fall Time
Reverse Recovery Rise Time
ns
9
tb
6
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 66599
S10-1289-Rev. A, 31-May-10
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Si4276DY
Vishay Siliconix
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
50
40
30
20
10
0
10
V
= 10 V thru 4 V
GS
8
T
= - 55 °C
C
6
T
= 25 °C
C
4
V
= 3 V
GS
T
= 125 °C
C
2
0
0.0
0.5
1.0
1.5
2.0
0.0
0.6
V
1.2
1.8
2.4
3.0
V
- Drain-to-Source Voltage (V)
- Gate-to-Source Voltage (V)
DS
GS
Output Characteristics
Transfer Characteristics
0.020
0.018
0.016
0.014
0.012
0.010
1400
1050
700
350
0
C
iss
V
= 4.5 V
GS
V
= 10 V
GS
C
oss
C
rss
0
10
20
30
40
50
0
6
V
12
18
24
30
- Drain-to-Source Voltage (V)
I
- Drain Current (A)
DS
D
Capacitance
On-Resistance vs. Drain Current
10
8
1.7
1.5
1.3
1.1
0.9
0.7
I
= 9.5 A
D
V
= 10 V; I = 9.5 A
D
GS
V
= 7.5 V
DS
6
V
I
= 4.5 V
GS
V
= 15 V
= 8.7 A
DS
D
4
V
9
= 24 V
DS
2
0
0
3
6
12
15
18
- 50 - 25
0
T
25
50
75
100 125 150
- Junction Temperature (°C)
Q
g
- Total Gate Charge (nC)
J
On-Resistance vs. Junction Temperature
Gate Charge
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Document Number: 66599
S10-1289-Rev. A, 31-May-10
Si4276DY
Vishay Siliconix
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
0.030
0.025
0.020
0.015
0.010
I
= 9.5 A
D
T
= 150 °C
J
T
= 125 °C
J
10
T
= 25 °C
J
1
T
2
= 25 °C
J
0.1
0.0
0
4
6
8
10
0.3
SD
0.6
0.9
1.2
V
- Source-to-Drain Voltage (V)
V
- Gate-to-Source Voltage (V)
GS
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
2.1
1.8
1.5
1.2
0.9
100
80
I
= 250 μA
D
60
40
20
0
- 50 - 25
0
25
50
75
100 125 150
0.001
0.01
0.1
1
10
Time (s)
T
- Temperature (°C)
J
Single Pulse Power, Junction-to-Ambient
Threshold Voltage
100
Limited by R
*
DS(on)
100 μs
1 ms
10
1
10 ms
100 ms
1 s
T
= 25 °C
A
0.1
Single Pulse
10 s
DC
BVDSS Limited
0.01
0.1
1
10
100
V
- Drain-to-Source Voltage (V)
DS
* V
> minimum V at which R
is specified
DS(on)
GS
GS
Safe Operating Area, Junction-to-Ambient
Document Number: 66599
S10-1289-Rev. A, 31-May-10
www.vishay.com
5
Si4276DY
Vishay Siliconix
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
15
12
9
6
3
0
Package Limited
0
25
50
75
100
125
150
T
- Case Temperature (°C)
C
Current Derating*
1.5
1.2
0.9
0.6
0.3
0.0
5
4
3
2
1
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
A
- Ambient Temperature (°C)
T
- Case Temperature (°C)
C
Power Derating, Junction-to-Ambient
Power Derating, Junction-to-Foot
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
www.vishay.com
6
Document Number: 66599
S10-1289-Rev. A, 31-May-10
Si4276DY
Vishay Siliconix
CHANNEL-1 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
1
Duty Cycle = 0.5
0.2
0.1
Notes:
P
DM
0.1
t
1
0.05
t
2
t
t
2
1
1. Duty Cycle, D =
2. Per Unit Base = R
= 85 °C/W
0.02
thJA
(t)
3. T
-
T
A
= P
Z
JM
DM thJA
4. Surface Mounted
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
10
100
600
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Document Number: 66599
S10-1289-Rev. A, 31-May-10
www.vishay.com
7
Si4276DY
Vishay Siliconix
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
30
24
18
12
6
5
4
3
2
1
0
V
= 10 V thru 4 V
GS
T
= - 55 °C
C
T
= 25 °C
C
V
= 3 V
GS
T
= 125 °C
C
0
0.0
0.5
1.0
1.5
2.0
0.0
0.6
V
1.2
1.8
2.4
3.0
- Gate-to-Source Voltage (V)
V
- Drain-to-Source Voltage (V)
GS
DS
Output Characteristics
Transfer Characteristics
0.060
0.045
0.030
0.015
0.000
500
400
300
200
100
0
C
iss
V
= 4.5 V
GS
V
= 10 V
GS
C
oss
C
rss
0
5
10
15
20
25
30
0
6
V
12
18
24
30
I
- Drain Current (A)
- Drain-to-Source Voltage (V)
D
DS
On-Resistance vs. Drain Current
Capacitance
10
8
1.7
1.5
1.3
1.1
0.9
0.7
I
= 6.8 A
D
V
= 10 V; I = 6.8 A
D
GS
V
= 7.5 V
DS
6
V
= 4.5 V
GS
= 6.1 A
V
= 15 V
DS
I
D
4
V
= 24 V
DS
2
0
0
2
4
6
8
- 50 - 25
0
T
25
50
75
100 125 150
Q
- Total Gate Charge (nC)
- Junction Temperature (°C)
g
J
Gate Charge
On-Resistance vs. Junction Temperature
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Document Number: 66599
S10-1289-Rev. A, 31-May-10
Si4276DY
Vishay Siliconix
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
0.060
0.045
0.030
0.015
0
I
= 6.8 A
D
T
= 125 °C
J
T
= 150 °C
J
10
T
= 25 °C
J
T
= 25 °C
J
1
0.1
0.0
0
2
V
4
6
8
10
0.3
0.6
0.9
1.2
V
- Source-to-Drain Voltage (V)
- Gate-to-Source Voltage (V)
SD
GS
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
2.1
1.9
1.7
1.5
1.3
1.1
50
40
30
20
10
0
I
= 250 μA
D
- 50 - 25
0
25
50
75
100 125 150
0.001
0.01
0.1
1
10
100
1000
Time (s)
T
- Temperature (°C)
J
Single Pulse Power, Junction-to-Ambient
Threshold Voltage
100
Limited by R
*
DS(on)
10
100 μs
1 ms
1
10 ms
100 ms
T
= 25 °C
0.1
A
1 s
10 s
DC
Single Pulse
BVDSS Limited
0.01
0.1
1
10
100
V
- Drain-to-Source Voltage (V)
DS
* V
> minimum V at which R
is specified
DS(on)
GS
GS
Safe Operating Area, Junction-to-Ambient
Document Number: 66599
S10-1289-Rev. A, 31-May-10
www.vishay.com
9
Si4276DY
Vishay Siliconix
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
8
Package Limited
6
4
2
0
0
25
50
75
100
125
150
T
- Case Temperature (°C)
C
Current Derating*
1.5
1.2
0.9
0.6
0.3
0.0
4
3
2
1
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
T
A
- Ambient Temperature (°C)
T
- Case Temperature (°C)
C
Power Derating, Junction-to-Foot
Power Derating, Junction-to-Ambient
* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
www.vishay.com
10
Document Number: 66599
S10-1289-Rev. A, 31-May-10
Si4276DY
Vishay Siliconix
CHANNEL-2 TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
P
DM
0.05
0.02
t
1
t
2
t
1
1. Duty Cycle, D =
t
2
2. Per Unit Base = R
= 90 °C/W
thJA
(t)
= P
Z
3. T - T
A
DM thJA
JM
4. Surface Mounted
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
1
100
1000
10
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
10
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?66599.
Document Number: 66599
S10-1289-Rev. A, 31-May-10
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11
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
2
5
4
E
H
1
3
S
h x 45
D
C
0.25 mm (Gage Plane)
A
All Leads
0.101 mm
q
e
B
A
1
L
0.004"
MILLIMETERS
Max
INCHES
DIM
A
Min
Min
Max
1.35
0.10
0.35
0.19
4.80
3.80
1.75
0.20
0.51
0.25
5.00
4.00
0.053
0.004
0.014
0.0075
0.189
0.150
0.069
0.008
0.020
0.010
0.196
0.157
A1
B
C
D
E
e
1.27 BSC
0.050 BSC
H
h
5.80
0.25
0.50
0°
6.20
0.50
0.93
8°
0.228
0.010
0.020
0°
0.244
0.020
0.037
8°
L
q
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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1
VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
0.288
7.3
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
0.050
1.27
0.088
2.25
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
0.288
7.3
0.050
1.27
0.196
5.0
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
www.vishay.com
1
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
(0.711)
0.022
0.050
(0.559)
(1.270)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
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22
Document Number: 72606
Revision: 21-Jan-08
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相关型号：
SI4300DY-T1
TRANSISTOR 6400 mA, 30 V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, SO-8, FET General Purpose Small Signal
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