SI9165BQ-T1 [VISHAY]
Switching Regulator/Controller,;
| 型号： | SI9165BQ-T1 |
| 厂家： | 
VISHAY |
| 描述： | Switching Regulator/Controller, |
| 文件： | 总8页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si9165
New Product
Vishay Siliconix
Si9165
High Frequency 600-mA Synchronous Buck/Boost Converter
FEATURES
• Voltage Mode Control
• Fully Integrated MOSFET Switches
• 2.7-V to 6-V Input Voltage Range
• Integrated UVLO and POR
• Integrated Soft-Start
• Synchronization
• Programmable PWM/PSM Control
• Shutdown Current <1 µA
– Up to 600-mA Output Current @ 3.3 V in PWM
– Up to 2-MHz Adjustable Switching Frequency in PWM
– Less than 200-µA Quiescent Current in PSM
DESCRIPTION
The Si9165 provides fully integrated synchronous buck or
boost converter solution for the latest one cell Lithium Ion
cellular phones. Capable of delivering up to 600 mA of output
current at +3.3 V, the Si9165 provides ample power for
various baseband circuits as well as for some PAs. It
combines the 2-MHz switching controller with fully integrated
high-frequency MOSFETs to deliver the smallest and most
efficient converter available today. The 2-MHz switching
frequency reduces the inductor height to new level of 2 mm
and minimizes the output capacitance requirement to less
than 10 µF with peak-to-peak output ripple as low as 10 mV.
Combined with low-gate charge high-frequency MOSFETs,
the Si9165 delivers efficiency up to 95%. The programmable
pulse skipping mode maintains this high efficiency even
during the standby and idle modes to increase overall battery
life and talktime. In order to extract the last ounce of power
from the battery, the Si9165 is designed with 100% duty cycle
control for buck mode. With 100% duty cycle, the Si9165
operates like a saturated linear regulator to deliver the highest
potential output voltage for longer talktime.
The Si9165 is available in TSSOP-20 pin package. In order to
satisfy the stringent ambient temperature requirements, the
Si9165 is rated to handle the industrial temperature range of
-25°C to 85°C.
STANDARD APPLICATION CIRCUITS
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Si9165
Vishay Siliconix
New Product
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to GND
Continuous Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . .-65 to 150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
DD
MODE, PWM/PSM, SYNC, SD, V , R
COMP, FB. -0.3 V to V
DD
REF OSC
a
+0.3 V
Power Dissipation (Package)
b
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to V +0.3 V
O
S
20-Pin TSSOP (Q Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Thermal Impedance (Θ
)
JA
Voltages Referenced to PGND
20-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125°C/W
V , V
6.5 V
IN/OUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S
Notes
COIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4 V to V
+0.4 V
IN/OUT
a. Device mounted with all leads soldered or welded to PC board.
Peak Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 A
b. Derate 8.0 mW/°C above 25°C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Voltages Referenced to GND
Voltages Referenced to PGND
V , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V
DD
S
IN/OUT
MODE, PWM/PSM, SYNC, SD . . . . . . . . . . . . . . . . . . . . . 0 V to V
F
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 kHz to 2 MHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 kΩ to 300 kΩ
Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.1 µF
DD
osc
R
osc
V
REF
SPECIFICATIONS
Limits
Test Conditions
Unless Otherwise Specified
-25°C to 85°C
2.7 V < V < 6V,
DD
Parameter
Reference
Symbol
Mina
Typb
Maxa
Unit
V
= 3.3 V, V = 3.3 V
IN/OUT
S
I
= 0
1.268
1.280
1.3
1.3
3
1.332
1.320
REF
Output Voltage
V
V
REF
T = 25°C, I
= 0
REF
A
Load Regulation
Power Supply Rejection
UVLO
∆V
V
= 3.3 V, -500 µA < I <0
REF
mV
dB
REF
DD
P
60
SRR
Under Voltage Lockout (turn-on)
Hysteresis
V
2.3
2.4
0.1
2.5
UVLOLH
V
V
V
- V
UVLOLH UVLOHL
HYS
Soft-start Time
SS time
tss
6
ms
Mode
Logic High
V
0.7 V
DD
IH
V
Logic Low
V
0.3 V
DD
IL
L
Input Current
SD, SYNC, PWM/PSM
Logic High
I
-1.0
2.4
1.0
µA
V
IH
V
Logic Low
V
0.8
1.0
IL
L
Input Current
I
-1.0
µA
S-60752—Rev. B, 05-Apr-99
2
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Si9165
New Product
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SPECIFICATIONS
Limits
Test Conditions
Unless Otherwise Specified
-25°C to 85°C
2.7 V < V < 6V,
DD
Parameter
Symbol
Mina
Typb
Maxa
Unit
MHz
%
V
= 3.3 V, V = 3.3 V
IN/OUT
S
Oscillator
Maximum Frequency
Accuracy
F
2
MAX
Nominal 1.60 MHz, R
= 30 kΩ
-20
20
OSC
Max Duty Cycle (Buck, Non LDO
Mode)
75
50
85
65
D
Fsw = 2 MHz
MAX
Max Duty Cycle (Boost)
SYNC Range
F
/
SYNC
1.2
1.5
F
OSC
SYNC Low Pulse Width
SYNC High Pulse Width
50
50
ns
SYNC t , t
50
1
r
f
Error Amplifier
Input Bias Current
I
V
= 1.5 V
-1
µA
dB
BIAS
FB
Open Loop Voltage Gain
A
50
60
1.30
1.30
2
VOL
T = 25°C
1.270
1.258
1.330
1.342
A
FB Threshold
Unity Gain BW
V
V
FB
BW
MHz
Source (V = 1.05 V), V
=
COMP
FB
-3
3
-1
0.75 V
Output Current
I
mA
mA
EA
Sink (V = 1.55 V), V
= 0.75 V
1
FB
COMP
Output Current
Boost
Mode
V
V
V
≤ V
≥ V
= 2.7 to 5.0 V
= 2.7 to 6.0 V
600
600
150
150
c
IN
IN
OUT
Output Current
(PWM)
Buck
d
OUT
Mode
I
OUT
Boost
= 3.3 V, V
= 3.6 V
= 2.7 V
c
IN
OUT
Mode
Output Current
(PSM)
Buck
V
= 3.6 V, V
d
IN
OUT
Mode
r
r
N-channel
P-channel
130
160
300
330
DS(on)
DS(on)
r
V
≥ 3.3 V
S
mΩ
°C
DS(on)
Over Temperature Protection
Trip Point
Rising Temperature
165
25
Hysteresis
Supply Current
Normal Mode
I
V
= 3.3 V, F = 2 MHz
OSC
500
180
750
250
1
DD
DD
PSM Mode
V
= 3.3 V
µA
DD
Shutdown Mode
V
= 3.3 V, SD = 0 V
DD
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. V = V
V
= V
= V = V , L = 1.5 µH
IN/OUT S O
IN
DD, OUT
d. V = V = V = V
, V
= V , L = 1.5 µH
IN
DD
S
IN/OUT OUT O
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Si9165
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TYPICAL CHARACTERISTICS (25°C UNLESS OTHERWISE NOTED)
S-60752—Rev. B, 05-Apr-99
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Si9165
New Product
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TYPICAL CHARACTERISTICS (25°C UNLESS OTHERWISE NOTED)
PIN CONFIGURATION
ORDERING INFORMATION
Temperature
Range
Part Number
Package
Si9165BQ-T1
-25 to 85°C
Tape and Reel
Temperature
Range
Eval Kit
Board Type
Si9165DB
-25 to 85°C
Surface Mount
PIN DESCRIPTION
Pin
Symbol
Description
1
N/C
SD
Not Used
Shuts down the IC completely and decreases current consumed by the IC to <1 µA.
2
3
PWM/PSM
Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification is disabled.
Input node for buck mode and output node for boost mode.
4, 5, 6
V
IN/OUT
Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization.
7
SYNC
GND
If not used, the pin must be connected to V , or logic high.
DD
8
9
Low power controller ground
V
1.3-V reference. Decoupled with 0.1-µF capacitor.
Output voltage feedback connected to the inverting input of an error amplifier.
Error amplifier output for external compensation network.
External resistor to determine the switching frequency.
Input supply voltage for the analog circuitry. Input voltage range is 2.7 V to 6 V.
Direct output voltage sensing to control peak inductor current in PSM mode.
Supply voltage for the internal MOSFET drive circuit.
Power ground.
REF
10
FB
11
COMP
Rosc
12
13
V
DD
14
V
O
15
V
S
16, 17
18
PGND
MODE
COIL
Determines the converter topology. Connect to AGND for buck or V for boost.
DD
19, 20
Inductor connection node
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FUNCTIONAL BLOCK DIAGRAM
DETAIL OPERATIONAL DESCRIPTION
Start-Up
gate voltage to PGND potential. Note that the Si9165 will
always soft starts in the PWM mode regardless of the voltage
level on the PWM/PSM pin.
The UVLO circuit prevents the internal MOSFET switches and
oscillator circuit from turning on, if the voltage on VDD pin is
less than 2.5 V. With typical UVLO hysteresis of 0.1 V,
controller is continuously powered on until the VDD voltage
drops below 2.4 V. This hysteresis prevents the converter
from oscillating during the start-up phase and unintentionally
locking up the system. Once the VDD voltage exceeds the
UVLO threshold, and with no other shutdown condition
detected, an internal Power-On-Reset timer is activated while
most circuitry, except the output driver, are turned on. After
the POR timeout of about 1 ms, the internal soft-start
capacitor is allowed to charge. When the soft-start capacitor
voltage reaches 0.5 V, the PWM circuit is enabled.
Thereafter, the constant current charging the soft-start
capacitor will force the output voltage to rise gradually without
overshooting. To prevent negative undershoot, the
synchronous switch is tri-stated until the duty cycle reaches
about 10%. In tri-state, the high-side p-channel MOSFET is
turned off by pulling up the gate voltage to VS potential. The
low-side n-channel MOSFET is turned off by pulling down the
Shutdown
The Si9165 is designed to conserve as much battery life as
possible by decreasing current consumption of IC during
normal operation as well as the shutdown mode. With logic
low level on the SD pin, current consumption of the Si9165 is
decreased to less than 1 µA by shutting off most of the
circuits. The logic high enables the controller and starts up as
described in “Start-Up” section above.
Over Temperature Protection
The Si9165 is designed with over temperature protection
circuit to prevent MOSFET switches from running away. If the
temperature reaches 165°C, internal soft-start capacitor is
discharged, shutting down the output stage. Converter
remains in the disabled mode until the temperature in the IC
decreases below 140°C.
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PWM Mode
the Si9165 is designed with pulse skipping mode. If the
PWM/PSM pin is connected to logic low level, converter
operates in pulse skipping modulation (PSM) mode. During
the pulse skipping mode, quiescent current of the controller is
decreased to approximately 200 µA, instead of 500 µA during
the PWM mode. This is accomplished by turning off most of
internal control circuitry and utilizing a simple constant on-
time control with feedback comparator. The controller is
designed to have a constant on-time and a minimum off-time
acting as the feedback comparator blanking time. If the output
voltage drops below the desired level, the main switch is first
turned on and then off. If the applied on-time is insufficient to
provide the desired voltage, the controller will force another on
and off sequence, until the desired voltage is accomplished. If
the applied on-time forces the output to exceed the desired
level, as typically found in the light load condition, the
converter stays off. The excess energy is delivered to the
output slowly, forcing the converter to skip pulses as needed
to maintain regulation. The on-time and off-time are set
internally based on inductor used (1.5-µH Typical), Mode pin
selection and maximum load current. Wide duty cycle range
can be achieved in both buck and boost configurations. In
pulse skipping mode, synchronous rectifier drive is also
disabled to further decrease the gate charge loss, which in
turn improves overall converter efficiency.
With PWM/PSM mode pin in logic high condition, the Si9165
operates in constant frequency (PWM) mode. As the load
and line varies, switching frequency remain constant. The
switching frequency is programmed by the Rosc value as
shown by the Oscillator curve. In the PWM mode, the
synchronous drive is always enabled, even when the output
current reaches 0 A. In continuous current mode, transfer
function of the converter remain constant, providing fast
transient response. If the converter operates in discontinuous
current mode, overall loop gain decreases and transient
response time can be ten times longer than if the converter
remain in continuous current mode. This transient response
time advantage can significantly decrease the hold-up
capacitors needed on the output of dc-dc converter to meet
the transient voltage regulation. Therefore, the PWM/PSM pin
is available to dynamically program the controller.
The maximum duty cycle of the Si9165 can reach 100% in
buck mode. This allows the system designers to extract out
the maximum stored energy from the battery. Once the
controller delivers 100% duty cycle, converter operates like a
saturated linear regulator. At 100% duty cycle, synchronous
rectification is completely turned off. Up to a maximum duty
cycle of 80% at 2-MHz switching frequency, controller
maintains perfect output voltage regulation. If the input
voltage drops below the level where the converter requires
greater than 80% duty cycle, controller will deliver 100% duty
cycle. This instantaneous jump in duty cycle is due to fixed
BBM time, MOSFET delay/rise/fall time, and the internal
propagational delays. In order to maintain regulation,
controller might fluctuate its duty cycle back and forth from
100% to something less than maximum duty cycle while the
converter is operating in this input voltage range. If the input
voltage drops further, controller will remain on 100%. If the
input voltage increases to a point where it requires less than
80% duty cycle, synchronous rectification is once again
activated.
Reference
The reference voltage of the Si9165 is set at 1.3 V. The
reference voltage is internally connected to the non-inverting
inputs of the error amplifier. The reference is decoupled with
0.1-µF capacitor.
Error Amplifier
The error amplifier gain-bandwidth product and slew rate is
critical parameters which determines the transient response
of converter. The transient response is function of both small
and large signal response. The small signal is the converter
closed loop bandwidth and phase margin while the large
signal is determined by the error amplifier dv/dt and the
inductor di/dt slew rate. Besides the inductance value, error
amplifier determines the converter response time. In order to
minimize the response time, the Si9165 is designed with 2-
MHz error amplifier gain-bandwidth product to generate the
widest converter bandwidth and 3.5 V/µsec slew rate for ultra-
fast large signal response.
The maximum duty cycle under boost mode is internally
limited to 75% to prevent inductor saturation. If the converter
is turned on for 100% duty cycle, inductor never gets a chance
to discharge its energy and eventually saturates. In boost
mode, synchronous rectifier is always turned on for minimum
or greater duration as long as the switch has been turned on.
The controller will deliver 0% duty cycle, if the input voltage is
greater than the programmed output voltage. Because of
signal propagation time and MOSFET delay/rise/fall time,
controller will not transition smoothly from minimum
controllable duty cycle to 0% duty cycle. For example,
controller may decrease its duty cycle from 5% to 0% abruptly,
instead of gradual decrease you see from 75% to 5%.
Oscillator
The oscillator is designed to operate up to 2-MHz minimal.
The 2-MHz operating frequency allows the converter to
minimize the inductor and capacitor size, improving the power
density of the converter.
Even with 2-MHz switching
Pulse Skipping Mode
frequency, quiescent current is only 500 µA with unique power
saving circuit design. The switching frequency is easily
programmed by attaching a resistor to ROSC pin. See
oscillator frequency versus ROSC curve to select the proper
values for desired operating frequency. The tolerance on the
operating frequency is ±20% with 1% tolerance resistor.
The gate charge losses produced from the Miller capacitance
of MOSFETs are the dominant power dissipation parameter
during light load (i.e. < 10 mA). Therefore, less gate switching
will improve overall converter efficiency. This is exactly why
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Synchronization
maximum controllable duty cycle will vary depending on the
switching frequency.
The synchronization to external clock is easily accomplished
by connecting the external clock into the SYNC pin. A logic
high to low transition synchronizes the clock. The external
clock frequency must be within 1.2 to 1.5 times the internal
clock frequency.
Output MOSFET Stage
The high- and low-side switches are integrated to provide
optimum performance and to minimize the overall converter
size. Both, high and low-side switches are designed to handle
up to 600 mA of continuous current. The MOSFET switches
were designed to minimize the gate charge loss as well as the
conduction loss. For the high frequency operation, switching
losses can exceed conduction loss, if the switches are
designed incorrectly. Under full load, efficiency of 90% is
accomplished with 3.6-V battery voltage in both buck and
boost modes (+2.7-V output voltage for buck mode and +5-V
output voltage for boost mode).
Break-Before-Make Timing
A proper BBM time is essential in order to prevent shoot-
through current and maintain high efficiency. The break-
before-make time is set internally at 20 ns @ VS = 3.6 V. The
high and low-side MOSFET drain voltages are monitored and
when the drain voltage reaches the 1.75 V below or above its
initial starting voltage, 20 ns BBM time is set before the other
switch turns on. The maximum controllable duty cycle is
limited by the BBM time. Since the BBM time is fixed,
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