SIHU3N50DA-GE3 [VISHAY]
MOSFET N-CHANNEL 500V 3A IPAK;
| 型号： | SIHU3N50DA-GE3 |
| 厂家： | 
VISHAY |
| 描述： | MOSFET N-CHANNEL 500V 3A IPAK |
| 文件： | 总9页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiHU3N50DA
Vishay Siliconix
www.vishay.com
D Series Power MOSFET
FEATURES
PRODUCT SUMMARY
• Optimal design
VDS (V) at TJ max.
DS(on) max. at 25 °C (Ω)
Qg (max.) (nC)
550
- Low area specific on-resistance
- Low input capacitance (Ciss
R
VGS = 10 V
3.2
)
12
2
- Reduced capacitive switching losses
- High body diode ruggedness
- Avalanche energy rated (UIS)
• Optimal efficiency and operation
- Low cost
Q
gs (nC)
gd (nC)
Q
3
Configuration
Single
D
- Simple gate drive circuitry
- Low figure-of-merit (FOM): Ron x Qg
- Fast switching
IPAK
(TO-251)
D
G
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
S
N-Channel MOSFET
S
D
G
• Consumer electronics
- Displays (LCD or plasma TV)
• Server and telecom power supplies
- SMPS
• Industrial
- Welding, induction heating, motor drives
• Battery chargers
ORDERING INFORMATION
Package
IPAK (TO-251)
Lead (Pb)-free and Halogen-free
SiHU3N50DA-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-Source Voltage
Gate-Source Voltage
Gate-Source Voltage AC (f > 1 Hz)
VDS
500
30
V
VGS
30
3.0
T
C = 25 °C
Continuous Drain Current (TJ = 150 °C)
VGS at 10 V
ID
TC = 100 °C
1.9
A
Pulsed Drain Currenta
IDM
5.5
Linear Derating Factor
Single Pulse Avalanche Energyb
0.56
9
W/°C
mJ
W
EAS
PD
Maximum Power Dissipation
69
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
Reverse Diode dV/dtd
TJ, Tstg
-55 to +150
24
°C
TJ = 125 °C
for 10 s
dV/dt
V/ns
°C
0.22
300
Soldering Recommendations (Peak Temperature)c
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 2.3 mH, Rg = 25 Ω, IAS = 2.8 A.
c. 1.6 mm from case.
d. ISD ≤ ID, starting TJ = 25 °C.
S14-1304-Rev. A, 23-Jun-14
Document Number: 91615
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU3N50DA
Vishay Siliconix
www.vishay.com
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
RthJA
TYP.
MAX.
UNIT
Maximum Junction-to-Ambient
Maximum Junction-to-Case (Drain)
-
-
62
°C/W
RthJC
1.8
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-Source Breakdown Voltage
VDS
ΔVDS/TJ
VGS(th)
IGSS
VGS = 0 V, ID = 250 μA
Reference to 25 °C, ID = 1 mA
VDS = VGS, ID = 250 μA
500
-
-
-
V
V/°C
V
VDS Temperature Coefficient
-
3
-
-
-
-
-
0.59
Gate-Source Threshold Voltage (N)
Gate-Source Leakage
-
-
4.5
100
1
VGS
=
30 V
nA
VDS = 500 V, VGS = 0 V
-
Zero Gate Voltage Drain Current
IDSS
μA
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
10
3.2
-
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
RDS(on)
gfs
VGS = 10 V
ID = 1.5 A
2.6
1
Ω
VDS = 8 V, ID = 1.5 A
S
Input Capacitance
Ciss
Coss
Crss
-
-
-
177
26
7
-
-
-
VGS = 0 V,
Output Capacitance
V
DS = 100 V,
f = 1 MHz
Reverse Transfer Capacitance
pF
Effective Output Capacitance, Energy
Relatedb
Co(er)
Co(tr)
-
-
21
28
-
-
VDS = 0 V to 400 V, VGS = 0 V
Effective Output Capacitance, Time
Relatedc
Total Gate Charge
Qg
Qgs
Qgd
td(on)
tr
-
-
-
-
-
-
-
-
6
2
12
-
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
V
GS = 10 V
ID = 1.5 A, VDS = 400 V
nC
3
-
12
9
24
18
22
26
-
VDD = 400 V, ID = 1.5 A
Rg = 9.1 Ω, VGS = 10 V
ns
Turn-Off Delay Time
Fall Time
td(off)
tf
11
13
2.6
Gate Input Resistance
Drain-Source Body Diode Characteristics
Rg
f = 1 MHz, open drain
Ω
D
MOSFET symbol
showing the
integral reverse
P - N junction diode
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current
IS
-
-
-
-
3
A
G
ISM
5.5
S
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
VSD
trr
TJ = 25 °C, IS = 1.5 A, VGS = 0 V
-
-
-
-
-
1.2
570
1.36
-
V
ns
μC
A
285
0.68
5
TJ = 25 °C, IF = IS = 1.5 A,
dI/dt = 100 A/μs, VR = 25 V
Qrr
IRRM
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS
.
.
S14-1304-Rev. A, 23-Jun-14
Document Number: 91615
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU3N50DA
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
3.0
2.5
2.0
1.5
1.0
0.5
0
6
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
6 V
TJ = 25 °C
5
4
3
2
1
0
ID = 1.5 A
BOTTOM 5 V
VGS = 10 V
-60 -40 -20
0
20 40 60 80 100 120 140 160
0
5
10
15
20
25
30
VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
4
3
2
1
0
1000
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
6 V
TJ = 150 °C
Ciss
100
10
1
VGS = 0 V, f = 1 MHz
C
C
iss = Cgs + Cgd, Cds shorted
rss = Cgd
BOTTOM 5 V
Coss
Coss = Cds + Cgd
Crss
0
100
200
300
400
500
0
5
10
15
20
25
30
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
6
1000
100
10
3
5
4
3
2
1
0
2.5
2
TJ = 25 °C
Eoss
TJ = 150 °C
1.5
1
Coss
0.5
0
VDS = 31.6 V
0
5
10
15
20
25
0
100
200
300
400
500
VDS
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - Coss and Eoss vs. VDS
S14-1304-Rev. A, 23-Jun-14
Document Number: 91615
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU3N50DA
Vishay Siliconix
www.vishay.com
3
2
1
0
24
20
16
12
8
VDS = 400 V
VDS = 250 V
DS = 100 V
V
4
0
25
50
75
100
125
150
0
2
4
6
8
10
12
Qg, Total Gate Charge (nC)
TC, Case Temperature (°C)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 10 - Maximum Drain Current vs. Case Temperature
10
625
600
575
550
525
500
TJ = 150 °C
1
TJ = 25 °C
0.1
VGS = 0 V
1.4
ID = 250 μA
0.01
475
0.2
0.4
0.6
0.8
1.0
1.2
1.6
-60 -40 -20
0
20 40 60 80 100 120 140 160
VSD, Source-Drain Voltage (V)
TJ, Junction Temperature (°C)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Fig. 11 - Typical Drain-to-Source Voltage vs. Temperature
10
IDM Limited
100 μs
1
Limited by RDS(on)
*
1 ms
Operation in this Area
Limited by RDS(on)
0.1
10 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
BVDSS Limited
0.01
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S14-1304-Rev. A, 23-Jun-14
Document Number: 91615
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU3N50DA
Vishay Siliconix
www.vishay.com
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
VDD
D.U.T.
RG
+
V
-
DD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
QG
10 V
90 %
QGS
QGD
10 %
VGS
VG
td(on) tr
td(off) tf
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
L
Current regulator
VDS
Same type as D.U.T.
Vary tp to obtain
required IAS
50 kΩ
12 V
0.2 µF
D.U.T
IAS
RG
+
-
0.3 µF
VDD
+
-
VDS
D.U.T.
10 V
0.01 Ω
tp
VGS
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
Document Number: 91615
S14-1304-Rev. A, 23-Jun-14
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHU3N50DA
Vishay Siliconix
www.vishay.com
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
• Low stray inductance
• Ground plane
D.U.T.
• Low leakage inductance
current transformer
-
+
-
-
+
Rg
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
P.W.
D =
Period
Period
V
GS = 10 Va
D.U.T. lSD waveform
D.U.T. VDS waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current
ISD
Ripple ≤ 5 %
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91614.
S14-1304-Rev. A, 23-Jun-14
Document Number: 91615
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-251AA (HIGH VOLTAGE)
4
3
A
E1
E
Thermal PAD
A
4
0.010
M
A B
C
0.25
c2
b4
L2
4
A
θ1
θ2
D1
4
B
C
3
Seating
plane
5
C
B
C
L3
L1
(Datum A)
L
B
A
A1
3 x b2
3 x b
c
View A - A
M
0.010
C A B
0.25
2 x e
Base
metal
5
Plating
(c)
b1, b3
Lead tip
5
c1
(b, b2)
Section B - B and C - C
MILLIMETERS
INCHES
MILLIMETERS
INCHES
MAX.
DIM.
A
MIN.
2.18
0.89
0.64
0.65
0.76
0.76
4.95
0.46
0.41
0.46
5.97
MAX.
2.39
1.14
0.89
0.79
1.14
1.04
5.46
0.61
0.56
0.86
6.22
MIN.
0.086
0.035
0.025
0.026
0.030
0.030
0.195
0.018
0.016
0.018
0.235
MAX.
0.094
0.045
0.035
0.031
0.045
0.041
0.215
0.024
0.022
0.034
0.245
DIM.
D1
E
MIN.
5.21
6.35
4.32
MAX.
MIN.
0.205
0.250
0.170
-
6.73
-
-
0.265
-
A1
b
E1
e
b1
b2
b3
b4
c
2.29 BSC
2.29 BSC
L
8.89
1.91
0.89
1.14
0'
9.65
2.29
1.27
1.52
15'
0.350
0.075
0.035
0.045
0'
0.380
0.090
0.050
0.060
15'
L1
L2
L3
θ1
θ2
c1
c2
D
25'
35'
25'
35'
ECN: S-82111-Rev. A, 15-Sep-08
DWG: 5968
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension are shown in inches and millimeters.
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at the
outermost extremes of the plastic body.
4. Thermal pad contour optional with dimensions b4, L2, E1 and D1.
5. Lead dimension uncontrolled in L3.
6. Dimension b1, b3 and c1 apply to base metal only.
7. Outline conforms to JEDEC outline TO-251AA.
Document Number: 91362
Revision: 15-Sep-08
www.vishay.com
1
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.224
(5.690)
0.180
0.055
(1.397)
(4.572)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 72594
Revision: 21-Jan-08
www.vishay.com
3
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Revision: 09-Jul-2021
Document Number: 91000
1
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