SIP21107DVP-30-E3 [VISHAY]
150-mA Low Noise, Low Dropout Regulator; 150 mA的低噪声，低压差稳压器
| 型号： | SIP21107DVP-30-E3 |
| 厂家： | 
VISHAY |
| 描述： | 150-mA Low Noise, Low Dropout Regulator |
| 文件： | 总13页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
New Product
SiP21106/7/8
Vishay Siliconix
150-mA Low Noise, Low Dropout Regulator
APPLICATIONS
FEATURES
•
•
•
•
•
•
Cellular Phones, Wireless Handsets
• TSC75-6L Package (1.6 x 1.6 x 0.6 mm), and
TSOT23-5L Package Options
PDAs
•
•
•
1.0 % Output Voltage Accuracy at 25 °C
Low Dropout Voltage: 135 mV at 150 mA
SiP21106 Low Noise: 60 µV(rms)
MP3 Players
Digital Cameras
Pagers
RoHS
COMPLIANT
(10 Hz to 100 kHz Bandwidth)
With 10 nF Over Full Load Range
Wireless Modem
• Noise-Sensitive Electronic Systems
•
•
•
•
35 µA (typical) Ground Current at 1 mA Load
1 µA Maximum Shutdown Current at 85 °C
Output Auto Discharge at Shutdown Mode
Built-in Short Circuit (330 mA typical) and Thermal Pro-
tection (160 °C typical)
DESCRIPTION
The SiP21106 BiCMOS 150 mA low noise LDO voltage reg-
ulators are the perfect choice for low battery operated low
powered applications. An Ultra low ground current and low
dropout voltage of 135 mV at 150 mA load helps to extend
battery life for portable electronics. Systems requiring a quiet
voltage source, such as RF applications, will benefit from the
SiP21106 low output noise.
The SiP21107 do not require a noise bypass cpacitor and
provides an error flag pin (POK or Power OK). POK output
requires an external pull-up resistor and goes low when the
supply has not come up to voltage.
•
•
•
SiP21108 Adjustable Output Voltage
SiP21107 POK Error Flag
- 40 °C to + 125 °C Junction Temperature Range for
Operation
•
Uses Low ESR Ceramic Capacitors
• Fixed Voltage Output 1.3 V to 5 V in 50 mV Steps
The SiP21108 output is adjusted with an external resistor
network.
The SiP21106/7/8 regulators allow stable operation with very
small ceramic output capacitors, reducing board space and
component cost. They are designed to maintain regulation
while delivering 330 mA peak current upon turn-on. During
start-up, an active pull-down circuit improves the output tran-
sient response and regulation. In shutdown mode, the output
automatically discharges to ground through a 100 Ω NMOS.
The SiP21106/7/8 are available in TSOT23-5L and a super
thin lead (Pb)-free TSC75-6L packages for operation over
the industrial operation range (- 40 °C to 85 °C).
TYPICAL APPLICATION CIRCUIT
1
2
3
5
4
VIN
VOUT
VOUT
EN
VIN
1
2
3
BP
NC
6
5
4
EN
C
OUT = 1 µF
CIN = 1 µF
CBypass = 10 nF
GND
EN
GND
VIN
SiP21106
SiP21106
EN
BP
VIN
VOUT
VOUT
CIN = 1 µF
CBypass = 10 nF
COUT = 1 µF
TSOT23-5L Package
TSC75-6L Package
Document Number: 74442
S-70067–Rev. B, 22-Jan-07
www.vishay.com
1
New Product
SiP21106/7/8
Vishay Siliconix
1
CIN=1µF
2
5
4
VIN
VOUT
VIN
VOUT
OUT = 1 µF
EN
1
2
3
POK
NC
6
5
4
POK
EN
C
GND
EN
GND
VIN
SiP21107
POK
EN
3
SiP21107
VOUT
POK
VIN
VOUT
CIN = 1 µF
COUT =1 µF
TSOT23-5L Package
TSC75L-6 Package
EN
1
2
3
Adj
NC
6
5
4
1
2
3
5
EN
VIN
VOUT
VIN
VOUT
CIN = 1 µF
COUT =1µF
GND
VIN
GND
EN
SiP21108
VOUT
SiP21108
EN
4
VIN
CIN = 1 µF
VOUT
Adj
C
OUT = 1 µF
TSC75-6L Package
TSOT23-5L Package
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
Unit
Input Voltage, VIN to GND
- 0.3 to 6
- 0.3 to 6
V
V
EN (See Detailed Description)
Output Current (IOUT
Output Voltage (VOUT
)
Short Circuit Protected
- 0.3 to VIN + 0.3
V
)
TSC75-6L
TSOT23-5L
440
Package Power Dissipation (PD)a
420
131
mW
b
Package Thermal Resistance (θJA
)
180
°C/W
Maximum Junction Temperature, TJ(max)
125
- 65 to 150
260
Storage Temperature, TSTG
°C
c
Lead Temperature, TL
Notes:
a. Derate 7.6 mW/°C for TSC75-6L package and 5.5 mW/°C for TSOT23-5L package above TA = 70 °C.
b. Device mounted with all leads soldered or welded to PC board.
c. Soldering for 5 sec.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Parameter
Limit
Unit
V
Input Voltage, VIN
2.2 to 5.5
- 40 to 85
Operating Ambient Temperature TA
°C
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2
Document Number: 74442
S-70067–Rev. B, 22-Jan-07
New Product
SiP21106/7/8
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
V
IN = VOUT(nom) + 1.0 V = VEN
IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF
- 40 °C < TA < 85 °C for full
Parameter
Symbol
Tempa Minb Typc Maxb Unit
Input Voltage Range
VIN
Full
2.2
5.5
1.0
2.5
V
Room - 1.0
Output Voltage Accuracy
Line Regulation
VOUT
VDO
VDO
IOUT = 1 mA
%
Full
Full
- 2.5
All others
- 0.2 0.006 0.2
%/V
mV
For 4.6 V to 5.0 V
- 0.4
0.4
Room
Full
45
55
IOUT = 50 mA
Dropout Voltaged
(2.2 V ≤ VOUT(nom) < 2.6 V)
Room
Full
90
I
I
OUT = 100 mA
OUT = 150 mA
IOUT = 50 mA
OUT = 100 mA
OUT = 150 mA
IOUT = 1 mA
106
135
160
45
Room
Full
250
300
Room
Full
55
Dropout Voltage
(VOUT(nom) ≥ 2.6 V)
Room
Full
90
I
I
mV
µA
106
135
160
35
Room
Full
180
220
75
Room
Full
85
Ground Pin Currente
IGND
Room
Full
39
75
I
OUT = 150 mA
SiP21106
85
V
V
OUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz, Room
1 mA < IOUT < 150 mA, CBP = 0.01 µF
60
µV
µV
Output Noise Voltagef (RMS)
Ripple Rejection
eN
SiP21107/8
OUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz, Room
1 mA < IOUT < 150 mA
350
f = 1 kHz
f = 10 kHz
f = 100 kHz
Room
Room
Room
70
55
25
PSRR
LDR
IOUT = 150 mA
dB
VOUT ≥ 2.6 V,
OUT : 1 mA to 150 mA
OUT < 2.6 V,
Room
0.003 0.006
I
I
Load Regulation
%/mA
V
Room
Room
Room
Room
0.005 0.009
OUT : 1 mA to 150 mA
Auto Discharge Resistance
RDIS
VOUT = 2 V
100
160
20
Ω
Thermal Shutdown Junction
Temperature
TJ(S/D)
°C
Thermal Hysteresis
THYST
IO_LIMIT
ICC(off)
VENH
Output Current Limit
Shutdown Supply Current
VOUT = 0 V
VEN = 0 V
Room 170
Full
330
600
1
mA
µA
0.02
High = Regulator ON (Rising)
Low = Regulator OFF (Falling)
Full
Full
1.2
5.5
0.4
EN Pin Input Voltage
V
VENL
EN Pin Input Current
IEN
ton
Room
0.009
70
µA
µs
EN to VOUT delay; IOUT = 1 mA
Output Voltage Turn-On Time
Document Number: 74442
S-70067–Rev. B, 22-Jan-07
www.vishay.com
3
New Product
SiP21106/7/8
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
V
IN = VOUT(nom) + 1.0 V
I
OUT = 1 mA, CIN = 1 µF, COUT = 1 µF
- 40 °C < TA < 85 °C for full
Parameter
Symbol
Tempa Minb Typc Maxb Unit
Adjustable Voltage Section (SiP21108 Version only)
Room 1.188 1.2 1.212
V
Feedback Voltage
VAdj
Full 1.170
1.230
Error Flag Section (SiP21107 Version only)
RPU to VOUT or VIN
ISINK = 0.5 mA
POK(OFF) Leakage
IOFF
Full
Full
1
µA
V
POK(ON) Voltage
POK Thresholdg
POK Hysteresis
VPOKL
VPOKLH
VHYST
0.4
96
VIN rising, IOUT = 1 mA, POK goes high
VIN falling, IOUT = 1 mA, POK goes low
Full
90
%
Room
1.5
Notes:
a. Room = 25 °C, Full = - 40 to 85 °C. Derate 7.6 mW/°C for TSC75 and 5.5 mW/°C for SOT23 above TA = 70 °C
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Dropout voltage is defined as the input-to-output differential voltage at which the output voltage drops 2 % below its nominal
value with constant load. For outputs = 2.2 V, dropout voltage is not applicable due to 2.2 V minimum input voltage requirement.
e. Ground current is specified for normal operation as well as “drop-out” operation.
f. Output noise is proportional to output voltage. Use formula eN = 60 µV(rms)*VOUT/2.8 V.
g. POK threshold percentage is calculated by VIN/VOUT x 100 %.
TIMING WAVEFORMS
V
V
IN
V
EN
t
r
1 µs
0 V
t
ON
NOM
0.95 V
NOM
V
OUT
Figure 1.
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Document Number: 74442
S-70067–Rev. B, 22-Jan-07
New Product
SiP21106/7/8
Vishay Siliconix
PIN CONFIGURATION
BP/Adj/POK
NC
EN
BP/Adj/POK
NC
EN
1
6
5
GND
GND
2
4
3
V
OUT
V
IN
V
V
IN
OUT
TOP VIEW
BOTTOM VIEW
TSC75-6L PACKAGE (1.6 x 1.6 x 0.6 mm)
V
V
IN
V
V
1
2
3
5
4
5
4
1
2
IN
OUT
OUT
GND
EN
GND
EN
3
BP/Adj/POK
BP/Adj/POK
TOP VIEW
BOTTOM VIEW
TSOT23-5L Package
Figure 2.
PIN DESCRIPTION
Pin Number
TSC75-6L
Pin Number
TSOT23-5L
Name
Function
By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to
EN
1
3
V
IN if unused. Do not leave floating.
2
3
4
5
2
1
5
-
GND
VIN
Ground pin. For better thermal capability, directly connected to large ground plane.
Input supply pin. Bypass this pin with a 1 µF ceramic or tantalum capacitor to ground.
VOUT
NC
Output voltage. Connect COUT between this pin and ground.
No Connection.
- BP (SiP21106): Noise bypass pin. For low noise applications, a 10 nF ceramic capacitor
should be connected from this pin to ground.
- Adj (SiP21108): Adjust input pin. Connect feedback resistors to program the output
voltage for trim value of 1.2005 V.
- POK (SiP21107): Power OK (Error Flag) pin. Open-drain output, which requires
connecting a pull-up resistor to VIN or VOUT. POK pin is actively high to indicate an output
normal operation condition on regulator and goes low to indicate under-voltage fault
condition.
6
4
BP/Adj/POK
Document Number: 74442
S-70067–Rev. B, 22-Jan-07
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5
New Product
SiP21106/7/8
Vishay Siliconix
ORDERING INFORMATION
Part Number
Marking
AA
BG
BP
BR
BT
Voltage
Adjustable
1.8
Temperature Range
Package
SiP21108DVP-T1-E3
SiP21106DVP-18-E3
SiP21106DVP-25-E3
SiP21106DVP-26-E3
SiP21106DVP-28-E3
SiP21106DVP-30-E3
SiP21106DVP-33-E3
SiP21106DVP-46-E3
SiP21106DVP-285-E3
SiP21107DVP-18-E3
SiP21107DVP-25-E3
SiP21107DVP-26-E3
SiP21107DVP-28-E3
SiP21107DVP-30-E3
SiP21107DVP-33-E3
SiP21107DVP-46-E3
SiP21107DVP-285-E3
SiP21108DT-T1-E3
SiP21106DT-18-E3
SiP21106DT-25-E3
SiP21106DT-26-E3
SiP21106DT-28-E3
SiP21106DT-285-E3
SiP21106DT-30-E3
SiP21106DT-33-E3
SiP21106DT-46-E3
SiP21107DT-18-E3
SiP21107DT-25-E3
SiP21107DT-26-E3
SiP21107DT-28-E3
SiP21107DT-285-E3
SiP21107DT-30-E3
SiP21107DT-33-E3
SiP21107DT-46-E3
2.5
2.6
2.8
BV
BY
CM
CT
DG
DP
DR
DT
DV
DY
3.0
3.3
4.6
2.85
1.8
- 40 °C to 85 °C
TSC75-6L
2.5
2.6
2.8
3.0
3.3
EM
ET
4.6
2.85
Adjustable
1.8
N9
N1
NA
NC
N2
2.5
2.6
2.8
NE
NG
N3
2.85
3.0
3.3
N4
4.6
- 40 °C to 85 °C
TSOT23-5L
N5
1.8
NB
ND
N6
2.5
2.6
2.8
NF
NH
N7
2.85
3.0
3.3
N8
4.6
Note:
Other fixed output voltage options are available. Please contact your Vishay sales representative or distributor for details.
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6
Document Number: 74442
S-70067–Rev. B, 22-Jan-07
New Product
SiP21106/7/8
Vishay Siliconix
TYPICAL CHARACTERISTICS
3.00
1.00
2.50
0.50
0.00
2.00
IOUT = 1 mA
IOUT = 0 mA
1.50
IOUT = 150 mA
- 0.50
- 1.00
- 1.50
1.00
0.50
0.00
SiP21106: 2.8 V
SiP21106: 2.8 V
- 40
- 15
10
Temperature (°C)
Output Voltage Accuracy vs. Temperature
35
60
85
0.00
1.00
2.00
3.00
IN(V)
4.00
5.00
V
Output Voltage vs. Input Voltage
180
180
160
140
120
100
80
SiP21106: 2.8 V
160
140
120
100
80
TA = + 85 °C
IOUT = 150 mA
TA = + 25 °C
60
IOUT = 100 mA
40
TA = - 40 °C
20
SiP21106: 2.8 V
100 125 150
0
60
2
2.5
3
3.5
4
4.5
5
0
25
50
75
IOUT (mA)
(V)
VOUT
Dropout Voltage vs. Output Voltage
Dropout Voltage vs. Load Current
180
160
140
120
100
80
41
40
39
38
37
36
35
34
IOUT = 150 mA
IOUT = 150 mA
IOUT = 100 mA
IOUT = 1 mA
60
IOUT = 50 mA
40
SiP21106: 2.8 V
60
SiP21106: 2.8 V
60 85
20
- 40
- 40
- 15
10
Temperature (°C)
Ground Current vs. Temperature
35
85
- 15
10
Temperature (°C)
Dropout Voltage vs. Temperature
35
Document Number: 74442
S-70067–Rev. B, 22-Jan-07
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New Product
SiP21106/7/8
Vishay Siliconix
TYPICAL CHARACTERISTICS
50
40
30
20
10
0
50
VIN = 5.5 V
IOUT = 150 mA
IOUT = 1 mA
45
VIN = 3.8 V
40
35
30
25
SiP21106: 2.8 V
SiP21106: 2.8 V
0
25
50
75
100
125
150
0.0
1.0
2.0
3.0
4.0
5.0
(mA)
IOUT
VIN (V)
Ground Current vs. Output Current
Ground Current vs. Input Voltage at 25 °C
2.820
2.800
2.780
2.760
2.740
2.720
80
70
60
50
40
30
20
10
IOUT = 150 mA
SiP21106: 2.8 V
IN = 3.8 V
SiP21106: 2.8 V
IN = 3.8 V
OUT = 3.0 V
V
V
V
C
IN = 1 µF
IOUT = 1 mA
COUT = 1 µF
CBP = 10 nF
IOUT = 0 mA
IOUT = 100 mA
IOUT = 50 mA
IOUT = 150 mA
0
-10
- 40
- 15
10
35
60
85
0.01K
0.1K
1K
100K
10K
1000K
Temperature (°C)
Output Voltage Accuracy vs. Load Current
Frequency (Hz)
PSRR
400
SiP21106: 2.8 V
350
300
250
200
150
100
50
0
0.001
0.0056
0.01
0.056
0.1
BP Capacitance (µF)
Output Noise vs. BP Capacitance
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Document Number: 74442
S-70067–Rev. B, 22-Jan-07
New Product
SiP21106/7/8
Vishay Siliconix
TYPICAL OPERATING WAVEFORMS
I
(100 mA/DIV)
OUT
I
(100 mA/DIV)
OUT
V
(50 mV/DIV)
OUT
V
(50 mV/DIV)
OUT
SiP21106: 2.8 V
SiP21106: 4.6 V
V
V
C
C
C
= 3.8 V
= 2.8 V
= 1 µF
IN
OUT
V
= 5.5 V
IN
V
= 4.6 V
= 1 µF
OUT
IN
C
C
C
IN
= 1 µF
OUT
= 1 µF
OUT
= 10 nF
BP
= 10 nF
BP
50 µS/DIV
50 µS/DIV
Load Transient Response
Load Transient Response
SiP21106: 2.8 V
SiP21106: 4.6 V
V
V
= 3.8 to 4.8 V
V
V
I
= 5.0 to 5.5 V
IN
IN
= 2.8 V
= 4.6 V
OUT
OUT
I
= 150 mA
= 150 mA
OUT
OUT
C
C
= 1 µF
C
C
C
= 1 µF
IN
IN
OUT
= 1 µF
= 1 µF
COUT= 10 nF
= 10 nF
BP
BP
V
(1 V/DIV)
IN
AC Coupling
AC Coupling
V
(200 mV/DIV)
IN
V
(10 mV/DIV)
OUT
V
(10 mV/DIV)
OUT
200 µS/DIV
200 µS/DIV
Line Transient Response
Line Transient Response
SiP21106: 2.8 V
= 3.8 to 4.8 V
SiP21106: 4.6 V
V
IN
V
= 5.0 to 5.5 V
IN
V
= 2.8 V
OUT
V
= 4.6 V
= 1 mA
OUT
I
= 1 mA
I
OUT
OUT
C
C
C
= 1 µF
= 1 µF
C
= 1 µF
IN
OUT
IN
OUT
C
= 1 µF
= 10 nF
= 10 nF
C
BP
BP
V
(1 V/DIV)
IN
AC Coupling
AC Coupling
(200 mV/DIV)
V
IN
V
(10 mV/DIV)
OUT
V
(10 mV/DIV)
OUT
200 µS/DIV
200 µS/DIV
Line Transient Response
Line Transient Response
Document Number: 74442
S-70067–Rev. B, 22-Jan-07
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9
New Product
SiP21106/7/8
Vishay Siliconix
TYPICAL OPERATING WAVEFORMS
SiP21106: 2.8 V
SiP21106: 2.8 V
V
V
= 3.8 V
IN
V
= 3.8 V
IN
= 2.8 V
OUT
V
= 2.8 V
= 1 µF
OUT
C
C
= 1 µF
IN
C
C
C
IN
= 1 µF
COUT= 10 nF
= 1 µF
OUT
BP
= 10 nF
BP
I
(100 mA/DIV)
OUT
I
(50 mA/DIV)
OUT
50 mS/DIV
Output Short Circuit Current
50 mS/DIV
Output Short Thermal Cycling
SiP21106: 2.8 V
V
V
C
C
C
= 3.8 V
IN
SiP21106: 2.8 V
IN
= 2.8 V
OUT
V
V
= 3.8 V
= 1 µF
IN
= 2.8 V
= 1 µF
OUT
= 1 µF
OUT
C
C
C
= 10 nF
IN
BP
= 1 µF
OUT
BP
I
= 150 mA
OUT
V
(1 V/DIV)
EN
= 10 nF
V
(500 mV/DIV)
EN
I
= 150 mA
OUT
V
(500 mV/DIV)
OUT
V
(500 mV/DIV)
OUT
20 µS/DIV
Output Voltage Power-Down
20 µS/DIV
Output Voltage Start-Up
TYPICAL WAVEFORMS
1
0.1
SiP21106: 2.8 V
SiP21106: 2.8 V
V
V
= 3.8 V
V
V
C
C
C
I
= 4.5 V
IN
IN
= 2.8 V
= 2.8 V
OUT
OUT
C
= 1 µF
= 1 µF
IN
IN
C
C
= 1 µF
= 10 nF
= 1 µF
OUT
V
V
(100 µV/DIV)
= 60 µV
OUT
OUT
= 10 nF
= 150 mA
BP
BP
I
= 100 mA
OUT
OUT
NOISE
RMS
0.01
10
2 ms/DIV
Output Noise
100
1K
Frequency (Hz)
Output Noise Spectral Density
10K
100K
1M
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Document Number: 74442
S-70067–Rev. B, 22-Jan-07
New Product
SiP21106/7/8
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
Enable
Error-Amp
Bandgap
Reference
*
** ***
BP/Adj/POK
VOUT
Current Limit &
Thermal
POK
Ref
SiP21106: BP
SiP21107: POK
SiP21108: Adj
SiP21106: BP
SiP21107: POK
SiP21108: Adj
*
***
**
GND
Figure 3.
Document Number: 74442
S-70067–Rev. B, 22-Jan-07
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11
New Product
SiP21106/7/8
Vishay Siliconix
DETAILED DESCRIPTION
Output Voltage Selection
The SiP21106 has fixed voltage outputs that are preset to
voltages from 1.8 V to 4.6 V (see Ordering Information).
As shown in the block diagram, the circuit consists of a band-
gap reference, error amplifier, P-Channel pass transistor and
an internal feedback resistor voltage divider, which is used to
monitor and control the output voltage.
V
IN
A constant 1.2 V bandgap reference voltage is applied to the
non-inverting input of the error amplifier. The error amplifier
compares this reference with the feedback voltage on its
inverting input and amplifies the difference. If the feedback
voltage is lower than the reference voltage, the pass-transis-
tor gate is pulled low. This increases the PMOS's gate to
source voltage and allows more current to pass through the
transistor to the output which increases the output voltage.
Conversely, if the feedback voltage is higher than the refer-
ence voltage, the pass transistor gate is pulled high,
decreasing the gate-to-source voltage, thereby allowing less
current to pass to the output and causing it to drop.
1.2 V
Reference
+
Error-Amp
V
OUT
-
R
R
1
2
Figure 4.
The SiP21108 has a user-adjustable output that can be set
through the resistor feedback network consisting of R1 and
R2. R2 range of 100K to 400K is recommended to be
consistent with ground current specification. R1 can then be
determined by the following equation:
Internal P-Channel Pass Transistor
A 0.9 Ω (typical) P-Channel MOSFET is used as the pass
transistor for the SiP21106/7/8 part series. The MOSFET
transistor offers many advantages over the more, formerly,
common PNP pass transistor designs, which ultimately
result in longer battery lifetime. The main disadvantage of
PNP pass transistors is that they require a certain base cur-
rent to stay on, which significantly increases under heavy
load conditions. In addition, during dropout, when the pass
transistor saturates, the PNP regulators waste considerable
current. In contrast, P-Channel MOSFETS require virtually
zero-base drive and do not suffer from the stated problems.
These savings in base drive current translate to lower quies-
cent current which is typical around 35 µA as shown in the
Typical Characteristics.
VOUT
(
)
- 1
R1 = R2 x
Vref
Where Vref is typically 1.2005 V. Use 1 % or better resistors
for better output voltage accuracy (see Figure 4).
Current Limit
The SiP21106/7/8 include a current limit block which moni-
tors the current passing through the pass transistor through
a current mirror and controls the gate voltage of the MOS-
FET, limiting the output current to 330 mA (typical). This cur-
rent limit feature allows for the output to be shorted to ground
for an indefinite amount of time without damaging the device.
Shutdown and Auto-Dischage/No-Discharge
Bringing the EN voltage low will place the part in shutdown
mode where the device output enters a high-impedance
state and the quiescent current is reduced to below 1 µA,
reducing the drain on the battery in standby mode and
increasing standby time. Connect EN pin to input for normal
operation. The output has an internal pull down to discharge
the output to ground when the EN pin is low. The internal pull
down is a 100 Ω typical resistor, which can discharge a 1 µF
in less than 1 ms. Refer to Typical Operating Waveforms for
turn-off waveforms.
Thermal-Overload Protection
The thermal overload protection limits the total power dissi-
pation and protects the device from being damaged. When
the junction temperature exceeds TJ = 150 °C, the device
turns the P-Channel pass transistor off allowing the device to
cool down. Once the temperature drops by about 20 °C, the
thermal sensor turns the pass transistor on again and
resumes normal operation. Consequently, a continuous ther-
mal overload condition will result in a pulsed output. It is gen-
erally recommended to not exceed the junction temperature
rating of 125 °C for continuous operation.
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Document Number: 74442
S-70067–Rev. B, 22-Jan-07
New Product
SiP21106/7/8
Vishay Siliconix
Noise Reduction in SiP21106
Operating Region and Power Dissipation
For the SiP21106, an external 10 nF bypass capacitor at BP
pin is used to create a low pass filter for noise reduction. The
startup time is fast, since a power-on circuit pre-charges the
bypass capacitor. After the power-up sequence the pre-
charge circuit is switched to standby mode in order to save
current. It is therefore not recommended to use larger
bypass capacitor values than 50 nF. When the circuit is used
without a capacitor, stable operation is guaranteed.
An important consideration when designing power supplies
is the maximum allowable power dissipation of a part. The
maximum power dissipation in any application is dependant
on the maximum junction temperature, TJ(max) = 125 °C, the
ambient temperature, TA, and the junction-to-ambient ther-
mal resistance for the package, which is the summation of
θJ-C, the thermal resistance of the package, and θC-A , the
thermal resistance through the PC board and copper traces.
Power dissipation may be formulaically expressed as:
POK Status in SiP21107
The POK comparator monitors the output until the supply
comes up to specified percentage of VIN. This open drain
NMOS output requires an external pull-up resistor to either
VOUT or VIN. The internal NMOS can drive up to 0.5 mA
loads. POK pin is actively high to indicate an output normal
operation condition on regulator and goes low to indicate
under-voltage on regulator.
T
- T
A
(max)
J
P
(max)
=
θ J-C + θ C-A
The GND pin of the SiP21106/7/8 acts as both the electrical
connection to GND as well as a path for channeling away
heat. Connect this pin to a GND plane to maximize heat dis-
sipation.Once maximum powChanneler dissipation is calcu-
lated using the equation above, the maximum allowable
output current for any input/output potential can be calcu-
lated as
APPLICATION INFORMATION
Input/Output Capacitor Selection and Regulator
Stability
It is recommended that a low ESR 1 µF capacitor be used on
the SiP21106/7/8 input. A larger input capacitance with lower
ESR would improve noise rejection and line-transient
response. A larger input bypass capacitor may be required in
applications involving long inductive traces between the
source and LDO. The circuit is stable with only a small output
capacitor equal to 6 nF/mA (≈ 1 µF at 150 mA) of load. Since
the bandwidth of the error amplifier is around 1 - 3 MHz and
the dominant pole is at the output node, the capacitor should
be capacitive in this range, i.e., for 150 mA load current, an
ESR < 0.4 Ω is necessary. Parasitic inductance of about
10 nH can be tolerated. Applying a larger output capacitor
would increase power supply rejection and improve load-
transient response. Some ceramic dielectrics such as the
Z5U and Y5V exhibit large capacitance and ESR variation
over temperature. If such capacitors are used, a 2.2 µF or
larger value may be needed to ensure stability over the
industrial temperature range. If using higher quality ceramic
capacitors, such as those with X7R and Y7R dielectrics, a
1 µF capacitor will be sufficient at all operating temperatures.
P(max)
IOUT(max)
=
VIN - VOUT
PCB Layout
The component placement around the LDO should be done
carefully to achieve good dynamic line and load response.
The input and noise capacitor should be kept close to the
LDO. The rise in junction temperature depends on how effi-
ciently the heat is carried away from junction-to-ambient. The
junction-to-lead thermal impedance is a characteristic of the
package and is fixed. The thermal impedance between lead-
to-ambient can be reduced by increasing the copper area on
PCB. Increase the input, output and ground trace area to
reduce the junction-to-ambient thermal impedance.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see http://www.vishay.com/ppg?74442.
Document Number: 74442
S-70067–Rev. B, 22-Jan-07
www.vishay.com
13
相关型号：
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VISHAY
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