SIP21108DR-T1-E3 [VISHAY]
150-mA Low Noise, Low Dropout Regulator; 150 mA的低噪声，低压差稳压器
| 型号： | SIP21108DR-T1-E3 |
| 厂家： | 
VISHAY |
| 描述： | 150-mA Low Noise, Low Dropout Regulator |
| 文件： | 总19页 (文件大小：570K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiP21106, SiP21107, SiP21108
Vishay Siliconix
150-mA Low Noise, Low Dropout Regulator
DESCRIPTION
FEATURES
The SiP21106 BiCMOS 150 mA low noise LDO voltage
regulators are the perfect choice for low battery operated low
powered applications. An ultra low ground current and low
dropout voltage of 135 mV at 150 mA load helps to extend
battery life for portable electronics. Systems requiring a quiet
voltage source, such as RF applications, will benefit from the
SiP21106 low output noise.
The SiP21107 do not require a noise bypass capacitor and
provides an error flag pin (POK or Power OK). POK output
requires an external pull-up resistor and goes low when the
supply has not come up to voltage.
•
•
•
SC70-5L (2.1 mm x 2.1 mm x 0.95 mm)
TSOT23-5L (3.05 mm x 2.85 mm x 1.0 mm)
TSC75-6L package (1.6 mm x 1.6 mm
x 0.55 mm), TSOT23-5L and SC70-5L
Package Options
RoHS
COMPLIANT
•
•
•
1.0 % output voltage accuracy at 25 °C
Low dropout voltage: 135 mV at 150 mA
SiP21106 low noise: 60 µV(rms) (10 Hz to 100 kHz
bandwidth) with 10 nF over full load range
35 µA (typical) ground current at 1 mA load
1 µA maximum shutdown current at 85 °C
Output auto discharge at shutdown mode
Built-in short circuit (330 mA typical) and thermal
protection (160 °C typical)
SiP21108 adjustable output voltage
SiP21107 POK Error Flag
- 40 °C to + 125 °C junction temperature range for
operation
Uses low ESR ceramic capacitors
•
•
•
•
The SiP21108 output is adjusted with an external resistor
network.
The SiP21106, SiP21107, SiP21108 regulators allow stable
operation with very small ceramic output capacitors,
reducing board space and component cost. They are
designed to maintain regulation while delivering 330 mA
peak current upon turn-on. During start-up, an active
pull-down circuit improves the output transient response and
regulation. In shutdown mode, the output automatically
discharges to ground through a 100 Ω NMOS.
The SiP21106, SiP21107, SiP21108 are available in
TSOT23-5L a super thin lead (Pb)-free TSC75-6L and
SC70-5L packages for operation over the industrial operation
range (- 40 °C to 85 °C).
•
•
•
•
•
•
Fixed voltage output 1.2 V to 5 V in 50 mV steps
Compliant to RoHS Directive 2002/95/EC
APPLICATIONS
•
•
•
•
•
•
Cellular phones, wireless handsets
PDAs
MP3 players
Digital cameras
Pagers
Wireless modem
• Noise-sensitive electronic systems
TYPICAL APPLICATION CIRCUIT
1
2
3
5
VIN
VOUT
VOUT
EN
VIN
BP
NC
EN
C
OUT = 1 µF
CIN = 1 µF
CBypass = 10 nF
GND
EN
GND
VIN
SiP21106
SiP21106
EN
4
BP
VIN
VOUT
VOUT
CIN = 1 µF
CBypass = 10 nF
COUT = 1 µF
TSOT23-5L/SC70-5LPackage
TSC75-6L Package
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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1
SiP21106, SiP21107, SiP21108
Vishay Siliconix
TYPICAL APPLICATION CIRCUIT
1
CIN=1µF
2
5
4
EN
VIN
VOUT
POK
NC
POK
VOUT
EN
C
OUT = 1 µF
GND
EN
GND
VIN
SiP21107
POK
SiP21107
VOUT
3
VIN
POK
VOUT
CIN = 1 µF
COUT =1 µF
TSOT23-5L/SC70-5LPackage
TSC75L-6 Package
EN
Adj
1
2
3
5
EN
VIN
VOUT
VIN
VOUT
CIN = 1 µF
COUT =1µF
GND
NC
GND
EN
SiP21108
VOUT
SiP21108
EN
4
VIN
VIN
VOUT
Adj
CIN = 1 µF
C
OUT = 1 µF
TSC75-6L Package
TSOT23-5L/SC70-5L Package
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
- 0.3 to 6.5
- 0.3 to 6.5
Short Circuit Protected
- 0.3 to VIN + 0.3
TSOT23-5L
305
Unit
Input Voltage, VIN to GND
V
V
EN (See Detailed Description)
Output Current (IOUT
Output Voltage (VOUT
)
V
)
TSC75-6L
SC70-5L
187
Package Power Dissipation (PD)a
420
131
mW
b
Package Thermal Resistance (θJA
)
180
294
°C/W
Maximum Junction Temperature, TJ(max)
Storage Temperature, TSTG
125
- 65 to 150
260
°C
c
Lead Temperature, TL
Notes:
a. Derate 7.6 mW/°C for TSC75-6L package, 5.5 mW/°C for TSOT23-5L and 3.4 mW/°C for SC70-5L package above TA = 70 °C.
b. Device mounted with all leads soldered or welded to multilayer 1S2P PC board.
c. Soldering for 5 s.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Parameter
Limit
2.2 to 6
- 40 to 85
Unit
V
Input Voltage, VIN
Operating Ambient Temperature TA
°C
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
SiP21106, SiP21107, SiP21108
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
IN = VOUT(nom) + 1.0 V = VEN
V
IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF
- 40 °C < TA < 85 °C for full
Parameter
Symbol
Temp.a Min.b Typ.c Max.b Unit
Input Voltage Range
VIN
Full
Room - 1.0
Full - 2.5
Room - 1.5
Full - 4
Room 1.188
2.2
6
1.0
V
IOUT = 1 mA
2.5
Output Voltage Accuracy
VOUT
%
1.5
SiP21106/7 (1.2 V) IOUT = 1 mA
4
1.2
1.212
1.230
0.2
Feedback Voltage
(SiP21108 Version only)
VAdj
V
Full
Full
1.170
- 0.2 0.006
Line Regulation
Load Regulation
LNR
%/V
VOUT ≥ 2.6 V,
OUT: 1 mA to 150 mA
Room
Room
0.003 0.006
0.005 0.009
I
I
LDR
%/mA
VOUT < 2.6 V,
OUT: 1 mA to 150 mA
Room
Full
35
39
75
85
75
85
1
IOUT = 1 mA
Ground Pin Currente
IGND
µA
µA
Room
Full
I
OUT = 150 mA
VEN = 0 V
SiP21106
Shutdown Supply Current
ICC(off)
Full
0.02
60
V
OUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz, Room
1 mA < IOUT < 150 mA, CBP = 0.01 µF
Output Noise Voltagef (RMS)
Output Voltage Turn-On Time
eN
µV
µs
SiP21107/8
V
OUT(nom) = 2.8 V, BW = 10 Hz to 100 kHz, Room
1 mA < IOUT < 150 mA
350
EN to VOUT delay; IOUT = 1 mA
ton
70
75
f = 1 kHz
f = 10 kHz
f = 100 kHz
f = 1 kHz
Room
Room
Room
Room
Room
Room
Room 170
Room
Room
Room
Full
SiP21106, CBP = 0.01 µF
56
I
OUT = 10 mA
40
Ripple Rejection
PSRR
dB
72
SiP21107/8
SiP21106, CBP = 0 µF
OUT = 10 mA
VOUT = 0 V
f = 10 kHz
f = 100 kHz
53
I
38
Output Current Limit
IO_LIM
RDIS
330
100
120
45
600
mA
EN = 0 V, VOUT = 1 V
Auto Discharge Resistance
Ω
For VOUT < 2.2 V, EN = 0 V, VOUT = 1 V
IOUT = 50 mA
55
Dropout Voltaged
(2.2 V ≤ VOUT(nom) < 2.6 V)
Room
Full
90
VDO
I
I
OUT = 100 mA
OUT = 150 mA
IOUT = 50 mA
OUT = 100 mA
OUT = 150 mA
106
135
160
45
Room
Full
250
300
mV
Room
Full
55
Dropout Voltage
(VOUT(nom) ≥ 2.6 V)
Room
Full
90
VDO
I
I
106
135
160
Room
Full
180
220
VENH
VENL
High = Regulator On (Rising)
Low = Regulator Off (Falling)
Full
Full
1.2
EN Pin Input Voltage
EN Pin Input Current
V
0.4
IEN
Room
0.009
µA
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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SiP21106, SiP21107, SiP21108
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
IN = VOUT(nom) + 1.0 V
V
IOUT = 1 mA, CIN = 1 µF, COUT = 1 µF
- 40 °C < TA < 85 °C for full
Parameter
Symbol
TJ(S/D)
THYST
Temp.a Min.b Typ.c Max.b Unit
Thermal Shutdown Junction Temperature
Thermal Hysteresis
Room
Room
160
20
°C
Error Flag Section (SiP21107 Version only)
RPU to VOUT or VIN
POK(OFF) Leakage
POK(ON) Voltage
IOFF
Full
Full
1
µA
V
EN = 0 V, IPOK = 0.5 mA
VPOKL
0.4
VOUT rising, POK goes high
90
93
91
96
VOUT(nom) ≥ 2.2 V, IOUT = 1 mA
POK Thresholdg
VPOKLH
Full
VOUT rising, POK goes high
%
VOUT(nom) < 2.2 V, IOUT = 1 mA
VIN falling, IOUT = 1 mA, POK goes low
VOUT to POK delay, IOUT = 1 mA
POK Hysteresis
VHYST
Room
1.5
40
POK Voltage Delay Time
TP_Delay
µs
Notes:
a. Room = 25 °C, Full = - 40 to 85 °C. Derate 7.6 mW/°C for TSC75 and 5.5 mW/°C for SOT23 above TA = 70 °C.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Dropout voltage is defined as the input-to-output differential voltage at which the output voltage drops 2 % below its nominal
value with constant load. For outputs = 2.2 V, dropout voltage is not applicable due to 2.2 V minimum input voltage requirement.
e. Ground current is specified for normal operation as well as “drop-out” operation.
f. Output noise is proportional to output voltage. Use formula eN = 60 µV(rms)*VOUT/2.8 V.
g. POK threshold percentage is calculated by VIN/VOUT x 100 %. The POK is measured with a differential voltage across VIN and VOUT until POK
turn on (low threshold) or off (high threshold). For VOUT less than 2.2 V, POK is guaranteed functionality only.
TIMING WAVEFORMS
V
IN
V
EN
t
r
1 µs
0 V
t
ON
V
NOM
0.95 V
NOM
V
OUT
Figure 1.
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
SiP21106, SiP21107, SiP21108
Vishay Siliconix
PIN CONFIGURATION
BP/Adj/POK
EN
BP/Adj/POK
EN
6
5
1
2
NC
GND
GND
NC
4
3
V
OUT
V
IN
V
V
IN
OUT
TOP VIEW
BOTTOM VIEW
TSC75-6L Package (1.6 mm x 1.6 mm x 0.55 mm)
V
V
IN
V
V
1
2
3
5
4
5
4
1
2
IN
OUT
OUT
GND
EN
GND
EN
3
BP/Adj/POK
BP/Adj/POK
TOP VIEW
BOTTOM VIEW
TSOT23-5L/SC70-5LPackage
Figure 2.
PIN DESCRIPTION
Pin Number
Pin Number
TSC75-6L
TSOT23-5L/
SC70-5L
Name
Function
By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to
IN if unused. Do not leave floating.
EN
1
3
V
2
3
4
5
2
1
5
-
GND
VIN
Ground pin. For better thermal capability, directly connected to large ground plane.
Input supply pin. Bypass this pin with a 1 µF ceramic or tantalum capacitor to ground.
VOUT
NC
Output voltage. Connect COUT between this pin and ground.
No Connection.
- BP (SiP21106): Noise bypass pin. For low noise applications, a 10 nF ceramic capacitor
should be connected from this pin to ground.
- Adj (SiP21108): Adjust input pin. Connect feedback resistors to program the output
voltage for trim value of 1.2005 V.
- POK (SiP21107): Power OK (error flag) pin. Open-drain output, which requires
connecting a pull-up resistor to VIN or VOUT. POK pin is actively high to indicate an output
normal operation condition on regulator and goes low to indicate under-voltage fault
condition.
6
4
BP/Adj/POK
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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SiP21106, SiP21107, SiP21108
Vishay Siliconix
ORDERING INFORMATION
Part Number
Marking
Voltage
Temperature Range
Package
SiP21108DVP-T1-E3
AA
Adjustable
SiP21106DVP-12-E3
SiP21106DVP-18-E3
SiP21106DVP-25-E3
SiP21106DVP-26-E3
SiP21106DVP-28-E3
SiP21106DVP-285-E3
SiP21106DVP-30-E3
SiP21106DVP-33-E3
SiP21106DVP-46-E3
SiP21106DVP-475-E3
SiP21107DVP-12-E3
SiP21107DVP-18-E3
SiP21107DVP-25-E3
SiP21107DVP-26-E3
SiP21107DVP-28-E3
SiP21107DVP-30-E3
SiP21107DVP-33-E3
SiP21107DVP-46-E3
SiP21107DVP-285-E3
SiP21108DT-T1-E3
SiP21106DT-12-E3
SiP21106DT-18-E3
SiP21106DT-25-E3
SiP21106DT-26-E3
SiP21106DT-28-E3
SiP21106DT-285-E3
SiP21106DT-30-E3
SiP21106DT-33-E3
SiP21106DT-45-E3
SiP21106DT-46-E3
SiP21106DT-475-E3
SiP21107DT-12-E3
SiP21107DT-18-E3
SiP21107DT-25-E3
SiP21107DT-26-E3
SiP21107DT-28-E3
SiP21107DT-285-E3
SiP21107DT-30-E3
SiP21107DT-33-E3
SiP21107DT-46-E3
BA
BG
BP
BR
BT
CT
BV
BY
CM
CU
DA
DG
DP
DR
DT
DV
DY
EM
ET
N9
NP
N1
NA
NC
N2
NE
NG
N3
NM
N4
NJ
1.2
1.8
2.5
2.6
2.8
2.85
3
3.3
4.6
4.75
1.2
1.8
2.5
2.6
2.8
3
- 40 °C to 85 °C
TSC75-6L
3.3
4.6
2.85
Adjustable
1.2
1.8
2.5
2.6
2.8
2.85
3
3.3
4.5
4.6
4.75
1.2
1.8
2.5
2.6
2.8
2.85
3
- 40 °C to 85 °C
TSOT23-5L
NQ
N5
NB
ND
N6
NF
NH
N7
N8
3.3
4.6
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
SiP21106, SiP21107, SiP21108
Vishay Siliconix
ORDERING INFORMATION
SiP21108DR-T1-E3
SiP21106DR-12-E3
SiP21106DR-18-E3
SiP21106DR-25-E3
SiP21106DR-26-E3
SiP21106DR-28-E3
SiP21106DR-285-E3
SiP21106DR-30-E3
SiP21106DR-33-E3
SiP21106DR-46-E3
SiP21106DR-475-E3
SiP21107DR-12-E3
SiP21107DR-18-E3
SiP21107DR-25-E3
SiP21107DR-26-E3
SiP21107DR-28-E3
SiP21107DR-285-E3
SiP21107DR-30-E3
SiP21107DR-33-E3
SiP21107DR-46-E3
N9
NP
N1
NA
NC
N2
NE
NG
N3
N4
NJ
Adjustable
1.2
1.8
2.5
2.6
2.8
2.85
3
3.3
4.6
- 40 °C to 85 °C
SC70-5L
4.75
1.2
NQ
N5
NB
ND
N6
NF
NH
N7
N8
1.8
2.5
2.6
2.8
2.85
3
3.3
4.6
Note:
Other fixed output voltage options are available. Please contact your Vishay sales representative or distributor for details.
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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SiP21106, SiP21107, SiP21108
Vishay Siliconix
TYPICAL CHARACTERISTICS
3.0
2.5
1.00
0.50
2.0
IOUT = 1 mA
IOUT = 0 mA
0.00
1.5
IOUT = 150 mA
- 0.50
- 1.00
- 1.50
1.0
0.5
SiP21106: 2.8 V
60
SiP21106: 2.8 V
0.0
0
1
2
3
4
5
6
- 40
- 15
10
35
85
VIN(V)
Temperature (°C)
Output Voltage vs. Input Voltage
Output Voltage Accuracy vs. Temperature
180
160
140
120
100
80
180
160
140
120
100
80
SiP21106: 2.8 V
TA = + 85 °C
TA = + 25 °C
IOUT = 150 mA
60
IOUT
= 100 mA
40
TA = - 40 °C
20
SiP21106: 2.8 V
100 125 150
0
60
2.0
0
25
50
75
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
6.0
IOUT (mA)
V
IN
Dropout Voltage vs. Input Voltage
Dropout Voltage vs. Load Current
180
160
140
120
100
80
41
40
39
38
37
36
35
34
IOUT = 150 mA
IOUT = 150 mA
IOUT = 100 mA
IOUT = 1 mA
60
IOUT = 50 mA
40
SiP21106: 2.8 V
60 85
SiP21106: 2.8 V
60 85
20
- 40
- 40
- 15
10
Temperature (°C)
Ground Current vs. Temperature
35
- 15
10
Temperature (°C)
Dropout Voltage vs. Temperature
35
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
SiP21106, SiP21107, SiP21108
Vishay Siliconix
TYPICAL CHARACTERISTICS
50
50
VIN = 5.5 V
IOUT = 150 mA
40
45
VIN = 3.8 V
IOUT = 1 mA
30
20
10
0
40
35
30
25
SiP21106: 2.8 V
SiP21106: 2.8 V
100 125 150
0
1
2
3
4
5
6
0
25
50
75
(mA)
IOUT
VIN (V)
Ground Current vs. Output Current
Ground Current vs. Input Voltage at 25 °C
80
70
60
50
40
30
20
10
0
2.820
2.800
2.780
2.760
2.740
2.720
SiP21106
BP = 10 nF
IOUT = 10 mA
SiP21106: 2.8 V
C
VIN = 3.8 V
IOUT = 1 mA
IOUT = 50 mA
IOUT = 150 mA
10
100
1000
10 000
100 000
1 000 000
- 40
- 15
10
Temperature (°C)
Output Voltage Accuracy vs. Load Current
35
60
85
Frequency (Hz)
PSRR
400
350
300
250
200
150
100
50
SiP21106: 2.8 V
0
0.001
0.0056
0.01
0.056
0.1
BP Capacitance (µF)
Output Noise vs. BP Capacitance
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
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SiP21106, SiP21107, SiP21108
Vishay Siliconix
TYPICAL OPERATING WAVEFORMS
I
(100 mA/DIV)
OUT
I
(100 mA/DIV)
OUT
V
(50 mV/DIV)
OUT
V
(50 mV/DIV)
OUT
SiP21106: 2.8 V
SiP21106: 4.6 V
V
V
C
C
C
= 3.8 V
= 2.8 V
= 1 µF
IN
OUT
V
= 5.5 V
IN
V
= 4.6 V
= 1 µF
OUT
IN
C
C
C
IN
= 1 µF
OUT
= 1 µF
OUT
= 10 nF
BP
= 10 nF
BP
50 µs/DIV
50 µs/DIV
Load Transient Response
Load Transient Response
SiP21106: 2.8 V
SiP21106: 4.6 V
V
V
= 3.8 to 4.8 V
V
V
I
= 5.0 to 5.5 V
IN
IN
= 2.8 V
= 4.6 V
OUT
OUT
I
= 150 mA
= 150 mA
OUT
OUT
C
C
= 1 µF
C
C
C
= 1 µF
IN
IN
OUT
= 1 µF
= 1 µF
COUT= 10 nF
= 10 nF
BP
BP
V
(1 V/DIV)
IN
AC Coupling
AC Coupling
V
(200 mV/DIV)
IN
V
(10 mV/DIV)
OUT
V
(10 mV/DIV)
OUT
200 µs/DIV
200 µs/DIV
Line Transient Response
Line Transient Response
SiP21106: 2.8 V
= 3.8 to 4.8 V
SiP21106: 4.6 V
V
IN
V
= 5.0 to 5.5 V
IN
V
= 2.8 V
OUT
V
= 4.6 V
= 1 mA
OUT
I
= 1 mA
I
OUT
OUT
C
C
C
= 1 µF
= 1 µF
C
= 1 µF
IN
OUT
IN
OUT
C
= 1 µF
= 10 nF
= 10 nF
C
BP
BP
V
(1 V/DIV)
IN
AC Coupling
AC Coupling
(200 mV/DIV)
V
IN
V
(10 mV/DIV)
OUT
V
(10 mV/DIV)
OUT
200 µs/DIV
200 µs/DIV
Line Transient Response
Line Transient Response
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
SiP21106, SiP21107, SiP21108
Vishay Siliconix
TYPICAL OPERATING WAVEFORMS
SiP21106: 2.8 V
SiP21106: 2.8 V
V
V
= 3.8 V
IN
V
= 3.8 V
IN
= 2.8 V
OUT
V
= 2.8 V
= 1 µF
OUT
C
C
= 1 µF
IN
C
C
C
IN
= 1 µF
COUT= 10 nF
= 1 µF
OUT
BP
= 10 nF
BP
I
(100 mA/DIV)
OUT
I
(50 mA/DIV)
OUT
50 ms/DIV
Output Short Circuit Current
50 ms/DIV
Output Short Thermal Cycling
SiP21106: 2.8 V
V
V
C
C
C
= 3.8 V
IN
SiP21106: 2.8 V
IN
= 2.8 V
IN = 1 µF
= 1 µF
OUT
V
V
= 3.8 V
= 2.8 V
= 1 µF
OUT
OUT
C
C
C
IN
= 10 nF
BP
V
(500 mV/DIV)
= 1 µF
EN
OUT
BP
I
= 150 mA
= 10 nF
OUT
V
(1 V/DIV)
EN
I
= 150 mA
OUT
V
(500 mV/DIV)
OUT
V
(500 mV/DIV)
OUT
20 µs/DIV
Output Voltage Power-Down
20 µs/DIV
Output Voltage Start-Up
SiP21107: 1.8 V
V
(500 mV/DIV)
OUT
V
= 2.8 V
IN
V
= 1.8 V
OUT
C
C
C
IN = 1 µF
= 1 µF
OUT
V
(500 mV/DIV)
= 10 nF
OUT
BP
I
= 1 mA
OUT
POK (1 V/DIV)
SiP21107: 2.8 V
V
V
C
C
C
= 3.8 V
POK (1 V/DIV)
IN
= 2.8 V
IN = 1 µF
= 1 µF
OUT
OUT
= 10 nF
BP
I
= 1 mA
OUT
20 ms/DIV
20 ms/DIV
POK pin goes low to indicate output under-voltage
fault condition
POK pin goes low to indicate output under-voltage
fault condition
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
www.vishay.com
11
SiP21106, SiP21107, SiP21108
Vishay Siliconix
TYPICAL OPERATING WAVEFORMS
SiP21107: 1.8 V
V (500 mV/DIV)
OUT
V
V
C
C
= 2.8 V
IN
OUT
= 1.8 V
IN = 1 µF
= 1 µF
OUT
V
(500 mV/DIV)
OUT
C
= 10 nF
= 1 mA
BP
I
OUT
SiP21107: 2.8 V
V
V
C
C
C
= 3.8 V
IN
OUT
POK (1 V/DIV)
= 2.8 V
IN = 1 µF
= 1 µF
OUT
POK (1 V/DIV)
= 10 nF
BP
I
= 1 mA
OUT
20 µs/DIV
20 µs/DIV
POK pin is actively high to indicate an output normal
operation condition on regular
POK pin is actively high to indicate an output normal
operation condition on regular
TYPICAL WAVEFORMS
1
0.1
SiP21106: 2.8 V
VIN = 3.8 V
SiP21106: 2.8 V
V
V
C
C
C
= 4.5 V
V
= 2.8 V
IN
OUT
= 2.8 V
C
C
C
I
IN = 1 µF
OUT
OUT
= 1 µF
= 1 µF
IN
BP = 10 nF
= 1 µF
V
(100 µV/DIV)
OUT
OUT
= 100 mA
= 10 nF
OUT
BP
I
= 150 mA
V
= 60 µV
OUT
NOISE
RMS
0.01
10
100
1K
10K
100K
1M
2 ms/DIV
Output Noise
Frequency (Hz)
Output Noise Spectral Density
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
Enable
Error-Amp
Bandgap
Reference
*
** ***
BP/Adj/POK
VOUT
Current Limit and
Thermal
+
POK
-
0.94
VOUT
SiP21106: BP
SiP21107: POK
SiP21108: Adj
SiP21106: BP
SiP21107: POK
SiP21108: Adj
*
***
**
GND
Figure 3.
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Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
SiP21106, SiP21107, SiP21108
Vishay Siliconix
DETAILED DESCRIPTION
V
IN
As shown in the block diagram, the circuit consists of a
bandgap reference, error amplifier, P-channel pass
transistor and an internal feedback resistor voltage divider,
which is used to monitor and control the output voltage.
A constant 1.2 V bandgap reference voltage is applied to the
non-inverting input of the error amplifier. The error amplifier
compares this reference with the feedback voltage on its
inverting input and amplifies the difference. If the feedback
voltage is lower than the reference voltage, the
pass-transistor gate is pulled low. This increases the
PMOS's gate to source voltage and allows more current to
pass through the transistor to the output which increases the
output voltage. Conversely, if the feedback voltage is higher
than the reference voltage, the pass transistor gate is pulled
high, decreasing the gate-to-source voltage, thereby
allowing less current to pass to the output and causing it to
drop.
1.2 V
Reference
+
Error-Amp
V
OUT
-
R
R
1
2
Figure 4.
The SiP21108 has a user-adjustable output that can be set
through the resistor feedback network consisting of R1 and
R2. R2 range of 100K to 400K is recommended to be
consistent with ground current specification. R1 can then be
determined by the following equation:
Internal P-Channel Pass Transistor
VOUT
A 0.9 Ω (typical) P-channel MOSFET is used as the pass
transistor for the SiP21106, SiP21107, SiP21108 part series.
The MOSFET transistor offers many advantages over the
more, formerly, common PNP pass transistor designs, which
ultimately result in longer battery lifetime. The main
disadvantage of PNP pass transistors is that they require a
certain base current to stay on, which significantly increases
under heavy load conditions. In addition, during dropout,
when the pass transistor saturates, the PNP regulators
waste considerable current. In contrast, P-channel
MOSFETS require virtually zero-base drive and do not suffer
from the stated problems. These savings in base drive
current translate to lower quiescent current which is typical
around 35 µA as shown in the Typical Characteristics.
(
)
- 1
R1 = R2
x
V
ref
Where Vref is typically 1.2005 V. Use 1 % or better resistors
for better output voltage accuracy (see Figure 4).
Current Limit
The SiP21106, SiP21107, SiP21108 include a current limit
block which monitors the current passing through the pass
transistor through a current mirror and controls the gate
voltage of the MOSFET, limiting the output current to 330 mA
(typical). This current limit feature allows for the output to be
shorted to ground for an indefinite amount of time without
damaging the device.
Thermal-Overload Protection
Shutdown and Auto-Dischage/No-Discharge
The thermal overload protection limits the total power
dissipation and protects the device from being damaged.
When the junction temperature exceeds TJ = 150 °C, the
device turns the P-channel pass transistor off allowing the
device to cool down. Once the temperature drops by about
20 °C, the thermal sensor turns the pass transistor on again
and resumes normal operation. Consequently, a continuous
thermal overload condition will result in a pulsed output. It is
generally recommended to not exceed the junction
temperature rating of 125 °C for continuous operation.
Bringing the EN voltage low will place the part in shutdown
mode where the device output enters a high-impedance
state and the quiescent current is reduced to below 1 µA,
reducing the drain on the battery in standby mode and
increasing standby time. Connect EN pin to input for normal
operation. The output has an internal pull down to discharge
the output to ground when the EN pin is low. The internal pull
down is a 100 Ω typical resistor, which can discharge a 1 µF
in less than 1 ms. Refer to Typical Operating Waveforms for
turn-off waveforms.
Noise Reduction in SiP21106
Output Voltage Selection
For the SiP21106, an external 10 nF bypass capacitor at BP
pin is used to create a low pass filter for noise reduction. The
startup time is fast, since a power-on circuit pre-charges the
bypass capacitor. After the power-up sequence the
pre-charge circuit is switched to standby mode in order to
save current. It is therefore not recommended to use larger
bypass capacitor values than 50 nF. When the circuit is used
without a capacitor, stable operation is guaranteed.
The SiP21106 has fixed voltage outputs that are preset to
voltages from 1.2 V to 4.6 V (see Ordering Information).
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
www.vishay.com
13
SiP21106, SiP21107, SiP21108
Vishay Siliconix
POK Status in SiP21107
The GND pin of the SiP2110 acts as both the electrical
connection to GND as well as a path for channeling away
heat. Connect this pin to a GND plane to maximize heat
dissipation. Once maximum power dissipation is calculated
using the equation above, the maximum allowable output
current for any input/output potential can be calculated as
The POK comparator monitors the output until the supply
comes up to specified percentage of VIN. This open drain
NMOS output requires an external pull-up resistor to either
VOUT or VIN. The internal NMOS can drive up to 0.5 mA
loads. POK pin is active high to indicate that output is within
percentage tolerance. POK goes low when output is outside
of this tolerance as when in dropout, over current and
thermal shutdown.
P(max)
IOUT(max)
=
V - VOUT
IN
APPLICATION INFORMATION
PCB Layout
The component placement around the LDO should be done
carefully to achieve good dynamic line and load response.
The input and noise capacitor should be kept close to the
LDO. The rise in junction temperature depends on how
efficiently the heat is carried away from junction-to-ambient.
The junction-to-lead thermal impedance is a characteristic of
the package and is fixed. The thermal impedance between
lead-to-ambient can be reduced by increasing the copper
area on PCB. Increase the input, output and ground trace
area to reduce the junction-to-ambient thermal impedance.
Input/Output Capacitor Selection and Regulator Stability
It is recommended that a low ESR 1 µF capacitor be used on
the SiP21106, SiP21107, SiP21108 input. A larger input
capacitance with lower ESR would improve noise rejection
and line-transient response. A larger input bypass capacitor
may be required in applications involving long inductive
traces between the source and LDO. The circuit is stable with
only a small output capacitor equal to 6 nF/mA (≈ 1 µF at
150 mA) of load. Since the bandwidth of the error amplifier is
around 1 MHz - 3 MHz and the dominant pole is at the output
node, the capacitor should be capacitive in this range, i.e., for
150 mA load current, an ESR < 0.4 Ω is necessary. Parasitic
inductance of about 10 nH can be tolerated. Applying a larger
output capacitor would increase power supply rejection and
improve load-transient response. Some ceramic dielectrics
such as the Z5U and Y5V exhibit large capacitance and ESR
variation over temperature. If such capacitors are used, a
2.2 µF or larger value may be needed to ensure stability over
the industrial temperature range. If using higher quality
ceramic capacitors, such as those with X7R and Y7R
dielectrics, a 1 µF capacitor will be sufficient at all operating
temperatures.
Operating Region and Power Dissipation
An important consideration when designing power supplies
is the maximum allowable power dissipation of a part. The
maximum power dissipation in any application is dependant
on the maximum junction temperature, TJ(max) = 125 °C, the
ambient temperature, TA, and the junction-to-ambient
thermal resistance for the package, which is the summation
of θJ-C, the thermal resistance of the package, and θC-A, the
thermal resistance through the PC board and copper traces.
Power dissipation may be expressed as:
T
- T
A
(max)
J
P
(max)
=
θ J-C + θ C-A
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?74442.
www.vishay.com
14
Document Number: 74442
S09-1047-Rev. G, 08-Jun-09
Package Information
Vishay Siliconix
THIN SOT-23 : 5- AND 6-LEAD (POWER IC ONLY)
e1
e1
5
1
4
3
6
1
5
2
4
3
E1
E1
E
E
2
−B−
−B−
e
e
M
M
0.15
0.15
C
B
A
C
B
A
b
b
SOT23-5L Format
SOT23-6L Format
0.17 Ref
4xq1
−A−
D
C
R
A2
A
L
2
R
Gauge Plane
Seating Plane
Q
Seating Plane
L
(L1)
0.08 C
−C−
A1
4xq1
MILLIMETERS
INCHES
Dim
Min
Nom
Max
Min
Nom
Max
0.91
0.01
0.90
0.30
0.10
2.90
2.70
1.525
1.00
0.05
1.10
0.10
1.00
0.45
0.20
3.10
2.98
1.70
0.036
0.0004
0.035
0.012
0.004
0.114
0.106
0.060
0.039
0.002
0.043
0.004
0.039
0.018
0.008
0.122
0.117
0.067
A
A1
A2
b
c
D
E
E1
e
e1
L
0.95
0.037
0.32
0.013
0.15
0.006
3.05
0.120
2.85
0.112
1.65
0.065
0.95 BSC
1.90
0.0374 BSC
0.075
1.80
0.30
2.00
0.60
0.070
0.012
0.080
0.024
0.40
0.016
0.60 REF
0.25 BSC
−
0.024 REF
0.010 BSC
−
L1
L2
R
Q
Q1
0.10
0_
−
0.004
0_
−
4_
8_
4_
8_
4_
10_ NOM
12_
4_
10_ NOM
12_
ECN: S-40083—Rev. A, 02-Feb-04
DWG: 5926
Document Number: 72821
29-Jan-04
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1
Package Information
Vishay Siliconix
SC-70: 3/4/5/6-LEADS (PIC ONLY)
0.15 (0.006)
C
D
e1
A
A
D
E
N5
N4
N3
E/2
E1/2
C
E/1
0.15 (0.006)
Pin 1
N1
N2
B
e
See Detail A
M
b
C
0.10 (0.004)
C
A
B
U1
A2
A1
A
SEATING
PLANE
C
0.10 (0.004)
C
H
(b)
b1
0.15 (0.0059)
GAGE PLANE
c1
c
Base Metal
U
L
SECTIION A-A
DETAIL A
LEAD COUNT
NOTES:
Pin
Code
1.
2.
Dimensioning and tolerancing per ANSI Y14.5M-1994.
3
−
2
−
3
−
4
−
2
3
−
4
5
2
3
4
−
5
6
2
3
4
5
6
N1
N2
N3
N4
N5
Controlling dimensions: millimeters converted to inch dimensions are
not necessarily exact.
3.
4.
Dimension “D” does not include mold flash, protrusion or gate burr.
Mold flash, protrusion or gate burr shall not exceed 0.15 mm
(0.006 inch) per side.
The package top shall be smaller than the package bottom.
Dimension “D” and “E1” are determined at the outer most extremes
of the plastic body exclusive of mold flash, tie bar burrs, gate burrs
and interlead flash, but including any mismatch between the top and
bottom of the plastic body.
Document Number: 73201
19-Nov-04
www.vishay.com
1
Package Information
Vishay Siliconix
MILLIMETERS
INCHES
Dim
A
Min
0.80
0.00
0.80
0.15
0.15
0.08
0.08
1.90
2.00
1.15
Nom
−
Max
1.10
0.10
1.00
0.30
0.25
0.25
0.20
2.15
2.20
1.35
Min
0.031
0.000
0.031
0.006
0.006
0.003
0.003
0.074
0.078
0.045
Nom
Max
0.043
0.004
0.040
0.012
0.010
0.010
0.008
0.084
0.086
0.055
−
−
−
A1
A2
b
0.90
−
0.035
−
0.20
−
0.008
−
b1
c
0.13
2.10
2.10
1.25
0.65 BSC
1.30 BSC
0.36
−
0.005
0.082
0.082
0.050
0.0255 BSC
0.0512 BSC
0.014
−
c1
D
E
E1
e
e1
L
0.26
0_
0.46
8_
0.010
0_
0.018
8_
U
4_
10_
4_
10_
U1
ECN: S-42145—Rev. A, 22-Nov-04
DWG: 5941
Document Number: 73201
19-Nov-04
www.vishay.com
2
Package Information
Vishay Siliconix
PowerPAK® TSC75-6L (Power IC only)
D1
Exposed pad
e
b
D
Pin4
Pin 5 Pin6
K
K
PPAK TSC75
(1.6 x 1.6 mm)
E1
E
Exposed pad
L
Pin3
Pin 2
e1
Pin1
K2
K2
Pin 1 Dot
By Marking
Top View
Bottom View
A
C
A1
Side View
MILLIMETERS
INCHES
DIM
A
Min
0.50
0
Nom
0.55
-
Max
0.65
0.05
0.30
0.20
1.65
1.05
1.65
0.65
Min
0.020
0
Nom
0.022
-
Max
0.026
0.002
0.012
0.010
0.065
0.041
0.065
0.026
A1
b
0.20
0.10
1.55
0.95
1.55
0.55
0.25
0.15
1.60
1.00
1.60
0.60
0.50 BSC
1.00 BSC
-
0.008
0.006
0.0061
0.037
0.061
0.022
0.010
0.008
0.063
0.039
0.063
0.024
0.020 BSC
0.039 BSC
-
C
D
D1
E
E1
e
e1
K
0.15
0.20
0.20
-
-
0.006
0.008
0.008
-
K2
L
-
0.25
0.30
0.010
0.012
ECN: S-61919-Rev. A, 02-Oct-06
DWG: 5955
Document Number: 74416
02-Oct-06
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1
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree
to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and
damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay
or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to
obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 11-Mar-11
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1
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