WSF2816-39H1CA [WEDC]
128KX16 SRAM/512KX16 FLASH MODULE; 128KX16 SRAM / 512KX16闪存模块
| 型号： | WSF2816-39H1CA |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 128KX16 SRAM/512KX16 FLASH MODULE |
| 文件： | 总15页 (文件大小：607K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WSF2816-39XX
White Electronic Designs
128KX16 SRAM/512KX16 FLASH MODULE
FEATURES
ꢀ
Access Times of 35ns (SRAM) and 90ns (FLASH)
Packaging
ꢀ
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
ꢀ
ꢀ
Weight:
• 66 pin, PGA Type, 1.075" square HIP, Hermetic
Ceramic HIP (Package 400)
WSF2816-39G2UX - 8 grams typical
WSF2816-39H1X - 13 grams typical
• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880")
square (Package 510) 3.56mm (0.140") height.
Designed to fit JEDEC 68 lead 0.990” CQFJ
footprint (FIGURE 2)
FLASH MEMORY FEATURES
ꢀ
100,000 Erase/Program Cycles
Sector Architecture
ꢀ
ꢀ
ꢀ
128Kx16 SRAM
ꢀ
512Kx16 5V FLASH
• 8 equal size sectors of 64K bytes each
Organized as 128Kx16 of SRAM and 512Kx16 of
Flash Memory with separate Data Buses
• Any combination of sectors can be concurrently
erased. Also supports full chip erase
ꢀ
Both blocks of memory are User Configurable as
256Kx8
ꢀ
ꢀ
ꢀ
5 Volt Programming; 5V 10ꢀ Supply
Embedded Erase and Program Algorithms
Hardware Write Protection
ꢀ
ꢀ
Low Power CMOS
Commercial, Industrial and Military Temperature
Ranges
Note: For programming information refer to Flash Programming 4M5 Application Note.
ꢀ
TTL Compatible Inputs and Outputs
FIGURE1 – PIN CONFIGURATION
FOR WSF2816-39H1X
Pin Description
FD0-15
SD0-15
A0-18
SWE1-2
SCS1-2
OE#
VCC
GND
NC
FWE1-2
FCS1-2
Flash Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
Top View
1
12
23
34
45
56
#
#
SRAM Write Enable
SRAM Chip Selects
Output Enable
SD
8
9
SWE
2
#
SD15
SD14
SD13
SD12
OE#
FD
8
9
V
CC
FD15
FD14
FD13
FD12
SD
SCS
GND
SD11
2
#
FD
FCS
2
#
#
Power Supply
Ground
Not Connected
SD10
FD10
FWE
2
A
A
A
A
A
13
14
15
16
18
A
6
7
FD11
#
#
Flash Write Enable
Flash Chip Select
A
A
A
V
10
A
A3
A4
A5
A
0
1
2
7
6
5
4
11
A17
NC
A
Block Diagram
12
CC
SWE
1
#
A
8
9
0
1
2
A
SWE1
#
SCS1
#
SWE2
#
SCS2
#
FWE1
#
FCS1
#
FWE2 # FCS2#
OE#
SD7
SD6
SD5
SD4
A
FWE
1
1
#
#
FD
FD
FD
FD
A
0-16
SD0
SD1
SD2
SCS1
#
FD
FD
FD
FCS
512K x 8
FLASH
128K x 8
SRAM
128K x 8
SRAM
512K x 8
FLASH
NC
GND
FD
8
8
8
8
SD3
3
11
22
33
44
55
66
FD0-7
FD8-15
SD0-7
SD8-15
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
FIGURE 2 – PIN CONFIGURATION FOR WSF2816-39G2UX
Top View
Pin Description
FD0-15
SD0-15
A0-18
SWE1-2
SCS1-2
OE#
VCC
GND
NC
FWE1-2
FCS1-2
Flash Data Inputs/Outputs
SRAM Data Inputs/Outputs
Address Inputs
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SD
SD
SD
SD
SD
SD
SD
SD
GND
SD
SD
SD10
SD11
SD12
SD13
SD14
SD15
0
1
2
3
4
5
6
7
FD
FD
FD
FD
FD
FD
FD
FD
0
1
2
3
4
5
6
7
#
#
SRAM Write Enable
SRAM Chip Selects
Output Enable
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Power Supply
Ground
Not Connected
GND
8
FD8
#
#
Flash Write Enable
Flash Chip Select
9
FD9
FD10
FD11
FD12
FD13
FD14
FD15
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Block Diagram
SWE1
#
SCS1
#
SWE2
#
SCS2
#
FWE1
#
FCS1
#
FWE2 # FCS2#
OE#
A
0-16
512K x 8
FLASH
128K x 8
SRAM
128K x 8
SRAM
512K x 8
FLASH
8
8
8
8
FD0-7
FD8-15
SD0-7
SD8-15
The White 68 lead G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2U has the TCE
and lead inspection advantage of
the CQFP form.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
SRAM TRUTH TABLE
Parameter
Symbol
TA
TSTG
VG
TJ
VCC
Min
-55
-65
-0.5
Max
+125
+150
7.0
150
7.0
Unit
°C
°C
V
°C
V
SCS#
OE#
X
L
H
X
SWE#
Mode
Standby
Read
Read
Write
Data I/O
High Z
Data Out
High Z
Power
Standby
Active
Active
Active
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
H
L
L
L
X
H
H
L
Data In
-0.5
Parameter
Flash Data Retention
Flash Endurance (write/erase cycles)
CAPACITANCE
TA = +25°C
20 years
100,000
Test
Symbol
Condition
Max Unit
NOTES: 1. Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability.
OE# Capacitance
WE# Capacitance
CS# Capacitance
COE VIN = 0V, f = 1.0MHz 50 pF
CWE VIN = 0V, f = 1.0MHz 20 pF
CCS VIN = 0V, f = 1.0MHz 20 pF
Data I/O Capacitance
Address Line Capacitance
This parameter is guaranteed by design but not tested.
CI/O
VIN = 0V, f = 1.0MHz 20 pF
CAD VIN = 0V, f = 1.0MHz 50 pF
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCC
VIH
Min
4.5
2.2
Max
5.5
VCC + 0.3
+0.8
Unit
V
V
Supply Voltage
Input High Voltage
Input Low Voltage
VIL
-0.5
V
DC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
SRAM Operating Supply Current x 16 Mode
Standby Current
SRAM Output Low Voltage
Symbol
ILI
ILO
ICCx16
ISB
VOL
Conditions
Min
Max
10
10
325
20
0.4
Unit
µA
µA
mA
mA
V
VCC = 5.5, VIN = GND to VCC
SCS# = VIH, OE# = VIH, VOUT = GND to VCC
SCS# = VIL, OE# = FCS# = VIH, f = 5MHz, VCC = 5.5
FCS# = SCS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5
IOL = 8.0mA, VCC = 4.5
SRAM Output High Voltage
Flash VCC Active Current for Read (1)
VOH
ICC1
ICC2
VOL
VOH1
VOH2
VLKO
IOH = -4.0mA, VCC = 4.5
2.4
V
FCS# = VIL, OE# = SCS# = VIH
FCS# = VIL, OE# = SCS# = VIH
IOL = 8.0mA, VCC = 4.5
IOH = -2.5 mA, VCC = 4.5
IOH = -100 µA, VCC = 4.5
120
140
0.45
mA
mA
V
V
V
Flash VCC Active Current for Program or Erase (2)
Flash Output Low Voltage
Flash Output High Voltage
Flash Output High Voltage
Flash Low VCC Lock Out Voltage
NOTES:
0.85 x VCC
VCC -0.4
3.2
V
1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2mA/MHz, with OE# at VIH
CC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
.
2.
I
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
SRAM AC CHARACTERISTICS
SRAM AC CHARACTERISTICS
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
-35
-35
Parameter
Parameter
Symbol
Unit
Symbol
Unit
Read Cycle
Write Cycle
Min
35
Max
Min
35
25
25
20
25
0
Max
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
tRC
tAA
tOH
tACS
tOE
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
tWC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold from Write Time
tCW
tAW
tDW
tWP
tAS
tAH
tOW1
tWHZ1
tDH
0
35
20
1
tCLZ
3
0
1
tOLZ
0
4
1
tCHZ
20
20
1
tOHZ
20
0
1. This parameter is guaranteed by design but not tested.
1. This parameter is guaranteed by design but not tested.
FIGURE 3
AC Test Circuit
AC TEST CONDITIONS
Parameter
Typ
Unit
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Notes: VZ is programmable from -2V to +7V.
V
IL = 0, VIH = 3.0
V
ns
V
5
1.5
1.5
≈
V
I
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
Z is typically the midpoint of VOH and VOL
OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
V
I
.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
FIGURE 4 – SRAM TIMING WAVEFORM — READ CYCLE
tRC
ADDRESS
tAA
tRC
SCS#
ADDRESS
DATA I/O
tAA
tCHZ
tACS
tOH
tCLZ
SOE#
PREVIOUS DATA VALID
DATA VALID
tOE
tOLZ
tOHZ
READ CYCLE 1 (SCS# = OE# = V , SWE# = V
IL IH
)
DATA I/O
DATA VALID
HIGH IMPEDANCE
READ CYCLE 2 (SWE# = V
IH
)
FIGURE 5 – SRAM WRITE CYCLE — SWE# CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
SCS#
tAS
tWP
SWE#
tOW
tWHZ
tDW
tDH
DATA I/O
DATA VALID
WRITE CYCLE 1, SWE# CONTROLLED
FIGURE 6 – SRAM WRITE CYCLE — SCS# CONTROLLED
tWC
ADDRESS
tAW
tAH
tAS
tCW
SCS#
tWP
SWE#
tDW
tDH
DATA I/O
DATA VALID
WRITE CYCLE 2, SCS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FWE# CONTROLLED
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
-90
Parameter
Symbol
Unit
Min
90
0
45
0
Max
Write Cycle Time
tAVAV
tELWL
tWLWH
tAVWL
tWC
tCS
tWP
tAS
ns
ns
ns
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
ns
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
tDVWH
tWHDX
tWLAX
tWHEH
tWHWL
tWHWH1
tWHWH2
tGHWL
tDS
tDH
tAH
tCH
tWPH
45
0
45
0
ns
ns
ns
ns
20
ns
300
15
µs
sec
µs
µs
sec
ns
Read Recovery Time Before Write
0
50
VCC Set-up Time
tVCS
Chip Programming Time
Output Enable Setup Time
Output Enable Hold Time (1)
Chip Erase Time
11
64
tOES
tOEH
0
10
ns
sec
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH1 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
4. For Toggle and Data# Polling.
FLASH AC CHARACTERISTICS – READ ONLY OPERATIONS
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
-90
Parameter
Symbol
Min
Unit
Max
Read Cycle Time
Address Access Time
Chip Select Access Time
OE# to Output Valid
Chip Select to Output High Z (1)
OE# High to Output High Z (1)
Output Hold from Address, CS# or OE# Change, whichever is first
1. Guaranteed by design, not tested.
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tRC
tACC
tCE
tOE
tDF
90
ns
ns
ns
ns
ns
ns
ns
90
90
35
20
20
tDF
tOH
0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FCS# CONTROLLED
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
-90
Parameter
Symbol
Unit
Min
90
0
45
0
Max
Write Cycle Time
FWE# Setup Time
FCS# Pulse Width
Address Setup Time
tAVAV
tWLEL
tELEH
tWC
tWS
tCP
ns
ns
ns
tAVEL
tAS
ns
Data Setup Time
Data Hold Time
Address Hold Time
FWE# Hold From FWE# High
FCS# Pulse Width High
Duration Of Byte Programming Operation (1)
Duration Of Erase Operation (2)
Read Recovery Before Write
Chip Programming Time
Chip Erase Time (3)
tDVEH
tEHDX
tELAX
tEHWH
tEHEL
tWHWH1
tWHWH2
tGHEL
tDS
tDH
tAH
tWH
tCPH
45
0
45
0
ns
ns
ns
ns
20
ns
300
15
µs
sec
ns
sec
sec
0
11
64
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH1 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
FIGURE 7 – AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS
tRC
Addresses
Addresses Stable
tACC
FCS#
OE#
tDF
tOE
FWE#
tCE
tOH
High Z
High Z
Outputs
Output Valid
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
FIGURE 8 – WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE# CONTROLLED
Data# Polling
Addresses
FCS#
5555H
tWC
PA
PA
tAH
tRC
tAS
tGHWL
OE#
tWP
tWHWH1
FWE#
tWPH
tDH
tCS
tDF
tOH
tOE
A0H
PD
DOUT
D7#
Data
tDS
5.0 V
tCE
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device.
4.
DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
FIGURE 9 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY
tAH
tAS
Addresses
FCS#
5555H
2AAAH
5555H
5555H
2AAAH
SA
tGHWL
OE#
tWP
FWE#
tWPH
tCS
tDH
Data
VCC
AAH
55H
80H
AAH
55H
10H/30H
tDS
tVCS
Note: SA is the sector address for Sector Erase.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
FIGURE 10 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM
OPERATIONS FOR FLASH MEMORY
tCH
FCS#
tDF
tOE
OE#
tOEH
FWE#
tCE
tOH
High Z
D7 =
Valid Data
D7#
D7
tWHWH 1 or 2
D0-D7
D0-D6 = Invalid
D7
D0-D6
D7
Valid Data
tOE
High Z
D7
Valid Data
tWHWH 1 or 2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
FIGURE 11 – WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS# CONTROLLED
Data# Polling
Addresses
FWE#
5555H
tWC
PA
PA
tAH
tAS
tGHEL
OE#
tCP
tWHWH1
FCS#
tCPH
tDH
tWS
D7#
A0H
PD
DOUT
Data
tDS
5.0 V
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device.
4.
DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
The White 68 lead G2U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G2U has the TCE
and lead inspection advantage of
the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF2816-39XX
White Electronic Designs
ORDERING INFORMATION
W S F 2816 - 39 X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
M = Military Screened
I = Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C = Commercial
PACKAGE TYPE:
H1 = 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400)
G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510)
ACCESS TIME (ns)
39 = 35ns SRAM and 90ns FLASH
2Mbit of SRAM and 8Mbit of Flash
Organization: 128K x 16 SRAM and
512K x 16 Flash
Flash
SRAM
WHITE ELECTRONIC DESIGNS CORP.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2003
Rev. 6
15
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
相关型号：
WSF41632-22G2TC
Memory Circuit, Flash+SRAM, 512KX32, CMOS, CQMA68, 22.40 MM, CERAMIC, QFP-68
MICROSEMI
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