W83L177R [WINBOND]
100MHZ 2-DIMM SDRAM BUFFER FOR NOTEBOOK; 2 100MHZ -DIMM SDRAM缓存适用于笔记本
| 型号： | W83L177R |
| 厂家： | 
WINBOND |
| 描述： | 100MHZ 2-DIMM SDRAM BUFFER FOR NOTEBOOK |
| 文件： | 总9页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W83L177R
100MHZ 2-DIMM SDRAM BUFFER FOR NOTEBOOK
1.0 GENERAL DESCRIPTION
The W83L177R is a 10 outputs SDRAM clock buffer for 2-DIMMs models incorporate with
W83L197R-16 which is the clock synthesizer especially for the 100MHz models such as Intel BX
chipsets.(Refer the datasheet fo Winbond W83L197R-16)
The W83L177R receives the clock from chipset by the Buffer_In pin and provides almost zero-
delay (less than 4ns propagation delay) SDRAM buffer outputs for the 10 SDRAM clocks which are
synchronous with the CPU clock outputs priovided by W83L197R-16. The clock skew between any
two clock outputs is less than 250ps and the output buffer impedance is about 15 ohms.
The W83L177R also provides I2C serial bus interface to program the registers to enable or disable
each SDRAM clock outputs.
2.0 PRODUCT FEATURES
·
·
·
·
10 SDRAM clocks for 2-DIMMs
Clock skew less than 250ps
Almost none delay Buffer-in controlling SDRAM clocks(< 4ns propagation delay)
2
·
·
·
·
I C 2-wire serial interface
Programmable registers to enable/stop each output
Incorporate with W83L197R-16
28pin-SOP package (209mil)
Publication Release Date: Mar. 1999
Revision 0.10
- 1 -
W83L177R
PRELIMINARY
3.0 BLOCK DIAGRAM
SDATA
SCLK
device Control
Serial port
OE
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
Buffer_In
SDRAM8
SDRAM9
4.0 PIN CONFIGURATION
Vdd
SDRAM7
SDRAM6
Vss
Vdd
SDRAM 5
SDRAM 4
Vss
* OE
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
28
27
26
25
Vdd
SDRAM 0
SDRAM 1
Vss
Vdd
SDRAM 2
SDRAM 3
24
23
22
21
20
19
18
17
16
15
Vss
BUFFER_IN
Vdd
SDRAM 8
Vss
VddIIC
*SDATA
SDRAM 9
Vss
VssIIC
13
14
*SCLOCK
Publication Release Date: Mar. 1999
Revision 0.10
- 2 -
W83L177R
PRELIMINARY
5.0 PIN DESCRIPTION
IN - Input
OUT - Output
I/O - Bi-directional Pin
* - Internal 250kW pull-up
SYMBOL
PIN
I/O
FUNCTION
SDRAM [ 0:9]
2,3,6,7,11,18, O SDRAM clock outputs which have the same frequency as
22,23,26,27
CPU clocks.
*SDATA
*SDCLK
*OE
14
15
20
I/O Serial data of I2C 2-wire control interface
IN Serial clock of I2C 2-wire control interface
IN Internal 250K ohm pull-up resistor. Tri-states outputs
when LOW.
BUFFER_IN
VDDIIC
VSSIIC
Vdd
9
IN Clock Input from the chipset
Power supply for I2C core logic, 3.3 V supply
Ground for I2C core logic
13
16
1,5,10,19,24, Power supply
28
Vss
4,8,12,17,21, Circuit Ground
25
Publication Release Date: Mar. 1999
Revision 0.10
- 3 -
W83L177R
PRELIMINARY
6.0 FUNTION DESCRIPTION
6.1 2-WIRE I2C CONTROL INTERFACE
The clock generator is a slave I2C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
’ o
W83L177R initializes with default register settings, and then it ptional to use the 2-wire control
interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address and [1101 0010], command
code checking [0000 0000], and byte count checking. After successful reception of each byte, an
acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to
write to internal I2C registers after the string of data. The sequence order is as follows:
Bytes sequence order for I2C controller :
Clock Address
A(6:0) & R/W
8 bits dummy
8 bits dummy
Byte count
Byte0,1,2...
until Stop
Ack
Ack
Ack
Ack
Command code
Set R/W to 1 when read back the data sequence is as follows :
Clock Address
A(6:0) & R/W
Byte2, 3, 4...
until Stop
Byte 1
Ack
Byte 0
Ack
6.2 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true
power up. Registers are set to the values shown only on true power up. "Command Code" byte and
"Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data
(bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.
After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
Publication Release Date: Mar. 1999
- 4 -
Revision 0.10
W83L177R
PRELIMINARY
6.2.1 Register 0: (1 = Active, 0 = Inactive)
Bit
7
@PowerUp
Pin
-
Description
-
-
Reserved
6
-
Reserved
5
-
-
Reserved
4
-
-
Reserved
3
1
1
1
1
7
6
3
2
SDRAM3 (Active / Inactive)
SDRAM2 (Active / Inactive)
SDRAM1 (Active / Inactive)
SDRAM0 (Active / Inactive)
2
1
0
6.2.2 Register 1: (1 = Active, 0 = Inactive)
Bit
7
@PowerUp
Pin
27
26
23
22
-
Description
1
1
1
1
-
SDRAM7 (Active / Inactive)
SDRAM6 (Active / Inactive)
SDRAM5 (Active / Inactive)
SDRAM4 (Active / Inactive)
Reserved
6
5
4
3
2
-
-
Reserved
1
-
-
Reserved
0
-
-
Reserved
6.2.3 Register 2: (1 = Active, 0 = Inactive)
Bit
7
@PowerUp
Pin
Description
1
1
-
18
11
-
SDRAM9 (Active / Inactive)
SDRAM8 (Active / Inactive)
Reserved
6
5
-
4
-
Reserved
-
3
-
Reserved
-
2
-
Reserved
-
1
-
Reserved
-
0
-
Reserved
Publication Release Date: Mar. 1999
Revision 0.10
- 5 -
W83L177R
PRELIMINARY
7.0 SPECIFICATIONS
7.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused
inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).
Symbol
Vdd , VIN
TSTG
Parameter
Rating
Voltage on any pin with respect to GND
- 0.5 V to + 7.0 V
Storage Temperature
Ambient Temperature
Operating Temperature
- 65°C to + 150°C
- 55°C to + 125°C
0°C to + 70°C
TB
TA
7.2 AC CHARACTERISTICS
Vdd = 3.3V
± 5 % , TA = 0°C to +70°C, Test load = 30 pF
Parameter
Symbo
l
Min Typ
Max
Units
Test Conditions
Input frequency
fIN
tR
0
150
4.0
MHz
Output Rise Time
Output Fall Time
1.5
1.5
V/ns Measured from 0.4V to 2.4V
tF
4.0
V/ns Measured from 0.4V to 2.4V
Output Skew, Rising Edges
Output Skew, Falling Edges
Output Enable Time
tSR
tSF
tEN
tDIS
tPR
250
250
8.0
ps
ps
ns
ns
ns
1.0
1.0
1.0
Output Disable Time
8.0
Rising
Delay
Edge
Propagation
<4.0
Falling Edge Propagation
Delay
tPF
1.0
<4.0
55
ns
Duty Cycle
tD
45
15
%
Measure at 1.5V
AC Output Impedance
ZO
W
Publication Release Date: Mar. 1999
Revision 0.10
- 6 -
W83L177R
PRELIMINARY
7.3 DC CHARACTERISTICS
Vdd = 3.3V 5 %, TA = 0 C to +70°C
±
°
Parameter
Symbol
VIL
Min
Typ
Max
Units
Vdc
Test Conditions
Input Low Voltage
Vss-03
0.8
Input High Voltage
2.0
-5
Vdd+0.5
+5
VIH
Vdc
Input Leakage Current,
BUFFER_IN
mA
IIL
Input Leakage Current
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
-20
+5
50
mA
IIL
IOL=1mA
IOH=-1mA
VOL=1.5V
VOH=1.5V
VOL
VOH
IOL
mVdc
3.1
65
70
Vdc
mA
100
110
160
185
mA
IOH
CIN
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
5
6
7
pF
pF
nH
COUT
LIN
Publication Release Date: Mar. 1999
Revision 0.10
- 7 -
W83L177R
PRELIMINARY
8.0 ORDERING INFORMATION
Part Number
Package Type
Production Flow
Commercial, 0°C to +70°C
W83L177R
28 PIN SOP
9.0 HOW TO READ THE TOP MARKING
W83L177R
28051234
814GBB
1st line: Winbond logo and the type number: W83L177R
2nd line: Tracking code 2 8051234
2: wafers manufactured in Winbond FAB 2
8051234: wafer production series lot number
3rd line: Tracking code 814 G B B
814: packages made in '98, week 14
G: assembly house ID; A means ASE, S means SPIL, G means GR
BB: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to
their respective owners.
Publication Release Date: Mar. 1999
- 8 -
Revision 0.10
W83L177R
PRELIMINARY
10.0 PACKAGE DRAWING AND DIMENSIONS
28-SOP
D
15
2
DIMENSION IN MM DIMENSION IN INCH
MIN. NOM MAX. MIN. NOM MAX.
SYMBOL
2.00
0.079
A
A1
A2
b
0.05
1.65 1.75 1.85
0.002
0.065
DTEAIL A
0.069
0.073
0.015
0.010
0.22
0.09
0.38 0.009
0.25 0.004
H
E
E
c
10.20
5.30 5.60
7.80 8.20
0.65
9.90
5.00
0.389 0.401 0.413
0.197 0.209 0.220
0.291 0.307 0.323
0.0256
10.50
D
E
HE
7.40
e
L
L1
0.95
0.037
0.55 0.75
1.25
0.021 0.030
0.050
0.004
8
Y
0.10
8
1
14
0
0
q
A2
A
SEATING PLANE
SEATING PLANE
Y
q
L
L1
DETAIL A
e
b
A1
Headquarters
No. 4, Creation Rd. III
Science-Based Industrial Park
Hsinchu, Taiwan
TEL: 886-35-770066
Winbond Electronics
(North America) Corp.
2730 Orchard Parkway
San Jose, CA 95134 U.S.A.
TEL: 1-408-9436666
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II
123 Hoi Bun Rd., Kwun Tong
Kowloon, Hong Kong
TEL: 852-27516023-7
FAX: 852-27552064
FAX: 886-35-789467
www: http://www.winbond.com.tw/
FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the
trade marks of products and companies mentioned in this data sheet belong to their
respective owners.
These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal
injury. Winbond customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Winbond for any damages resulting
from such improper use or sale.
Publication Release Date: Mar. 1999
- 9 -
Revision 0.10
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