W981216AH_技术文档

W981216AH

2M x 16 bit x 4 Banks SDRAM

Features

·

3.3V±0.3V power supply

Up to 133 MHz clock frequency

2,097,152 words x 4 banks x 16 bits organization

Auto Refresh and Self Refresh

CAS latency: 2 and 3

Burst Length: 1, 2, 4, 8 , and full page

Burst read, Single Writes Mode

Byte data controlled by UDQM and LDQM

Power-Down Mode

Auto-Precharge and controlled precharge

4k refresh cycles / 64ms

Interface: LVTTL

Package: TSOP II 54 pin, 400 mil - 0.80

General Description

W981216AH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 2M words x 4 banks x

16 bits. Using pipelined architecture and 0.20um process technology, W981216AH delivers a data bandwidth of up to 266M

bytes per second (-75). To fully comply to the personal computer industrial standard, W981216AH is sorted into two speed

grades: -75 and -8H. The -75 is compliant to the PC133/CL3 specification, the –8H is compliant to PC100/CL2 specification.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of

1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated

by the SDRAM internal counrter in burst operation. Random column read is also possible by providing its address at each clock

cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst legnth, latency cycle, interleave or sequential burst

to maximize its performance. W981216AH is ideal for main memory in high performance applications.

Key Parameters

Symbol

tCK

Description

min/max

min

-75 (PC133) -8H (PC100)

Clock Cycle Time

7.5ns

5.4ns

20ns

8ns

6ns

tAC

Access Time from CLK

max

min

max

tRP

Precharge to Active Command

Active to Read/Write Command

Operation Current ( Single bank )

Burst Operation Current

20ns

80mA

110mA

2mA

tRCD

ICC1

ICC4

ICC6

20ns

85mA

120mA

2mA

Self-Refresh Current

Revision 1.0

Publication Release Date: March, 1999

- 1 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

BLOCK DIAGRAM

CLK

CLOCK

BUFFER

CKE

CS

CONTROL

SIGNAL

GENERATOR

RAS

COMMAND

CAS

DECODER

COLUMN DECODER

WE

CELL ARRAY

BANK #0

CELL ARRAY

BANK #1

A10

MODE

REGISTER

SENSE AMPLIFIER

A0

SENSE AMPLIFIER

ADDRESS

BUFFER

A9

DMn

A11

BS0

BS1

DQ0

DATA CONTROL

CIRCUIT

DQ

BUFFER

DQ15

REFRESH

COUNTER

COLUMN

COUNTER

UDQM

LDQM

COLUMN DECODER

CELL ARRAY

BANK #2

CELL ARRAY

BANK #3

SENSE AMPLIFIER

NOTE:

The cell array configuration is 4096 * 512 * 16.

Revision 1.0

Publication Release Date: March, 1999

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W981216AH

2M x 16 bit x 4 Banks SDRAM

Pin Assignment

Pin Number Pin Name

Function

Address

Description

Multiplexed pins for row and column address.

Row address : A0 ~ A11. Column address: A0 ~ A8.

Select bank to activate during row address latch time, or bank to

read/write during address latch time.

23 ~ 26, 22,

29 ~35

A0~ A11

20, 21

BS0, BS1

Bank Select

2, 4, 5, 7, 8,

10, 11, 13,

42, 44, 45,

47, 48, 50,

51, 53

DQ0 ~

DQ15

Data Input/

Output

Multiplexed pins for data output and input.

19

CS#

Chip Select

Disable or enable the command decoder. When command

decoder is disabled, new command is ignored and previous

operation continues.

18

17

RAS#

CAS#

Row Address

Strobe

Column

Command input. When sampled at the rising edge of the clock,

RAS#, CAS# and WE# define the operation to be executed.

Referred to RAS#

Address Strobe

Write Enable

input/output

mask

16

39, 15

WE#

UDQM/

LDQM

Referred to RAS#

The output buffer is placed at Hi-Z(with latency of 2) when DQM

is sampled high in read cycle. In write cycle, sampling DQM

high will block the write operation with zero latency.

System clock used to sample inputs on the rising edge of clock.

CKE controls the clock activation and deactivation. When CKE

is low, Power Down mode, Suspend mode, or Self Refresh

mode is entered.

38

37

CLK

CKE

Clock Inputs

Clock Enable

1, 14, 27

28, 41, 54

3, 9, 43, 49

VCC

VSS

VCC

Power ( +3.3 V ) Power for input buffers and logic circuit inside DRAM.

Ground Ground for input buffers and logic circuit inside DRAM.

Power ( + 3.3 V Separated power from VCC, used for output buffers to improve

Q

) for I/O buffer

Ground for I/O

buffer

noise.

6, 12, 46, 52

36, 40

V

SS

Q

Separated ground from VSS, used for output buffers to improve

noise.

No connection

NC

No Connection

Revision 1.0

Publication Release Date: March, 1999

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W981216AH

2M x 16 bit x 4 Banks SDRAM

Pin Assignment (Top View)

VCC

VSS

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

1

DQ15

VSSQ

DQ14

DQ13

CC

DQ0

2

3

VCCQ

DQ1

4

DQ2

5

VSSQ

V

Q

6

DQ12

DQ11

VSSQ

DQ10

DQ9

DQ3

7

DQ4

8

VCCQ

9

DQ5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

DQ6

VSSQ

VCCQ

DQ8

VSS

DQ7

VCC

NC

LDQM

WE

UDQM

CLK

CKE

NC

CAS

RAS

CS

A11

A9

BS0

BS1

A10/AP

A0

A8

A7

A6

A1

A5

A2

A4

A3

VCC

VSS

Revision 1.0

Publication Release Date: March, 1999

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W981216AH

2M x 16 bit x 4 Banks SDRAM

ABSOLUTE MAXIMUM RATINGS

SYMBOL

VIN,VOUT

VCC,VCCQ

TOPR

ITEM

RATING

-0.3~VCC+0.3

-0.3~4.6

0~70

UNIT

V

NOTES

Input, Output Voltage

1

Power Supply Voltage

Operating Temperature

Storage Temperature

Soldering Temperature(10s)

Power Dissipation

V

°C

W

TSTG

-55~150

260

TSOLDER

PD

1

IOUT

Short Circuit Output Current

50

MA

RECOMMENDED DC OPERATING CONDITIONS ( Ta = 0 to 70°C )

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

NOTES

VCC

VCCQ

VIH

Power Supply Voltage

3.0

2.0

-0.3

3.3

-

3.6

V

2

Power Supply Voltage (for I/O Buffer)

Input High Voltage

VCC+0.3

0.8

VIL

Input Low Voltage

-

Note: VIH(max) = VCC/VCCQ+1.2V for pulse width < 5ns

VIL(min) = VSS/VSSQ-1.2V for pulse width < 5ns

CAPACITANCE (VCC=3.3V, Af = 1MHz, Ta=25°C)

SYMBOL

PARAMETER

MIN

MAX

UNIT

Input Capacitance (A0 to A11, BS0 ,BS1, CS, RAS, CAS, WE, DQM, CKE)

Input Capacitance (CLK)

-

4

pf

CI

CO

Input/Output capacitance

6.5

Note: These parameters are periodically sampled and not 100% tested.

Revision 1.0

Publication Release Date: March, 1999

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W981216AH

2M x 16 bit x 4 Banks SDRAM

AC CHARACTERISTICS AND OPERATING CONDITION

(Vcc=3.3V±0.3V, Ta=0° to 70°C Notes:5, 6, 7, 8)

-75 (PC133)

-8H (PC100)

MIN MAX

SYMBOL

PARAMETER

UNIT

MIN

MAX

tRC

tRAS

tRCD

tCCD

tRP

Ref/Active to Ref/Active Command Period

Active to precharge Command Period

Active to Read/Write Command Delay Time

Read/Write(a) to Read/Write(b)Command Period

Precharge to Active Command Period

Active(a) to Active(b) Command Period

Write Recovery Time

65

45

20

1

68

48

20

1

100000

ns

cycle

20

15

10

7.5

10

7.5

2.5

20

10

8

tRRD

tWR

CL*=2

CL*=3

CL*=2

CL*=3

tCK

CLK Cycle Time

1000

10

8

1000

tCH

tCL

tAC

CLK High Level width

CLK Low Level width

Access Time from CLK

3

CL*=2

CL*=3

6

5.4

ns

tOH

tHZ

Output Data Hold Time

Output Data High Impedance Time

Output Data Low Impedance Time

Power Down Mode Entry Time

Transition Time of CLK (Rise and Fall)

Data-in Set-up Time

2.7

0

3

7.5

8

tLZ

0

tSB

0

7.5

10

0

8

tT

0.5

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

0.5

2

10

tDS

tDH

Data-in Hold Time

1

tAS

Address Set-up Time

2

tAH

Address Hold Time

1

tCKS

tCKH

tCMS

tCMH

tREF

tRSC

CKE Set-up Time

2

CKE Hold Time

1

Command Set-up Time

Command Hold Time

2

1

Refresh Time

64

ms

ns

Mode register Set Cycle Time

15

16

(CL=CAS Latency)

Revision 1.0

Publication Release Date: March, 1999

- 6 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

DC CHARACTERISTICS (VCC = 3.3V ± 0.3V, Ta=0°~70°C)

-75 (PC133)

MIN. MAX.

-8H (PC100)

MIN. MAX.

ITEMS

SYMBOL

UNIT NOTES

OPERATING CURRENT

tCK=min , tRC=min

Active Precharge command cycling

without Burst operation

1 bank operation

ICC1

85

80

3

STANDBY CURRENT

tCK=min , CS#=VIH

VIH/L=VIH(min)/VIL(max)

Bank : inactive state

STANDBY CURRENT

CLK=VIL , CS#=VIH

VIH/L=VIH(min)/VIL(max)

BANK : inactive state

CKE = VIH

ICC2

ICC2P

ICC2S

ICC2PS

45

1

40

1

3

CKE = VIL (Power Down mode)

CKE = VIH

10

1

10

1

CKE = VIL (Power Down mode)

mA

NO OPERATING CURRENT

tCK=min

CS#=VIH(min)

CKE = VIH

ICC3

50

10

45

10

CKE= VIL (Power Down mode)

ICC3P

BANK : active state (4 banks)

BURST OPERATING CURRENT

tCK = min

Read / Write command cycling

AUTO REFRESH CURRENT

tCK = min

Auto Refresh command cycling

SELF REFRESH CURRENT

Self Refresh mode

ICC4

ICC5

ICC6

120

190

2

110

180

2

3,4

3

CKE = 0.2V

ITEM

SYMBOL

MIN.

-5

MAX.

UNIT

µA

V

NOTES

INPUT LEAKAGE CURRENT

( 0V £ VIN £ VCC , all other pins not under test = 0V )

OUTPUT LEAKAGE CURRENT

( Output disable , 0V £ VOUT £ VCCQ )

LVTTL OUTPUT H LEVEL VOLTAGE

( IOUT = -2mA )

II(L)

5

IO(L)

VOH

VOL

-5

²

2.4

-

²

LVTTL OUTPUT L LEVEL VOLTAGE

( IOUT = 2mA )

0.4

V

Revision 1.0

Publication Release Date: March, 1999

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W981216AH

2M x 16 bit x 4 Banks SDRAM

NOTES:

1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.

2. All voltages are referenced to VSS

3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of

tCK and tRC.

4. These parameters depend on the output loading conditions. Specified values are obtained with output open.

5. Power up sequence is further described in the "Functional Description" section.

6. AC TESTING CONDITIONS

Output Reference Level

Output Load

Input Signal Levels

1.4V/1.4V

See diagram B below

2.4V/0.4V

2ns

Transition Time (Rise and Fall) of Input Signal

Input Reference Level

1.4V

3.3 V

1.2K

1.4 V

50 ohms

50pF

output

Z = 50 ohms

50pF

0.87K

AC TEST LOAD (A)

AC TEST LOAD (B)

7. Transition times are measured between VIH and VIL

.

8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.

Revision 1.0

Publication Release Date: March, 1999

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W981216AH

2M x 16 bit x 4 Banks SDRAM

Operation Mode

Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth

table for the operation commands.

Table 1 Truth Table ( note (1) , (2) )

A11,

A9-0

Device state

Idle

command

CKEn-1

H

CKEn

x

DQM

x

BS0,1

v

A10

v

CS

L

H

L

RA

L

CAS

H

L

WE

H

L

Bank Active

v

Bank Precharge

Precharge All

Any

H

x

v

L

H

L

H

L

H

v

x

v

x

L

Any

H

x

L

Write

Active (3)

Idle

H

x

v

H

L

Write with Autoprecharge

Read

H

x

v

L

H

x

v

L

H

L

Read with Autoprecharge

Mode Register Set

No - Operation

Burst Stop

H

x

v

L

H

x

v

L

Any

H

x

H

x

H

x

H

L

Active (4)

Any

H

x

Device Deselect

Auto - Refresh

Self - Refresh Entry

Self Refresh Exit

H

x

Idle

H

L

x

L

H

Idle

H

x

L

idle

(S.R.)

L

H

L

x

H

L

x

H

x

H

x

Clock suspend Mode Entry

Power Down Mode Entry

Active

Idle

Active (5)

H

L

H

x

H

L

x

H

x

H

x

Clock Suspend Mode Exit

Power Down Mode Exit

Active

Any

(power down)

L

H

x

L

x

H

L

x

H

x

H

x

Data write/Output Enable

Data Write/Output Disable

Active

H

x

H

x

Notes: (1) v= valid x = Don't care L= Low Level H= High Level

(2) CKEn signal is input level when commands are provided.

(3) These are state of bank designated by BS0, BS1 signals.

(4) Device state is full page burst operation.

(5) Power Down Mode can not be entered in the burst cycle.

When this command asserts in the burst cycle, device state is clock suspend mode.

Revision 1.0

Publication Release Date: March, 1999

- 9 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Functional Description

Power Up and Initialization

The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be

followed to guarantee the device being preconditioned to each user specific needs.

During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held

in the "NOP" state. The power up voltage must not exceed VCC+0.3V on any of the input pins or VCC supplies. After power up,

an initial pause of 200us is required followed by a precharge of all banks using the precharge command. To prevent data

contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause

period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register.

An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure

proper subsequent operation.

Programming Mode Register

After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a

precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode

Register Set Command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address

input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command

may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for

Mode Register Set Cycle and Operation Table.

Bank Activate Command

The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to

RAS# activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write

operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be

precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between

successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum

time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time

(tRRD). The maximum time that each bank can be held active is specified as tRAS(max).

Read and Write Access Modes

After a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low

at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation

(WE high), or a write operation (WE low). The address inputs determine the starting column address.

Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate

command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using

the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access

operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or

between active banks on every clock cycle.

Revision 1.0

Publication Release Date: March, 1999

- 10 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Burst Read Command

The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising

edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst

(sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the

next page explain the address sequence of interleave mode and sequence mode.

Burst Command

The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising

edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied

on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each

subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be

ignored.

Read Interrupted by a Read

A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses

are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on

the outputs until the CAS latency from the interrupting Read Command the is satisfied.

Read Interrupted by a Write

To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance

state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the

write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the

DQ bus and DQM masking is no longer needed.

Write Interrupted by a Write

A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is

interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the

programmed burst length is satisfied.

Write Interrupted by a Read

A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs

must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention.

When the Read Command is activated, any residual data from the burst write cycle will be ignored.

Burst Stop Command

A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write

Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other

burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the

rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst

read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any

residual data from the burst write cycle will be ignored.

Revision 1.0

Publication Release Date: March, 1999

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W981216AH

2M x 16 bit x 4 Banks SDRAM

Table 2 Address Sequence of Sequential Mode

DATA

Data 0

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

Access Address

n

Burst Length

BL= 2 (disturb address is A0)

n + 1

No address carry from A0 to A1

n + 2

BL= 4 (disturb addresses are A0 and A1)

No address carry from A1 to A2

n + 3

n + 4

n + 5

BL= 8 (disturb addresses are A0, A1 and A2)

No address carry from A2 to A3

n + 6

n + 7

.

Addressing Sequence of Sequential Mode

A column access is performed by increasing the address from the column address which is input to the

device. The disturb address is varied by the Burst Length as shown in Table 2.

Addressing Sequence of Interleave Mode

A column access is started in the input column address and is performed by inverting the address bit in the

sequence shown in Table 3.

Table 3 Address Sequence of Interleave Mode

DATA

Access Address

Burst Length

BL = 2

Data 0

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

A8 A7 A6 A5 A4 A3 A2 A1 A0

BL = 4

BL = 8

Revision 1.0

Publication Release Date: March, 1999

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W981216AH

2M x 16 bit x 4 Banks SDRAM

Auto-Precharge Command

If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-

precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically

before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the

end of the scheduled burst cycle. The number of clocks is determined by CAS latency.

A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore,

use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge

operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge

command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-

Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst

write cycle. This delay is referred to as Write tDPL. The bank undergoing auto-precharge can not be reactivated until tDPL and tRP are

satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-precharge Command, the

interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min).

Precharge Command

The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when

CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge

each bank separately or all banks simultaneously. Three address bits, A10, A12, and A13, are used to define which bank(s) is to

be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated

before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must

be greater than or equal to the Precharge time (tRP).

Self Refresh Command

The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock.

All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to

keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except

CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self

Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation

and before the next command can be issued. This delay is equal to the RAS cycle time plus the Self Refresh exit time.

Power Down Mode

The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the

power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down

mode longer than the Refresh period (tREF) of the device.

The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next

rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCES(min) +

tCK(min).

Revision 1.0

Publication Release Date: March, 1999

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W981216AH

2M x 16 bit x 4 Banks SDRAM

No Operation Command

The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from

registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS,

CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is

still executing, such as a burst read or write cycle.

Deselect Command

The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought

high, the RAS, CAS, and WE signals become don't cares.

Clock Suspend Mode

During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the

banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any

clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the

time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are

issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high

to when Clock Suspend mode is exited.

Revision 1.0

Publication Release Date: March, 1999

- 14 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Timing Waveform

Command Input Timing

t

CL

tCH

t

CK

VIH

CLK

V^IL

t

T

t

T

t

CMS

t

CMH

t

CMH

tCMS

CS

t

CMH

RAS

t

CMS

t

CMH

CAS

WE

t

AS

tAH

A0-A11

BS0, 1

t

CKS

t

CKH

tCKH

t

CKS

t

CKS

t

CKH

CKE

Revision 1.0

Publication Release Date: March, 1999

- 15 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Read Timing

Read CAS Latency

CLK

CS

RAS

CAS

WE

A0-A11

BS0, 1

t

AC

t

AC

t

HZ

t

OH

t

OH

t

LZ

Valid

Data-Out

Valid

Data-Out

DQ

Read Command

Burst Length

Revision 1.0

Publication Release Date: March, 1999

- 16 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Control Timing of Input Data

(Word Mask)

CLK

t

CMS

t

CMH

t

CMH

t

CMS

DQM

t

DS

t

DH

t

DS

tDH

t

DS

t

DH

t

DS

tDH

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

DQ0 -15

(Clock Mask)

CLK

tCKH

t

CKS

t

CKH

tCKS

CKE

t

DS

tDH

tDS

t

DH

t

DS

t

DH

t

DS

tDH

Valid

Data-in

Valid

Data-in

Valid

Data-in

Valid

Data-in

DQ0 -15

Control Timing of Output Data

(Output Enable)

CLK

t

CMH

t

CMS

t

CMS

tCMH

DQM

t

AC

t

HZ

t

AC

t

AC

t

AC

tLZ

t

OH

t

OH

tOH

t

OH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

OPEN

DQ0 -15

(Clock Mask)

CLK

tCKH

tCKS

t

CKH

tCKS

CKE

t

AC

t

AC

tAC

t

AC

tOH

t

OH

tOH

Valid

Data-Out

Valid

Data-Out

Valid

Data-Out

DQ0 -15

Revision 1.0

Publication Release Date: March, 1999

- 17 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Mode Register Set Cycle

t

RSC

CLK

t

CMS

tCMH

CS

t

CMS

tCMH

RAS

CAS

WE

t

CMS

t

CMH

t

CMS

t

CMH

t

AS

t_AH

A0-A10

BS

Register

set data

A0

A2 A10 A0

BurstAL0ength

A0

A1

A2

A3

A4

A5

A6

SeqAue0ntial

InteArle0ave

Burst Length

0

1

A00

A10

A00

A0

0

A10

0

1

0

1

0

1

0

1

A10

A20

A40

A80

A20

A40

A80

Addressing Mode

CAS Latency

ResAe0rved

FullAP0age

ResAe0rved

A30

A00

A10

AddressAin0g Mode

SeqAue0ntial

InteArle0ave

A07 "0" (Test Mode)

A8 "0"

A09

Reserved

A6 A50 A4

CAS LAa0tency

ResAe0rved

0

1

A00

A10

A00

0

1

0

1

0

WriteA0Mode

2

A30

4

"0"

A10

AA101

ResAe0rved

BS0 "0"

BAS01 "0"

A90

A00

A10

Single Write Mode

Burst read aAn0d Burst write

Burst read aAnd0 single write

Revision 1.0

Publication Release Date: March, 1999

- 18 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Operating Timing Example

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

t^RC

RAS

CAS

t^RAS

t^RP

t^RAS

tRP

t^RP

tRAS

WE

BS0

BS1

tRCD

RAa

RBb

RAc

RBd

A10

RAe

A0-A9,

A11

CBx

RBb

CAy

CAw

CBz

DQM

CKE

DQ

t^AC

tAC

bx3

cy2

bx1

aw0

aw2 aw3

bx0

bx2

cy1

cy3

aw1

cy0

tRRD

Precharge

Read

Active

Read

Active

Bank #0

Bank #1

Read

Active

Precharge

Read

Precharge

Active

Bank #2

Bank #3

Idle

Revision 1.0

Publication Release Date: March, 1999

- 19 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)

(CLK = 100 MHz)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

tRC

t

RC

tRC

RAS

CAS

tRAS

t

RP

t

RAS

t

RP

t

RAS

t

RP

t

RAS

WE

BS0

BS1

A10

t

RCD

t

RCD

tRCD

RAe

RBd

RAa

RBb

RAc

A0-A9,

A11

CBz

RAa

CAw

CAy

RAe

CBx

RBb

RAc

RBd

DQM

CKE

t

AC

t

AC

tAC

aw0 aw1 aw2

aw3

bx0 bx1 bx2 bx3

cy0

cy1 cy2

cy3

dz0

DQ

t

RRD

t

RRD

t

RRD

tRRD

Read

AP*

Active

AP*

Read

Active

AP*

Bank #0

Bank #1

Bank #2

Bank #3

Read

Active

Read

Active

Idle

* AP is the internal precharge start timing

Revision 1.0

Publication Release Date: March, 1999

- 20 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Interleaved Bank Read (Burst Length=8, CAS Latency=3)

(CLK = 100 MHz)

6

7

8

11 12 13

16 17 18

1

2

3

5

9

10

14 15

19

21

0

4

20

22 23

CLK

CS

t^RC

tRC

RAS

t^RAS

t^RP

t^RAS

tRP

tRAS

tRP

CAS

WE

BS0

BS1

t^RCD

RAa

RAc

A10

RBb

A0-A9

A11

CAx

CBy

CAz

DQM

CKE

tAC

ax5 ax6

tAC

by7

ax0 ax1

ax2

ax3

ax4

by0

by1

by4 by5

by6

DQ

CZ0

tRRD

Read

Active

Idle

Precharge

Active

Read

Bank #0

Bank #1

Bank #2

Precharge

Active

Precharge

Read

Bank #3

Revision 1.0

Publication Release Date: March, 1999

- 21 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Interleaved Bank Read (Burst Length=8, CAS Latency=3, Autoprecharge)

(CLK = 100 MHz)

11 12 13

6

7

8

16 17 18

1

2

3

5

9

10

14 15

19

21

0

4

20

22 23

CLK

CS

t

RC

tRC

RAS

CAS

t

RAS

t

RP

tRAS

t

RAS

tRP

WE

BS0

BS1

A10

tRCD

t

RCD

RBb

RAc

RAa

A0-A9

DQM

CAz

CAx

CBy

CKE

DQ

t

CAC

t

CAC

t

CAC

ax3

ax4

ax0

ax2

ax5 ax6

ax7

by0

by1

by4

by5

by6

ax1

CZ0

t

RRD

t

RRD

AP*

Read

Active

Bank #0 Active

Bank #1

Read

Active

Read

AP*

Bank #2

Idle

Bank #3

* AP is the internal precharge start timing

Revision 1.0

Publication Release Date: March, 1999

- 22 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Interleaved Bank Write (Burst Length=8)

(CLK = 100 MHz)

6

7

8

11

12 13

16 17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22 23

CLK

CS

t^RC

RAS

CAS

t^RAS

tRAS

tRP

tRAS

tRP

tRCD

WE

BS0

BS1

RBb

RAc

RAa

A10

A0-A9,

A11

CAx

RBb

CBy

CAz

DQM

CKE

DQ

ax0

ax1

ax4

ax5

ax6

ax7 by0

by1 by2

by3

by4

by5

by6

by7

CZ0

CZ1

CZ2

t^RRD

t_RRD

Active

Write

Precharge

Active

Write

Bank #0

Bank #1

Active

Write

Precharge

Bank #2

Bank #3

Idle

Revision 1.0

Publication Release Date: March, 1999

- 23 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Interleaved Bank Write (Burst Length=8, Autoprecharge)

(CLK = 100 MHz)

11 12 13

6

7

8

16 17 18

0

1

2

3

4

5

9

10

14 15

19 20 21 22 23

CLK

CS

tRC

RAS

CAS

tRP

tRAS

tRP

WE

BS0

BS1

tRCD

RAa

RBb

RAb

RAc

A10

A0-A9,

A11

CAx

CBy

CAz

DQM

CKE

DQ

ax4

by2

by5

ax0 ax1

ax5

ax6

ax7

by0 by1

by3

by4

by6

by7

CZ0

CZ1

CZ2

t^RRD

AP*

Write

AP*

Active

Write

Bank #0

Bank #1

Bank #2

Bank #3

Active

Write

Idle

* AP is the internal precharge start timing

Revision 1.0

Publication Release Date: March, 1999

- 24 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Page Mode Read (Burst Length=4, CAS Latency=3)

(CLK = 100 MHz)

6

7

8

11 12 13

16 17 18

1

2

3

5

9

10

14 15

19

21

0

4

20

22 23

CLK

CS

tCCD

tRAS

tRP

tRAS

tRP

RAS

CAS

WE

BS0

BS1

tRCD

RAa

RBb

A10

A0-A9,

A11

CBx

CAy

CAm

CBz

CAI

DQM

CKE

tAC

am1

am2 bz0

bz1

bz2

bz3

a0

a1

a3

bx0

Ay0

Ay1 Ay2

am0

a2

bx1

DQ

tRRD

Read

Bank #0 Active

Bank #1

Read

Precharge

Active

Read

AP*

Bank #2

Idle

Bank #3

* AP is the internal precharge start timing

Revision 1.0

Publication Release Date: March, 1999

- 25 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Page Mode Read / Write (Burst Length=8, CAS Latency=3)

(CLK = 100 MHz)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

t

RAS

t

RP

RAS

CAS

WE

BS0

BS1

t

RCD

RAa

A10

A0-A9,

A11

CAx

CAy

DQM

CKE

tAC

t

WR

ax5

ay1

ax0

ax1

ax3

ay0

ay2

ay4

ax2

ax4

ay3

DQ

Q Q

Q

D

Bank #0

Bank #1

Bank #2

Bank #3

Active

Idle

Read

Write

Precharge

Revision 1.0

Publication Release Date: March, 1999

- 26 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

AutoPrecharge Read (Burst Length = 4, CAS Latency = 3)

(CLK = 100 MHz)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

t

RC

t

RC

RAS

t

RAS

t

RP

t

RAS

t

RP

CAS

WE

BS0

BS1

A10

t

RCD

t

RCD

RAa

RAb

A0-A9,

A11

CAx

RAa

CAw

RAb

DQM

CKE

DQ

t

AC

t

AC

aw0 aw1 aw2 aw3

bx2

bx0

bx1

bx3

Bank #0

Bank #1

Bank #2

Bank #3

AP*

Active

Idle

Read

Active

Read

AP*

* AP is the internal precharge start timing

Revision 1.0

Publication Release Date: March, 1999

- 27 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

AutoPrecharge Write (Burst Length = 4)

(CLK = 100 MHz)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

tRC

RAS

CAS

tRAS

tRP

tRAS

tRP

WE

BS0

BS1

tRCD

RAc

RAa

RAb

A10

A0-A9,

A11

CAw

RAb

CAx

RAc

DQM

CKE

DQ

bx0

aw1 aw2

bx1

bx3

bx2

aw0

aw3

Active

Idle

Bank #0

Bank #1

Bank #2

Bank #3

Write

Active

Write

Active

AP*

* AP is the internal precharge start timing

Revision 1.0

Publication Release Date: March, 1999

- 28 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

AutoRefresh cycle

(CLK = 100 MHz)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22 23

CLK

CS

tRP

tRC

RAS

CAS

WE

BS0,1

A10

A0-A9,

A11

DQM

CKE

DQ

All Banks

Prechage

Auto

Refresh

Auto Refresh (Arbitrary Cycle)

Revision 1.0

Publication Release Date: March, 1999

- 29 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

SelfRefresh Cycle

(CLK = 100 MHz)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

tRP

RAS

CAS

WE

BS0,1

A10

A0-A9,

A11

DQM

t^CKS

tCKS

tSB

CKE

DQ

t^CKS

tRC

Self Refresh Cycle

No Operation Cycle

All Banks

Precharge

Self Refresh

Entry

Arbitrary Cycle

Revision 1.0

Publication Release Date: March, 1999

- 30 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Burst Read and Single Write (Burst Lenght = 4, CAS Latency = 3)

(CLK = 100 MHz)

6

7

8

11 12 13

16 17 18

1

2

3

5

9

10

14

15

19

21

0

4

20

22 23

CLK

CS

RAS

CAS

tRCD

WE

BS0

BS1

A10

RBa

A0-A9,

A11

CBz

RBa

CBv

CBw

CBx CBy

DQM

CKE

tAC

DQ

av0 av1

av3

aw0

ax0 ay0

az1

az2

az3

az0

av2

Q

D

Q

Read

Active

Single Write

Read

Bank #0

Bank #1

Bank #2

Bank #3

Idle

Revision 1.0

Publication Release Date: March, 1999

- 31 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

PowerDown Mode

(CLK = 100 MHz)

6

7

8

11

12

13

16

17

18

1

2

3

5

9

10

14

15

19

21

0

4

20

22

23

CLK

CS

RAS

CAS

WE

BS

RAa

A10

A0-A9

DQM

CAa

CAx

tSB

CKE

DQ

tCKS

ax0

ax2

ax3

ax1

Active

NOP

Precharge

NOPActive

Precharge Standby

Power Down mode

Active Standby

Power Down mode

Note: The PowerDown Mode is entered by asserting CKE "low".

All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode.

When CKE goes high, command input must be No operation at next CLK rising edge.

Revision 1.0

Publication Release Date: March, 1999

- 32 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Autoprecharge Timing ( Read Cycle )

0

1

2

3

4

5

6

7

8

9

10

11

(1) CAS Latency=2

( a ) burst length = 1

Command

Read AP

Read

Act

t

RP

DQ

Q0

( b ) burst length = 2

Command

AP

Q0

Act

t

RP

DQ

Q1

( c ) burst length = 4

Command

Read

AP

Q2

Act

Q4

t

RP

DQ

Q0

Q1

Q3

( d ) burst length = 8

Command

Read

AP

Q6

Act

t

RP

DQ

Q2

Act

Q3

Q5

Q7

(2) CAS Latency=3

( a ) burst length = 1

Command

Read AP

Read

t

RP

DQ

Q0

( b ) burst length = 2

Command

AP

Act

t

RP

DQ

Q1

AP

Q1

( c ) burst length = 4

Command

Read

Act

Q4

t

RP

DQ

Q2

Q3

( d ) burst length = 8

Command

Read

AP

Q5

Act

t

RP

DQ

Q1

Q6

Q7

Note )

Read

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

AP

Act

When the Auto precharge command is asserted, the period from Bank Activate command to

the start of internal precgarging must be at least t^RAS(min).

Revision 1.0

Publication Release Date: March, 1999

- 33 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Autoprecharge timing ( Read Cycle )

0

1

2

3

4

5

6

7

8

9

10

11

(3) CAS Latency=4

( a ) burst length = 1

Command

Read AP

Read

Act

Q0

tRP

DQ

( b ) burst length = 2

Command

Act

Q1

AP

tRP

DQ

Q0

AP

Q0

( c ) burst length = 4

Read

Act

Q3

Command

tRP

DQ

Q1

Q2

( d ) burst length = 8

Command

Read

AP

Q4

Act

Q7

tRP

DQ

Q0

Q3

Q5

Q6

Note )

Read

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

AP

Act

When the Auto precharge command is asserted, the period from Bank Activate

command to the start of internal precgarging must be at least tRAS(min).

Revision 1.0

Publication Release Date: March, 1999

- 34 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Autoprecharge timing ( Write Cycle )

0

1

2

3

4

5

6

7

8

9

10

11

(1) CAS Latency=2

( a ) burst length = 1

Command

Write

D0

AP

Act

tWR

t

RP

DQ

( b ) burst length = 2

Command

Write

D0

AP

Act

AP

t

WR

tRP

DQ

( c ) burst length = 4

Command

D1

Write

D0

Act

D6

t

WR

t

RP

DQ

( d ) burst length = 8

Command

D2

D3

Write

D0

AP

Act

t

WR

tRP

DQ

D4

D5

D7

(2) CAS Latency=3

( a ) burst length = 1

Command

Write AP

Act

tWR

tRP

DQ

D0

( b ) burst length = 2

Command

Write

D0

AP

Act

t

WR

tRP

DQ

( c ) burst length = 4

Command

D1

Write

D0

AP

D4

Act

D7

t

WR

tRP

DQ

D2

D3

( d ) burst length = 8

Command

DQ

Write

D0

AP

Act

tWR

tRP

D5

D6

Note )

Write

represents the Write with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

AP

Act

When the Auto precharge command is asserted, the period from Bank Activate

command to the start of internal precgarging must be at least tRAS(min)..

Revision 1.0

Publication Release Date: March, 1999

- 35 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Autoprecharge timing ( Write Cycle )

0

1

2

3

4

5

6

7

8

9

10

11

(3) CAS Latency=4

( a ) burst length = 1

Command

Write AP

Act

tWR

tRP

DQ

D0

( b ) burst length = 2

Command

Act

Write

AP

tWR

tRP

DQ

( c ) burst length = 4

Command

D0

D1

AP

D4

Act

D7

Write

D0

tWR

tRP

DQ

D2

D3

( d ) burst length = 8

Command

Write

D0

AP

Act

tWR

tRP

DQ

D5

D6

Note )

Write

represents the Read with Auto precharge command.

represents the start of internal precharging.

represents the Bank Activate command.

AP

Act

When the Auto precharge command is asserted, the period from Bank Activate

command to the start of internal precgarging must be at least tRAS(min).

Revision 1.0

Publication Release Date: March, 1999

- 36 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Timing Chart of Read to Write cycle

In the case of Burst Length=4

1

2

3

4

5

6

7

8

9

10

11

0

(1) CAS Latency=2

( a ) Command

Read Write

DQM

DQ

D0

D1

D2

D3

( b ) Command

Read

Write

DQM

DQ

D0

D1

D2

D3

(2) CAS Latency=3

( a ) Command

Read Write

DQM

DQ

D0

D1

( b ) Command

Read

Write

DQM

D0

D1

D2

DQ

(3) CAS Latency=4

( a ) Command

Read Write

DQM

DQ

D0

D1

D2

D1

D3

D2

( b ) Command

DQM

Read

Write

DQ

D0

Note ) The Output data must be masked by DQM to avoid I/O conflict

Revision 1.0

Publication Release Date: March, 1999

- 37 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Timing Chart of Write-to-Read cycle

In the case of Burst Length=4

1

2

3

4

5

6

7

8

9

10

11

0

(1) CAS Latency=2

Write Read

( a ) Command

DQM

DQ

D0

Q0

Q1

Q0

Q2

Q1

Q3

Q2

( b ) Command

Read

Write

DQM

DQ

D0

D1

Q3

(2) CAS Latency=3

( a ) Command

DQM

Read

Write

DQ

D0

Q0

Q1

Q0

Q2

Q1

Q3

Q2

( b ) Command

DQM

Write

Read

D0

D1

Q3

DQ

(3) CAS Latency=4

( a ) Command

Write Read

DQM

DQ

D0

Q0

Q1

Q0

Q2

Q1

Q3

Q2

( b ) Command

DQM

Write

Read

DQ

D0

D1

Q3

Revision 1.0

Publication Release Date: March, 1999

- 38 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Timing chart of Burst Stop cycle ( Burst stop Command )

0

1

2

3

4

5

6

7

8

9

10

11

(3) Read cycle

( a ) CAS latency =2

Command

Read

BST

DQ

Q4

Q3

Q2

Q0

Q1

Q0

Q2

Q1

Q0

Q3

BST

Q2

( b )CAS latency = 3

Command

Read

DQ

Q4

Q3

( c )CAS latency = 4

BST

Q1

Command Read

Q4

DQ

(2) Write cycle

Command

BST

Write

D0

DQ

D1

D2

D3

D4

Note )

represents the Burst stop command

BST

Revision 1.0

Publication Release Date: March, 1999

- 39 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Timing chart of Burst Stop cycle ( Precharge Command )

In the case of Burst Lenght = 8

0

1

2

3

4

5

6

7

8

9

10

11

(1) Read cycle

( a )CAS latency =2

Commad

PRCG

Read

DQ

Q4

Q0

Q1

Q0

Q2

Q1

Q0

Q3

( b )CAS latency = 3

Commad

PRCG

Read

DQ

Q4

Q3

Q2

Q3

( c )CAS latency = 4

Commad

PRCG

DQ

Q1

Q2

Q4

(2) Write cycle

( a ) CAS latency =2

PRCG

Commad

Write

tWR

DQM

DQ

D4

D0

D1

D2

D3

( b )CAS latency = 3

PRCG

tWR

Commad

Write

DQM

DQ

D0

( c )CAS latency = 4

PRCG

tWR

Write

DQM

DQ

D0

D1

D2

D3

D4

Note )

PRCG represents the Precharge command

Revision 1.0

Publication Release Date: March, 1999

- 40 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

CKE/DQM Input timing ( Write cycle )

1

CLK cycle No.

2

3

4

5

7

6

External

CLK

Internal

CKE

DQM

DQ

D1

D2

D3

D5

D6

DQM MASK

CKE MASK

( 1 )

CLK cycle No.

External

2

3

4

5

7

1

6

CLK

Internal

CKE

DQM

DQ

D1

D2

D3

D5

D6

DQM MASK

( 2 )

CKE MASK

1

2

3

4

5

6

7

CLK cycle No.

External

CLK

Internal

CKE

DQM

DQ

D1

D2

D3

D4

D5

D6

CKE MASK

( 3 )

Revision 1.0

Publication Release Date: March, 1999

- 41 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

CKE/DQM Input timing ( Read cycle )

1

CLK cycle No.

2

6

3

4

5

7

External

Internal

CKE

DQM

DQ

Q6

Q1

Q2

Q3

Q4

Open

( 1 )

1

2

3

4

5

7

CLK cycle No.

6

External

Internal

CLK

CKE

DQM

DQ

Q6

Q3

Q1

Q2

Q4

Open

( 2 )

1

CLK cycle No.

2

3

4

5

6

7

External

CLK

Internal

CKE

DQM

DQ

Q6

Q1

Q4

Q5

Q3

Q2

( 3 )

Revision 1.0

Publication Release Date: March, 1999

- 42 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Self Refresh/Power Down Mode Exit Timing

Asynchronous Control

Input Buffer turn on time ( Power down mode exit time ) is specified by tCKS(min) + tCK(min)

A ) tCK < tCKS(min)+tCK(min)

tCK

CLK

CKE

t^CKS(min)+t^CK(min)

Command

NOP

Input Buffer Enable

B) tCK >= tCKS(min) + tCK (min)

t^CK

CLK

t

CKS(min)+tCK(min)

CKE

Command

Input Buffer Enable

Note )

All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode

and Self Refresh mode

NOP

Represents the No-Operation command

Command

Represents one command

Revision 1.0

Publication Release Date: March, 1999

- 43 -

W981216AH

2M x 16 bit x 4 Banks SDRAM

Package Dimension

54L TSOP (II) mil

54

28

H_E

E

1

27

e

b

C

D

L

A2

A1

A

L1

ZD

Y

SEATING PLANE

Controlling Dimension : Millimeters

DIMENSION

(MM)

DIMENSION

(INCH)

SYMBOL

MIN.

NOM.

MAX.

MIN.

NOM.

MAX.

1.20

0.15

0.047

0.006

A

A1

0.05

0.24

0.10

1.00

0.002

0.009

0.004

0.039

A2

b

0.32

0.40

0.016

0.012

0.006

c

0.15

22.12

10.06

11.56

22.22

10.16

22.62

10.26

11.96

0.871

0.396

0.455

0.875

0.400

0.463

0.0315

0.020

0.032

0.905

0.404

0.471

D

E

11.76

0.80

0.50

0.80

H

E

e

0.60

0.10

0.016

0.024

0.004

L

0.40

L1

Y

ZD

0.71

0.028

Revision 1.0

Publication Release Date: March, 1999

- 44 -


型号：	W981216AH
厂家：	WINBOND
描述：	2M x 16 bit x 4 Banks SDRAM 2M ×16位×4银行SDRAM 动态存储器
文件：	总44页 (文件大小：2152K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W981216AH [WINBOND]

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