WM8782SEDS/RV [WOLFSON]
24-Bit, 192kHz Stereo ADC; 24位， 192kHz立体声ADC
| 型号： | WM8782SEDS/RV |
| 厂家： | 
WOLFSON MICROELECTRONICS PLC |
| 描述： | 24-Bit, 192kHz Stereo ADC |
| 文件： | 总20页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8782
w
24-Bit, 192kHz Stereo ADC
DESCRIPTION
FEATURES
SNR 100dB (‘A’ weighted @ 48kHz)
The WM8782 is a high performance, low cost stereo audio
ADC designed for recordable media applications.
THD -93dB (at –1dB)
Sampling Frequency: 8 – 192kHz
Master or Slave Clocking Mode
The device offers stereo line level inputs along with two
control input pins (FORMAT, IWL) to allow operation of the
audio interface in three industry standard modes. An
internal op-amp is integrated on the front end of the chip to
System Clock (MCLK): 128fs, 192fs, 256fs, 384fs, 512fs,
768fs
accommodate analogue input signals greater than 1Vrms
.
-
Audio Data Interface Modes
The device also has a high pass filter to remove residual
DC offsets.
16-24 bit I2S, 16-24 bit Left, 16-24 bit Right Justified
Supply Voltages
WM8782 offers Master or Slave mode clocking schemes.
A control input pin M/S is used to allow Slave mode
operation or Master mode operation. A stereo 24-bit multi-
bit sigma-delta ADC is used with 128x, 64x or 32x over-
sampling, according to sample rate. Digital audio output
word lengths from 16-24 bits and sampling rates from 8kHz
to 192kHz are supported.
-
-
Analogue: 2.7 to 5.5V
Digital core: 2.7V to 3.6V
20-lead SSOP or 20-lead TSSOP package
Accelerated Lifetime Screened Devices available.
APPLICATIONS
Recordable DVD Players
Personal Video Recorders
STB
Studio Audio Processing Equipment
Automotive
The device is a hardware controlled device and is supplied
in a 20-lead SSOP package.
The device is available over a functional temperature range of
-40C to +85C
BLOCK DIAGRAM
Production Data, April 2010, Rev 4.7
WOLFSON MICROELECTRONICS plc
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Copyright 2010 Wolfson Microelectronics plc
WM8782
Production Data
TABLE OF CONTENTS
DESCRIPTION....................................................................................................... 1
FEATURES............................................................................................................ 1
APPLICATIONS..................................................................................................... 1
BLOCK DIAGRAM ................................................................................................ 1
TABLE OF CONTENTS......................................................................................... 2
PIN CONFIGURATION.......................................................................................... 3
ORDERING INFORMATION.................................................................................. 3
PIN DESCRIPTION................................................................................................ 4
ABSOLUTE MAXIMUM RATINGS........................................................................ 5
THERMAL PERFORMANCE................................................................................. 5
RECOMMENDED OPERATING CONDITIONS..................................................... 6
ELECTRICAL CHARACTERISTICS ..................................................................... 6
TERMINOLOGY............................................................................................................... 7
SIGNAL TIMING REQUIREMENTS ...................................................................... 8
SYSTEM CLOCK TIMING................................................................................................ 8
AUDIO INTERFACE TIMING – MASTER MODE ............................................................ 8
AUDIO INTERFACE TIMING – SLAVE MODE................................................................ 9
SLAVE MODE MCLK / BCLK TIMING ........................................................................... 10
DEVICE DESCRIPTION ...................................................................................... 11
INTRODUCTION............................................................................................................ 11
ADC................................................................................................................................ 11
ADC DIGITAL FILTER ................................................................................................... 11
DIGITAL AUDIO INTERFACE........................................................................................ 12
POWER ON RESET ...................................................................................................... 15
DIGITAL FILTER CHARACTERISTICS .............................................................. 17
ADC FILTER RESPONSES........................................................................................... 17
ADC HIGH PASS FILTER.............................................................................................. 18
APPLICATIONS INFORMATION ........................................................................ 19
RECOMMENDED EXTERNAL COMPONENTS............................................................ 19
RECOMMENDED EXTERNAL COMPONENTS VALUES............................................. 19
PACKAGE DIMENSIONS.................................................................................... 20
20 PIN SSOP ................................................................................................................. 20
20 PIN TSSOP ............................................................................................................... 21
IMPORTANT NOTICE ......................................................................................... 21
ADDRESS:.....................................................................................................................21
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WM8782
PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
11
M/S
1
MCLK
DOUT
LRCLK
DGND
DVDD
BCLK
AINL
2
AINOPL
COM
3
4
5
AINR
AINOPR
6
7
AGND
IWL
FSAMPEN
FORMAT
VMID
8
AVDD
9
VREFP
VREFGND
10
ORDERING INFORMATION
DEVICE
TEMPERATURE
RANGE
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PEAK SOLDERING
TEMPERATURE
WM8782SEDS/V
-40C to +85C
20-lead SSOP
(Pb-free)
MSL2
260oC
WM8782SEDS/RV
-40C to +85C
20-lead SSOP
MSL2
260oC
(Pb-free, tape and reel)
Note:
Reel quantity = 2,000
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PIN DESCRIPTION
NAME
TYPE
DESCRIPTION
PIN NO.
Digital Input
Digital Output
Digital Input / Output
Supply
Master Clock
1
2
3
4
5
6
7
MCLK
DOUT
LRCLK
DGND
DVDD
BCLK
IWL
ADC Digital Audio Data
Audio Interface Left / Right Clock
Digital Negative Supply
Digital Positive Supply
Audio Interface Bit Clock
Word Length
Supply
Digital Input / Output
Digital Tristate Input
0 = 16 bit
1 = 20 bit
Z = 24 bit
Digital Tristate Input
Digital Tristate Input
Fast Sampling Rate Enable
0 = 48kHz
8
9
FSAMPEN
FORMAT
1= 96kkHz
Z= 192kHz
Audio Mode Select
0 = RJ
1 = LJ
Z = I2S
Analogue Output
Supply
Mid rail Voltage Decoupling Capacitor
Negative Supply and Substrate Connection
10
11
12
13
14
15
16
17
18
19
20
VMID
VREFGND
VREFP
AVDD
Analogue Output
Supply
Positive Reference Voltage Decoupling Pin; 10uF external decoupling
Analogue Positive Supply
Supply
Analogue Negative Supply and Substrate Connection
Right Channel Internal Op-Amp Output
Right Channel Input
AGND
AINOPR
AINR
Analogue Output
Analogue Input
Analogue Input
Analogue Output
Analogue Input
Digital Input
Common mode high impedance input should be set to midrail.
Left Channel Internal Op-Amp Output
Left Channel Input
COM
AINOPL
AINL
Interface Mode Select
M/S
0 = Slave mode (128fs, 192fs, 256fs, 384fs, 512fs, 768fs)
1 = Master mode (256fs, 128fs)
(fs=word clock frequency)
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WM8782
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level is specified in Ordering Information.
CONDITION
MIN
-0.3V
MAX
+4.5V
Digital supply voltage
Analogue supply voltage
Voltage range digital inputs
Voltage range analogue inputs
-0.3V
+7V
DGND -0.3V
AGND -0.3V
-55C
DVDD + 0.3V
AVDD +0.3V
+125C
Ambient temperature (supplies applied)
Storage temperature
-65C
+150C
Pb free package body temperature (reflow 10 seconds)
Package body temperature (soldering 2 minutes)
Notes:
+260C
+183C
1. Analogue and digital grounds must always be within 0.3V of each other.
THERMAL PERFORMANCE
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
81
MAX
UNIT
°C/W
Thermal resistance – junction to
ambient
RθJA
See note 1
Notes:
1. Figure given for package mounted on 4-layer FR4 according to JESD51-7. (No forced air flow is assumed).
2. Thermal performance figures are estimated.
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RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
WM8782SEDS,
MIN
TYP
MAX
UNIT
Digital supply range
DVDD
2.7
3.6
V
WM8782SEDS/R
WM8782SEDS,
Analogue supply range
AVDD
2.7
-40
5.5
V
WM8782SEDS/R
Ground
DGND,AGND
TA
0
V
Operating temperature range
WM8782SEDS,
+85
C
WM8782SEDS/R
Notes:
1. Digital supply DVDD must never be more than 0.3V greater than AVDD.
ELECTRICAL CHARACTERISTICS
Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vrms
kΩ
ADC Performance – WM8782SEDS, WM8782SEDS/R (+25˚C)
Full Scale Input Signal Level
1.0
(for ADC 0dB Input)
Input resistance, using
recommended external resistor
network on p22.
10
Input capacitance
20
pF
dB
Signal to Noise Ratio
(see Terminology note 1,2,4)
SNR
SNR
THD
weighted,
@ fs = 48kHz
Unweighted,
@ fs = 48kHz
weighted,
93
100
98
98
dB
dB
@ fs = 48kHz,
AVDD = 3.3V
weighted,
Signal to Noise Ratio
(see Terminology note 1,2,4)
98
98
98
dB
dB
dB
@ fs = 96kHz
Unweighted,
@ fs = 96kHz
weighted,
@ fs = 96kHz
AVDD = 3.3V
Total Harmonic Distortion
1kHz, -1dB Full Scale
@ fs = 48kHz
-93
-93
-92
dB
dB
dB
1kHz, -1dB Full Scale
@ fs = 96kHz
1kHz, -1dB Full Scale
@ fs = 192kHz
Dynamic Range
DNR
-60dBFS
93
100
90
dB
dB
Channel Separation
1kHz Input
(see Terminology note 4)
Channel Level Matching
Channel Phase Deviation
Power Supply Rejection Ratio
1kHz signal
1kHz signal
0.1
0.0001
50
dB
Degree
dB
PSRR
1kHz 100mVpp, applied
to AVDD, DVDD
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Test Conditions
DVDD = 3.3V, AVDD = 5.0V, TA = +25oC, 1kHz signal, A-weighted, fs = 48kHz, MCLK = 256fs, 24-bit audio data, Slave Mode
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (TTL Levels)
Input LOW level
VIL
0.8
V
Input HIGH level
VIH
2.0
-1
V
Input leakage current – digital pad
±0.2
85
+1
µA
µA
Input leakage current – digital
tristate input (Note 3)
Input capacitance
5
pF
V
Output LOW
VOL
VOH
IOL=1mA
0.1 x DVDD
+4%
Output HIGH
IOH= -1mA
0.9 x DVDD
–4%
V
Analogue Reference Levels
Midrail Reference Voltage
VMID
AVDD to VMID and
VMID to VREFN
AVDD/2
V
Potential Divider Resistance
Buffered Reference Voltage
VREF source current
VREF sink current
RVMID
VREFP
IVREF
70
kΩ
V
–4%
AVDD/2
+4%
5
5
mA
mA
IVREF
Supply Current
Analogue supply current
Digital supply current
Power Down
AVDD = 5V
26
5
mA
mA
mA
DVDD = 3.3V
0.5
Notes:
1. All performance measurements are done with a 20kHz low pass filter, and where noted an A-weight filter. Failure to
use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the
Electrical Characteristics. The low pass filter removes out of band noise; although this is not audible, it may affect
dynamic specification values.
2. VMID is decoupled with 10uF and 0.1uF capacitors close to the device package. Smaller capacitors may reduce
performance.
3. This high leakage current is due to the topology of the instate pads. The pad input is connected to the midpoint of an
internal resistor string to pull input to vmid if undriven.
TERMINOLOGY
1. Signal-to-noise ratio (dB) – Ratio of output level with 1kHz full scale input, to the output level with all zeros into the
digital input, over a 20Hz to 20kHz bandwidth. (No Auto-zero or Automute function is employed in achieving these
results).
2. Dynamic range (dB) – DR is a measure of the difference between the highest and lowest portions of a signal. Normally
a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g.
THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) – THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Channel Separation (dB) – Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, Slave Mode, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK duty cycle
TMCLKL
TMCLKH
TMCLKY
TMCLKDS
11
11
ns
ns
ns
28
40:60
60:40
Table 1 Master Clock Timing Requirements
AUDIO INTERFACE TIMING – MASTER MODE
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRCLK propagation delay from BCLK falling edge
DOUT propagation delay from BCLK falling edge
tDL
0
0
10
10
ns
ns
tDDA
Table 2 Digital Audio Data Timing – Master Mode
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WM8782
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
tLRSU
tLRH
tDD
50
20
20
10
10
0
ns
ns
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
DOUT propagation delay from BCLK falling edge
10
Table 3 Digital Audio Data Timing – Slave Mode
Note:
LRCLK should be synchronous with MCLK.
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SLAVE MODE MCLK / BCLK TIMING
A
B
MCLK1
V_LOW
BCLK
V_LOW
V_HI
MCLK2
D
Keep-out area for MCLK/BCLK relationship
C
Figure 4 MCLK / BCLK prohibited timing relationship in slave mode
TIMING
TIME (ns)
DESCRIPTION
A
B
C
D
9
4
9
4
MCLK falling edge to BCLK falling edge keep-out window
MCLK rising edge to BCLK falling edge keep-out window
Table 4 Prohibited area timings
In slave mode operation, there are two windows where the BCLK falling edge relative to the MCLK
falling/rising edge is not allowed, as defined in Figure 4 and Table 4. Any device with clocks operating
in this area may cause incorrect operation of the ADC, as detailed in WTR0444.
This specification is guaranteed by design rather than test, and the timings are related to the
switching level of the MCLK and BCLK pads. Simulation has shown the switching level range for both
the MCLK and BCLK pads across process, voltage and temperature to be as per the table below.
SWITCHING LEVEL
MIN (V)
1.1
MAX (V)
1.4
V_LOW
V_HI
1.3
1.6
Table 5 Simulated switching area range
If the above timing constraints cannot be met in slave mode, it is recommended that WM8782A
silicon is used in place of WM8782.
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WM8782
DEVICE DESCRIPTION
INTRODUCTION
The WM8782 is a stereo 24-bit ADC designed for demanding recording applications such as DVD
recorders, studio mixers, PVRs, and AV amplifiers. The WM8782 consists of stereo line level inputs,
followed by a sigma-delta modulator and digital filtering.
The device offers stereo line level inputs along with two control input pins (FORMAT, IWL) to allow
operation of the audio interface in three industry standard modes (left justified, right justified or I2S) .
An internal op-amp is integrated on the front end of the chip to accommodate analogue input signals
greater than 1Vrms. The device also has a high pass filter to remove residual DC offsets.
The WM8782 offers Master or Slave mode clocking schemes. A control input pin M/S is used to allow
Slave mode or Master mode operation. The WM8782 supports master clock rates from 128fs to 768fs
and digital audio output word lengths from 16-24 bits. Sampling rates from 8kHz to 192kHz are
supported, delivering high SNR operating with 128x, 64x or 32x over-sampling, according to the
sample rate.
The line inputs are biased internally through the operational amplifier to VMID
.
ADC
The WM8782 uses a multi-bit over sampled sigma-delta ADC. A single channel of the ADC is
illustrated in Figure 5.
ANALOG
INTEGRATOR
LIN/RIN
TO ADC DIGITAL FILTERS
MULTI
BITS
Figure 5 Multi-Bit Oversampling Sigma Delta ADC Schematic
The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high
frequency noise.
The ADC Full Scale input is 1.0V rms at AVDD = 5.0 volts. Any input voltage greater than full scale
will possibly overload the ADC and cause distortion. Note that the full scale input has a linear
relationship with AVDD. The internal op-amp and appropriate resistors can be used to reduce signals
greater than 1Vrms before they reach the ADC.
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface.
ADC OUTPUT PHASE
In the input to output data-path, the digital output data DOUT, is a phase inverted representation of
the analogue input signal.
ADC DIGITAL FILTER
The ADC digital filters contain a digital high pass filter. The high-pass filter response detailed in Digital
Filter Characteristics. The operation of the high pass filter removes residual DC offsets that are
present on the audio signal.
.
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DIGITAL AUDIO INTERFACE
The digital audio interface uses three pins:
DOUT: ADC data output
LRCLK: ADC data alignment clock
BCLK: Bit clock, for synchronisation
The digital audio interface takes the data from the internal ADC digital filters and places it on DOUT
and LRCLK. DOUT is the formatted digital audio data stream output from the ADC digital filters with
left and right channels multiplexed together. LRCLK is an alignment clock that controls whether Left
or Right channel data is present on the DOUT line. DOUT and LRCLK are synchronous with the
BCLK signal with each data bit transition signified by a BCLK high to low transition. DOUT is always
an output. BCLK and LRCLK maybe an inputs or outputs depending whether the device is in Master
or Slave mode. (see Master and Slave Mode Operation, below).
Three different audio data formats are supported:
Left justified
Right justified
I2S
MASTER AND SLAVE MODE OPERATION
The WM8782 can be configured as either a master or slave mode device. As a master device the
WM8782 generates BCLK and LRCLK and thus controls sequencing of the data transfer on DOUT. In
slave mode, the WM8782 responds with data to clocks it receives over the digital audio interface. The
mode can be selected by setting the MS input pin (see Table 6 Master/Slave selection below).
Master and slave modes are illustrated below.
Figure 6 Master Mode
PIN
Figure 7 Slave Mode
DESCRIPTION
M/S
Master/Slave Selection
0 = Slave Mode
1= Master Mode
Table 6 Master/Slave selection
AUDIO INTERFACE CONTROL
The Input Word Length and Audio Format mode can be selected by using IWL and FORMAT pins.
PIN DESCRIPTION
IWL
Word Length
0 = 16 bit
1 = 20 bit
Z = 24 bit
FORMAT
Audio Mode Select
0 = RJ
1 = LJ
Z = I2S
Table 7 Audio Data Format Control
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AUDIO DATA FORMATS
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRCLK
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.
Figure 8 Left Justified Audio Interface (assuming n-bit word length)
In Right Justified mode, the LSB is available on the last rising edge of BCLK before an LRCLK
transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.
Figure 9 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following an LRCLK transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
Figure 10 I2S Audio Interface (assuming n-bit word length)
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MASTER CLOCK AND AUDIO SAMPLE RATES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock (MCLK). The external master system clock can be applied directly through the MCLK
input pin. In a system where there are a number of possible sources for the reference clock it is
recommended that the clock source with the lowest jitter be used to optimise the performance of the
ADC.
The master clock is used to operate the digital filters and the noise shaping circuits. The WM8782
supports master clocks of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs, where fs is the audio sampling
frequency (LRCLK). In Slave Mode, the WM8782 automatically detects the audio sample rate. In
Master Mode, LRCLK is generated for rate 256fs, unless the user changes this to 128fs using the
FSAMPEN pin = z (see Table 9 below). BCLK is also generated in Master Mode. BCLK=MCLK/4 for
256fs, and BCLK=MCLK/2 for 128fs.
Table 8 shows the common MCLK frequencies for different sample rates.
SAMPLING RATE
(LRCLK)
Master Clock Frequency (MHz)
128fs
192fs
256fs
384fs
512fs
768fs
8kHz
16kHz
32kHz
44.1kHz
48kHz
96kHz
192kHz
1.024
2.048
1.536
3.072
6.144
8.467
9.216
18.432
36.864
2.048
4.096
8.192
3.072
6.144
4.096
8.192
6.144
12.288
24.576
4.096
12.288
16.384
5.6448
6.144
11.2896 16.9340 22.5792 33.8688
12.288
24.576
-
18.432
36.864
-
24.576
36.864
12.288
24.576
-
-
-
-
Table 8 Master Clock Frequency Selection
In Slave mode, the WM8782 has a master detection circuit that automatically determines the
relationship between the master clock frequency and the sampling rate (to within +/- 32 system
clocks). If there is a greater than 32 clocks error the interface sets itself to the highest rate available
(768fs). There must be a fixed number of MCLKS per LRCLK, although the WM8782 is tolerant of
phase variations or jitter on these clocks.
FSAMPEN
The FSAMPEN pin controls the over sampling rate of the ADC. The WM8782 can operate at sample
rates from 8kHz to 192kHz. The WM8782 uses a sigma-delta modulator that operates at an optimal
frequency of 6.144MHz.
By default the WM8782 generates the ADC frequency at 128xOSR. At fs=48kHz, the ADC frequency
is 128xOSR = 128x48kHz = 6.144MHz.
If fs=96KHz, the FSAMPEN pin must be set to 1. In this case, the ADC frequency is 64xOSR =
64x96kHz = 6.144MHz.
If fs=192KHz, the FSAMPEN pin must be set to z. In this case, the ADC frequency is 32xOSR =
32x192kHz = 6.144MHz.
It is recommended that the above settings are used for both master and slave mode.
PIN
DESCRIPTION
M/S
Master/Slave Selection
0 = Slave Mode (128fs, 192fs,
256fs, 384fs, 512fs, 768fs)
1= Master Mode (256fs, 128fs
when FSAMPEN=z)
FSAMPEN
Fast sampling rate enable
0 = 48ken (128x OSR)
1= 96ken (64x OSR)
z= 192ken (32x OSR)
Table 9 Master/Slave and Sampling Rate Enable Selection
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WM8782
POWER DOWN CONTROL
The WM8782 can be powered down by stopping MCLK. Power down mode using MCLK is entered
after 65536/fs clocks. On power-up, the WM8782 applies the power-on reset sequence described
below.
When MCLK is stopped DOUT is forced to zero.
POWER ON RESET
Figure 11 Power Supply Timing Requirements – Power-on
Figure 12 Power Supply Timing Requirements – Power-down
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Production Data
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = DGND = 0V, TA = +25°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Input Timing Information
DVDD level to activate POR –
power on
Vpora
Vpora
Vpora
Vporr
Vporr
Vporr
tpor
Measured from DGND
Measured from AGND
Measured from AGND
Measured from DGND
Measured from AGND
Measured from AGND
0.7
0.7
V
V
AVDD level to activate POR –
power on
VMID level to activate POR –
power on
0.7
V
DVDD level to release POR –
power on (see notes 1 and 2)
DVDD Min
AVDD Min
1
V
AVDD level to release POR –
power on (see notes 1 and 2)
V
VMID level to release POR –
power on (see notes 1 and 2)
V
POR active period (see notes
1 and 2)
Measured from POR
active to POR release
30
Defined by DVDD/AVDD/
VMID Rise Time
0.8
s
(note 6)
DVDD level to activate POR –
power off (see note 5)
Vpor_off
Vpor_off
Vpor_off
tpon
Measured from DGND
Measured from AGND
Measured from AGND
V
V
AVDD level to activate POR –
power off (see note 5)
0.8
0.7
30
VMID level to activate POR –
power off (see note 5)
V
Power on – POR propagation
delay through device
Measured from rising
EDGE of POR
s
s
Power down – POR
propagation delay through
device
tpoff
Measured from falling
EDGE of POR
30
Notes:
1. POR is activated when DVDD or AVDD or VMID reach their stated Vpora level (Figure 11)
2. POR is only released when DVDD and AVDD and VMID have all reached their stated Vporr levels (Figure 11).
3. The rate of rise of VMID depends on the rate of rise of AVDD, the internal 50kΩ resistance and the external decoupling
capacitor. Typical tolerance of 50K resistor can be taken as +/-20%.
4. If AVDD, DVDD or VMID suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go
below Vpor_off,), then the chip will not reset and will resume normal operation when the voltage is back to the
recommended level again.
5. The chip will enter reset at power down when AVDD or DVDD or VMID falls below Vpor_off. This may be important if the
supply is turned on and off frequently by a power management system.
6. The minimum tpor period is maintained even if DVDD, AVDD and VMID have zero rise time. This specification is
guaranteed by design rather than test.
PD, April 2010, Rev 4.7
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Production Data
WM8782
DIGITAL FILTER CHARACTERISTICS
The WM8782 digital filter characteristics scale with sample rate.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC Sample Rate (Single Rate – 48Hz typically)
Passband
+/- 0.01dB
-6dB
0
0.4535fs
+/- 0.01
0.4892fs
Passband Ripple
Stopband
dB
0.5465fs
-65
Stopband Attenuation
Group Delay
f > 0.5465fs
dB
fs
22
ADC Sample Rate (Dual Rate – 96kHz typically)
Passband
+/- 0.01dB
-6dB
0
0.4535fs
+/- 0.01
0.4892fs
Passband Ripple
Stopband
dB
0.5465fs
-65
Stopband Attenuation
Group Delay
f > 0.5465fs
dB
fs
22
Table 10 Digital Filter Characteristics
ADC FILTER RESPONSES
0.02
0.015
0.01
0
-20
-40
-60
-80
0.005
0
-0.005
-0.01
-0.015
-0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0
0.5
1
1.5
2
2.5
3
Frequency (Fs)
Frequency (Fs)
Figure 13 Digital Filter Frequency Response
Figure 14 ADC Digital Filter Ripple
PD, April 2010, Rev 4.7
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WM8782
Production Data
ADC HIGH PASS FILTER
The WM8782 has a digital highpass filter to remove DC offsets. The filter response is characterised by the following
polynomial.
1 - z-1
H(z) =
1 - 0.9995z-1
0
-5
-10
-15
0
0.0005
0.001
Frequency (Fs)
0.0015
0.002
Figure 15 ADC Highpass Filter Response
PD, April 2010, Rev 4.7
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Production Data
WM8782
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 16 External Components Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT
REFERENCE
SUGGESTED
VALUE
DESCRIPTION
C1 and C8
C2 and C7
C5 and C6
R1
10F
0.1F
10F
10k
10k
5k
De-coupling for DVDD and AVDD
De-coupling for DVDD and AVDD
Analogue input AC coupling caps
Current limiting resistors
R2 and R5
R3 and R6
R4
Internal op-amp input resistor
Internal op-amp feedback resistor
Common mode resistor
3.3k
0.1F
10F
0.1F
10F
C4
Reference de-coupling capacitors for VMID pin
C3
C9
Reference de-coupling capacitors for VREFP pin
C10
Table 11 External Components Description
The above Table 11 shows resistor values which will give a gain of 0.5. This assumes an input signal of 2Vrms to C4 and
C5.
PD, April 2010, Rev 4.7
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WM8782
Production Data
PACKAGE DIMENSIONS
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
DM0015.C
b
e
20
11
E1
E
GAUGE
PLANE
1
10
D
0.25
L
c
A1
A A2
L
1
-C-
C
0.10
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
-----
MAX
2.0
-----
1.85
0.38
0.25
7.50
A
A1
A2
b
c
D
e
E
E1
L
0.05
1.65
0.22
0.09
6.90
-----
1.75
0.30
-----
7.20
0.65 BSC
7.80
7.40
5.00
0.55
8.20
5.60
0.95
5.30
0.75
L1
1.25 REF
0o
4o
8o
-
JEDEC.95, MO 150
REF:
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
PD, April 2010, Rev 4.7
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