XA9572XL-10VQG64I [XILINX]

Flash PLD, 10ns, 72-Cell, CMOS, PQFP64, VQFP-64;


型号：	XA9572XL-10VQG64I
厂家：	XILINX, INC
描述：	Flash PLD, 10ns, 72-Cell, CMOS, PQFP64, VQFP-64 输入元件可编程逻辑
文件：	总4页 (文件大小：61K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XA9500XL High-Performance

CPLD Automotive XA Product

Family

DS108-1 (v1.5) September 29, 2005

Preliminary Product Specification

data sheet (DS056) for pin tables

Features

•

Xilinx received TS 16949 Certification in March 2005.

•

AEC-Q100 device qualification and full PPAP support

available in both extended temperature Q-grade and

I-grade.

Description

The XA9500XL 3.3V CPLD Automotive XA product family is

targeted for leading-edge, high-performance automotive

applications that require either automotive industrial (–40°C

to +85°C ambient) or extended (–40°C to +125°C ambient)

temperature reconfigurable devices.

•

Guaranteed to meet full electrical specifications over

T_A= –40°C to +125°C (Q-grade)

•

System frequency up to 100 MHz (10 ns)

Available in small footprint packages

Optimized for high-performance 3.3V systems

5V tolerant I/O pins accept 5V, 3.3V, and 2.5V

signals — ideal for multi-voltage system interfacing

and level shifting

Power Estimation

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

in the XA9500XL device can be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

Technology: 0.35µm CMOS process

•

Advanced system features

In-system programmable enabling higher system

reliability through reduced handling and reducing

production programming times

Superior pin-locking and routability with

FastCONNECT™ II switch matrix allowing for

multiple design iterations without board re-spins

Input hysteresis on all user and boundary-scan pin

inputs to reduce noise on input signals

Bus-hold circuitry on all user pin inputs which

reduces cost associated with pull-up resistors and

reduces bus loading

For a general estimate of I_CC, the following equation may be

used:

I_CC(mA) = MC_HP(0.5) + MC_LP(0.3) + MC(0.0045 mA/MHz) f

where:

MC_HP= Macrocells in high-performance (default)

mode

Full IEEE Standard 1149.1 boundary-scan (JTAG)

for in-system device testing

MC_LP= Macrocells in low-power mode

MC = Total number of macrocells used

f = Clock frequency (MHz)

Fast concurrent programming

•

Slew rate control on individual outputs for reducing EMI

generation

This calculation is based on typical operating conditions

using a pattern of 16-bit up/down counters in each Function

Block with no output loading. The actual I_CCvalue varies

with the design application and should be verified during

normal system operation.

Refer to XC9500XL Family data sheet (DS054) for

architecture description

Refer to XC9536XL data sheet (DS058), the

XC9572XL data sheet (DS057), and the XC95144XL

Table 1: XA9500XL Device Family

Device Temperature Grade

XA9536XL

Macrocells

Usable Gates

800

Registers

_SYSTEM(MHz)

I, Q

100

XA9572XL

1,600

XA95144XL

144

3,200

144

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS108-1 (v1.5) September 29, 2005

www.xilinx.com

Preliminary Product Specification

XA9500XL High-Performance CPLD Automotive XA Product Family

Table 2: XA9500XL Packages and User I/O Pins (not including four dedicated JTAG pins)

Device

XA9536XL

XA9572XL

XA95144XL

VQG44

VQG64

TQG100

CSG144

117

(1)

Absolute Maximum Ratings

Symbol

Description

Min.

Max.

Units

V_CC

V_IN

Supply voltage relative to GND

Input voltage relative to GND⁽²⁾

Voltage applied to 3-state output⁽²⁾

Storage temperature (ambient)

Junction temperature

–0.5

–65

4.0

5.5

V_TS

T_STG

T_J

5.5

+150

^oC

Notes:

1. All automotive customers are required to use Low Power/Density Mode.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions

is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.

3. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the

device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the

forcing current being limited to 200 mA.

4. For soldering guidelines, see the Package Information on the Xilinx website.

Recommended Operating Conditions

Symbol

T_A

Parameter

Min

–40

3.0

2.3

Max

+125

3.6

Units

°C

Ambient temperature

V_CCINT

V_CCIO

Supply voltage for internal logic and input buffers

Supply voltage for output drivers for 3.3V operation

Supply voltage for output drivers for 2.5V operation

Low-level input voltage

3.6

2.7

V_IL

V_IH

V_O

0.80

5.5

High-level input voltage

2.0

Output voltage

V_CCIO

Quality and Reliability Characteristics

Symbol

T_DR

Parameter

Min

Max

Units

Data Retention

Years

N_PE

Program/erase cycles (Endurance) @ T_A= 70°C

10,000

Cycles

www.xilinx.com

DS108-1 (v1.5) September 29, 2005

Preliminary Product Specification

XA9500XL High-Performance CPLD Automotive XA Product Family

Component Availability

Pins

Type

Code

100

144

Quad Flat Pack

Quad Flat Pack Thin Quad Flat Pack Chip Scale Package

VQG44

I,Q

VQG64

TQG100

CSG144

XA9536XL

XA9572XL

XA95144XL

-10

I,Q

Notes:

1. Q = Automotive Extended Temperature (T_A= –40°C to +125°C).

2. I = Automotive Industrial Temperature (T_A= –40°C to +85°C).

3. All packages Pb-free.

Ordering Information

Example:

Device Type

Speed Grade

XA9572XL -10 VQG 44Q

Temperature Range

Number of Pins

Package Type

Device Ordering Options

Device

Speed

Package

Temperature

XA9536XL

-10 10 ns pin-to-pin

delay

VQG44 44-pin Quad Flat Pack (VQFP)

Q = Automotive

Extended

T_A= –40°C to +125°C

XA9572XL

VQG64 64-pin Quad Flat Pack (VQFP)

I = Automotive

Industrial

T_A= –40°C to +85°C

XA95144 XL

TQG100 100-pin Thin Quad Flat Pack (TQFP)

CSG144 144-pin Chip Scale Package (CSP)

DS108-1 (v1.5) September 29, 2005

www.xilinx.com

Preliminary Product Specification

XA9500XL High-Performance CPLD Automotive XA Product Family

THE WARRANTY ON THESE PRODUCTS DO NOT EXTEND TO ANY IMPLEMENTATION IN AN APPLICATION OR

ENVIRONMENT THAT IS NOT CONTAINED WITHIN XILINX’S SPECIFICATIONS. PRODUCTS ARE NOT DESIGNED TO

BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS. FURTHER, PRODUCTS

ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF THE VEHICLE UNLESS THERE IS

A FAIL-SAFE OR REDUNDANCY FEATURE AND ALSO A WARNING SIGNAL TO THE OPERATOR OF THE VEHICLE

UPON FAILURE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF THE CUSTOMER

SUBJECT TO APPLICABLE LAWS AND REGULATIONS.

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Revision

05/17/02

07/17/02

02/03/03

05/21/04

10/18/04

09/29/05

Initial Xilinx release.

1.1

Updated N_PEQuality and Reliability specification.

1.2

Added reference to XC9500XL, XC9536XL, and XC9572XL data sheets.

Updated the VQ44 column of Table 2 and the Component Availability table on page 2.

Extensive edits to update family from IQ to XA.

1.3

1.4

1.5

Changes to packaging information.

www.xilinx.com

DS108-1 (v1.5) September 29, 2005

Preliminary Product Specification

相关型号：