1ED020I12FTAXUMA2中文资料_数据手册_规格书

1ED020I12FTA

Single IGBT Driver IC

SP001054670

1

Overview

Main Features

•

Single channel isolated IGBT Driver

For 600V/1200V IGBTs

2 A rail-to-rail output

Vcesat-detection

Active Miller Clamp

Two level turn off

Product Highlights

•

Coreless transformer isolated driver

Basic insulation according to DIN EN 60747-5-2

Basic insulation recognized under UL 1577

Integrated protection features

Suitable for operation at high ambient temperature

AEC Qualified

Typical Application

•

Drive inverters for HEV and EV

Auxiliary inverters for HEV and EV

High Power DC/DC inverters

Description

The 1ED020I12FTA is a galvanic isolated single channel IGBT driver in PG-DSO-20 package that provides an

output current capability of typically 2A.

All logic pins are 5V CMOS compatible and could be directly connected to a microcontroller.

The data transfer across galvanic isolation is realized by the integrated Coreless Transformer Technology.

The 1ED020I12FTA provides several protection features like IGBT two level turn off, desaturation protection, active

Miller clamping and active shut down.

Type

Package

Marking

1ED020I12FTA

PG-DSO-20

1ED020I12FTA

Data Sheet

www.infineon.com

1

Rev. 3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Table of Contents

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2

3

3.1

3.2

Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4

4.1

4.2

4.3

4.3.1

4.3.2

4.3.3

4.3.4

4.4

4.5

4.6

4.7

4.8

4.8.1

4.8.2

4.8.3

4.9

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Internal Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

READY Status Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Active Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Non-Inverting and Inverting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Two-Level Turn-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Minimal On Time / Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

External Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5

5.1

5.2

5.3

Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Recommended Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Logic Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Two-level Turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.4

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

5.4.6

5.4.7

5.4.8

5.4.9

6

Insulation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Certified according to DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation . . . . . . . . . . 22

Recognized under UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1

6.2

6.3

7

8

9

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Data Sheet

2

Rev.3.0

2016-04-05

EiceDRIVER™

1ED020I12FTA

9.1

9.2

Reference Layout for Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Printed Circuit Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Data Sheet

3

Rev. 3.0, 2016-04-05

1ED020I12FTA

Single IGBT Driver IC

List of Figures

Figure 2-1 Block Diagram 1ED020I12FTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3-1 Pin Configuration PG-DSO-20 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4-1 Application Example Bipolar Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4-2 Application Example Unipolar Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7-1 Propagation Delay, Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7-2 Principle Switching Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7-3 Typical Switching Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 7-4 DESAT Switch-OFF Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7-5 Short Switch ON Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 7-6 Short Switch OFF Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 7-7 Short Switch OFF Pulses, Ringing Surpression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 7-8 VCC2 Ramp Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7-9 VCC2 Ramp Down and VCC2 Drop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7-10 Typical T_TLSETTime over C_TLSETCapacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 8-1 PG-DSO-20 (Plastic (Green) Dual Small Outline Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 9-1 Reference Layout for Thermal Data (Copper thickness 102 μm) . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Data Sheet

4

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

List of Tables

Table 3-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5-2 Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5-3 Recommended Operating Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 5-4 Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5-5 Logic Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5-6 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5-7 Active Miller Clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5-8 Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5-9 Dynamic Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5-10 Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5-11 Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 5-12 Two-level Turn-off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6-1 Certified according to DIN EN 60747-5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 6-2 Recognized under UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Data Sheet

5

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Block Diagram

2

Block Diagram

VCC1 18

IN+ 13

UVLO

6

8

VCC2

&

K4

2V

delay

CLAMP

&

delay

TX

RX

1

VCC1

VCC2

VEE2

20MHz

&

IN-

14

VCC1

OSC LOGIC

7

5

3

OUT

RDY 15

/FLT 16

/RST 17

&

VCC2

/RDY

VEE2

DECODER

RX

TX ENCODER

500µA

1

250Ω

TLSET

DESAT

VCC1

7V

VCC2

&

K3

S

FLT2

^FLTQ

Q

S

R

1

9V

R

VCC1

≥1

RST

delay

1

4

GND2

VEE2

1ED020I12FTA

1

11

12

19

20

1

2

9

10

GND1 GND1

VEE2 VEE2

Figure 2-1 Block Diagram 1ED020I12FTA

Data Sheet

6

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Pin Configuration and Functionality

3

Pin Configuration and Functionality

3.1

Pin Configuration

Table 3-1 Pin Configuration

Pin No. Name Function

1

VEE2

DESAT

GND2

TLSET

VCC2

OUT

Negative power supply output side

Desaturation protection

Signal ground output side

Two level set

2

3

4

5

6

Positive power supply output side

Driver output

7

8

CLAMP

VEE2

GND1

IN+

Miller clamping

9

Negative power supply output side

Ground input side

10

11

12

13

14

15

16

17

18

19

20

Ground input side

Non inverted driver input

Inverted driver input

IN-

RDY

Ready output

FLT

Fault output, low active

Reset input, low active

Positive power supply input side

Ground input side

RST

VCC1

GND1

Ground input side

Data Sheet

7

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Pin Configuration and Functionality

1

2

3

4

5

6

7

8

9

VEE2

GND1 20

GND1 19

VCC1 18

/RST 17

/FLT 16

RDY 15

IN- 14

VEE2

DESAT

GND2

TLSET

VCC2

OUT

CLAMP

VEE2

IN+ 13

GND1 12

GND1 11

10 VEE2

Figure 3-1 Pin Configuration PG-DSO-20 (top view)

3.2

Pin Functionality

GND1

Ground connection of the input side.

IN+ Non Inverting Driver Input

IN+ control signal for the driver output if IN- is set to low. (The IGBT is on if IN+ = high and IN- = low)

A minimum pulse width is defined to make the IC robust against glitches at IN+. An internal Pull-Down-Resistor

ensures IGBT Off-State.

IN- Inverting Driver Input

IN- control signal for driver output if IN+ is set to high. (IGBT is on if IN- = low and IN+ = high)

A minimum pulse width is defined to make the IC robust against glitches at IN-. An internal Pull-Up-Resistor

ensures IGBT Off-State.

/RST Reset Input

Function 1: Enable/shutdown of the input chip. (The IGBT is off if /RST = low). A minimum pulse width is

defined to make the IC robust against glitches at /RST.

Function 2: Resets the DESAT-FAULT-state of the chip if /RST is low for a time T_RST. An internal Pull-Up-Resistor

is used to ensure /FLT status output.

/FLT Fault Output

Open-drain output to report a desaturation error of the IGBT (FLT is low if desaturation occurs)

RDY Ready Status

Open-drain output to report the correct operation of the device (RDY = high if both chips are above the UVLO

level and the internal chip transmission is faultless).

Data Sheet

8

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Pin Configuration and Functionality

VCC1

5 V power supply of the input chip

VEE2

Negative power supply pins of the output chip. If no negative supply voltage is available, all VEE2 pins have to

be connected to GND2.

DESAT Desaturation Detection Input

Monitoring of the IGBT saturation voltage (V_CE) to detect desaturation caused by short circuits. If OUT is high,

V_CEis above a defined value and a certain blanking time has expired, the desaturation protection is activated

and the IGBT is switched off. The blanking time is adjustable by an external capacitor.

CLAMP Miller Clamping

Ties the gate voltage to ground after the IGBT has been switched off at a defined voltage to avoid a parasitic

switch-on of the IGBT.During turn-off, the gate voltage is monitored and the clamp output is activated when

the gate voltage goes below 2 V below VEE2.

GND2 Reference Ground

Reference ground of the output chip.

OUT Driver Output

Output pin to drive an IGBT. The voltage is switched between VEE2 and VCC2. In normal operating mode Vout

is controlled by IN+, IN- and /RST. During error mode (UVLO, internal error or DESAT) Vout is set to VEE2

independent of the input control signals.

VCC2

Positive power supply pin of the output side.

TLSET Two Level Turn Off Adjust

Circuitry at TLSET adjust the two level turn off time with an external capacitor to GND2 and the two level

voltage with an external Zener diode to GND2, for wave forms please see Figure 7-4.

Data Sheet

9

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Functional Description

4

Functional Description

4.1

Introduction

The 1ED020I12FTA is an advanced IGBT gate driver for motor drives typical greater 10 kW. Control and

protection functions are included to make possible the design of high reliability systems.

The device consists of two galvanic separated parts. The input chip can be directly connected to a standard

5 V DSP or microcontroller with CMOS in/output and the output chip is connected to the high voltage side.

An effective active Miller clamp function avoids the need of negative gate driving in some applications and

allows the use of a simple bootstrap supply for the high side driver.

A rail-to-rail driver output enables the user to provide easy clamping of the IGBTs gate voltage during short

circuit of the IGBT. So an increase of short circuit current due to the feedback via the Miller capacitance can be

avoided. Further, a rail-to-rail output reduces power dissipation.

The device also includes an IGBT desaturation protection with a FAULT status output.

A two-level turn-off feature with adjustable delay protects against excessive overvoltage at turn-off in case of

overcurrent or short circuit condition. The same delay is applied at turn-on to prevent pulse width distortion.

A READY status output reports if the device is supplied and operates correctly.

10R

+5V

+15V

VCC1

GND1

VCC2

100n

1µ

1k

DESAT

SGND

IN+

CLAMP

OUT

10R

IN+

TLSET

GND2

VEE2

IN-

10V

47p

220p

RDY

FLT

RST

RDY

/FLT

/RST

1µ

-8V

1ED020I12FTA

Figure 4-1 Application Example Bipolar Supply

4.2

Supply

The driver 1ED020I12FTA is designed to support two different supply configurations, bipolar supply and

unipolar supply.

In bipolar supply the driver is typically supplied with a positive voltage of 15V at VCC2 and a negative voltage

of -8V at VEE2, refer to Figure 4-1. Negative supply prevents a dynamic turn on due to the additional charge

which is generated from IGBT input capacitance times negative supply voltage. If an appropriate negative

supply voltage is used, connecting CLAMPxx to IGBT gate is redundant and therefore typically not necessary.

For unipolar supply configuration the driver is typically supplied with a positive voltage of 15V at VCC2.

Erratically dynamic turn on of the IGBT could be prevented with active Miller clamp function, so CLAMP output

is directly connected to IGBT gate, refer to Figure 4-2.

Data Sheet

10

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Functional Description

10R

+5V

+15V

VCC1

GND1

VCC2

1µ

100n

1k

DESAT

SGND

IN+

CLAMP

OUT

10R

IN+

TLSET

GND2

VEE2

IN-

10V

47p

220p

RDY

FLT

RST

RDY

/FLT

/RST

1ED020I12FTA

Figure 4-2 Application Example Unipolar Supply

4.3

Internal Protection Features

4.3.1

Undervoltage Lockout (UVLO)

To ensure correct switching of IGBTs the device is equipped with an undervoltage lockout for both chips, refer

to Figure 7-8 and Figure 7-9.

If the power supply voltage V_VCC1of the input chip drops below V_UVLOL1a turn-off signal is sent to the output

chip before power-down. The IGBT is switched off and the signals at IN+ and IN- are ignored as long as V_VCC1

reaches the power-up voltage V_UVLOH1

.

If the power supply voltage V_VCC2of the output chip goes down below V_UVLOL2the IGBT is switched off and

signals from the input chip are ignored as long as V_VCC2reaches the power-up voltage V_UVLOH2. VEE2 is not

monitored, otherwise negative supply voltage range from 0 V to -12 V would not be possible.

4.3.2

READY Status Output

The READY output at pin /RDY shows the status of three internal protection features.

•

UVLO of the input chip

UVLO of the output chip after a short delay

Internal signal transmission after a short delay

It is not necessary to reset the READY signal since its state only depends on the status of the former mentioned

protection signals.

4.3.3

Watchdog Timer

During normal operation the internal signal transmission is monitored by a watchdog timer. If the

transmission fails for a given time, the IGBT is switched off and the READY output reports an internal error.

4.3.4

Active Shut-Down

The Active Shut-Down feature ensures a safe IGBT off-state if the output chip is not connected to the power

supply, IGBT gate is clamped at OUT to VEE2.

Data Sheet

11

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Functional Description

4.4

Non-Inverting and Inverting Inputs

There are two possible input modes to control the IGBT. At non-inverting mode IN+ controls the driver output

while IN- is set to low. At inverting mode IN- controls the driver output while IN+ is set to high, refer to

Figure 7-2. A minimum input pulse width is defined to filter occasional glitches.

4.5

Driver Output

The output driver section uses only MOSFETs to provide a rail-to-rail output. This feature permits that tight

control of gate voltage during on-state and short circuit can be maintained as long as the drivers supply is

stable. Due to the low internal voltage drop, switching behaviour of the IGBT is predominantly governed by

the gate resistor. Furthermore, it reduces the power to be dissipated by the driver.

4.6

Two-Level Turn-Off

The Two-Level Turn-OFF introduces a second turn off voltage level at the driver output in between ON- and

OFF-level, refer to Figure 7-3. This additional level ensures lower V_CEovershoots at turn off by reducing gate

emitter voltage of the IGBT at short circuits or over current events. The V_GElevel is adjusting the current of the

IGBT at the end two level turn off interval, the required timing is depending on stray inductance and over

current at beginning of two level turn off interval.

Reference voltage level and hold up time could be adjusted at TLSET pin. The reference voltage is set by the

required Zener diode connected between pin TLSET and GND2. The holdup time is set by the capacitor

connected to the same pin TLSET and GND2.

The hold time can be adjusted during switch on using the whole capacitance connected at pin TLSET including

capacitor, parasitic wiring capacitance and junction capacitance of Zener diode. When a switch on signal is

given the IC starts to discharge C_TLSET. Discharging C_TLSETis stopped after 500 ns. Then Ctlset is charged with

an internal charge current I_TLSET. When the voltage of the capacitor C_TLSETexceeds 7 V a second current source

starts charging C_TLSETup to V_ZDIODE. At the end of this discharge-charge cycle the gate driver is switched on.

The time between IN initiated switch-on signal (minus an internal propagation delay of approximately 200 ns)

and switch-on of the gate drive is sampled and stored digitally. It represents the two level turn off set time

T_TLSETduring switch-off. Due to digitalization the tpdon time can vary in time steps of 50 ns.

If switch off is initiated from IN+, IN- or /RST signal, the gate driver is switched off immediately after internal

propagation delay of approximately 200 ns and V_OUTbegins to decrease to the second gate voltage level.

For switch off initiated by DESAT, the gate driver switch off is delayed by desaturation sense to OUT delay,

afterwards V_OUTbegins to decrease to the second gate voltage level.

For reaching second gate voltage level the output voltage V_OUTis sensed and compared with the Zener voltage

V_ZDIODE. When V_OUTfalls below the reference voltage V_ZDIODEof the Zener diode the switch off process is

interrupted and V_OUTis adjusted to V_ZDIODE. OUT is switched to VEE2 after the holdup time has passed.

The Two-Level Turn-OFF function cannot be disabled.

Data Sheet

12

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Functional Description

4.7

Minimal On Time / Off Time

The 1ED020I12FTA driver requires minimal on and off time for proper operation in the application. Minimal on

time must be greater than the adjustable two level plateau time T_TLSET, shorter on times will be suppressed by

generating of the plateau time refer to Figure 7-5. Due to the short on time, the voltage at TLSET pin does not

reach the comparator threshold; therefore the driver does not turn on. A similar principle takes place for off

time. Minimal off time must be greater than T_TLSET; shorter off times will be suppressed, which means OUT

stays on refer to Figure 7-6. A two level turn off plateau cannot be shortened by the driver. If the driver has

entered the turn off sequence it cannot switch off due to the fact, that the driver has already entered the shut

off mode. But if the driver input signal is turned on again, it will leave the lower level after T_TLSETtime by

switching OUT to high, refer to Figure 7-7.

4.8

External Protection Features

4.8.1

Desaturation Protection

A desaturation protection ensures the protection of the IGBT at short circuit. When the DESAT voltage goes up

and reaches 9 V, the output is driven low, refer to Figure 7-4. Further, the FAULT output is activated. A

programmable blanking time is used to allow enough time for IGBT saturation. Blanking time is provided by a

highly precise internal current source and an external capacitor.

4.8.2

Active Miller Clamp

In a half bridge configuration the switched off IGBT tends to dynamically turn on during turn on phase of the

opposite IGBT. A Miller clamp allows sinking the Miller current across a low impedance path in this high dV/dt

situation. Therefore in many applications, the use of a negative supply voltage can be avoided.

During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes

below typical 2 V (related to VEE2). The clamp is designed for a Miller current up to 2 A.

4.8.3

Short Circuit Clamping

During short circuit the IGBTs gate voltage tends to rise because of the feedback via the Miller capacitance. An

additional protection circuit connected to OUT and CLAMP limits this voltage to a value slightly higher than

the supply voltage. A current of maximum 500 mA for 10 μs may be fed back to the supply through one of this

paths. If higher currents are expected or a tighter clamping is desired external Schottky diodes may be added.

4.9

RESET

The reset input has two functions.

Firstly, /RST is in charge of setting back the FAULT output. If /RST is low longer than a given time, /FLT will be

cleared at the rising edge of /RST, refer to Figure 7-4; otherwise, it will remain unchanged. Moreover, it works

as enable/shutdown of the input logic, refer to Figure 7-2.

Data Sheet

13

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Electrical Parameters

5

Electrical Parameters

5.1

Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction

of the integrated circuit. Unless otherwise noted all parameters refer to GND1.

Table 5-1 Absolute Maximum Ratings

Parameter

Symbol

Values

Max.

Unit

Note

Min.

-0.3

-12

–

1)

Positive power supply output side

Negative power supply output side

V_VCC2

V_VEE2

20

0.3

28

V

Maximum power supply voltage output side V_max2

(V_VCC2- V_VEE2

–

)

Gate driver output

V_OUT

I_OUT

V_VEE2-0.3 V_VCC2+0.3

V

A

–

Gate driver high output maximum current

–

2.4

t = 2 µs

Gate & Clamp driver low output maximum

current

Maximum short circuit clamping time

t_CLP

–

10

μs

I_CLAMP/OUT=

500 mA

Positive power supply input side

V_VCC1

-0.3

6.5

V

–

Logic input voltages

(IN+,IN-,RST)

V_LogicIN

Opendrain Logic output voltage (FLT)

Opendrain Logic output voltage (RDY)

Opendrain Logic output current (FLT)

Opendrain Logic output current (RDY)

Pin DESAT voltage

V_FLT#

V_RDY

-0.3

–

6.5

10

V

–

V

I_FLT#

mA

I_RDY

–

10

–

1)

V_DESAT

V_CLAMP

-0.3

V_VCC2+0.3 V

3)

Pin CLAMP voltage

V_VCC2

+0.3²⁾

V

Junction temperature

T_J

-40

-55

–

150

100

700

139

117

1.5

°C

–

Storage temperature

T_S

°C

Power dissipation, per input part

Power dissipation, per output part

Thermal resistance (Input part)

Thermal resistance (Output chip active)

ESD Capability

P_{D, IN}

P_{D, OUT}

R_THJA,IN

R_THJA,OUT

V_ESD

mW

K/W

kV

⁴⁾@T_A= 25°C

–

Human Body

Model⁵⁾

1) With respect to GND2.

2) May be exceeded during short circuit clamping.

Data Sheet

14

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Electrical Parameters

3) With respect to VEE2.

4) Output IC power dissipation is derated linearly at 8.5 mW/°C above 68°C. Input IC power dissipation does not require

derating. See Figure 9-1 for reference layouts for these thermal data. Thermal performance may change significantly

with layout and heat dissipation of components in close proximity.

5) According to EIA/JESD22-A114-B (discharging a 100 pF capacitor through a 1.5 kΩ series resistor).

5.2

Operating Parameters

Note: Within the operating range the IC operates as described in the functional description. Unless otherwise

noted all parameters refer to GND1.

Table 5-2 Operating Parameters

Parameter

Symbol

Values

Max.

Unit

Note

Min.

13

1)

Positive power supply output side

Negative power supply output side

V_VCC2

V_VEE2

20

0

V

-12

–

Maximum power supply voltage output side V_max2

(V_VCC2- V_VEE2

28

–

)

Positive power supply input side

V_VCC1

4.5

5.5

V

–

Logic input voltages

(IN+,IN-,RST)

V_LogicIN

-0.3

2)

Pin CLAMP voltage

Pin DESAT voltage

Pin TLSET voltage

Ambient temperature

V_CLAMP

V_DESAT

V_TLSET

T_A

V_VEE2-0.3 V_VCC2

V

–

1)

-0.3

-40

V_VCC2

125

V

1)

V

°C

–

Common mode transient immunity³⁾

1) With respect to GND2.

|DV_ISO/dt| –

50

kV/μs

@ 500 V

2) May be exceeded during short circuit clamping.

3) The parameter is not subject to production test - verified by design/characterization

5.3

Recommended Operating Parameters

Note: Unless otherwise noted all parameters refer to GND1.

Table 5-3 Recommended Operating Parameters

Parameter

Symbol

V_VCC2

Value

15

Unit

Note

1)

Positive power supply output side

Negative power supply output side

V

1)

V_VEE2

-8

Positive power supply input side

1) With respect to GND2.

V_VCC1

5

–

Data Sheet

15

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Electrical Parameters

5.4

Electrical Characteristics

Note: The electrical characteristics include the spread of values in supply voltages, load and junction

temperatures given below. Typical values represent the median values at T_A= 25°C. Unless otherwise

noted all voltages are given with respect to their respective GND (GND1 for pins 11 to 20, GND2 for pins 1

to 10).

5.4.1

Voltage Supply

Table 5-4 Voltage Supply

Parameter

Symbol

Values

Typ.

Unit

Note

Min.

–

Max.

4.3

–

UVLO Threshold Input Chip

UVLO Hysteresis Input Chip

V_UVLOH1

V_UVLOL1

V_HYS1

4.1

3.8

–

V

–

3.5

0.15

–

(V_UVLOH1- V_UVLOL1

)

UVLO Threshold Output Chip V_UVLOH2

V_UVLOL2

–

12.0

11.0

0.9

12.6

V

–

10.4

0.7

–

UVLO Hysteresis Output Chip V_HYS2

(V_UVLOH1- V_UVLOL1

)

Quiescent Current Input Chip I_Q1

–

7

9

mA

V_VCC1=5 V

IN+ = High,

IN- = Low

=>OUT = High,

RDY = High,

/FLT = High

Quiescent Current Output

Chip

I_Q2

–

4.5

6

mA

V_VCC2=15 V

V_VEE2=-8 V

IN+ = High,

IN- = Low

=>OUT = High,

RDY = High,

/FLT = High

Data Sheet

16

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Electrical Parameters

5.4.2

Logic Input and Output

Table 5-5 Logic Input and Output

Parameter

Symbol

Values

Typ.

Unit

V

Note

–

Min.

–

Max.

1.5

IN+,IN-, RST Low Input Voltage V_IN+L

,

–

V_IN-L

V_RSTL#

IN+,IN-, RST High Input Voltage V_IN+H

V_IN-H

,

3.5

–

V

–

V_RSTH#

IN-, RST Input Current

I_IN-, I_RST#

100

400

μA

V_IN-= GND1

V_RST#= GND1

IN+ Input Current

I_IN+

,

–

100

400

μA

V_IN+= VCC1

RDY,FLT Pull Up Current

I_PRDY, I_PFLT#

V_RDY= GND1

V_FLT#= GND1

Input Pulse Suppression IN+, T_MININ+

IN- T_MININ-

,

30

40

–

ns

–

Input Pulse Suppression RST T_MINRST

for ENABLE/SHUTDOWN

30

Pulse Width RST

for Reseting FLT

T_RST

800

FLT Low Voltage

RDY Low Voltage

V_FLTL

V_RDYL

–

300

mV

I_SINK(FLT#)= 5 mA

I_SINK(RDY)= 5 mA

Data Sheet

17

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Electrical Parameters

5.4.3

Gate Driver

Table 5-6 Gate Driver

Parameter

Symbol

Values

Typ.

Unit

Note

Min.

Max.

High Level Output

Voltage

V_OUTH1

V_OUTH2

V_OUTH3

V_OUTH4

I_OUTH

V_VCC2-1.2

V_VCC2-2.5

V_VCC2-9

–

V_VCC2-0.8

V_VCC2-2.0

V_VCC2-5

V_VCC2-10

-2.0

–

V

A

I_OUTH= -20 mA

I_OUTH= -200 mA

I_OUTH= -1 A

I_OUTH= -2 A

High Level Output

Peak Current

-1.5

IN+ = High, IN- = Low;

OUT = High

Low Level Output

Voltage

V_OUTL1

V_OUTL2

V_OUTL3

V_OUTL4

–

V_VEE2+0.04 V_VEE2+0.09

V

A

I_OUTL= 20 mA

I_OUTL= 200 mA

I_OUTL= 1 A

–

V_VEE2+0.3

V_VEE2+2.1

V_VEE2+7

2.0

V_VEE2+0.85

–

V_VEE2+5.0

–

I_OUTL= 2 A

Low Level Output Peak I_OUTL

Current

1.5

IN+ = Low, IN- = Low;

OUT = Low,

V_VCC2=15 V,

V_VEE2=-8 V

5.4.4

Active Miller Clamp

Table 5-7 Active Miller Clamp

Parameter

Symbol

Values

Typ.

Unit

Note

Min.

Max.

Low Level Clamp

Voltage

V_CLAMPL1

V_CLAMPL2

V_CLAMPL3

I_CLAMPL

–

2

V_VEE2+0.03 V_VEE2+0.08

V

A

I_OUTL= 20 mA

I_OUTL= 200 mA

V_VEE2+0.3

V_VEE2+1.9

–

V_VEE2+0.8

V_VEE2+4.8

–

I_OUTL= 1 A

1)

Low Level Clamp

Current

Clamp Threshold

Voltage

V_CLAMP

1.6

2.1

2.4

V

Related to VEE2

1) The parameter is not subject to production test - verified by design/characterization

Data Sheet

18

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Electrical Parameters

5.4.5

Short Circuit Clamping

Table 5-8 Short Circuit Clamping

Parameter

Symbol

Values

Typ.

Unit

V

Note

Min.

–

Max.

1.3

Clamping voltage (OUT)

(V_OUT-V_VCC2

V_CLPout

0.8

1.3

0.7

IN+=High, IN- = Low,

OUT = High

I_OUT= 500 mA

(pulse test,

)

t_CLPmax= 10 μs)

Clamping voltage

(CLAMP) (V_VCLAMP-V_VCC2

V_CLPclamp

–

V

IN+ = High, IN- = Low,

OUT = High

I_CLAMP= 500 mA

(pulse test,

)

t_CLPmax= 10 μs)

Clamping voltage (CLAMP) V_CLPclamp

1.1

IN+ = High, IN- = Low,

OUT = High

I_CLAMP= 20 mA

5.4.6

Dynamic Characteristics

Dynamic characteristics are measured with V_VCC1= 5 V, V_VCC2= 15 V and V_VEE2= -8 V.

Table 5-9 Dynamic Characteristics

Parameter

Symbol

Values

Typ.

Unit

Note

Min.

1.5

Max.

2.0

IN+, IN- Input to output

propagation delay ON and

OFF

T_PDON

1.75

μs

C_TLSET= 0 pF,

C_LOAD= 100 pF,

T_A= 25°C

N+, IN- Input to output

propagation delay

distortion (T_PDOFF-T_PDON

T_PDISTO

T_PDONt

T_PDISTOt

T_PDONt

T_PDISTOt

-50

1.5

0

50

ns

μs

ns

μs

ns

C_TLSET= 0 pF,

C_LOAD= 100 pF,

T_A= 25°C

)

N+, IN- Input to output

propagation delay ON and

OFF

1.9

45

2.3

70

C_TLSET= 0 pF,

C_LOAD= 100 pF,

T_A= 125°C

N+, IN- Input to output

propagation delay

distortion (T_PDOFF-T_PDON

-20

1.45

-60

C_TLSET= 0 pF,

C_LOAD= 100 pF,

T_A= 125°C

)

IN+, IN- Input to output

propagation delay ON and

OFF

1.75

-5

2.05

50

C_TLSET= 0 pF,

C_LOAD= 100 pF,

T_A= -40°C

IN+ Input to output

propagation delay

distortion (T_PDOFF-T_PDON

C_TLSET= 0 pF,

C_LOAD= 100 pF,

T_A= -40°C

)

Data Sheet

19

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Electrical Parameters

Table 5-9 Dynamic Characteristics (cont’d)

Parameter

Symbol

Values

Typ.

Unit

Note

Min.

10

Max.

60

Rise Time

T_RISE

30

ns

C_LOAD= 1 nF,

V_L10%, V_H90%

150

10

400

20

800

40

C_LOAD= 34 nF

V_L10%, V_H90%

Fall Time

T_FALL

C_LOAD= 1 nF

V_L10%, V_H90%

100

250

500

C_LOAD= 34 nF

V_L10%, V_H90%

5.4.7

Desaturation Protection

Table 5-10 Desaturation Protection

Parameter Symbol

Values

Unit

Note

Min.

450

Typ.

500

Max.

550

Blanking Capacitor Charge I_DESATC

Current

μA

V_VCC2=15 V,

V_VEE2=-8 V

V_DESAT= 2 V

Blanking Capacitor

Discharge Current

I_DESATD

11

15

–

mA

V_VCC2=15 V,

V_VEE2=-8 V

V_DESAT=6 V

Desaturation Reference

Level

V_DESAT

8.5

–

9

9.5

V

V_VCC2=15 V

Desaturation Sense to OUT T_DESATOUT

TLTO

250

–

320

2.25

110

ns

μs

mV

V_OUT=90%

C_LOAD= 1 nF

Desaturation Sense to FLT T_DESATFLT

Low Delay

–

V_{FLT #}=10%;

I_{FLT #}=5 mA

Desaturation Low Voltage V_DESATL

40

70

IN+=Low, IN-=Low,

OUT=Low

Data Sheet

20

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Electrical Parameters

5.4.8

Active Shut Down

Table 5-11 Active Shut Down

Parameter

Symbol

Values

Typ.

Unit

V

Note

Min.

–

Max.

2.0

1)

Active Shut Down Voltage

1) With reference to VEE2

V_ACTSD

–

I_OUT= -200 mA,

V_CC2open

5.4.9

Two-level Turn-off

Table 5-12 Two-level Turn-off

Parameter

Symbol

Values

Typ.

Unit

Note

Min.

7.5

Max.

External reference voltage

range (Zener-Diode)

V_ZDIODE

V_TLSET

I_TLSET

–

V_CC2-0.5

V

–

Reference Voltage for setting

two-level delay time

6.6

7

7.3

V

–

Current for setting two-level

delay time and external

420

500

550

μA

V_TLSET= 10 V

reference voltage (Zener-Diode)

External Capacitance Range

C_TLSET

0

–

220

pF

–

Data Sheet

21

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Insulation Characteristics

6

Insulation Characteristics

Insulation characteristics are guaranteed only within the safety maximum ratings which must be ensured by

protective circuits in application. Surface mount classification is class A in accordance with CECCOO802.

This coupler is suitable for “basic insulation” only within the safety ratings. Compliance with the safety ratings

shall be ensured by means of suitable protective circuits.

6.1

Certified according to DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic

Insulation

Table 6-1 Certified according to DIN EN 60747-5-2

Description

Symbol

Characteristic

Unit

–

Installation classification per EN 60664-1, Table 1

for rated mains voltage ≤ 150 V_RMS

for rated mains voltage ≤ 300 V_RMS

I-IV

I-III

I-II

for rated mains voltage ≤ 600 V_RMS

Climatic Classification

40/125/21

–

Pollution Degree (EN 60664-1)

Minimum External Clearance

Minimum External Creepage

2

–

CLR

8

mm

–

CPG

CTI

8

Minimum Comparative Tracking Index

Maximum Repetitive Insulation Voltage

Highest Allowable Overvoltage

Maximum Surge Insulation Voltage

175

1420

6000

V_IORM

V_IOTM

V_IOSM

V_PEAK

V

6.2

Recognized under UL 1577

Table 6-2 Recognized under UL 1577

Description

Symbol

V_ISO

Characteristic

3750

Unit

V_rms

Insulation Withstand Voltage / 1 min

Insulation Test Voltage / 1 s

V_ISO

4500

6.3

Reliability

For Qualification Report please contact your local Infineon Technologies office.

Data Sheet

22

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Timing Diagrams

7

Timing Diagrams

All diagrams related to the Two-level switch-off feature

50%

IN+

90%

10%

50%

OUT

T_RISE

T_FALL

T_PDON

T_PDOFF

Figure 7-1 Propagation Delay, Rise and Fall Time

IN+

IN-

/RST

OUT

Figure 7-2 Principle Switching Behavior

IN+

V_ZDIODE

V_TLSET, typ. 7V

TLSET

T_ADJ1

T_TLSET

T_PD

V_ZDIODE

T_PD

T_TLFALL

OUT

T_PDONADJ

T_TLSET

Figure 7-3 Typical Switching Behavior

Data Sheet

23

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Timing Diagrams

IN+

T_PDON

T_TLSET

OUT

T_DESATOUT

V_DESATtyp. 9V

DESAT

/FLT

T_DESATFLT

/RST

>T_RSTmin

Figure 7-4 DESAT Switch-OFF Behavior

IN+

TLSET

T_PD

T_TLSET

T_PDON

T_PDOFF

OUT

Figure 7-5 Short Switch ON Pulses

Data Sheet

24

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Timing Diagrams

IN+

T_TLSET

TLSET

T_PD

T_PDON

T_PDOFF

T_PDON

T_PDOFF

OUT

Figure 7-6 Short Switch OFF Pulses

IN+

TLSET

T_PD

T_TLSET

T_PD

T_PDON

T_PDOFF

T_PDON

OUT

forced turn off after three

consecutive on -cycles

Figure 7-7 Short Switch OFF Pulses, Ringing Surpression

Data Sheet

25

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Timing Diagrams

V_UVLOH2

VCC2

IN+

T_PDON

T_PDOFF

OUT

I_DESAT

RDY

Figure 7-8 VCC2 Ramp Up

V_UVLOH2

V_UVLOL2

VCC2

T_PDD

IN+

T_TLSET

TLSET

Vz

T_PDON

OUT

RDY

/FLT

Figure 7-9 VCC2 Ramp Down and VCC2 Drop

Data Sheet

26

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Timing Diagrams

5

4

3

2

1

0

50

100

150

200

C_TLSET[pF]

Figure 7-10 Typical T_TLSETTime over C_TLSETCapacitance

Data Sheet

27

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Package Outlines

8

Package Outlines

Figure 8-1 PG-DSO-20 (Plastic (Green) Dual Small Outline Package)

Data Sheet

28

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Application Notes

9

Application Notes

9.1

Reference Layout for Thermal Data

The PCB layout shown in Figure 9-1 represents the reference layout used for the thermal characterisation. Pins

11, 12, 19 and 20 (GND1) and pins 1, 2, 9 and 10 (VEE2) require ground plane connections for achiving

maximum power dissipation. The 1ED020I12FTA is conceived to dissipate most of the heat generated through

this pins.

Figure 9-1 Reference Layout for Thermal Data (Copper thickness 102 μm)

9.2

Printed Circuit Board Guidelines

Following factors should be taken into account for an optimum PCB layout.

•

Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits.

The same minimum distance between two adjacent high-side isolated parts of the PCB should be

maintained to increase the effective isolation and reduce parasitic coupling.

•

In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be

kept as short as possible.

Lowest trace length for VEE2 to GND2 decoupling could be achieved with capacitor closed to pins 2 and 4.

Data Sheet

29

Rev.3.0

2016-04-05

1ED020I12FTA

Single IGBT Driver IC

Revision History

Page or Item

Subjects (major changes since previous revision)

Rev. 3.0, 2016-04-05

All

Update latest template

Page 8

Page 14

removed Target Application Figure

Editorial changes, typos:

- Symbol changed from Vmax2 to Vcc2 in Gate driver output

- Pin CLAMP voltage unit changed from °C to V

- Desaturation protection filter time changed

Page 6

Updated Block Diagram

Page 14,

Page 15,

Page 16,

Page 17,

Page 18,

Page 19,

Page 20,

Page 21

removed “Test Condition” from table header

Data Sheet

30

Rev.3.0

2016-04-05

Please read the Important Notice and Warnings at the end of this document

Trademarks of Infineon Technologies AG

µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,

DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,

HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™,

OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,

SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™.

Trademarks updated November 2015

Other Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no For further information on technology, delivery terms

Edition 2016-04-05

Published by

Infineon Technologies AG

81726 Munich, Germany

event be regarded as a guarantee of conditions or and conditions and prices, please contact the nearest

characteristics ("Beschaffenheitsgarantie").

Infineon Technologies Office (www.infineon.com).

WARNINGS

With respect to any examples, hints or any typical

values stated herein and/or any information regarding

the application of the product, Infineon Technologies

hereby disclaims any and all warranties and liabilities

of any kind, including without limitation warranties of

non-infringement of intellectual property rights of any

third party.

In addition, any information given in this document is

subject to customer's compliance with its obligations

stated in this document and any applicable legal

requirements, norms and standards concerning

customer's products and any use of the product of

Infineon Technologies in customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments to

evaluate the suitability of the product for the intended

application and the completeness of the product

information given in this document with respect to

such application.

Due to technical requirements products may contain

dangerous substances. For information on the types

in question please contact your nearest Infineon

Technologies office.

Do you have a question about any

aspect of this document?

Email: erratum@infineon.com

Except as otherwise explicitly approved by Infineon

Technologies in

a written document signed by

authorized representatives of Infineon Technologies,

Infineon Technologies’ products may not be used in

any applications where a failure of the product or any

consequences of the use thereof can reasonably be

expected to result in personal injury.

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP,	针数：	20
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	24 weeks
风险等级：	1.63	高边驱动器：	YES
接口集成电路类型：	HALF BRIDGE BASED IGBT DRIVER	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e4	长度：	12.8 mm
湿度敏感等级：	3	标称负供电电压：	-8 V
功能数量：	1	端子数量：	20
最高工作温度：	125 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	2.65 mm
最大供电电压：	20 V	最小供电电压：	13 V
标称供电电压：	15 V	电源电压1-最大：	5.5 V
电源电压1-分钟：	4.5 V	电源电压1-Nom：	5 V
表面贴装：	YES	温度等级：	AUTOMOTIVE
端子面层：	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	断开时间：	2 µs
接通时间：	2 µs	宽度：	7.6 mm
Base Number Matches：	1

型号	制造商	描述	价格	文档
1ED020I12FTXUMA1	INFINEON	Half Bridge Based MOSFET Driver, 2A, PDSO16, GREEN, PLASTIC, SOP-16	获取价格
1ED020I12FXUMA1	INFINEON	Half Bridge Based MOSFET Driver, 2A, PDSO16, GREEN, PLASTIC, SOP-16	获取价格
1ED1	TE	High Performance Compact RFI Power Line Filters with IEC Connectors	获取价格
1ED1	MACOM	Medium Performance Compact EMI Power Inlet Filter	获取价格
1ED1_11	MACOM	Medium Performance Compact EMI Power Inlet Filter	获取价格
1ED2	MACOM	Medium Performance Compact EMI Power Inlet Filter	获取价格
1ED3120MC12H	INFINEON	EiceDRIVERâ¢ 1ED31xxMC12H Compact	获取价格
1ED3120MU12H	INFINEON	EiceDRIVERâ¢ 1ED31xxMU12H Compact	获取价格
1ED3121MC12H	INFINEON	EiceDRIVERâ¢ 1ED31xxMC12H Compact	获取价格
1ED3121MU12H	INFINEON	EiceDRIVERâ¢ 1ED31xxMU12H Compact	获取价格

1ED020I12FTAXUMA2

1ED020I12FTAXUMA2 概述

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