1ED020I12FTA中文资料_数据手册_规格书

Preliminary Datasheet, Version 1.2, May 2010

EICEDRIVER®

1ED020I12FTA

Single IGBT Driver IC

Power Management & Drives

N e v e r s t o p t h i n k i n g .

1ED020I12FTA

Revision History:

2010-05-21

Version 1.2

Previous Version:

0

Page

Subjects (major changes since last revision)

May 2010

Edition 2010-05-21

Published by Infineon Technologies AG,

Campeon 1-12,

85579 Neubiberg, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

EICEDRIVER®

1ED020I12FTA

Single IGBT Driver IC

Product Highlights

•

Coreless transformer isolated driver

Galvanic Insulation

Integrated protection features

Suitable for operation at high ambient temperature

Automotive Qualified (pending)

Two level turn off

Features

Typical

Application

•

Single channel isolated IGBT Driver

For 600V/1200V IGBTs

2A rail-to-rail output

Vcesat-detection

•

Drive inverters for HEV and EV

Auxilliary inverters for HEV and EV

Inverters for electrical drives in CAV

High Power DC/DC inverters

Active Miller Clamp

Input Side

Output Side

VCC2,H

VCC1

DESAT

OUT

IN+, IN-, /RST

EiceDRIVER^TM

1ED020I12FTA

/FLT, RDY

CLAMP

TLSET

GND1

VCC1

VEE2,H GND2,H

VCC2,L

CPU

DESAT

OUT

IN+, IN-, /RST

/FLT, RDY

EiceDRIVER^TM

1ED020I12FTA

CLAMP

TLSET

GND1

VEE2,L GND2,L

Figure 1: Typical Application

Type

1ED020I12FTA

Gate drive current

+/- 2A

Package

PG-DSO-20-55

Preliminary Datasheet

1

Version 1.2, 2010-05-21

EICEDRIVER®

1ED020I12FTA

Preliminary Datasheet

2

Version 1.2, 2010-05-21

EICEDRIVER®

1ED020I12FTA

1

Block Diagram and Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Internal Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

READY status output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Active Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Non-Inverting and Inverting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Two-Level Turn-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Minimal On Time / Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

External Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Active Miller Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.3

2.4

2.5

2.6

2.7

2.7.1

2.7.2

2.7.3

2.8

3

Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

3.2

4

Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Recommended Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Voltage Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Logic Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Two-level Turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1

4.2

4.3

4.4

4.4.1

4.4.2

4.4.3

4.4.4

4.4.5

4.4.6

4.4.7

4.4.8

4.4.9

5

Insulation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

According to DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation . . . . . . . . . . . . . . . . . . . . . . . 19

According to UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1

5.2

5.3

6

7

Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8

Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Reference Layout for Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Printed Circuit Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.1

8.2

Prelim Datasheet

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Version 1.2, 2010-05-21

EICEDRIVER®

1ED020I12FTA

Prelim Datasheet

4

Version 1.2, 2010-05-21

EICEDRIVER®

1ED020I12FTA

Block Diagram and Application

1

Block Diagram and Application

VCC1

IN+

VCC2

18

13

UVLO

6

&

K4

2V

delay

CLAMP

8

&

TX

RX

1

VCC1

VCC2

VEE2

20MHz

IN- 14

&

VCC1

OSC

7

5

OUT

RDY

15

16

17

&

VCC2

500µA

/RDY

VEE2

250Ω

DECODER RX

TX ENCODER

&

1

TLSET

VCC1

7V

VCC2

/FLT

/RST

&

K3

DESAT

GND2

S

3

4

^FLTQ

≥1

1

9V

R

VCC1

RST

delay

1

VEE2

1ED020I12FTA

1

11

GND1

12

GND1

19

GND1

20

GND1

1

2

9

10

Figure 1: Block Diagram 1ED020I12FTA

10R

+5V

+15V

VCC1

100n

VCC2

1µ

1k

DESAT

SGND

GND1

CLAMP

OUT

10R

IN+

TLSET

GND2

VEE2

IN-

100p

10V

10p

RDY

FLT

/FLT

1µ

RS

-8V

/RST

1ED020I12FTA

Figure 2: Application Example

Preliminary Datasheet

5

Version 1.2, 2010-05-21

EICEDRIVER®

1ED020I12FTA

Functional Description

2

Functional Description

2.1

Introduction

The 1ED020I12FTA is an advanced IGBT gate driver for motor drives typical greater 10kW. Control and protection

functions are included to make possible the design of high reliability systems.

The device consists of two galvanic separated parts. The input chip can be directly connected to a standard 5V

DSP or microcontroller with CMOS in/output and the output chip is connected to the high voltage side.

An effective active Miller clamp function avoids the need of negative gate driving in some applications and allows

the use of a simple bootstrap supply for the high side driver.

A rail-to-rail driver output enables the user to provide easy clamping of the IGBTs gate voltage during short circuit

of the IGBT. So an increase of short circuit current due to the feedback via the Miller capacitance can be avoided.

Further, a rail-to-rail output reduces power dissipation.

The device also includes an IGBT desaturation protection with a FAULT status output.

A two-level turn-off feature with adjustable delay protects against excessive overvoltage at turn-off in case of

overcurrent or short circuit condition. The same delay is applied at turn-on to prevent pulse width distortion.

A READY status output reports if the device is supplied and operates correctly.

2.2

Internal Protection Features

Undervoltage Lockout (UVLO)

2.2.1

To ensure correct switching of IGBTs the device is equipped with an undervoltage lockout for both chips.

If the power supply voltage V_VCC1of the input chip drops below V_UVLOL1a turn-off signal is sent to the output chip

before power-down. The IGBT is switched off and the signals at IN+ and IN- are ignored as long as V_VCC1reaches

the power-up voltage V_UVLOH1

.

If the power supply voltage V_VCC2of the output chip goes down below V_UVLOL2the IGBT is switched off and signals

from the input chip are ignored as long as V_VCC2reaches the power-up voltage V_UVLOH2

.

2.2.2

READY status output

The READY output at pin /RDY shows the status of three internal protection features.

•

UVLO of the input chip

UVLO of the output chip after a short delay

Internal signal transmission

It is not necessary to reset the READY signal since its state only depends on the status of the former mentioned

protection signals.

2.2.3

Watchdog Timer

The 1ED020I12FA incorporates two levels of protection to ensure signal integrity by two independent watchdog

timers. First level ensures the short term signal integrity by resending the (turn on/off) signals with a watchdog

period of typical 500ns. The second level monitors the internal signal transmission during normal operation. If the

transmission fails for a given time, the IGBT is switched off and the READY output reports an internal error.

2.2.4

Active Shut-Down

The Active Shut-Down feature ensures a safe IGBT off-state if the output chip is not connected to the power

supply.

Preliminary Datasheet

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EICEDRIVER®

1ED020I12FTA

Functional Description

2.3

Non-Inverting and Inverting Inputs

There are two possible input modes to control the IGBT. At non-inverting mode IN+ controls the driver output while

IN- is set to low. At inverting mode IN- controls the driver output while IN+ is set to high. A minimum input pulse

width is defined to filter occasional glitches.

2.4

Driver Output

The output driver section uses only MOSFETs to provide a rail-to-rail output. This feature permits that tight control

of gate voltage during on-state and short circuit can be maintained as long as the drivers supply is stable. Due to

the low internal voltage drop, switching behaviour of the IGBT is predominantly governed by the gate resistor.

Furthermore, it reduces the power to be dissipated by the driver.

2.5

Two-Level Turn-Off

The Two-Level Turn-OFF introduces a second turn off voltage level at the driver output in between ON- and OFF-

level. This additional level ensures lower V_CEovershoots at turn off by reducing gate emitter voltage of the IGBT

at short circuits or over current events. The V_GElevel is adjusting the current of the IGBT at the end two level turn

off interval, therequired timing is depending on stray inductance and over current at beginning of two level turn off

interval.

Reference voltage level and hold up time could be adjusted at TLSET pin. The reference voltage is set by the

required Zener diode connected between pin TLSET and GND2. The hold up time is set by the capacitor

connected to the same pin TLSET and GND2.

The hold time can be adjusted during switch on using the whole capacitance connected at pin TLSET including

capacitor, parasitic wiring capacitance and junction capacitance of Zener diode. When a switch on signal is given

the IC starts to discharge C_TLSET. Discharging C_TLSETis stopped after 500nsec. Then Ctlset is charged with an

internal charge current Itlset. When the voltage of the capacitor Ctlset exceeds 7V a second current source starts

charging Ctlset up to V_ZDIODE. At the end of this discharge-charge cycle the gate driver is switched on.

The time between IN initiated switch-on signal (minus an internal propagation delay of approximately 200ns) and

switch-on of the gate drive is sampled and stored digitally. It represents the two level turn off set time T_TLSETduring

switch-off. Due to digitalization the tpdon time can vary in time steps of 50nsec.

If switch off is initiated from IN+, IN- or /RST signal, the gate driver is switched off immediately after internal

propagation delay of approximately 200ns and V_OUTbegins to decrease. For switch off initiated by DESAT, the

gate driver switch off is delayed by desaturation sense to OUT delay. The output voltage V_OUTis sensed and

compared with the Zener voltage V_ZDIODE. When V_OUTfalls below the reference voltage V_ZDIODEof the Zener diode

the switch off process is interrupted and Vout is adjusted to V_ZDIODE. OUT is switched to VEE2 after the hold up

time has passed.

The Two-Level Turn-OFF function can not be disabled.

2.6

Minimal On Time / Off Time

The 1ED020I12FTA driver requires minimal on and off time for propper operation in the application. Minimal on

time must be greater than the adjustable two level plateau time T_TLSET, shorter on times will be surpressed by

generating of the plateau time. Due to the short on time, the voltage at TLSET pin does not reach the comparator

threshold, therefore the driver do not turn on. A similar principle takes place for off time. Minimal off time must be

greater than T_TLSET, shorter off times will be surpressed, which means OUT stays on. A two level turn off plateau

can not be shortened by the driver. If the driver has entered the turn off sequence it can not switch off due to the

fact, that the driver has already entered the shut off mode. But if the driver input signal is turned on again, it will

leave the lower level after T_TLSETtime by switching OUT to high.

Preliminary Datasheet

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EICEDRIVER®

1ED020I12FTA

Functional Description

2.7

External Protection Features

Desaturation Protection

2.7.1

A desaturation protection ensures the protection of the IGBT at short circuit. When the DESAT voltage goes up

and reaches 9V, the output is driven low. Further, the FAULT output is activated. A programmable blanking time

is used to allow enough time for IGBT saturation. Blanking time is provided by a highly precise internal current

source and an external capacitor.

2.7.2

Active Miller Clamping

A Miller clamp allows sinking the Miller current during a high dV/dt situation. Therefore, the use of a negative

supply voltage can be avoided in many applications. During turn-off, the gate voltage is monitored and the clamp

output is activated when the gate voltage goes below 2V (related to VEE2). The clamp is designed for a Miller

current up to 2A.

2.7.3

Short Circuit Clamping

During short circuit the IGBTs gate voltage tends to rise because of the feedback via the Miller capacitance. An

additional protection circuit connected to OUT and CLAMP limits this voltage to a value slightly higher than the

supply voltage. A current of maximum 500 mA for 10us may be fed back to the supply through one of this paths.

If higher currents are expected or a tighter clamping is desired external Schottky diodes may be added.

2.8

RESET

The reset input has two functions.

Firstly, /RST is in charge of setting back the FAULT output. If /RST is low longer than a given time , /FLT will be

reseted at the rising edge of /RST; otherwise, it will remain unchanged. Moreover, it works as enable/shutdown of

the input logic.

Preliminary Datasheet

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1ED020I12FTA

Pin Configuration and Functionality

3

Pin Configuration and Functionality

3.1

Pin Configuration

Symbol

VEE2

DESAT

GND2

TLSET

VCC2

OUT

Function

1

2

3

4

5

Negative power supply output side

Desaturation protection

Signal ground output side

Two level set

6

7

Positive power supply output side

Driver output

8

9

CLAMP

VEE2

GND1

IN+

IN-

RDY

FLT

RST

Miller clamping

Negative power supply output side

Signal ground input side

Non inverted driver input

Inverted driver input

10

11

12

13

14

15

16

17

18

19

20

Ready output

Fault output, low active

Reset input, low active

Positive power supply input side

Signal ground input side

VCC1

GND1

1

2

3

4

5

6

7

8

9

VEE2

GND1 20

GND1 19

VCC1 18

/RST 17

/FLT 16

RDY 15

IN- 14

IN+ 13

GND1 12

GND1 11

DESAT

GND2

TLSET

VCC2

OUT

CLAMP

VEE2

10 VEE2

Figure 3: Pin Configuration PG-DSO-20-55 (top view)

Preliminary Datasheet

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1ED020I12FTA

Pin Configuration and Functionality

3.2

Pin Functionality

GND1

Ground connection of the input side.

IN+ Non-inverting driver input

IN+ control signal for the driver output if IN- is set to low. (The IGBT is on if IN+ = high and IN- = low)

A minimum pulse width is defined to make the IC robust against glitches at IN+. An internal Pull-Down-Resistor

ensures IGBT Off-State.

IN- Inverting driver input

IN- control signal for driver output if IN+ is set to high. (IGBT is on if IN- = low and IN+ = high)

A minimum pulse width is defined to make the IC robust against glitches at IN-. An internal Pull-Up-Resistor

ensures IGBT Off-State.

/RST (Reset) input

Function 1: Enable/shutdown of the input chip. (The IGBT is off if /RST = low). A minimum pulse width is defined

to make the IC robust against glitches at IN-.

Function 2: Resets the DESAT-FAULT-state of the chip if /RST is low for a time T_RST. An internal Pull-Up-Resistor

is used to ensure FLT status output.

/FLT (Fault output)

Open-drain output to report a desaturation error of the IGBT (FLT is low if desaturation occurs)

RDY (Ready status)

Open-drain output to report the correct operation of the device. (RDY = high if both chips are above the UVLO

level and the internal chip transmission is faultless)

VCC1

5V power supply of the input chip

VEE2

Negative power supply pins of the output chip. If no negative supply voltage is available, all VEE2 pins have to be

connected to GND2.

DESAT (Desaturation)

Monitoring of the IGBT saturation voltage (V_CE) to detect desaturation caused by short circuits. If OUT is high, V_CE

is above a defined value and a certain blanking time has expired, the desaturation protection is activated and the

IGBT is switched off. The blanking time is adjustable by an external capacitor.

CLAMP (Clamping)

Ties the gate voltage to ground after the IGBT has been switched off at a defined voltage to avoid a parasitic

switch-on of the IGBT.During turn-off, the gate voltage is monitored and the clamp output is activated when the

gate voltage goes below 2V (related to VEE2).

GND2

Reference ground of the output chip.

Preliminary Datasheet

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EICEDRIVER®

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Pin Configuration and Functionality

OUT (Driver output)

Output pin to drive an IGBT. The voltage is switched between VEE2 and VCC2. In normal operating mode Vout

is controlled by IN+, IN- and /RST. During error mode (UVLO, internal error or DESAT) Vout is set to VEE2

independent of the input control signals.

VCC2

Positive power supply pin of the output side.

TLSET (Two-Level turn-off)

Setting up the timing (with ext. capacitor) and voltage reference (with ext. Zener diode) for the two-level turn-off,

see figure 5.

Preliminary Datasheet

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Electrical Parameters

4

Electrical Parameters

4.1

Absolute Maximum Ratings

Note:Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of

the integrated circuit. Unless otherwise noted all parameters refer to GND1.

Parameter

Symbol

Limit Values

Unit Remarks

min.

-0.3

-12

max.

20

0.3

28

1)

Positive power supply output side

V_VCC2

V_VEE2

V_max2

V

1)

Negative power supply output side

Maximum power supply voltage output side

(V_VCC2-V_VEE2

)

Gate driver output

V_OUT

I_OUT

t_CLP

V_VEE2-0.3 V_max2+0.3

V

Gate driver high output maximum current

Gate driver low output maximum current

Maximum short circuit clamping time

2.4

10

A

us

t = 2µs

I_CLAMP/OUT

500mA

=

Positive power supply input side

Logic input voltages

(IN+,IN-,RST)

V_VCC1

V_LogicIN

-0.3

6.5

V

Opendrain Logic output voltage

(FLT)

Opendrain Logic output voltage

(RDY)

Opendrain Logic output current

(FAULT)

Opendrain Logic output current

(RDY)

V_FLT

V_RDY

I_FLT

-0.3

6.5

10

V

mA

I_RDY

10

1)

Pin DESAT voltage

Pin TLSET voltage

Pin CLAMP voltage

V_DESAT

V_TLSET

V_CLAMP

-0.3

V_VCC2+0.3

V

= -8V

VEE2

1)

V_VEE2-0.3 V_VCC2+0.3

2)

Junction temperature

Storage temperature

Power dissipation, Input chip

T_J

T_S

P_{D, IN}

-40

-55

150

100

°C

mW ³⁾@TA = 25°

mW ²⁾³⁾@TA = 25°

K/W ²⁾@TA = 25°C

Power dissipation, Output chip

Thermal resistance (Input chip active)

Thermal resistance (Output chip active)

ESD Capability

P_{D, OUT}

R_THJA,IN

R_THJA,OUT

V_ESD

700

139

117

1.5

kV

Human Body

Model⁴⁾

1) With respect to GND2.

2) may be exceeded during short circuit clamping

3) Output IC power dissipation is derated linearly at 8.5 mW/°C above 68°C. Input IC power dissipation does not require derating. See

section 8.1 for reference layouts for these thermal data. Thermal performance may change significantly with layout and heat dissipation

of components in close proximity.

4) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor).

Preliminary Datasheet

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EICEDRIVER®

1ED020I12FTA

Electrical Parameters

4.2

Operating Parameters

Note:Within the operating range the IC operates as described in the functional description. Unless otherwise

noted all parameters refer to GND1.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

13

-12

max.

20

0

1)

Positive power supply output side

V_VCC2

V_VEE2

V_max2

V

Negative power supply output side

Maximum power supply voltage output side

28

(V_VCC2-V_VEE2

)

Positive power supply input side

Logic input voltages

(IN+,IN-,RST)

Pin CLAMP voltage

Pin DESAT voltage

Pin TLSETvoltage

V_VCC1

V_LogicIN

4.5

-0.3

5.5

V

2)

V_CLAMP

V_DESAT

V_TLSET

T_A

V_VEE2-0.3

-0.3

V_VCC2

125

V

°C

1)

-0.3

-40

—

Ambient temperature

Common mode transient immunity³⁾

|∆V_ISO/dt|

50

kV/µs @ 500V

1) With respect to GND2.

2) May be exceeded during short circuit clamping

3) The parameter is not subject to production test - verified by design/characterization

4.3

Recommended Operating Parameters

Note:Unless otherwise noted all parameters refer to GND1.

Parameter

Symbol

Values

Unit Remarks

1)

Positive power supply output side

Negative power supply output side

Positive power supply input side

V_VCC2

V_VEE2

V_VCC1

15

-8

5

V

1)

1) With respect to GND2.

Preliminary Datasheet

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Electrical Parameters

4.4

Electrical Characteristics

Note:The electrical characteristics include the spread of values in supply voltages, load and junction temperatures

given below. Typical values represent the median values at T_A= 25°C. Unless otherwise noted all voltages

are given with respect to their respective GND (GND1 for pins 11 to 20, GND2 for pins 1 to 10).

4.4.1

Voltage Supply.

Parameter

Symbol

Limit Values

Unit Test Conditions

min.

typ.

max.

UVLO Threshold Input Chip

V_UVLOH1

V_UVLOL1

V_HYS1

4.1

3.8

4.3

V

3.5

0.15

UVLO Hysteresis Input Chip

(V_UVLOH1- V_UVLOL1

)

UVLO Threshold Output Chip

V_UVLOH2

V_UVLOL2

V_HYS2

12.0

11.0

0.9

12.6

V

10.4

0.7

UVLO Hysteresis Output Chip

(V_UVLOH1- V_UVLOL1

)

Quiescent Current Input Chip

I_Q1

7

9

6

mA V_VCC1=5V

IN+ = High, IN- = Low

=>OUT = High, RDY =

High, /FLT = High

Quiescent Current Output Chip

I_Q2

4.5

mA V_VCC2=15V

V_VEE2=-8V

IN+ = High, IN- = Low

=>OUT = High, RDY =

High, /FLT = High

4.4.2

Logic Input and Output

Parameter

Symbol

Limit Values

min. typ.

Unit Test Conditions

max.

IN+,IN-, RST Low Input Voltage

IN+,IN-, RST High Input Voltage

IN-, RST Input Current

V_IN+L,V_IN-

_L,V_RSTL

V_IN+H,V_IN-3.5

_HV_RSTH

1.5

V

I_{IN-, RST}

I

100

400

uA V_IN-=GND1

V_RST=GND1

IN+ Input Current

RDY,FLT Pull Up Current

I_IN+,

I_PRDY,

I_PFLT

100

400

uA V_IN+=VCC1

uA V_RDY=GND1

V_FLT=GND1

Input Pulse Suppression IN+, IN-

T_MININ+

T_MININ-

T_MINRST

T_RST

,

30

40

ns

Input Pulse Suppression RST

for ENABLE/SHUTDOWN

Pulse Width RST

for Reseting FLT

30

800

FLT Low Voltage

RDY Low Voltage

V_FLTL

V_RDYL

300

mV I_SINK(FLT)= 5mA

mV I_SINK(RDY)= 5mA

Preliminary Datasheet

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Electrical Parameters

4.4.3

Gate Driver

Parameter

Symbol

Limit Values

typ. max.

Unit Test Conditions

min.

High Level Output Voltage

V_OUTH1

V_OUTH2

V_OUTH3

V_OUTH4

I_OUTH

V_VCC2-1.2 V_VCC2-0.8

V

A

I_OUTH= -20mA

I_OUTH= -200mA

I_OUTH= -1A

V_VCC2-2.5 V_VCC2-2.0

V_VCC2-9

-1.5

V_VCC2-5

V_VCC2-10

-2.0

I_OUTH= -2A

High Level Output Peak Current

Low Level Output Voltage

IN+ = High, IN- = Low;

OUT = High

I_OUTL= 20mA

I_OUTL= 200mA

I_OUTL= 1A

V_OUTL1

V_OUTL2

V_OUTL3

V_OUTL4

I_OUTL

V_VEE2+0.04 V_VEE2+0.09

V_VEE2+0.3 V_VEE2+0.85

V

A

V_VEE2+2.1

V_VEE2+7

2.0

V_VEE2+5.0

—

I_OUTL= 2A

Low Level Output Peak Current

1.5

IN+ = Low, IN- = Low;

OUT = Low,

V_VCC2=15V,

V_VEE2=-8V

4.4.4

Active Miller Clamp

Parameter

Symbol

Limit Values

Unit Test Conditions

min.

typ.

max.

Low Level Clamp Voltage

V_CLAMPL1

V_CLAMPL2

V_CLAMPL3

I_CLAMPL

V_VEE2+0.03 V_VEE2+0.08 V

I_OUTL= 20mA

I_OUTL= 200mA

V_VEE2+0.3 V_VEE2+0.8

V_VEE2+1.9 V_VEE2+4.8

V

A

I_OUTL= 1A

1)

Low Level Clamp Current

Clamp Threshold Voltage

2

V_CLAMP

1.6

2.1

2.4

V

Related to VEE2

1) The parameter is not subject to production test - verified by design/characterization

4.4.5

Short Circuit Clamping

Parameter

Symbol

Limit Values

min. typ.

Unit Test Conditions

max.

1.3

Clamping voltage (OUT)

(V_OUT-V_VCC2

V_CLPout

0.8

1.3

0.7

V

IN+=High, IN-=Low,

OUT=High

)

I_OUT= 500mA (pulse

test,t_CLPmax=10us)

Clamping voltage (CLAMP)

(V_VCLAMP-V_VCC2

V_CLPclamp

IN+=High, IN-=Low,

OUT=High

)

I_CLAMP= 500mA (pulse

test,t_CLPmax=10us)

Clamping voltage (CLAMP)

V_CLPclamp

1.1

IN+=High, IN-=Low,

OUT=High

I_CLAMP= 20mA

Preliminary Datasheet

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Electrical Parameters

4.4.6

Dynamic Characteristics

Parameter

Symbol

Limit Values

min. typ.

1.6

Unit Test Conditions

max.

2.1

IN+ Input to output propagation delay

ON/OFF and IN- OFF

IN+ Input to output propagation delay

distortion (TPDOFF-TPDON)

T_PDON

1.8

30

us

ns

us

ns

us

ns

us

ns

us

ns

us

ns

C_TLSET=0, TA=25°C

C_TLSET=0, TA=125°C

C_TLSET=0, @TA=-40°C

T_PDISTO

0

60

IN- Input to output propagation delay ON T_PDON-

1.6

1.8

30

tbd

2.8¹⁾

IN- Input to output propagation delay

distortion (TPDOFF-TPDON)

IN+ Input to output propagation delay

ON/OFF and IN- OFF

IN+ Input to output propagation delay

distortion (TPDOFF-TPDON)

IN- Input to output propagation delay ON T_PDON-t

T_PDISTO-

T_PDONt

tbd

60

2.3

70

-545¹⁾

1.5

0

1.9

40

T_PDISTOt

1.5

1.9

40

tbd

3.0¹⁾

IN- Input to output propagation delay

distortion (TPDOFF-TPDON)

IN+ Input to output propagation delay

ON/OFF and IN- OFF

IN+ Input to output propagation delay

distortion (TPDOFF-TPDON)

IN- Input to output propagation delay ON T_PDON-t

T_PDISTO-t

T_PDONt

tbd

70

2.3

50

-700¹⁾

1.5

1.8

20

T_PDISTOt

0

1.5

1.8

20

tbd

3.0¹⁾

IN- Input to output propagation delay

distortion (TPDOFF-TPDON)

T_PDISTO-t

T_RISE

tbd

50

-700¹⁾

Rise Time

Fall Time

10

150

10

30

60

V_VCC2=15V,V_VEE2=-8V

C_LOAD= 1nF,

VL 10% ,VH 90%

400

20

800

40

ns

V_VCC2=15V,V_VEE2=-8V

C_LOAD= 34nF

VL 10% ,VH 90%

T_FALL

V_VCC2=15V,V_VEE2=-8V

C_LOAD= 1nF

VL 10% ,VH 90%

100

250

500

V_VCC2=15V,V_VEE2=-8V

C_LOAD= 34nF

VL 10% ,VH 90%

1) The maximum value of input to output propagation delay ON at IN- occures only in case of electromagnetic interferences, typically the

input to output delay is 2.1µs at TA =25°C, one worst case watchdog clock cycle shorter (see chapter 2.2.3). The turn OFF-signal is

prioritized/dominant and will not show up this behavior.

Preliminary Datasheet

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Electrical Parameters

4.4.7

Desaturation protection

Parameter

Symbol

Limit Values

min. typ.

450

Unit Test Conditions

max.

550

Blanking Capacitor Charge Current

Blanking Capacitor Discharge Current

I_DESATC

I_DESATD

500

15

uA V_VCC2=15V,V_VEE2=-8V

V_DESAT=2V

11

mA V_VCC2=15V,V_VEE2=-8V

V_DESAT=6V

Desaturation Reference Level

Desaturation Sense to OUT TLTO

V_DESAT

T_DESATOUT

8.5

9

270

9.5

320

V

V_VCC2=15V,V_VEE2=-8V

V_VCC2=15V,V_VEE2=0V

ns V_OUT=90%

C_LOAD= 1nF

Desaturation Sense to FLT Low Delay

Desaturation Low Voltage

T_DESATFLT

V_DESATL

2.25

110

us V_FLT=10%; I_FLT=5mA

40

70

mV IN+=Low, IN-=Low,

OUT=Low

4.4.8

Active Shut Down

Parameter

Symbol

Limit Values

Unit Test Conditions

min.

typ.

max.

2.0

1)

Active Shut Down Voltage

1) With reference to VEE2

V_ACTSD

V

I_OUT=-200mA,

V_CC2open

4.4.9

Two-level Turn-off

Parameter

Symbol

Limit Values

Unit Test Conditions

min.

7.5

typ.

max.

VCC2-0.5 V

External reference voltage range (Zener- V_ZDIODE

Diode)

Reference Voltage for setting two-level V_TLSET

delay time

6.6

7

7.3

V

Current for setting two-level delay time I_TLSET

and external reference voltage (Zener-

Diode)

420

500

550

uA V_TLSET=10V

External Capacitance Range

C_TLSET

0

220

pF

Preliminary Datasheet

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Insulation Characteristics

5

Insulation Characteristics

5.1

Complies with DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation

Description

Symbol

Characteristic

Unit

Installation classification per EN 60664-1, Table 1

for rated mains voltage ≤ 150 V_RMS

I-IV

I-III

I-II

for rated mains voltage ≤ 300 V_RMS

for rated mains voltage ≤ 600 V_RMS

Climatic Classification

40/125/21

Pollution Degree (EN 60664-1)

Minimum External Clearance

Minimum External Creepage

2

8

CLR

CPG

mm

Minimum Comparative Tracking Index

Maximum Repetitive Insulation Voltage

Highest Allowable Overvoltage¹⁾

Maximum Surge Insulation Voltage

CTI

175

1420

6000

V_IORM

V_IOTM

V_IOSM

V_PEAK

V

5.2

According to UL 1577

Description

Insulation Withstand Voltage / 1min

Insulation Test Voltage / 1sec

Symbol

V_ISO

Characteristic

3750

4500

Unit

V_rms

5.3

Reliability

For Qualification Report please contact your local Infineon Technologies office.

Preliminary Datasheet

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Timing Diagrams

6

Timing Diagrams

All diagrams related to the Two-level switch-off feature

IN+

V_ZDIODE

V_TLSET, typ. 7V

TLSET

T_{ADJ 1}

T_TLSET

T_PD

V_ZDIODE

T_PD

T_TLFALL

OUT

T_PDONADJ

T_TLSET

Figure 4: Typical Switching Behavior

IN+

T_PDON

T_TLSET

OUT

T_DESATOUT

V_DESATtyp. 9V

DESAT

/FLT

T_DESATFLT

/RST

>T_RSTmin

Figure 5: DESAT Switch-OFF Behavior

Preliminary Datasheet

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Timing Diagrams

IN+

TLSET

T_PD

T_TLSET

T_PDON

T_TLSET

T_PDON

T_PDOFF

OUT

Figure 6: Short Switch ON Pulses

IN+

T_TLSET

TLSET

T_PD

T_PDON

T_PDOFF

T_PDON

T_PDOFF

OUT

Figure 7: Short Switch OFF Pulses

IN+

TLSET

T_TLSET

T_PD

T_TLSET

T_PD

T_PDON

T_PDOFF

T_PDON

OUT

forced turn off after three

consecutive on -cycles

Figure 8: Short Switch OFF Pulses, Ringing Surpression

Preliminary Datasheet

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Timing Diagrams

V_UVLOH2

VCC2

IN+

T_PDON

T_PDOFF

OUT

I_DESAT

RDY

Figure 9: VCC2 Ramp Up

V_UVLOH2

VCC2

V_UVLOL2

T_PDD

IN+

T_TLSET

TLSET

Vz

T_PDON

OUT

RDY

/FLT

Figure 10: VCC2 Ramp Down and VCC2 Drop

Preliminary Datasheet

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Timing Diagrams

5

4

3

2

1

0

50

100

150

200

C_TLSET[pF]

Figure 11: Typical T_TLSETTime over C_TLSETCapacitance

Preliminary Datasheet

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Package Outlines

7

Package Outlines

PG-DSO-20-55

(Plastic Dual Small

Outline Package)

Figure 12: PG-DSO-20-55

Preliminary Datasheet

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Application Notes

8

Application Notes

8.1

Reference Layout for Thermal Data

The PCB layout shown in figure 12 represents the reference layout used for the thermal characterisation. Pins 11,

12, 19 and 20 (GND1) and pins 1, 2, 9 and 10 (VEE2) require ground plane connections for achiving maximum

power dissipation. The 1ED020I12FTA is conceived to dissipate most of the heat generated through this pins.

PCB + Top-Layer

PCB + Bottom-Layer

Figure 13: Reference layout for thermal data (Copper thickness 102mm)

8.2

Printed Circuit Board Guidelines

Following factors should be taken into account for an optimum PCB layout.

- Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits.

- The same minimum distance between two adjacent high-side isolated parts of the PCB should be maintained to

increase the effective isolation and reduce parasitic coupling.

- In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be kept

as short as possible.

Preliminary Datasheet

24

Version 1.2, 2010-05-21

w w w . i n f i n e o n . c o m / g a t e d r i v e r

Published by Infineon Technologies AG

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOP, SOP20,.4	针数：	20
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.62
Is Samacsys：	N	高边驱动器：	YES
接口集成电路类型：	HALF BRIDGE BASED IGBT DRIVER	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e4	长度：	12.8 mm
标称负供电电压：	-8 V	功能数量：	1
端子数量：	20	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	-8,5,15 V
认证状态：	Not Qualified	座面最大高度：	2.65 mm
子类别：	Peripheral Drivers	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
电源电压1-最大：	20 V	电源电压1-分钟：	14 V
电源电压1-Nom：	15 V	表面贴装：	YES
温度等级：	AUTOMOTIVE	端子面层：	Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
断开时间：	2 µs	接通时间：	2 µs
宽度：	7.6 mm	Base Number Matches：	1

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