NCP3418D
更新时间：2025-01-11 02:15:11
品牌：ONSEMI
描述：Dual Bootstrapped 12 V MOSFET Driver with Output Disable
概述
规格参数
数据手册NCP3418D 概述
Dual Bootstrapped 12 V MOSFET Driver with Output Disable 双自举12 V MOSFET驱动器输出禁用 MOSFET 驱动器
NCP3418D 规格参数
| 是否无铅： | 含铅 | 是否Rohs认证： | 不符合 |
| 生命周期： | Obsolete | 零件包装代码： | SOIC |
| 包装说明： | SOP, SOP8,.25 | 针数： | 8 |
| Reach Compliance Code： | not_compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.78 |
| 高边驱动器： | YES | 接口集成电路类型： | HALF BRIDGE BASED MOSFET DRIVER |
| JESD-30 代码： | R-PDSO-G8 | JESD-609代码： | e0 |
| 长度： | 4.9 mm | 湿度敏感等级： | 1 |
| 功能数量： | 1 | 端子数量： | 8 |
| 最高工作温度： | 85 °C | 最低工作温度： | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP8,.25 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | 235 |
| 电源： | 12 V | 认证状态： | Not Qualified |
| 座面最大高度： | 1.75 mm | 子类别： | MOSFET Drivers |
| 最大供电电压： | 13.2 V | 最小供电电压： | 4.6 V |
| 标称供电电压： | 12 V | 表面贴装： | YES |
| 温度等级： | COMMERCIAL EXTENDED | 端子面层： | Tin/Lead (Sn/Pb) |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 断开时间： | 0.06 µs | 接通时间： | 0.06 µs |
| 宽度： | 3.9 mm |
NCP3418D 数据手册
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PDF下载NCP3418, NCP3418A
Dual Bootstrapped 12 V
MOSFET Driver with
Output Disable
The NCP3418 and NCP3418A are dual MOSFET gate drivers
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. Each of the drivers is
capable of driving a 3000 pF load with a 25 ns propagation delay and a
20 ns transition time.
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MARKING
DIAGRAMS
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal,
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 30 V, with transient voltages as high as 35 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
The NCP3418A is identical to the NCP3418 except that there is no
internal charge pump diode.
8
8
SO−8
D SUFFIX
CASE 751
3418
3418A
ALYW
8
8
ALYW
1
1
1
8
1
8
1
3418
ALYW
3418A
ALYW
SO−8 EP
PD SUFFIX
CASE 751AC
1
A
L
Y
= Assembly Location
= Wafer Lot
= Year
The NCP3418 is pin−to−pin compatible with Analog Devices
ADP3418 with the following advantages:
W = Work Week
• Faster Rise and Fall Times
• Internal Charge Pump Diode Reduces Cost and Parts Count
• Thermal Shutdown for System Protection
• Integrated OVP
PIN CONNECTIONS
1
8
BST
IN
DRVH
SW
• Internal Pulldown Resistor Suppresses Transient Turn On of Either
MOSFET
OD
PGND
DRVL
Features
V
CC
• Anti Cross−Conduction Protection Circuitry
• Floating Top Driver Accommodates Boost Voltages of up to 30 V
• One Input Signal Controls Both the Upper and Lower Gate Outputs
• Output Disable Control Turns Off Both MOSFETs
• Complies with VRM 10.x Specifications
• Undervoltage Lockout
ORDERING INFORMATION
†
Device
Package
SO−8
Shipping
98 Units/Rail
NCP3418D
2500 Tape & Reel
NCP3418DR2
NCP3418ADR2
SO−8
• Thermal Shutdown
• Thermally Enhanced Package Available
2500 Tape & Reel
2500 Tape & Reel
SO−8
NCP3418ADR2G SO−8
NCP3418PD SO−8 EP
98 Units/Rail
2500 Tape & Reel
2500 Tape & Reel
NCP3418PDR2 SO−8 EP
NCP3418APDR2 SO−8 EP
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
May, 2004 − Rev. 10
NCP3418/D
NCP3418, NCP3418A
V
CC
4
Not present in
the NCP3418A
BST
1
2
IN
8
7
DRVH
SW
100 k
−
+
Nonoverlap
1.5 V
−
+
5
6
DRVL
PGND
4 V
120 k
3
OD
Figure 1. NCP3418/A Block Diagram
PIN DESCRIPTION
Pin
Symbol
Description
1
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this
bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value is between
100 nF and 1.0 mF. An external diode will be needed with the NCP3418A.
2
3
4
5
6
7
8
IN
Logic−Level Input. This pin has primary control of the drive outputs.
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.
Output drive for the lower MOSFET.
OD
V
CC
DRVL
PGND
SW
Power Ground. Should be closely connected to the source of the lower MOSFET.
Switch Node. Connect to the source of the upper MOSFET.
Output drive for the upper MOSFET.
DRVH
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2
NCP3418, NCP3418A
MAXIMUM RATINGS*
Rating
Value
0 to 85
0 to 150
Unit
°C
Operating Ambient Temperature, T
A
Operating Junction Temperature, T (Note 1)
°C
J
Package Thermal Resistance: SO−8
Junction−to−Case, R
45
123
°C/W
°C/W
q
JC
Junction−to−Ambient, R
(2−Layer Board)
q
JA
Package Thermal Resistance: SO−8 EP
Junction−to−Ambient, R (Note 2)
50
°C/W
°C
q
JA
Storage Temperature Range, T
−65 to 150
S
Lead Temperature Soldering (10 sec): Reflow (SMD styles only)
Standard (Note 3)
Lead Free (Note 4)
240 peak
260 peak
°C
JEDEC Moisture Sensitivity Level
SO−8 (240 peak profile)
SO−8 (260 peak profile)
SO−8 EP (240 peak profile)
SO−8 EP (260 peak profile)
1
1
1
3
−
1. Internally limited by thermal shutdown, 150°C min.
2. Rating applies when soldered to an appropriate thermal area on the PCB.
3. 60 − 180 seconds minimum above 183°C.
4. 60 − 180 seconds minimum above 237°C.
*The maximum package power dissipation must be observed.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
MAXIMUM RATINGS
Pin Symbol
Pin Name
V
MAX
V
MIN
V
Main Supply Voltage Input
Bootstrap Supply Voltage Input
15 V
−0.3 V
CC
BST
30 V wrt/PGND
35 V v 50 ns wrt/PGND
15 V wrt/SW
−0.3 V wrt/SW
SW
Switching Node
(Bootstrap Supply Return)
30 V
−1.0 V DC
−10 V< 200 ns
DRVH
High−Side Driver Output
Low−Side Driver Output
BST + 0.3 V
35 V v 50 ns wrt/PGND
15 V wrt/SW
−0.3 V wrt/SW
DRVL
V
CC
+ 0.3 V
−0.3 V DC
−2.0 V < 200 ns
IN
OD
DRVH and DRVL Control Input
Output Disable
V
V
+ 0.3 V
+ 0.3 V
0 V
−0.3 V
−0.3 V
0 V
CC
CC
PGND
Ground
NOTE: All voltages are with respect to PGND except where noted.
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3
NCP3418, NCP3418A
NCP3418−SPECIFICATIONS (Note 5) (V = 12 V, T = 0°C to +85°C, T = 0°C to +125°C unless otherwise noted.)
CC
A
J
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Supply
Supply Voltage Range
Supply Current
V
−
4.6
−
−
13.2
6.0
V
CC
I
BST = 12 V, IN = 0 V
2.0
mA
SYS
OD Input
Input Voltage High
Input Voltage Low
Input Current
−
−
−
−
2.0
−
−
−
−
−
V
V
−
0.8
−
−1.0
+1.0
mA
Propagation Delay Time (Note 6)
t
See Figure 2
−
−
40
40
60
60
ns
ns
pdlOD
t
pdhOD
PWM Input
Input Voltage High
−
−
−
−
−
−
2.0
−
−
−
−
−
V
V
Input Voltage Low
0.8
Input Current
−1.0
+1.0
mA
High−Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times (Note 6)
−
−
V
V
− V
− V
= 12 V (Note 8)
= 12 V (Note 8)
−
−
1.8
1.0
3.0
2.5
W
W
BST
SW
BST
SW
t
t
V
− V
= 12 V, C = 3.0 nF,
LOAD
−
−
18
10
25
15
ns
ns
rDRVH
fDRVH
BST
SW
See Figure 3
Propagation Delay (Notes 6 & 7)
t
t
V
BST
− V = 12 V
−
−
30
25
60
45
ns
ns
pdhDRVH
pdlDRVH
SW
Low−Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
−
−
V
= 12 V (Note 8)
−
−
1.8
1.0
3.0
2.5
W
W
CC
V
− V
= 12 V (Note 8)
CC
SW
t
t
C
= 3.0 nF, See Figure 3
−
−
16
11
25
15
ns
ns
rDRVL
fDRVL
LOAD
Propagation Delay
t
t
See Figure 3
−
−
30
20
60
30
ns
ns
pdhDRVL
pdlDRVL
Undervoltage Lockout
UVLO
−
−
−
3.9
4.3
0.5
4.6
V
V
Hysteresis
(Note 8)
Thermal Shutdown
Over Temperature Protection
Hysteresis
−
(Note 8)
(Note 8)
150
170
20
°C
°C
5. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
6. AC specifications are guaranteed by characterization, but not production tested.
7. For propagation delays, “t ’’ refers to the specified signal going high; “t ’’ refers to it going low.
pdh
pdl
8. GBD: Guaranteed by design; not tested in production.
Specifications subject to change without notice.
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4
NCP3418, NCP3418A
OD
t
pdlOD
t
pdhOD
90%
DRVH
or
10%
DRVL
Figure 2. Output Disable Timing Diagram
IN
t
t
fDRVL
pdlDRVL
t
pdlDRVH
t
rDRVL
DRVL
90%
90%
1.5 V
10%
10%
t
fDRVH
t
t
rDRVH
pdhDRVH
90%
90%
DRVH−SW
SW
10%
10%
t
pdhDRVL
4 V
Figure 3. Nonoverlap Timing Diagram (timing is referenced to the 90% and 10% points unless otherwise noted)
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5
NCP3418, NCP3418A
APPLICATIONS INFORMATION
IN
IN
DRVH
DRVH
DRVL
DRVL
Figure 4. DRVH Rise and DRVL Fall Times
Figure 5. DRVH Fall and DRVL Rise Times
15
10
5
40
30
20
trTG
trBG
trTG
trBG
10
0
0
1
2
4
1
2
4
3
5
3
5
LOAD CAPACITANCE (nF)
LOAD CAPACITANCE (nF)
Figure 6. Rise Time vs. Load Capacitance
Figure 7. Fall Time vs. Load Capacitance
60
50
40
30
20
I
CC
T = 25 °C
A
10
0
V
CC
= 12 V
C
= 3.3 nF
1000
1200
load
0
400
IN FREQUENCY (kHz)
200
600
800
Figure 8. VCC Supply Current vs. IN Frequency
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6
NCP3418, NCP3418A
APPLICATIONS INFORMATION
Theory of Operation
threshold, DRVL will go high after a propagation delay
(t ), turning the low−side MOSFET on. However, if
The NCP3418 and NCP3418A are single phase MOSFET
drivers optimized for driving two N−channel MOSFETs in
a synchronous buck converter topology. The NCP3418
features an internal diode, while the NCP3418A requires an
external BST diode for the floating top gate driver. A single
PWM input signal is all that is required to properly drive the
high−side and the low−side MOSFETs. Each driver is
capable of driving a 3.3 nF load at frequencies up to 500 kHz.
pdhDRVL
SW does not fall below 4.0 V in 300 ns, the safety timer
circuit will override the normal control scheme and drive
DRVL high. This will help insure that if the high−side
MOSFET fails to turn off it will not produce an over−voltage
at the output.
Similarly, to prevent cross conduction during the
low−side MOSFET’s turn−off and the high−side
MOSFET’s turn−on, the overlap circuit monitors the voltage
at the gate of the low−side MOSFET through the DRVL pin.
When the PWM signal goes high, DRVL will go low after
Low−Side Driver
The low−side driver is designed to drive
ground−referenced low R N−Channel MOSFET. The
voltage rail for the low−side driver is internally connected to
a
DS(on)
a propagation delay (t
), turning the low−side
pdlDRVL
MOSFET off. However, before the high−side MOSFET can
turn on, the overlap protection circuit waits for the voltage
at DRVL to drop below 1.5 V. Once this has occurred, DRVH
the V supply and PGND.
CC
When the NCP3418 is enabled, the low−side driver’s
output is 180_ out of phase with the PWM input. When the
device is disabled, the low−side gate is held low.
will go high after a propagation delay (t ), turning
pdhDRVH
the high−side MOSFET on.
High−Side Driver
The high−side driver is designed to drive a floating low
Application Information
Supply Capacitor Selection
R
DS(on)
N−channel MOSFET. The bias voltage for the high
For the supply input (V ) of the NCP3418, a local bypass
CC
side driver is developed by a bootstrap circuit referenced to
SW. The bootstrap capacitor should be connected between
the BST and SW pins.
The bootstrap circuit comprises an internal or external
diode, D1 (in which the anode is connected to V ), and an
capacitor is recommended to reduce noise and supply peak
currents during operation. Use a 1.0 to 4.7 mF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors
provide the best combination of low ESR and small size.
CC
Keep the ceramic capacitor as close as possible to the V
and PGND pins.
CC
external bootstrap capacitor, C . When the NCP3418 is
starting up, the SW pin is at ground, so the bootstrap capacitor
BST
Bootstrap Circuit
will charge up to V through D1. When the PWM input goes
CC
The bootstrap circuit uses a charge storage capacitor
high, the high−side driver will begin to turn on the high−side
MOSFET by pulling charge out of C . As the high−side
(C ) and the internal (or an external) diode. Selection of
BST
BST
MOSFET turns on, the SW pin will rise to V , forcing the
these components can be done after the high−side MOSFET
has been chosen.
IN
BST pin to V + V , which is enough gate−to−source
IN
CC
voltage to hold the MOSFET on. To complete the cycle, the
high−side MOSFET is switched off by pulling the gate down
to the voltage at the SW pin. When low−side MOSFET turns
on, the SW pin is held at ground. This allows the bootstrap
The bootstrap capacitor must have a voltage rating that is
able to withstand twice the maximum supply voltage. A
minimum 50 V rating is recommended. The capacitance is
determined using the following equation:
capacitor to charge up to V again.
CC
Q
GATE
DV
C
+
(eq. 1)
BST
The high−side driver’s output is in phase with the PWM input.
When the device is disabled, the high side gate is held low.
BST
where Q
is the total gate charge of the high−side
GATE
Safety Timer and Overlap Protection Circuit
MOSFET, and DV
is the voltage droop allowed on the
BST
The overlap protection circuit prevents both the high−side
MOSFET and the low−side MOSFET from being on at the
same time, and minimizes the associated off times. This will
reduce power losses in the switching elements. The overlap
protection circuit accomplishes this by controlling the delay
from turning off the high−side MOSFET to turning on the
low−side MOSFET.
To prevent cross conduction during the high−side
MOSFET’s turn−off and the low−side MOSFET’s turn−on,
the overlap circuit monitors the voltage at the SW pin. When
the PWM input signal goes low, DRVH will go low after a
high−side MOSFET drive. For example, a NTD60N03 has
a total gate charge of about 30 nC. For an allowed droop of
300 mV, the required bootstrap capacitance is 100 nF. A
good quality ceramic capacitor should be used.
If an external Schottky diode will be used for bootstrap,
it must be rated to withstand the maximum supply voltage
plus any peak ringing voltages that may be present on SW.
The average forward current can be estimated by:
I
+ Q
f
GATE MAX
(eq. 2)
F(AVG)
where f
is the maximum switching frequency of the
MAX
propagation delay (t ), turning the high−side
pdlDRVH
controller. The peak surge current rating should be checked
in−circuit, since this is dependent on the source impedance
MOSFET off. However, before the low−side MOSFET can
turn on, the overlap protection circuit waits for the voltage at
the SW pin to fall below 4.0 V. Once SW falls below the 4.0 V
of the 12 V supply and the ESR of C
BST.
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7
NCP3418, NCP3418A
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AB
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
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8
NCP3418, NCP3418A
PACKAGE DIMENSIONS
SOIC−8 EP
PD SUFFIX
CASE 751AC−01
ISSUE O
2 X
0.10
C
A−B
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE “b”
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
D
DETAIL A
A
EXPOSED
PAD
F
8
5
5
8
G
E1
E
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
2 X
MILLIMETERS
0.10 C D
2 X
DIM MIN
MAX
1.75
0.10
1.65
0.51
0.48
0.25
0.23
h
1
e
4
4
1
A
A1
A2
b
b1
c
1.35
0.00
1.35
0.31
0.28
0.17
0.17
0.20
C
PIN ONE LOCATION
BOTTOM VIEW
8 X b
A
A
B
0.25 C A−B
D
END VIEW
TOP VIEW
c1
D
4.90 BSC
E
E1
e
6.00 BSC
3.90 BSC
1.27 BSC
0.10
C
(b)
A2
A
8 X
L
0.40
1.27
L1
F
G
h
1.04 REF
0.10
C
2.24
3.20
2.51
0.50
8
c
c1
1.55
0.25
0
SEATING
PLANE
b1
q
_
_
A1
C
SIDE VIEW
SECTION A−A
H
GAUGE
PLANE
L
0.25
q
(L1)
DETAIL A
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9
NCP3418, NCP3418A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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For additional information, please contact your
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NCP3418/D
NCP3418D 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| NCP3418DR | ONSEMI | IC,DUAL MOSFET DRIVER,SOP,8PIN,PLASTIC | 获取价格 |
|
| NCP3418DR2 | ONSEMI | Dual Bootstrapped 12 V MOSFET Driver with Output Disable | 获取价格 |
|
| NCP3418DR2 | ROCHESTER | HALF BRDG BASED MOSFET DRIVER, PDSO8, SOIC-8 | 获取价格 |
|
| NCP3418DR2G | ONSEMI | Dual Bootstrapped 12 V MOSFET Driver with Output Disable | 获取价格 |
|
| NCP3418DR2G | ROCHESTER | HALF BRDG BASED MOSFET DRIVER, PDSO8, LEAD FREE, SOIC-8 | 获取价格 |
|
| NCP3418PD | ONSEMI | Dual Bootstrapped 12 V MOSFET Driver with Output Disable | 获取价格 |
|
| NCP3418PDG | ONSEMI | IC HALF BRDG BASED MOSFET DRIVER, PDSO8, SOIC-8, MOSFET Driver | 获取价格 |
|
| NCP3418PDR2 | ONSEMI | Dual Bootstrapped 12 V MOSFET Driver with Output Disable | 获取价格 |
|
| NCP3418PDR2 | ROCHESTER | HALF BRDG BASED MOSFET DRIVER, PDSO8, SOIC-8 | 获取价格 |
|
| NCP3418PDR2G | ONSEMI | HALF BRDG BASED MOSFET DRIVER, PDSO8, SOIC-8 | 获取价格 |
|
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