ML5245中文资料_数据手册_规格书

FEDL5245-05

1. December , 2020

ML5245

5 to 13 Series Cell Rechargeable Battery Protection IC

■ General Description

The ML5245 is a protection IC for 5- to13-cell Li-ion rechargeable battery pack. It detects individual cell

overvoltage/undervoltage and pack overcurrent/over-temperature, and then automatically turns on or turns off

the external charge/discharge NMOS-FETs accordingly.

Also, the ML5245 has a cell voltage monitor function so that the individual cell voltage can be monitored by

an external microcontroller.

■ Features

• Number of connected cells : 10-cell / 13-cell

• Highly accurate overvoltage / undervoltege detection function

Overvoltage detection accuracy

Undervoltage detection accuracy

: ±15mV(25℃)

: ±50mV(25℃)

• Charge / discharge overcurrent detection function

Dischrage overcurrent detection accuracy : ±10mV(25℃)

Charge overcurrent detection accuracy

: ±10mV(25℃)

• Short current detection function

Short current detection accuracy

: ±15mV(25℃)

• Adjustable detection delay time for overvoltage / undervoltage / short current with external capacitor

• Temperature detection function : with external NTC(10kΩ, B=3435) and 4.7kΩ resistor.

Discharge inhibition temperature

: 75℃ or higher

Charge inhibition temperature

: 55℃ or higher, -5℃ or lower

• Cell voltage monitor function : Cell voltage multiplied by 0.5 is outputted from VMON pin

• FET overheat protection function : stop large charge/discharge current through FET body-diode and

protect this IC from overheat.

• Number of connected cells, each detection voltage, each detectin delay time is selected with mask-option

(Code number)

• Low power consumption

Normal state

Power down state

: 25μA(typ), 60μA（max）

: 0.1μA(typ),1μA(max)

• Supply voltage

: +7V to +80V

• Operating temperature : -40℃ to +85℃

• Package : 30pin SSOP

Note) This product is not intended for automotive use and for any equipment, device, or system that requires a

specific quality or high level of reliability (e.g., medical equipment, transportation equipment, aerospace

machinery, nuclear-reactor controller, fuel-controller, various safety devices). If you are not sure

whether your application corresponds to such special purposes, please contact your local ROHM sales

representative in advance.

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■ Block Diagram

VDD

VREG

Voltage

V13

V12

V11

Regulator

CS

Control

Logic

/DOFF

/VMEN

Voltage

Clamp

V10

V9

Clock

Generator

V8

V7

Reference

Voltage

Generator

VNTC

TSNS

Temperature

Detector

V6

V5

V4

V3

V2

V1

CDOV

CDUV

Delay

Generator

Cell Voltage

Detector

Output

Buffer

VMON

Cell Voltage

Monitor

RSENSE

PSENSE

Charger/Load

Detector

Current

Detector

FET

Driver

GND

ISENSE CDLY

C_FET

D_FET

■ Pin Configuration (top view)

VDD

V13

V12

V11

V10

V9

V8

V7

V6

V5 10

V4 11

1

2

3

4

5

6

7

8

9

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VREG

/VMEN

CS

/DOFF

VNTC

TSNS

CDOV

CDUV

CDLY

VMON

PSENSE

RSENSE

C_FET

ISENSE

D_FET

V3 12

V2 13

V1 14

GND 15

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■ Pin Description

I/O

Description

Power supply input pin.

Connect and external CR filter for noise rejection

1

VDD

―

2

3

V13

V12

V11

V10

V9

I

Battery cell 13 high voltage input pin.

Battery cell 13 low voltage input and battery cell 12 high voltage input pin

Battery cell 12 low voltage input and battery cell 11 high voltage input pin

Battery cell 11 low voltage input and battery cell 10 high voltage input pin

Battery cell 10 low voltage input and battery cell 9 high voltage input pin

Battery cell 9 low voltage input and battery cell 8 high voltage input pin

Battery cell 8 low voltage input and battery cell 7 high voltage input pin

Battery cell 7 low voltage input and battery cell 6 high voltage input pin

Battery cell 6 low voltage input and battery cell 5 high voltage input pin

Battery cell 5 low voltage input and battery cell 4 high voltage input pin

Battery cell 4 low voltage input and battery cell 3 high voltage input pin

Battery cell 3 low voltage input and battery cell 2 high voltage input pin

Battery cell 2 low voltage input and battery cell 1 high voltage input pin

4

I

5

I

6

I

7

V8

I

8

V7

I

9

V6

I

10

11

12

13

14

15

V5

I

V4

I

V3

I

V2

I

V1

I

－

Ground pin

GND

Discharge FET control signal output pin. Should be tied to the gate pin of the external

NMOS FET.

16

D_FET

O

Current sense resistor input pin. Connect a resistor of the resistance value corresponding

to the detecting current between this pin and the GND pin. Should be tied to the GND if not

used.

17

ISENSE

I

Charge FET control signal output pin. Should be tied to the gate pin of the external NMOS

FET.

18

19

C_FET

O

Load open detection input pin. Should be connected to the lower node where load is

connected

RSENSE

IO

Charger connection / open detection input pin. Should be connected to the lower node

where charger is connected. if charger and load is connected to the same node,RSENSE

and PSENSE should be shorted.

20

21

PSENSE

VMON

IO

O

Cell voltage monitor output pin. Cell voltage multiplied by 0.5 is outputted. When cell

voltage is not outputted, voltage is 0V.

22

23

24

CDLY

CDUV

CDOV

IO

Short current detection delay time setting pin. Should be tied to the GND via capacitor.

Overdischarge detection delay time settgin pin. Shlould be tied to the GND via capacitor.

Overvoltage detection delay gtime setting pin. Should be tied to the GND via capacitor.

Input pin for high / low temperature charge / discharge inhibition. Connect a thermistor

between this pin and GND. Should be tied to the GND via 10kΩ resistor if not used.

Thermistor power supply. Should be connected to TSNS through a 4.7 kΩ resistor.

OFF control command input pin for the discharge FET. The "L" level input forces "L" on the

D_FET output, except when charge state is detected. Should be tied to the VREG pin if not

used.

25

26

TSNS

VNTC

I

O

27

28

/DOFF

CS

I

Input for selecting number of connected cells. “L” level selects 13 cell and “H” level selects

10 cell.

Cell voltage monitor output enable pin. This is Hi-z input and NMOS open-drain output,

and for using cell volagte monitor function, connect external plull-up resistor. If the “L”

pulse signal is inputted, this IC outputs the measured cell voltage into VMON pin during

one cell monitoring cycle. If the measured cell voltage is outputted, an “L” level interrupt

signal is outputted from this pin when the measured cell is changed.

Should be tied to VREG pin if not used.

29

30

/VMEN

VREG

IO

O

Built-in 4.3 V regulator output pin. Should be tied to GND through a 1 μF capacitor. Do not

use this pin as power supply for an external circuit.

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■ Absolute Maximum Ratings

GND= 0 V, Ta = +25 °C

Item

Symbol

V_DD

Condition

Applied to VDD pin

Rating

Unit

V

Supply voltage

－0.3 to +86.5

V_IN1

Applied to V1 to V13, D_FET pins

－0.3 to V_DD+0.3

V

Applied to CS, CDOV, CDUV,

CDLY, ISENSE, TSNS pins

Applied to C_FET, RSENSE,

PSENSE pins

V_IN2

－0.3 to V_REG+0.3

V

Input voltage

V_IN3

－86.5 to +0.3

V

Voltage difference agains the VDD

V_IN4

Applied to /VMEN, /DOFF pins

Applied to VREG, /VMEN pins

－0.3 to +6.5

V

V_OUT1

Applied to VMON, VNTC, CDOV,

CDUV, CDLY pins

V_OUT2

－0.3 to V_REG+0.3

V

Output voltage

V_OUT3

V_OUT4

P_D

Applied to D_FET pin

Applied to C_FET pin

―

－0.3 to V_DD+0.3

_DD－86.5 to V_DD+0.3

1.0

V

Power dissipation

W

Applied to VREG, VMON, /VMEN,

VNTC, CDOV, CDUV, CDLY,

D_FET, C_FET pins

Short-circuit

output current

I_OS

10

mA

°C

Storage

temperature

T_STG

—

－55 to＋150

■ Recommended Operating Conditions

GND= 0 V

Item

Symbol

V_DD

Condition

Applied to VDD pin

—

Range

7 to 80

Unit

V

Supply voltage

Operating temperature

T_OP

－40 to +85

°C

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■ Electrical characteristics

● DC Characteristics

V_DD=7V to 80V，GND=0V，Ta=－40 to +85°C

Sym

bol

Item

Condition

Min.

Typ.

—

Max.

V_REG

Unit

V

0.8×

V_REG

Digital "H" input voltage (Note 1)

Digital "L" input voltage (Note 1)

V_IH

V_IL

―

0.2×

V_REG

2

0

—

V

Digital "H" input current (Note 2)

Digital "L" input current (Note 2)

Cell monitoring pin Input current

(Note 3)

I_IH

I_IL

V_IH= V_REG

V_IL= GND

—

µA

–2

—

Norman mode

Average current

I_INV1

I_ILVC

―

0.1

3

2

µA

Cell monitoring pin Input leakage

current (Note 3)

Power down mode

―

"L” output voltage (Note 4)

Output leakage current (Note4)

V_OL

I_OLK

I_OL= 1mA

V_OH=5.5V, V_OL=0V

I_OH=－10µA

V_DD=18V to 60V

I_OL=100µA

―

0.2

2

V

–2

µA

"H" output voltage(Note5)

V_OH1

10

14

18

V

"L" output voltage(Note 6)

"L" output voltage(Note 7)

"L" output voltage(Note 8)

C_FET output leakage current

V_OL1

V_OL2

V_OL3

I_LCF

V_RE

G

―

–2

―

0.2

0.4

2

V

I_OL=1mA

I_OL=100µA

V

V_CFET=0 to V_DD

With no output load

VDD＝7V to 60V

With 14.7kΩ resistor

connected

µA

VREG pin output voltage

VNTC output voltage

3.8

2.2

4.3

2.4

4.8

2.6

V

V_NTC

Note 1：Applied to CS, /VMEN, /DOFF pins

Note 2：Applied to CS, /VMEN, /DOFF, TSNS, ISENSE pins

Note 3：Applied to V1 to V13 pins and defined in average current

Note 4：Applied to /VMEN pin

Note 5：Applied to C_FET, D_FET pins

Note 6：Applied to D_FET pin

Note 7：Applied to VMON pin

Note 8：Applied to CDOV, CDUV, CDLY pins

● Supply current characgteristics

V_DD= 7V to 60V，GND=0V，Ta=－40 to +85°C,

Symb

ol

Item

Condition

Min.

Typ.

Max.

Unit

With no output load,

VMON enabled

with 14.7kΩis connected to

VNTC

Current consumption in

normal operation mode

I_DD1

―

25

60

µA

Current consumption in

power down mode

I_DDS

―

0.1

1.0

µA

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● Code 001 : detection voltage characteristics (Ta=25°C)

V_DD=52V，GND=0V，Ta=+25°C

Symb

ol

Item

Condition

Min.

4.235

4.05

2.75

2.95

140

Typ.

4.25

4.10

2.80

3.00

150

‐40

Max.

4.265

4.15

2.85

3.05

160

unit

V

Overvoltage detection

threshold

V_OV

―

Overvoltage release

threshold

V_OVR

V_UV

V

Undervoltage detection

threshold

V

Undervoltage release

threshold

V_UVR

V_OCU

V_OCO

V_SHRT

V

Discharge overcurrent

detection threshold

Charge overcurrent

detection threshold

Short circuit

detection threshold

High temperature charge

inhibition detection

threshold

mV

‐50

‐30

285

300

315

V_CHD

V_CHR

V_DHD

V_DHR

V_CCD

V_CCR

―

1.09

1.17

0.74

0.82

2.10

2.01

1.12

1.22

0.77

0.85

2.13

2.06

1.15

1.27

0.80

0.88

2.16

2.11

V

High temperature charge

inhibition release

threshold

High temperature

discharge inhibition

detection threshold

High temperature charge

inhibition release

threshold

Low temperature charge

inhibition detection

threshold

Low temperature charge

inhibition release

threshold

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● Code 001 : detection voltage characteristics (Ta=0°C to 60°C)

V_DD=52V，GND=0V，Ta=0°C to +60°C

Symb

ol

Item

Condition

Min.

4.225

4.03

2.7

Typ.

4.25

4.10

2.8

Max.

4.275

4.17

2.9

Unit

V

Overvoltage detection

threshold

V_OV

V_OVR

V_UV

―

Overvoltage release

threshold

V

Undervoltage detection

threshold

V

Undervoltage release

threshold

V_UVR

V_OCU

V_OCO

V_SHRT

2.9

3.0

3.1

V

Discharge overcurrent

detection threshold

Charge overcurrent

detection threshold

Short circuit

detection threshold

High temperature charge

inhibition detection

threshold

135

-55

150

‐40

300

165

-25

mV

270

330

V_CHD

V_CHR

V_DHD

V_DHR

V_CCD

V_CCR

―

1.07

1.15

0.72

0.80

2.08

1.99

1.12

1.22

0.77

0.85

2.13

2.06

1.17

1.29

0.82

0.90

2.18

2.13

V

High temperature charge

inhibition release

threshold

High temperature

discharge inhibition

detection threshold

High temperature charge

inhibition release

threshold

Low temperature charge

inhibition detection

threshold

Low temperature charge

inhibition release

threshold

Charge detection

ISENSE pin threshold

Discharge detection

ISENSE pin threshold

VREG drop detection

threshold

V_ISC

V_ISD

―

‐11

1

‐6

6

‐1

11

mV

V

V_UREG

V_RREG

3.0

3.4

3.8

4.2

VREG drop release

threshold

V

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● Charger Detection / Removal and Load Removal Threshold Characteristics

(Ta=0°C to 60°C)

V_DD=52V，GND=0 V，Ta=0°C to +60°C

Symb

ol

Item

Condition

Min.

0.35×V_DD

0

Typ.

―

Max.

0.65×V_DD

0.4

Unit

V

Charger detection

PSENSE threshold

Wake-up from

power-down mode

In charge overcurrent

state

V_PC1

V_PLU

V_PLD

V_RL

0.2

V

Charger removal

PSENSE threshold

Power-down mode

In discharge overcurrent

state

0.65×V_DD0.75×V_DD0.85×V_DD

Load removal

RSENSE threshold

1.0

1.2

1.4

In charge overcurrent

state

Power-down mode

In discharge overcurrent

state

PSENSE pin

pull-up resistance

R_PU

200

500

1000

kΩ

RSENSE pin

pull-down resistance

R_PD

1

3

7

MΩ

Short-current state

PSENSE pin

Input leakage current

RSENSE pin

I_LPS

I_LRS

Without pull-up resistor

‐2

―

2

µA

Without pull-down resistor

Input leakage current

● Code 001 : Detection / Release Delay and Monitor Cycle Characteristics (Ta=0 to 60℃)

V_DD=52V，GND=0 V，Ta=0 to +60°C

Item

Symbol

t_DET

Condition

―

Min.

290

Typ.

400

Max.

630

Unit

ms

Cell voltage monitor cycle

Overvoltage detection delay

(Note)

t_OV

t_UV

t_OCO

t_OCU

C_OV=0.1F

3.0

5.0

13.0

630

sec

ms

Undervoltage detection delay

(Note)

C_UV=0.1F

Charge overcurrent detection

delay

―

290

400

Discharge overcurrent

detection delay

Short circuit detection delay

Temperature monitor cycle

Temperature measurement

time

t_SC

t_PT

C_DLY=10nF

―

0.6

1.0

1.4

ms

290

400

630

t_TM

―

2

3

5

ms

Defined with

temperature

monitoring times

Temperature detection /

release delay

t_TDR

―

2

―

times

Charge state

detection/release delay

Discharge state detection /

release delay

t_ISC

t_ISD

―

50

100

150

ms

Discharge overcurrent

state

Short-current state

Charge overcurrent

state

Load removal detection delay

t_ORL

50

100

150

ms

Charger removal detection

delay

t_OCHG

(Note) The maximum time of ovcrcharge / overdischarge detection delay time is introduced by adding time lag

due to cell voltage monitor cycle and overvoltage / undervoltage delay timer time (t_OV,t_UV)

.

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● Cell voltage monitor output characteristics (Ta=25℃)

V_DD=52V，GND=0 V，Ta=25°C, with no load on VMON output

Item

Symbol

V_CELO4

V_CELO1

Condition

Min.

1.985

1.475

Typ.

2.00

1.5

Max.

2.015

1.525

Unit

V

Cell voltage=4V

Cell voltage=3V

VMON output voltage

V

● Cell voltage monitor output characteristics (Ta=0 to 60℃)

V_DD=52V，GND=0 V，Ta=0 to +60°C, with no load on VMON output

Item

Cell voltage monitor

range

Symbol

V_VMR

Condition

Min.

Typ.

Max.

Unit

―

0.1

―

4.5

V

V_CELO4

V_CELO1

Cell voltage=4V

Cell voltage=3V

1.98

2.00

1.5

2.02

V

VMON output voltage

1.475

1.525

VMON output current

capability

I_VCO

t_VEL

―

－100

1

―

1.8

3

＋100

―

µA

µs

/VMEN pin input

“L” pulse width

/VMEN pin output

”L” pulse width

Cell voltage output

stared

Switching the

measured cell

As per a cell

monitoring

T_INT

t_VMO

t_SVM

1.0

1.2

―

2.6

4.8

1

ms

VMON output time

VMON output settling

time

No output load

―

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■ Timing Chart

This section shows the timing diagrams of application circuit example 1 (charge / discharge route is

common)

● Overvoltage detection and recovery from overvoltage state with light load

Light load means that load is connected and ISENSE pin input voltage is lower than the Discharge

detection ISENSE pin threshold (V_ISD).

(Note 2)

(Note 3)

VOV

VOVR

Battery Cell

Voltage

t_DET

t_DETt_DETt_DETt_DETt_DET

t_DETt_DETt_DETt_DETt_DETt_DET

CDOV

0V

V_OH1

0V

t_OV

C_FET

(Note 1)

0V

V_OH1

D_FET

GND

PSENSE

RSNESE

V_ISD

GND

ISENSE

Charger is connected

Load is connected

State

Normal state

Overvoltage state

(Note 1) C_FET pin is pulled down with a resistor

(Note 2) Even if the voltage difference between Vn+1 and Vn reaches or rises above the overvoltage detection

threshold V_OV, there may be a time lag before starting the overvoltage detection delay timer because

cell voltages are monitored every 400 ms (typ.).

(Note 3) Even if the voltage difference between Vn+1 and Vn reaches or falls below the overvoltage release

threshold V_OVR, there may be a time lag before recovering from the overvoltage state because cell

voltages are monitored every 400 ms (typ.).

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● Overvoltage detection and recovery from overvoltage state with Heavy load

Heavy load means that load is connected and ISENSE pin input voltage is higher than the Discharge

detection ISENSE pin threshold (V_ISD).

(Note 2)

(Note 3)

VOV

Battery Cell

VOVR

Voltage

t_DET

t_DETt_DETt_DETt_DET

t_DETt_DETt_DET

t_DETt_DETt_DETt_DETt_DET

CDOV

0V

t_OV

V_OH1

C_FET

(Note 1)

0V

V_OH1

D_FET

GND

PSENSE

RSNESE

t_ISD

V_ISD

ISENSE

Heavy load is connected

Charger is connected

Normal state

Light load is connected

State

Overcharge state

Normal state

(Note 1) C_FET pin is pulled down with a resistor

(Note 2) Even if the voltage difference between Vn+1 and Vn reaches or rises above the overvoltage detection

threshold V_OV, there may be a time lag before starting the overvoltage detection delay timer because

cell voltages are monitored every 400 ms (typ.).

(Note 3) Even if the voltage difference between Vn+1 and Vn reaches or falls below the overvoltage release

threshold V_OVR, there may be a time lag before recovering from the overvoltage state because cell

voltages are monitored every 400 ms (typ.).

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● Undervoltage Detection, Transition to Power-down Mode and Recovery

(Note 1)

(Note 2)

VUVR

VUV

Battery Cell

Voltage

t_DET

t_DETt_DETt_DETt_DETt_DET

t_DETt_DETt_DETt_DETt_DETt_DET

CDUV

D_FET

C_FET

0V

t_UV

V_OH1

0V

V_OH1

V_PLD

V_PC

PSENSE

RSNESE

GND

V_ISC

ISENSE

Power down

state

Load is connected

Charger is connected

State

Undervoltage state

Normal state

(Note 1) Even if the voltage difference between Vn+1 and Vn reaches or falls below the undervoltage detection

threshold VUV, there may be a time lag before starting the undervoltage detection delay timer because

cell voltages are monitored every 400 ms (typ.).

(Note 2) Even if the voltage difference between Vn+1 and Vn reaches or rises above the undervoltage release

threshold VUVR, there may be a time lag before recovering from the undervoltage state because cell

voltages are monitored every 400 ms (typ.).

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● Undervoltage Detection and Large charger connection

(Note 1)

(Note 2)

VUVR

VUV

Battery Cell

Voltage

t_DET

t_DETt_DETt_DET

t_DETt_DETt_DETt_DETt_DET

CDUV

D_FET

C_FET

0V

t_UV

V_OH1

0V

V_OH1

PSENSE

RSNESE

GND

t_ISC

V_ISC

ISENSE

GND

Load is

connected

Large charger is

connected

Charger is

connected

State

Normal state

Undervoltage state

Normal state

(Note 1) Even if the voltage difference between Vn+1 and Vn reaches or falls below the undervoltage detection

threshold VUV, there may be a time lag before starting the undervoltage detection delay timer because

cell voltages are monitored every 400 ms (typ.).

(Note 2) Even if the voltage difference between Vn+1 and Vn reaches or rises above the undervoltage release

threshold VUVR, there may be a time lag before recovering from the undervoltage state because cell

voltages are monitored every 400 ms (typ.).

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● Discharge overcurrent detection, recovery from discharge overcurrent state by load

removal

V_OCU

GND

ISENSE

t_OCU

V_OH1

D_FET

0V

V_OH1

C_FET

(Note 1)

V_RL

PSENSE

RSNESE

GND

t_ORL

Load is not

connected

Load is connected

Load is not connected

Normal State

State

Normal state

Discharge overcurrent

state

(Note 1) C_FET pin is pulled down with a resistor.

● Charge overcurrent detection and recovery from charge overcurrent state by charger

removal

GND

V_OCO

ISENSE

t_OCO

V_OH1

D_FET

V_OH1

C_FET

(Note 1)

0V

V_PLU

PSENSE

RSNESE

GND

t_OCHG

Load is not

connected

Load is not

connected

Charger is connected

State

Normal state

Charge overcurrent state

Normal state

(Note 1) C_FET pin is pulled down with a resistor.

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● Short Current Detection and recovery from Short Current State by Load Removal

V_SC

GND

ISENSE

t_SC

CDLY

GND

V_OH1

D_FET

0V

V_OH1

C_FET

(Note 1)

PSENSE

RSNESE

V_RL

GND

t_ORL

Load is not

connected

Load is not

connected

Load is connected

State

Normal state

Short current detection

state

(Note 1) C_FET pin is pulled down with a resistor.

15/36

FEDL5245-05

ML5245

● High temperature charge inhibition detection and revcovery from high temperature

charge inhibition state

V_NTC

VNTC

Hi-Z

t_PT

V_CHR

V_CHD

TSNS

0V

t_TM

t_TDR

V_OH1

C_FET

(Note1)

0V

V_OH1

D_FET

V_ISD

ISENSE

GND

50℃≧

Temperature

≧45℃

Temperature ≧50℃

Temperature ≦50℃

Temperature ≦45℃

Status

High temperature

Charge inhibition state

Normal state

(Note 1) C_FET pin is pulled down with a resistor.

● High Temperature charge inihibition detection and heavy load connection

V_NTC

VNTC

TSNS

Hi-Z

t_PT

V_CHR

V_CHD

0V

t_TM

t_TDR

V_OH1

C_FET

(Note1)

0V

V_OH1

D_FET

t_ISD

V_ISD

ISENSE

GND

Heavy Load is

connected

Temperature ≧50℃

50℃≧Temperature ≧45℃

Temperature ≦50℃

Status

High Temperature charge

inhibition State

Normal State

(Note 1) C_FET pin is pulled down with a resistor.

16/36

FEDL5245-05

ML5245

● Low temperatrure charge inhibition detection, recovery from Low temperature charge

inhibition state

V_NTC

VNTC

TSNS

Hi-Z

t_PT

V_CCD

V_CCR

0V

t_TM

t_TDR

V_OH1

C_FET

(Note1)

0V

V_OH1

D_FET

V_ISD

ISENSE

GND

0℃≧

Temperature

≧-5℃

Temperature ≦-5℃

Temperature≧0℃

Temperature ≧-5℃

Status

Low Temperature charge

inhibition State

Normal State

(Note 1) C_FET pin is pulled down with a resistor.

● Low temperature Charge inhibition detection and Heavy Load connection

V_NTC

VNTC

Hi-Z

t_PT

V_CCD

V_CCR

TSNS

0V

t_TM

t_TDR

V_OH1

C_FET

(Note1)

0V

V_OH1

D_FET

t_ISD

V_ISD

ISENSE

GND

Heavy Load is

connected

Temperature ≦-5℃

0℃≧Temperature≧-5℃

Temperature ≧-5℃

Status

Low Temperature Charge

inhibition State

Normal State

(Note 1) C_FET pin is pulled down with a resistor.

17/36

FEDL5245-05

ML5245

● High Temperature Discharge inhibition and recovery from High Temperature Discharge

Inhibition State

V_NTC

VNTC

TSNS

Hi-Z

t_PT

V_DHR

V_DHD

0V

t_TM

t_TDR

V_OH1

D_FET

0V

C_FET

(Note1)

0V

V_ISD

ISENSE

GND

70℃≧

Temperature

≧65℃

Temperature ≦70℃

Temperature≦65℃

Temperature ≧70℃

Status

High Temperature

Charge Inhibition

State

High temperature Charge

Inhibition State

High Temperature Discharge

Inhibition State

(Note 1) C_FET pin is pulled down with a resistor.

● Cell Voltage Monitor Output (13 cell connected)

Upper most cell

Lowest cell

Upper most cell

V13-V12 cell

Not selected

V1-GND cell

V2-V1 cell

V13-V12 cell

Not selected

…

Internal Cell

Selection signal

/VMEN

t_INT

t_VEL

/VMEN is OUTPUT

/VMEN is INPUT

VMON

0V

t_SVM

Start from

Lowest cell

V1-GND

Cell voltage

V13-V12

Cell voltage

V2-V1

Cell Voltage

Output

Cell voltage

t_VMO

Cell Voltage Monitor Cycle t_DET

18/36

FEDL5245-05

ML5245

■ Function Description

● State of ML5245

The ML5245 has following ten states, which depend on individual cell voltages and the input level of the

ISENSE and TSNS pins.

1. Initial state

2. Normal state

3. Overvoltage state

4. Undervoltage state(including power-down mode)

5. Discharge overcurrent state

6. Charge overcurrent state

7. Short circuit state

8. High Temperature Charge Inhibition state

9. Low Temperature Charge Inhibition state

10. High Temperature Discharge Inhibition state

Each state is described below.

1. Initial State

The initial state refers to the period while the battery cells are being connected to the ML5233 and

connection of all the battery cells specified by the CS pin is completed, before transitioning to the

normal state.。

In the initial state, when the VREG pin voltage reaches or falls below the VREG drop detection

threshold, the D_FET pin output is set to the "L" level and the C_FET pin output to the "H" level, where

discharge is inhibited and charge is permitted.

When the VREG pin level reaches or rises above the VREG drop release threshold V_RREG, individual

cell voltage monitoring takes place. If all the battery cells specified by the CS pin reach or rise above

the undervoltage release threshold VUVR, the system transitions to the normal state. Overvoltage and

overcurrent detection is also performed in parallel.

CHG(+)

VDD

PACK(+)

PSENSE

RSENSE

C_FET

D_FET

GND

ISENSE

PACK(-)

CHG(-)

OFF

ON

19/36

FEDL5245-05

ML5245

2. Normal Operation State

The normal state refers to the period where all the battery cell voltages do not reach or rise above the

overvoltage/undervoltage detection threshold, the ISENSE pin voltage is below the overcurrent

detection threshold, and the TSNS pin voltage is above the high temperature detection threshold. In the

normal state, both the D_FET and C_FET pin outputs are set to the "H" level, where both charge and

discharge is permitted.

Individual cell voltages are monitored every 0.4 second for performing overvoltage/undervoltage

detection, while the pack temperature is also monitored using an external thermistor every 0.4 second.

The ISENSE pin voltage is always monitored to detect overcurrent in parallel.

CHG(+)

VDD

PACK(+)

PSENSE

RSENSE

C_FET

D_FET

GND

ISENSE

PACK(-)

CHG(-)

ON

3. Overvoltage State

When any one or more battery cell voltages reach or rise above the overvoltage detection threshold

VOV for longer than the overvoltage detection delay time tOV, the system enters the overvoltage state. In

the overvoltage state, the C_FET pin output is set to "Hi-Z" to inhibit charge, while the D_FET pin

output maintains the value in the previous state.

Battery cell voltages decrease gradually by self-discharge or a connected load. When all of them reach

or fall below the overvoltage detection release threshold VOVR, the system recovers from the

overvoltage state.

CHG(+)

VDD

PACK(+)

PSENSE

RSENSE

C_FET

D_FET

GND

ISENSE

PACK(-)

CHG(-)

ON

OFF

20/36

FEDL5245-05

ML5245

4. Undervoltage State

When any one or more battery cell voltages reach or fall below the undervoltage detection threshold

V_UVfor longer than the undervoltage detection delay time t_UV, the system enters the undervoltage state.

In the undervoltage state, the D_FET pin output is set to the "L" level to inhibit discharge, while the

C_FET pin output maintains the value in the previous state.

In the undervoltage state, a 500 kΩ pull-up resistor is connected between the PSENSE pin and VDD.

When the PSENSE pin voltage increases and reaches the charger removal PSENSE threshold VPLD after

turning off the external discharge FET, the system enters power-down mode to reduce current

consumption.

The PSENSE pin voltage decreases when a charger is present. If it reaches or falls below the charger

detection voltage VPC, the system wakes up all the circuits to resume monitoring individual battery cell

voltages.

If the system was in the overvoltage, undervoltage, high temperature or any overcurrent state before

entering power-down mode, these error flags are cleared during power-down. After wake-up, if these

errors are detected again for longer than the specified detection delay time, the system reenters the

corresponding error state.

Battery cell voltages increase while charging, and if all cell voltages reach or rise above the

undervoltage detection release threshold VUVR, the system recovers from the undervoltage state

CHG(+)

VDD

PACK(+)

PSENSE

RSENSE

C_FET

D_FET

GND

ISENSE

PACK(-)

CHG(-)

OFF

ON

21/36

FEDL5245-05

ML5245

5. Discharge Overcurrent State

When the load is connected and ISENSE pin voltage reaches or rises above the discharge overcurrent

detection threshold VOCU for longer than the discharge overcurrent detection delay time t_OCU, the system

enters the discharge overcurrent state, regardless of the individual battery cell voltages. In the discharge

overcurrent state, the D_FET pin output is set to the "L" level to inhibit discharge, while the C_FET pin

output is set to "Hi-Z" to monitor load removal.

In the discharge overcurrent state, the RSENSE pin is pulled-down with a resistor and a backflow

prevention diode. If the load is released, the RSENSE pin level approaches the GND level. The system

recovers from the discharge overcurrent state when the RSENSE pin level reaches or falls below the

load removal RSENSE threshold V_RLfor longer than the load removal detection delay time t_ORL

.

CHG(+)

VDD

PACK(+)

PSENSE

RSENSE

C_FET

D_FET

GND

ISENSE

PACK(-)

CHG(-)

OFF

22/36

FEDL5245-05

ML5245

6. Charge Overcurrent State

When the charger is connected and ISENSE pin voltage reaches or falls below the charge overcurrent

detection threshold VOCO for longer than the charge overcurrent detection delay time t_OCO, the system

enters the charge overcurrent state, regardless of the individual battery cell voltages. In the charge

overcurrent state the C_FET pin output is set to "Hi-Z" to inhibit charge, while the D_FET pin output

maintains the value in the previous state.

In the charge overcurrent state, a 500 kΩ pull-up resistor is connected between the PSENSE pin and

VDD pin to detect charger removal. If the charger is removed, the PSENSE pin level increases. The

system recovers from the charge overcurrent state when the PSENSE pin voltage reaches or rises above

the charger removal detection threshold V_PLUfor longer than the charger removal delay time t_OCHG

.

CHG(+)

VDD

PACK(+)

PSENSE

RSENSE

C_FET

D_FET

GND

ISENSE

PACK(-)

CHG(-)

ON

OFF

23/36

FEDL5245-05

ML5245

7. Short Circuit State

When the pack is overloaded and the ISENSE pin voltage reaches or rises above the short circuit

detection threshold V_SHRT, the capacitor connected to the CDLY pin is started to charge, regardless of

the battery cell voltages. When the CDLY pin voltage is increased to a specific level, the system enters

the short circuit state. In the short circuit state, the D_FET pin output is set to "L" level to inhibit

discharge, while the C_FET pin output is set to "Hi-Z" to detect load removal.

In the short circuit state, a pull-down resistor is connected between the RSENSE pin and the GND

pin through a backflow prevention diode. If the load is removed, the RSENSE pin level approaches the

GND level. The system recovers from the short circuit state when the RSENSE pin level reaches

or falls below the load removal detection threshold V_RLfor longer than the load removal detection delay

time tORL.

CHG(+)

VDD

PACK(+)

PSENSE

RSENSE

C_FET

D_FET

GND

ISENSE

PACK(-)

CHG(-)

OFF

24/36

FEDL5245-05

ML5245

8. High Temperature Charge Inhibition state

Pack temperature is monitored using an external thermistor every 0.4 seconds regardless of battery

cell voltages and current measurement. When the TSNS pin voltage reaches or falls below the high

temperature charge inhibition detection threshold V_CHDfor longer than the temperature detection delay

time t_TDR, the system enters the High Temperture Charge Inhibition state.

In the High Temperature Charge Inhibition state, the C_FET pin output is set to the "Hi-Z" state to

inhibit charge.

CHG(+)

VDD

VNTC

TSNS

2.4V

PACK(+)

V_CHD

V_CHR

C_FET

D_FET

GND

ISENSE

PACK(-)

CHG(-)

ON

OFF

25/36

FEDL5245-05

ML5245

9. Low Temperature Charge Inhibition state

Pack temperature is monitored using an external thermistor every 0.4 seconds regardless of battery

cell voltages and current measurement. When the TSNS pin voltage reaches or rises above the Low

Temperature Charge Inhibition detection threshold V_CCDfor longer than the temperature detection delay

time t_TDR, the system enters the Low Temperture Charge Inhibition state.

In the Low Temperature Charge Inhibition state, the C_FET pin output is set to the "Hi-Z" state to

inhibit charge.

CHG(+)

VDD

VNTC

TSNS

2.4V

PACK(+)

V_CCD

V_CCR

C_FET

D_FET

GND

ISENSE

PACK(-)

CHG(-)

ON

OFF

10. High Temperature Discharge Inhibition state

Pack temperature is monitored using an external thermistor every 0.4 seconds regardless of battery

cell voltages and current measurement. When the TSNS pin voltage reaches or falls below the high

temperature discharge inhibition detection threshold V_DHDfor longer than the temperature detection

delay time t_TDR, the system enters the High Temperture Discharge Inhibition state.

In the High Temperature Discharge Inhibition state, the D_FET pin output is set to the "L" state to

inhibit charge.

CHG(+)

VDD

VNTC

TSNS

2.4V

PACK(+)

V_DHD

V_DHR

C_FET

D_FET

GND

ISENSE

PACK(-)

CHG(-)

OFF

ON

26/36

FEDL5245-05

ML5245

● Cell voltage Monitoring function

ML5245 sequentially measures individual battery cell voltage from the lowermost cell to uppermost

cell of the battery pack during cell monitor cycle (400ms (typ.)). By inputting the cell voltage output

requirement signal (“L” pulse signal) from an external microcontroller, the measured cell voltage can be

outputted into VMON pin. Since /VMEN pin is Hi-Z input in input state and open drain output in output

state, connect external pull-up resistor.

The timing chart of a cell voltage monitoring function is shown in the following figure. When the input

level of /VMEN pin returns to “H” level after “L” level signal is once inputted to /VMEN pin, the

measured cell voltages will be outputted into VMON pin during a cell voltage monitor cycle. In such

period, /VMEN pin is in the output state and outputs an interrupt request signal whenever the measuring

cell is switched.

It is noted that the measured cell voltages is not be outputted even if “L” level signal is continuously

inputted to /VMEN pin since this cell voltage monitor function is enabled after the /VMEN pin is returned

from “L” to “H”.

After wake-up and power-on, 60ms(typ) of internal circuit settling time is set up. In this period,

inputting “L” pulse to /VEN pin is neglected.

While the cell voltage monitor function is enabled, ML5245 starts to measure the cell voltage from

lowermost cell to uppermost and the measured cell voltage is amplified by 0.5 and outputted into VMON

pin. During this period, /VMEN pin is in output state and an interrupt request signal, which has 1.8ms

(typ.) pulse width, is outputted whenever the selected cell is changed. After the one cell voltage monitor

cycle is completed, /VMEN pin returns to input state and remains the state until the cell voltage monitor

will be started after the “L” pulse signal is inputted. While the cell voltage monitor function is disenabled,

an output of VMON pin is 0V.

If the number of connected battery cells is less than 13 cells, VMON pin output is 0V during the

measuring period of unconnected cells and if any cells are not selected during cell voltage monitoring

cycle. When ML5245 is in power down state, this cell voltage monitoring function doesn’t run.

Upper most cell

Lowest cell

Upper most cell

V13-V12 cell

Not selected

V13-V12 cell

Not selected

V1-GND cell

V2-V1 cell

Not selected

…

Internal Cell

Selection signal

/VMEN

Cell voltage output

request signal

(“L” pulse, input)

Interrupt signal output

1.8ms(typ)

/VMEN is INPUT

/VMEN is OUTPUT

VMON

0V

Cell Voltage

Output

Start from

Lowest cell

V1-GND

Cell voltage

V13-V12

Cell voltage

V2-V1

Cell voltage

3ms(typ.)

Cell Voltage Monitor Cycle 400ms(typ.)

27/36

FEDL5245-05

ML5245

● Protection from FET overheating

If the charge/discharge connection is not separated, and one of charge/discharge FET is OFF,

charge/discharge current flows through the body-diode of the FET which is turned-off. In such case, if the

current is large, FET is much heated and might be broken.

ML5245 watchs charge/discharge state with ISENSE pin input voltage, and stops the currentflow of

body-diode of FETs.

If the ISENSE pin input voltage is higher than discharge state detection voltage V_ISDfor longer than

discharge state detection delay time t_ISD, not depending on charge inhiniting state of overvoltage, set the

C_FET pin “H” and stop the current flow through the body-diode of charge FET, and stop the

overheating of FET. And in this status, if the voltage of ISENSE pin input is lower than Discharge state

detection voltage V_ISDfor longer than discharge release delay time t_ISD, the C_FET pin output changes to

“Hi-Z” and the state returns to the charge inhibiting state such as overvoltage.

If the ISENSE pin input voltage is higher than charge state detection voltage V_ISCfor longer than charge

state detection delay time t_ISC, not depending on discharge inhiniting state of undervoltage, set the D_FET

pin “H” and stop the current flow through the body-diode of discharge FET, and stop the overheating of

FET. And in this status, if the voltage of ISENSE pin input is higher than Charge state detection voltage

V_ISCfor longer than Charge Release delay time t_ISC, the D_FET pin output changes to “L” and the state

returns to the disharge inhibiting state such as undervoltage.

If the charge circuit and discharge circuit is separated as shown in the Application Circuit Example 2,

and if the load is connected in charging state and discharge current flows, charge/discharge might be

repeated after charge FET is turned off by overvoltage detection or other detection. In such case, charge

FET’s protection from overheating function should be disabled by creating new code of the ML5245.

● External control of Discharge FET

The D_FET pin output can be directly set “L” to stop discharging by the /DOFF pin input, regardless of

the detected state on the ML5245.

But if the ISENSE pin input voltage is lower than charge state detection voltage V_ISCfor longer than

charge state detection delay time t_ISC, not depending on /DOFF input voltage, set the D_FET pin “H”.

If the input level of /DOFF is VREG, the state of D_FET depends on the status of the ML5245.

● Output Pin Values in Each Detection State

The output pin values in each detection state are shown in the table below.

state

Initial state

Normal state

D_FET

GND

14V

No change

GND

C_FET

14V

Hi-Z

No change

Hi-Z

PSENSE

Hi-Z

RSENSE

Hi-Z

VREG

4.3V

0V

Hi-Z

Overvoltage state

Undervoltage state

Power Down sate

Discharge overcurrent

state

No change No change

Pull-up

No change

Hi-Z

GND

Hi-Z

No change

Pull-down

4.3V

Charge overcurrent state No change

Hi-Z

Pull-up

No change

Pull-down

4.3V

Short current state

High temperture charge

inhibition state

GND

No change

Hi-Z

No change No change

4.3V

Low temperature charge

inhibition state

High temperature

discharge inhibition state

No change

GND

No change No change No change

(Note) “No change” means that the previous pin value is maintained in a new state.

In each state, it is expected that there is no charge/discharge current.

28/36

FEDL5245-05

ML5245

● Selecting the Number of Battery Cells

Cell count is selectable from predefined two values using the CS pin.

CS

Number of Battery cell

Unused Vn pins

GND

VREG

13cell

10cell

none

V1 to V3

If the number of cells is less than 13 cells, unconnected Vn pins should be tied to GND.

● Overvoltage / undervoltge detection delay time setting

Overvoltage detection delay time is calculated by adding two parameters; overvoltage detection delay

time t_OVwhich depends on the capacitance C_OVconnected to CDOV pin and GND, and time lag t_DELfrom

when the battery voltage raise above the overvoltage detectin voltage V_OVto when the cell voltage of

overvoltage state is monitored, and described by the following equation.

Overvoltage detection delay time (t_OV+t_DEL) [sec] = C_OV[µF] × 50 + t_DEL

If the battery cell voltage is higher than the overvoltage detection voltage, cell voltage is also monitored

with 400ms(typ.) interval, time lag tDEL is brought before the overvoltage delay timer starts. This time lag

is from 0 second to cell minotor cycle t_DET

.

Undervoltage detection delay time is calculated by adding two parameters; undervoltage detection delay

time t_UVwhich depends on the capacitance C_UVconnected to CDUV pin and GND, and time lag t_DELfrom

when the battery voltage fall below the undervoltage detectin voltage V_UVto when the cell voltage of

undervoltage state is monitored, and described by the following equation.

Undervoltage detection delay time (t_UV+t_DEL) [sec] = C_UV[µF] × 50 + t_DEL

If the battery cell voltage is lower than the undervoltage detection voltage, cell voltage is also monitored

with 400ms(typ.) interval, time lag tDEL is brought before the overvoltage delay timer starts. This time lag

is from 0 second to cell minotor cycle t_DET

.

If C_OV=0.1F 、C_UV=0.1F, overvoltage detection delay time and undervoltage detection delay time are

5.0+t_DELsecond.

● Setting Short Circuit Detection Delay

The short circuit detection delay (t_SC) depends on the charge time of the capacitor (C_DLY) connected to

the CDLY pin, which is described by the following equation.

Short circuit detection delay t_SC[ms] = C_DLY[nF] × 0.1

Recommended capacitance of C_DLYis 1nF. If the capacitance is small, 20 μs (typ.) should be added as a

delay of the short current detection comparator. Note that the delay time of external CR filter on the

ISENSE pin should be included.

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FEDL5245-05

ML5245

● Power-on/Power-off Sequence

Battery cells can be connected in any order, but it is recommend that the GND and VDD pins are

connected first, and then connection continues from lower to higher voltage cells. There are no

restrictions on the power supply voltage rise time at power-on, and power-off sequence or power supply

voltage fall time at power-off.

After power-on, the system usually transitions to the normal state. However, it may transition to the

undervoltage state due to chattering at power-on or other reasons. If it has transitioned to the undervoltage

state and moved to power-down mode, apply the charger connection detection threshold VPC or lower

level to the PSENSE pin to power it up again.

After power-on or power-up, there is 400ms(typ.) of stable time of internal cirucuit. During this interval,

VMON pin doesn’t output voltage value even if “L” signla is inputted in /VMEN pin.

● Handling VDD Pin and V0 to V13 Pins

Since the VDD pin is the power supply input, put a noise elimination RC filter in front of the VDD

input for stabilization. If the drive current on the external charge/discharge control FETs is large, the

resistor value of this noise filter should be adjusted so that the voltage drop across the resistor is smaller

than 1 V.

The V0 to V13 pins are the monitor pins for individual cell voltages. Put a noise elimination RC filter in

front of each battery cell to prevent false detection.

● Handling VREG Pin

The VREG pin is the power source of the built-in regulator which supplies power to the internal

modules. Connect a 1 μF or larger capacitor between this pin and GND for stabilization. Do not use it as a

power supply for external circuits since the supply current of the built-in regulator is limited.

● Unused pin Treatment

Following table shows how to haldle unused pins.

Unused pins

Recommended treatment

V1 to V8

Pull down

ISENSE

Pull down

CDLY、CDOV、CDUV

/DOFF, /VMEN

Open

Tied to the VREG pin

Tied to the TSNS pin through

4.7kΩ resistor

VNTC

TSNS

Pull down with a 10kΩ resistor

30/36

FEDL5245-05

ML5245

● Selectiong range of Number of battery cells

Number of Connected Battery Cells is selected from two preset numbers. Preset number is from 5 to 13.

CS pin level

GND

Setting range (connected cells)

5

6

7

8

9

10

11

12

13

VREG

● Detection voltage, setting range and step width

Presetting range of each detection voltage is shown below.

Detection voltage

Overvoltage detecttion

Overvoltage release

Undervoltge detection

Undervoltge relase

Charge overcurrent detection

Discharge overcurrent

detection

Symbol

V_OV

V_OVR

V_UV

V_UVR

V_OCO

Setting range

3.65V to 4.35V

3.5V to 4.25V

1.5V to 3.0V

2.3V to 3.5V

-30mV to -100mV

Setteing step witdth

25mV

100mV

10mV

V_OCU

V_SHRT

V_DHD

50mV to 300mV

100mV to 600mV

0.6V to 1.2V

50mV

100mV

10mV

Short circuit detection

High Temperature discharge

inhibition

High Tempearture charge

inhibition

Low Temperature charge

inhibition

V_CHD

V_CCD

0.7V to 1.3V

2.0V to 2.2V

10mV

● Overcurrent detection delay time setting range

Presetting range of charge / discharge overcurrent detection delay time is shown beloe.

Detection delay time

Symbol

t_OCU

Setting value [ms]

25

600

25

50

800

50

100

1000

100

200

1200

200

300

1600

300

400

2000

400

500

―

Discharge overcurrent

detection delay time

500

―

Charge overcurrent

detection delay time

t_OCO

600

800

1000

1200

1600

2000

31/36

FEDL5245-05

ML5245

■ Application Circuit Example

● Application Circuit Example 1 (10 cell, charge / discharge path is common)

PACK(+)

CHG(+)

R_VDD

1

2

3

4

5

6

30

29

28

27

VDD

V13

V12

V11

V10

V9

VREG

/VMEN

CS

C_REG

R_CELL

C_VDD

C_CELL

/DOFF

VNTC 26

TSNS 25

CDOV 24

CDUV 23

R_T

R_NTC

7 V8

8 V7

9 V6

C_OV

C_UV

CDLV

22

21

C_DLY

V5

10

11

12

13

14

15

VMON

R_PR

V4

PSENSE 20

V3

RSENSE

C_FET

19

18

17

16

V2

V1

ISENSE

D_FET

C_IS

GND

R_G

PACK(-)

CHG(-)

R_ISIN

R_G

R_IS

R_GS

The wire length indicated by a dotted line should be minimized, because the voltage drop

due to wire resistance may affect the current detection accuracy.

■ Recommended Values for External Components

Recommended

value

Recommended

value

Component

R_IS

R_ISIN

R_G,R_PR

R_GS

R_T

R_NTC

3mΩ

R_VDD

C_VDD

R_CEL

C_CEL

C_REG

C_IS

510Ω

1kΩ

10kΩ to 47kΩ

1MΩ

4.7kΩ

10kΩ, B3435

10µF or mode

1kΩ to 10kΩ

0.1µF or more

1µF or more

10nF

C_DLY

1nF to 10nF

(Note) This circuit example and the recommended values of external components are not always warranted.

Evaluation on customer’s application is required and select circuit and parts depend on customer’s

application.

32/36

FEDL5245-05

ML5245

● Application Circuit Example2 (13 cell, charge / discharge path is separated)

If battery discharging is enabled in the charging state, charge FET’s protection function from overheating

should be disabled by creating new code of the ML5245. Refer to the Protection from FET overheating in

page28 for detail.

PACK(+)

CHG(+)

MCU Power Supply

R_VDD

1

2

3

4

30

29

28

27

26

VDD

V13

V12

V11

VREG

/VMEN

CS

R_VMEN

C_REG

R_CELL

C_VDD

C_CELL

/DOFF

VNTC

5 V10

R_T

R_NTC

MCU

6

7

V9

V8

TSNS 25

CDOV 24

CDUV 23

C_OV

8 V7

9 V6

C_UV

CDLY

22

21

C_DLY

V5

10

11

12

13

14

15

VMON

R_PS

R_RS

V4

PSENSE 20

V3

RSENSE

C_FET

19

18

17

16

V2

V1

ISENSE

D_FET

C_IS

GND

R_ISIN

R_G

PACK(-)

CHG(-)

R_IS

R_G

The wire length indicated by a dotted line should be

minimized, because the voltage drop due to wire resistance

may affect the current detection accuracy.

R_GS

■ Recommended Values for External Components

Recommended

Value

Recommended

Value

Component

R_IS

R_ISIN

R_G,R_PS, R_RS

R_GS

3mΩ

R_VDD

C_VDD

R_CEL

C_CEL

C_REG

C_IS

510Ω

1kΩ

10kΩ to 47kΩ

1MΩ

4.7kΩ

10kΩ, B3435

100kΩ

10µF or more

1kΩ to 10kΩ

0.1µF or more

1µF or more

10nF

R_T

R_NTC

R_VMEN

C_DLY

1nF to 10nF

(Note) This circuit example and the recommended values of external components are not always warranted.

Evaluation on customer’s application is required and select circuit and parts depend on customer’s

application.

33/36

FEDL5245-05

ML5245

■ Package Dimensions

Caution regarding surface mount type packages

Surface mount type packages are susceptible to heat applied in solder reflow and moisture absorbed during

storage. Please contact your local ROHM sales representative for recommended mounting conditions (reflow

sequence, temperature and cycles) and storage environment.

34/36

FEDL5245-05

ML5245

■ Revision History

Page

Before

revision revision

Document No.

Issue date

Revision description

After

FEDL5245-01

FEDL5245-02

2017.10.12

2017.12.1

-

V1 issued.

In the Cell voltage monitor output characteristics, the

VMON output voltage at 25°C is added.

PSENSE pin status in undervoltage is modified from

“No change” to “Pull up”.

9

FEDL5245-03

FEDL5245-04

2019.08.22

2019.09.02

28

14

28

14

Timing chart: Charge overcurrent detection and

recovery from charge overcurrent state by charger

removal, mistype is corrected.

FEDL5245-05

2020.12.01

-

Changed Company name

36

Changed “Notes”

35/36

FEDL5245-05

ML5245

Notes

1) The information contained herein is subject to change without notice.

2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals,

application notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating

conditions, etc.) are within the ranges specified. LAPIS Technology disclaims any and all liability for any

malfunctions, failure or accident arising out of or in connection with the use of LAPIS Technology Products

outside of such usage conditions specified ranges, or without observing precautions. Even if it is used within such

usage conditions specified ranges, semiconductors can break down and malfunction due to various factors.

Therefore, in order to prevent personal injury, fire or the other damage from break down or malfunction of LAPIS

Technology Products, please take safety at your own risk measures such as complying with the derating

characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe

procedures. You are responsible for evaluating the safety of the final products or systems manufactured by you.

3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the

standard operation of semiconductor products and application examples. You are fully responsible for the

incorporation or any other use of the circuits, software, and information in the design of your product or system.

And the peripheral conditions must be taken into account when designing circuits for mass production. LAPIS

Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising

from the use of these circuits, software, and other related information.

4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS

Technology or any third party with respect to LAPIS Technology Products or the information contained in this

document (including but not limited to, the Product data, drawings, charts, programs, algorithms, and application

examples、etc.). Therefore LAPIS Technology shall have no responsibility whatsoever for any dispute,

concerning such rights owned by third parties, arising out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer

systems, gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our

Products in applications requiring a high degree of reliability (as exemplified below), please be sure to contact a

LAPIS Technology representative and must obtain written agreement: transportation equipment (cars, ships,

trains, etc.), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical

systems, servers, solar cells, and power transmission systems, etc. LAPIS Technology disclaims any and all

liability for any losses and damages incurred by you or third parties arising by using the Product for purposes not

intended by us. Do not use our Products in applications requiring extremely high reliability, such as aerospace

equipment, nuclear power control systems, and submarine repeaters, etc.

6) The Products specified in this document are not designed to be radiation tolerant.

7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document.

However, LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall

have no responsibility for any damages arising from any inaccuracy or misprint of such information.

8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS

Directive. LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance

with any applicable laws or regulations.

9) When providing our Products and technologies contained in this document to other countries, you must abide by

the procedures and provisions stipulated in all applicable export laws and regulations, including without

limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act..

10) Please contact a ROHM sales office if you have any questions regarding the information contained in this

document or LAPIS Technology's Products.

11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS

Technology.

(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.

2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan

https://www.lapis-tech.com/en/

36/36

型号	制造商	描述	价格	文档
ML5245-001MB	ROHM	cell voltage monitoring<br>overvoltage, undervoltage detection<br>charge/discharge overcurrent det	获取价格
ML5245-003MB	ROHM	cell voltage monitoring<br>overvoltage, undervoltage detection<br>charge/discharge overcurrent det	获取价格
ML5245-004MB	ROHM	cell voltage monitoring<br>overvoltage, undervoltage detection<br>charge/discharge overcurrent det	获取价格
ML5245-005MB	ROHM	cell voltage monitoring<br>overvoltage, undervoltage detection<br>charge/discharge overcurrent det	获取价格
ML5245-101MB	ROHM	cell voltage monitoring<br>overvoltage, undervoltage detection<br>charge/discharge overcurrent det	获取价格
ML5248	ROHM	电池电压、电流和温度测量短路电流检测内置高边NMOS-FET驱动器MCU接口：I2C内置电池均衡开关内置外部微控制器用电源	获取价格
ML5248MB	ROHM	cell voltage, current, and temperature measurement <br>short current detection<br>High-side NMOS FET driver built-in <br>microcontroller Interface : I<sup>2</sup>C <br>cell balance switch built-in <br>Built-in regulator for external microcontroller	获取价格
ML524PYA	COILCRAFT	High Reliability Power Inductors	获取价格
ML524PYA102MLZ	COILCRAFT	High Reliability Power Inductors	获取价格
ML524PYA103MLZ	COILCRAFT	High Reliability Power Inductors	获取价格

ML5245

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