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TPSM863252

更新时间：2025-06-29 05:39:59

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描述：3-V to 17-V input voltage, 3-A Eco-mode synchronous buck module

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TPSM863252 概述

3-V to 17-V input voltage, 3-A Eco-mode synchronous buck module

TPSM863252 数据手册

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TPSM863252, TPSM863257

ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

TPSM86325x 采用QFN 封装的3V 至17V 输入、3A 同步降压模块

1 特性

3 说明

• 特性和配置适用于各种应用

– 3V 至17V 输入电压范围

TPSM86325x 是一款输入电压范围为 3V 至 17V 的简

单易用型高效高功率密度同步降压模块，支持高达 3A

的连续电流。

– TPSM863252 的输出电压范围为0.6V 至10V

– TPSM863257 的输出电压范围为0.6V 至5.5V

– 0.6V 基准电压

– 25°C 时，基准精度为±1%

– 在-40°C 至125°C 温度范围内，基准精度为

±1.5%

– 集成式55mΩ和24mΩMOSFET

– 100 µA 低静态电流

– 1.2MHz 开关频率

TPSM86325x 采用 D-CAP3 控制模式提供快速瞬态响

应并支持低 ESR 输出电容器，无需外部补偿。该器件

可支持以高达95% 的占空比运行。

TPSM863252 在 Eco-mode 下运行，可在轻负载时保

持高效率。TPSM863257 在 FCCM 模式下运行，可在

所有负载条件下保持相同的频率和较低的输出纹波。该

器件集成了全面的断续模式 OVP、OCP、UVLO、

OTP 和UVP 保护。

– 以最大95 % 的高占空比运行

– 精密EN 阈值电压

该器件采用 QFN 封装。额定结温范围为 -40°C 至

125°C。

– 1.6 ms 固定软启动时间（典型值）

• 解决方案尺寸小巧且易于使用

– 轻负载下TPSM863252 采用Eco-mode，

TPSM863257 采用FCCM 模式

– 快速瞬态D-CAP3^™控制模式

– 通过集成自举电容器和电感器轻松布局

– 支持带预偏置输出电压的启动

– 开漏电源正常状态指示器

封装信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

(2)

TPSM863252

TPSM863257

RDX（QFN-FCMOD，

7）

4.00 mm x 3.30 mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

(2) 封装尺寸（长x 宽）为标称值，并包括引脚（如适用）。

– 非锁存OV、OT 和UVLO 保护

– UV 保护的断续模式

– 逐周期OC 和NOC 保护

– -40°C 至125°C 的工作结温范围

– 3.3mm x 4mm x 2mm QFN 封装

器件信息

模式

器件型号

输出电压

TPSM863252

ECO

0.6 V 至10 V

0.6V 至5.5V

TPSM863257

FCCM

2 应用

• 商用网络和服务器PSU

• 其他交流/直流适配器/PSU

• 工厂自动化和控制

• 测试和测量

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

V_OUT

VIN

VOUT

VIN

Cin

R_FBT

Cout

PGND

R_FBB

TPSM863252_1.05Vout

TPSM863252_5Vout

TPSM863257_1.05Vout

TPSM863257_5Vout

简化原理图

0.001

0.01

0.1

Iout (A)

TPSM86325x 在V_IN= 12V 时的效率

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLUSF51

TPSM863252, TPSM863257

ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

www.ti.com.cn

Table of Contents

7.3 Feature Description...................................................11

7.4 Device Functional Modes..........................................13

8 Application and Implementation..................................14

8.1 Application Information............................................. 14

8.2 Typical Application.................................................... 14

8.3 Power Supply Recommendations.............................18

8.4 Layout....................................................................... 19

9 Device and Documentation Support............................20

9.1 接收文档更新通知..................................................... 20

9.2 支持资源....................................................................20

9.3 Trademarks...............................................................20

9.4 静电放电警告............................................................ 20

9.5 术语表....................................................................... 20

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................4

6.5 Electrical Characteristics.............................................5

6.6 Typical Characteristics................................................7

7 Detailed Description......................................................10

7.1 Overview...................................................................10

7.2 Functional Block Diagram.........................................10

Information.................................................................... 20

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (March 2023) to Revision A (June 2023)

Page

• 将文档状态从“预告信息”更改为“量产数据”................................................................................................1

English Data Sheet: SLUSF51

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TPSM863252, TPSM863257

ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

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5 Pin Configuration and Functions

FB EN PG

VIN

PGND

VOUT

图5-1. TPSM863252x RDX Package, 7-Pin QFN-FCMOD (Top View)

表5-1. Pin Functions

Type⁽¹⁾

Description

Name

VIN

NO.

Input voltage supply pin. Connect the input decoupling capacitors between VIN and GND.

Switch pin of the power stage. Do not connect, leave floating.

Output connection. Connect recommended output capacitance from VOUT to PGND.

Power ground connection

VOUT

PGND

Power-good open drain output. PG pin can be floating.

Enable pin of buck converter. Drive EN high to turn on the converter; drive EN low to turn off

the converter. Internal pulldown to GND by a resister.

Converter feedback input. Connect to the center tap of the resistor divider between output

voltage and ground.

(1) A = Analog, P = Power, G = Ground

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English Data Sheet: SLUSF51

TPSM863252, TPSM863257

ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

Input voltage

Output voltage

VIN

FB, EN, PG

GND

0.3

VOUT(TPSM863252)

VOUT(TPSM863257)

Mil-STD-883D, Method 2002.3, 1 ms, 1/2 sine,

mounted

Mechanical shock

1500

Mechanical vibration

Mil-STD-883D, Method 2007.2, 20 to 2000 Hz

Operating Junction Temperature

Range, TJ

150

°C

–40

–55

Storage temperature, Tstg

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

± 2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per ANSI/ESDA/JEDEC

JS-002⁽²⁾

± 500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

Input voltage

Output voltage

Output current

T_J

VIN

FB, EN, PG

5.5

0.1

–0.1

GND

VOUT(TPSM863252)

VOUT(TPSM863257)

5.5

Operating junction temperature

Storage temperature

125

150

°C

–40

Tstg

6.4 Thermal Information

TPSM86325x

THERMAL METRIC⁽¹⁾

RDX

7 PINS

61.3

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_{θJA_effective}

R_θJC(top)

Junction-to-ambient thermal resistance on EVM board

Junction-to-case (top) thermal resistance

40⁽²⁾

60.8

English Data Sheet: SLUSF51

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ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

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6.4 Thermal Information (continued)

TPSM86325x

THERMAL METRIC⁽¹⁾

RDX

7 PINS

20.0

7.5

UNIT

R_θJB

Ψ_JT

Junction-to-board thermal resistance

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Y_JB

19.2

N/A

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) This RθJA_effective is tested on TPSM863252EVM board (4 layer board, copper thickness of top and bottom layer are 2 oz, and

copper thickness of internal GND is 1 oz) at VIN = 12 V, VOUT = 5 V, IOUT = 3 A , TA = 25^oC.

6.5 Electrical Characteristics

Over operating T_J= –40⁰C - 125⁰C, V_VIN= 12 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY VOLTAGE

VIN

I_VIN

Input voltage range

VIN Supply Current

VIN Shutdown Current

VIN

No load, V_EN= 5 V, non-switching, PSM

version

100

µA

No load, V_EN= 5 V, non-switching, FCCM

version

370

µA

I_INSDN

UVLO

No load, V_EN= 0 V

VIN Undervoltage Lockout

Wake up VIN voltage

Shut down VIN voltage

Hysteresis VIN voltage

2.8

2.6

2.9

2.7

3.0

2.8

200

FEEDBACK VOLTAGE

VFB

FB voltage

T_J= 25°C

594

591

600

606

609

VFB

T_J= –40°C to 125°C

MOSFET

T_J= 25°C, V_VIN≥5 V

T_J= 25°C, V_VIN= 3 V ⁽¹⁾

T_J= 25°C,V_VIN≥5 V

T_J= 25°C, V_VIN= 3 V

mΩ

R_DS

High-side MOSFET Rds(on)

Low-side MOSFET Rds(on)

(ON)HI

R_DS

(ON)LO

DUTY CYCLE and FREQUENCY CONTROL

F_SW

Switching Frequency

Minimum Off-time

T_J= 25°C, V_VOUT= 3.3 V

V_FB= 0.5 V

1.2

110

MHz

T_OFF(MIN)

(1)

T_ON(MIN)Minimum On-time

CURRENT LIMIT

I_{OCL_LS}

I_NOCL

Over Current threshold

Valley current set point

3.1

1.5

4.1

2.0

5.1

2.5

Negative Over Current threshold

LOGIC THRESHOLD

V_EN(ON)EN Threshold High-level

V_EN(OFF)EN Threshold Low-level

1.15

0.90

1.20

1.00

200

1.25

1.10

V_ENHYS

EN Hystersis

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English Data Sheet: SLUSF51

TPSM863252, TPSM863257

ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

www.ti.com.cn

6.5 Electrical Characteristics (continued)

Over operating T_J= –40⁰C - 125⁰C, V_VIN= 12 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EN Pull down resister

MΩ

REN1

OUTPUT DISCHARGE and SOFT START

t_SSInternal Soft-start Time

OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION

1.6

V_OVP

OVP Trip Threshold

OVP Prop deglitch

UVP Trip Threshold

UVP Prop deglitch

110

115

120

t_OVPDLY

V_UVP

t_UVPDLY

220

Output Hiccup enable delay relative to

SS time

t_UVPEN

UVP detect

PGOOD

TPGDLY PG Start-up Delay

VPGTH PG Threshold

PG from low to high

PG from high to low

VFB falling (fault)

VFB rising (good)

VFB rising (fault)

VFB falling (good)

IOL = 4 mA

110

105

115

110

120

115

0.4

VPG_L

IPGLK

PG Sink Current Capability

PG Leak Current

VPGOOD = 5.5 V

THERMAL PROTECTION

(1)

T_OTP

OTP Trip Threshold

OTP Hysteresis

155

°C

T_OTPHSY

(1)

(1) Specified by design

English Data Sheet: SLUSF51

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ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

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6.6 Typical Characteristics

T_J= –40°C to 125°C, V_IN= 12 V (unless otherwise noted)

120

480

440

400

360

320

280

240

110

100

-40

-20

100 120 140

-40

-20

100 120 140

Junction Temperature (^oC)

图6-1. TPSM863252 Quiescent Current

图6-2. TPSM863257 Quiescent Current

1.22

1.11

1.08

1.05

1.02

0.99

0.96

0.93

1.21

1.2

1.19

1.18

1.17

1.16

-40

-20

100 120 140

-40

-20

100 120 140

Junction Temperature (^oC)

图6-3. Enable On Threshold Voltage

图6-4. Enable Off Threshold Voltage

-40

-20

100 120 140

-40

-20

100 120 140

Junction Temperature (C)

图6-5. Low-Side R_DS(ON)

图6-6. High-Side R_DS(ON)

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English Data Sheet: SLUSF51

TPSM863252, TPSM863257

ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

www.ti.com.cn

6.6 Typical Characteristics (continued)

T_J= –40°C to 125°C, V_IN= 12 V (unless otherwise noted)

0.603

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

0.602

0.601

0.6

0.599

Vout = 1.05 V

Vout = 3.3 V

Vout = 5 V

0.598

-40

-20

100 120 140

0.001

0.01

0.1

Iout (A)

Junction Temperature (^oC)

图6-7. VREF Voltage

图6-8. TPSM863252 Efficiency at 0.6 V_OUT

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

90%

80%

70%

60%

50%

40%

30%

20%

10%

Vout = 1.05 V

Vout = 3.3 V

Vout = 5 V

Vin = 3.3 V

Vin = 5 V

Vin = 12 V

0.001

0.01

0.1

Iout (A)

0.001

0.01

0.1

Iout (A)

图6-9. TPSM863257 Efficiency at 0.6 V_OUT

图6-10. TPSM863252 Efficiency at 1.05 V_OUT

100%

90%

80%

70%

60%

50%

40%

30%

Vin = 5 V

Vin = 12 V

0.001

0.01

0.1

Iout (A)

图6-11. TPSM863257 Efficiency at 1.05 V_OUT

图6-12. TPSM863252 Efficiency at 3.3 V_OUT

English Data Sheet: SLUSF51

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ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

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6.6 Typical Characteristics (continued)

T_J= –40°C to 125°C, V_IN= 12 V (unless otherwise noted)

100%

90%

80%

70%

60%

50%

40%

30%

20%

0.9

0.8

0.7

0.6

0.5

0.4

Vin = 5 V

Vin = 12 V

10%

Vin = 6 V

Vin = 12 V

0.001

0.01

0.1

Iout (A)

0.001

0.01

0.1

Iout (A)

图6-13. TPSM863257 Efficiency at 3.3 V_OUT

图6-14. TPSM863252 Efficiency at 5 V_OUT

100%

90%

80%

70%

60%

50%

40%

30%

20%

10%

2500

2000

1500

1000

500

Vout = 0.6 V

Vout = 1.05 V

Vout = 3.3 V

Vout = 5 V

Vout = 10 V

Vin = 6 V

Vin = 12 V

0.001

0.01

0.1

Iout (A)

0.001

0.01

0.1

Iout (A)

图6-15. TPSM863257 Efficiency at 5 V_OUT

图6-16. TPSM863252 Frequency vs Loading at 12-V Input

Voltage

2400

2100

1800

1500

1200

900

600

Vout = 0.6 V

Vout = 1.05 V

Vout = 3.3 V

Vout = 5 V

300

0.5

1.5

2.5

Iout (A)

图6-17. TPSM863257 Frequency vs Loading at 12-V Input Voltage

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English Data Sheet: SLUSF51

TPSM863252, TPSM863257

ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPSM86325x is a 3-A, integrated, FET, synchronous buck module that operates from 3-V to 17-V input

voltage and TPSM863252 output voltage range is 0.6 V to 10 V. TPSM863257 output voltage range is 0.6 V to

5.5 V. The device employs a D-CAP3 control mode that provides fast transient response with no external

compensation components and an accurate feedback voltage. The proprietary D-CAP3 control mode enables

low external component count, ease of design, and optimization of the power design for cost, size, and

efficiency. The topology provides a seamless transition between CCM operating mode at higher load condition

and DCM operation mode at lighter load condition.

The Eco-mode version allows the TPSM863252 to maintain high efficiency at light load. The FCCM version

allows the TPSM863257 to maintain a fixed switching frequency and lower voltage output ripple. The

TPSM86325x is able to adapt to both low equivalent series resistance (ESR) output capacitors such as

POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors.

7.2 Functional Block Diagram

UV threshold

VIN

OV threshold

LDO

VREF

VREGOK

2.9 V /

2.7 V

Internal

VCC

PWM

Control Logic

Internal

BST

VIN

Internal

Compensa on

ꢀꢁOn/Off time

ꢀꢁMinimum On/Off

ꢀꢁLight load

Internal SS

ꢀꢁOCP/OVP/UVP/NOC/

XCON

TSD

VOUT

ꢀꢁSoft-Start

Clock

PGND

EN Threshold

OCL

AGND

THOK

155°C /20°C

NOCL

AGND

English Data Sheet: SLUSF51

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7.3 Feature Description

7.3.1 PWM Operation and D-CAP3^™Control Mode

The main control loop of the buck is an adaptive on-time pulse width modulation (PWM) controller that supports

a proprietary D-CAP3 control mode. The D-CAP3 control mode combines adaptive on-time control with an

internal compensation circuit for pseudo-fixed frequency and low external component count configuration with

both low-ESR and ceramic output capacitors. The device is stable even with virtually no ripple at the output. The

TPSM86325x also includes an error amplifier that makes the output voltage very accurate.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after an internal

one-shot timer expires. This one-shot duration is set proportional to the output voltage, V_OUT, and is inversely

proportional to the converter input voltage, V_IN, to maintain a pseudo-fixed frequency over the input voltage

range, hence, it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is

turned on again when the feedback voltage falls below the reference voltage. An internal ripple generation circuit

is added to reference voltage to emulate the output ripple, enabling the use of very low-ESR output capacitors

such as multi-layered ceramic caps (MLCC). No external current sense network or loop compensation is

required for D-CAP3 control mode.

7.3.2 Eco-mode Control

The TPSM86325x is designed with advanced Eco-mode to maintain high light load efficiency. As the output

current decreases from heavy load condition, the inductor current is also reduced and eventually comes to a

point that its rippled valley touches zero level, which is the boundary between continuous conduction and

discontinuous conduction mode. The rectifying MOSFET is turned off when the zero inductor current is detected.

As the load current further decreases, the converter runs into discontinuous conduction mode. The on time is

kept almost the same as it was in continuous conduction mode so that it takes longer time to discharge the

output capacitor with smaller load current to the level of the reference voltage. This event makes the switching

frequency lower, proportional to the load current, and keeps the light load efficiency high. Use the below

equation to calculate the transition point to the light load operation I_OUT(LL)current. The typical inductance is 1

uH.

(V - V_OUT) ì V_OUT

I_OUT(LL)

2 ì L ì f_SW

(1)

7.3.3 Soft Start and Prebiased Soft Start

The TPSM86325x has an internal fixed 1.6-ms soft-start time. The EN default status is low. When the EN pin

becomes high, the internal soft-start function begins ramping up the reference voltage to the PWM comparator.

If the output capacitor is prebiased at start-up, the devices initiate switching and start ramping up only after the

internal reference voltage becomes higher than the feedback voltage, V_FB. This scheme makes sure that the

converter ramps up smoothly into the regulation point.

7.3.4 Overvoltage Protection

The TPSM86325x has the overvoltage protection feature. When the output voltage becomes higher than the

OVP threshold, the OVP is triggered with a 24-μs deglitch time. Both the high-side MOSFET and the low-side

MOSFET drivers are turned off. When the overvoltage condition is removed, the device returns to switching.

7.3.5 Frequency

TPSM86325x default frequency is about 1.2 MHz. When output voltage is higher than 3.6 V and the ration of

output voltage to input voltage < 0.62 (the hysteresis is 0.04), frequency changes to 2 MHz to decrease output

voltage ripple. A summary is as below table.

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English Data Sheet: SLUSF51

TPSM863252, TPSM863257

ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

www.ti.com.cn

表7-1. TPSM86325x Frequency at CCM

Conditions

Frequency

1.2 MHz

2 MHz

Output voltage < 3.6 V

Duty ≥0.62

Output voltage ≥3.6 V

Duty < 0.62

7.3.6 Large Duty Operation

The TPSM86325x can support large duty operations up to 95% by smoothly dropping down the switching

frequency. When V_IN/ V_OUT< 1.6 and V_FBis lower than internal V_REF, the switching frequency is allowed to

smoothly drop to make t_ONextended to implement the large duty operation and keep output voltage. The

minimum switching frequency is limited to approximately 600 kHz.

7.3.7 Current Protection and Undervoltage Protection

The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley detect control circuit. The switch

current is monitored during the off state by measuring the low-side FET drain-to-source voltage. This voltage is

proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated.

During the on time of the high-side FET switch, the switch current increases at a linear rate determined by the

following:

• V_IN

• V_OUT

• On time

• Output inductor value

During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch

current is the load current, I_OUT. If the monitored valley current is above the OCL level, the converter maintains a

low-side FET on and delays the creation of a new set pulse, even the voltage feedback loop requires one, until

the current level becomes OCL level or lower. In subsequent switching cycles, the on time is set to a fixed value

and the current is monitored in the same manner.

There are some important considerations for this type of overcurrent protection. The load current is higher than

the overcurrent threshold by one half of the peak-to-peak inductor ripple current. Also, when the current is being

limited, the output voltage tends to fall as the demanded load current can be higher than the current available

from the converter, which can cause the output voltage to fall. When the FB voltage falls below the UVP

threshold voltage, the UVP comparator detects it and the device shuts down after the UVP delay time (typically

220 µs) and restarts after the hiccup wait time (typically 14 ms).

When the overcurrent condition is removed, the output voltage returns to the regulated value.

The TPSM863257 is a FCCM mode part. In this mode, the device has negative inductor current at light loading.

The device has NOC (negative overcurrent) protection to avoid too large negative current. NOC protection

detects the valley of inductor current. When the valley value of inductor current exceeds the NOC threshold, the

IC turns off the low side then turns on the high side. When the NOC condition is removed, the device returns to

normal switching.

7.3.8 Undervoltage Lockout (UVLO) Protection

UVLO protection monitors the internal regulator voltage. When the voltage is lower than UVLO threshold voltage,

the device is shut off. This protection is a non-latch protection.

7.3.9 Thermal Shutdown

The device monitors the temperature of itself. If the temperature exceeds the threshold value, the device is shut

off. This protection is a non-latch protection.

English Data Sheet: SLUSF51

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7.4 Device Functional Modes

7.4.1 Eco-mode Operation

The TPSM863252 operates in Eco-mode, which maintains high efficiency at light loading. As the output current

decreases from heavy load conditions, the inductor current is also reduced and eventually comes to a point

where the rippled valley touches zero level, which is the boundary between continuous conduction and

discontinuous conduction mode. The rectifying MOSFET is turned off when the zero inductor current is detected.

As the load current further decreases, the converter runs into discontinuous conduction mode. The on time is

kept almost the same as it was in continuous conduction mode so that it takes longer time to discharge the

output capacitor with smaller load current to the level of the reference voltage. This event makes the switching

frequency lower, proportional to the load current, and keeps the light load efficiency high.

7.4.2 FCCM Mode Operation

The TPSM863257 operates in forced CCM (FCCM) mode, which keeps the converter operating in continuous

current mode during light load conditions and allows the inductor current to become negative. During FCCM

mode, the switching frequency is maintained at an almost constant level over the entire load range, which is

suitable for applications requiring tight control of the switching frequency and output voltage ripple at the cost of

lower efficiency under light load.

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The device is a typical buck DC/DC converter that is typically used to convert a higher DC voltage to a lower DC

voltage with a maximum available output current of 3 A. The following design procedure can be used to select

component values for TPSM86325x. Alternately, the WEBENCH^®Power Designer software can be used to

generate a complete design. The WEBENCH Power Designer software uses an iterative design procedure and

accesses a comprehensive database of components when generating a design. This section presents a

simplified discussion of the design process.

8.2 Typical Application

The application schematic in 图 8-1 was developed to meet the requirements in 表 8-1. This circuit is available

as the evaluation module (EVM). The sections provide the design procedure.

图8-1 shows the 12-V input, 1.05-V output converter schematic.

Not install

图8-1. Schematic

8.2.1 Design Requirements

表8-1 shows the design parameters for this application.

表8-1. Design Parameters

Parameter

Output voltage

Output current

Conditions

MIN

TYP

1.05

MAX

Unit

V_OUT

I_OUT

0.3-A –2.7-A load step, 1-A/μs

slew rate

Transient response

±3% × V_OUT

ΔV_OUT

V_IN

Input voltage

4.5

V_OUT(ripple)

T_A

Output voltage ripple

Ambient temperature

CCM condition

°C

English Data Sheet: SLUSF51

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8.2.2 Detailed Design Procedure

8.2.2.1 Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the FB pin. TI recommends using 1%

tolerance or better divider resistors. Start by using 方程式2 to calculate V_OUT

To improve efficiency at very light loads, consider using larger value resistors. If the values are too high, the

regulator is more susceptible to noise and voltage errors from the FB input current are noticeable. Use a 10-kΩ

resistor for R₆to start the design.

= 0 . 6 × 1 +

(2)

OUT

8.2.2.2 Output Filter Selection

TPSM86325x integrates a 1-uH inductor. TI suggests to use below output cap to make loop stable. CFF range is

suggested to use 10 pF to 100 pF.

表8-2. Recommended Component Values

Minimum C_OUT

Typical C_OUT

Maximum C_OUT

Output Voltage

(V)

CFF (pF)

R5 (kΩ)

R6 (kΩ)

(μF)

0.8

1.05

2.5

3.3

7.5

10.0

30.0

100

—

95.0

135.0

220.0

470.0

100

The capacitor value and ESR determines the amount of output voltage ripple. The TPSM86325x are intended for

use with ceramic or other low-ESR capacitors. Use 方程式3 to determine the required RMS current rating for the

output capacitor.

V_OUTì V - V_OUT

(

)

I_CO(RMS)

12 ì V ì L_Oì f_SW

(3)

For this design, one MuRata GRM21BR61A226ME44L 22-µF output capacitor are used. The typical ESR is 2

mΩeach.

8.2.2.3 Input Capacitor Selection

The TPSM86325x requires an input decoupling capacitor and a bulk capacitor is needed depending on the

application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. TI recommends an

additional 0.1-µF capacitor from the VIN pin to ground to provide high frequency filtering. The capacitor voltage

rating must be greater than the maximum input voltage.

8.2.2.4 Enable Circuit

The EN pin controls the turn-on and turn-off of the device. When EN pin voltage is above the turn-on threshold,

the device starts switching and when the EN pin voltage falls below the turn-off threshold IC stops switching. The

default status is low. There is a 2-MΩinternal pulldown resister in the EN pin.

EN can be controlled by a typical divider resister circuit from Vin or by a voltage of lower than 5.5 V.

Because there is a 2-MΩ internal pulldown resister in the EN pin, TPSM86325x also supports to only connect a

top resister from VIN pin to EN pin. EN voltage is got by the divide net of top resister and 2 MΩ. EN voltage

cannot be allowed to be over 6 V.

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8.2.3 Application Curves

The following data is tested with V_IN= 12 V, V_OUT= 1.05 V, T_A= 25°C, unless otherwise specified.

0.8%

0.6%

0.4%

0.2%

0.8%

0.6%

0.4%

0.2%

Vin = 3.3 V

Vin = 5 V

Vin = 12 V

Vin = 17 V

Vin = 3.3 V

Vin = 5 V

Vin = 12 V

Vin = 17 V

-0.2%

-0.4%

-0.6%

-0.8%

-1%

-0.2%

-0.4%

-0.6%

-0.8%

-1%

0.5

1.5

2.5

0.5

1.5

2.5

Iout (A)

图8-2. TPSM863252 Load Regulation vs Loading

图8-3. TPSM863257 Load Regulation vs Loading

0.8%

0.6%

0.4%

0.2%

0.8%

0.6%

0.4%

0.2%

-0.2%

-0.4%

-0.6%

-0.8%

-1%

-0.2%

-0.4%

-0.6%

-0.8%

-1%

Vin (V)

图8-4. TPSM863252 Line Regulation vs V_INat 3-A

图8-5. TPSM863257 Line Regulation vs V_INat 3-A

Vout = 20mV/div (AC coupled)

SW = 5V/div

20us/div

1us/div

图8-6. TPSM863252 Output Voltage Ripple With

图8-7. TPSM863257 Output Voltage Ripple With

0.01-A Loading

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Vout = 50mV/div (AC coupled)

Vout = 20mV/div (AC coupled)

SW = 5V/div

Iout = 2A/div

200us/div

1us/div

图8-9. TPSM863252 Transient Response With 0.3 A

图8-8. TPSM86325x Output Voltage Ripple With 3-

to 2.7 A

A Loading

Vout = 50mV/div (AC coupled)

Iout = 2A/div

200us/div

图8-10. TPSM863252 Transient Response With 0.1 图8-11. TPSM863257 Transient Response With 0.3

A to 3 A

A to 2.7 A

Vin = 5V/div

Vout = 50mV/div (AC coupled)

EN = 2V/div

Iout = 2A/div

Vout = 500mV/div

200us/div

2ms/div

图8-12. TPSM863257 Transient Response With 0.1

图8-13. Start-Up Through EN, I_OUT= 3 A

A to 3 A

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Vin = 10V/div

EN = 2V/div

Vin = 5V/div

EN = 5V/div

Vout = 500mV/div

2ms/div

图8-14. Shutdown Through EN, I_OUT= 3 A

图8-15. Start-Up with V_INRising, I_OUT= 3 A

Vout = 500mV/div

Vin = 5V/div

EN = 5V/div

SW = 10V/div

Vout = 500mV/div

IL = 5A/div

10ms/div

100us/div

图8-16. Shutdown with V_INFalling, I_OUT= 3-A

图8-17. TPSM863252 Normal Operation to Output

Hard Short

Vout = 500mV/div

Vout = 1V/div

SW = 10V/div

IL = 5A/div

100us/div

10ms/div

图8-18. TPSM863257 Normal Operation to Output

图8-19. Output Hard Short Hiccup

Hard Short

8.3 Power Supply Recommendations

The TPSM86325x are designed to operate from input supply voltages in the range of 3 V to 17 V. Buck

converters require the input voltage to be higher than the output voltage for proper operation.

English Data Sheet: SLUSF51

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8.4 Layout

8.4.1 Layout Guidelines

• Make sure the VIN and GND traces are as wide as possible to reduce trace impedance. The wide areas are

also an advantage from the view point of heat dissipation.

• Place the input capacitor and output capacitor as close to the device as possible to minimize trace

impedance.

• Provide sufficient vias for the input capacitor and output capacitor.

• Connect a separate VOUT path to the upper feedback resistor.

• Place a voltage feedback loop away from the high-voltage switching trace, and preferably has ground shield.

• Make sure the trace of the FB node is as small as possible to avoid noise coupling.

• Make sure the GND trace between the output capacitor and the GND pin are as wide as possible to minimize

its trace impedance.

8.4.2 Layout Example

R_FBB

R_FBT

EN Control

GND

VIN

PGND

C_IN

C_OUT

VOUT

GND

VOUT

VIA (Connected to GND plane at bottom layer)

The line in the bottom layer

图8-20. Layout Example

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English Data Sheet: SLUSF51

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ZHCSR83A –MARCH 2023 –REVISED JUNE 2023

www.ti.com.cn

9 Device and Documentation Support

9.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.3 Trademarks

D-CAP3^™and TI E2E^™are trademarks of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.4 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

9.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

English Data Sheet: SLUSF51

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PACKAGE OPTION ADDENDUM

www.ti.com

18-Jun-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PTPSM863252RDXR

PTPSM863257RDXR

TPSM863252RDXR

ACTIVE QFN-FCMOD

RDX

3000

TBD

Call TI

-40 to 125

Samples

Call TI

RoHS (In

Work) & Green

(In Work)

Level-3-260C-168 HR

863252

TPSM863257RDXR

ACTIVE QFN-FCMOD

RDX

3000

RoHS (In

Work) & Green

(In Work)

Level-3-260C-168 HR

-40 to 125

863257

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Jun-2023

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE OUTLINE

RDX0007A

QFN-FCMOD - 2.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3.3

PIN 1 INDEX AREA

2.1

1.9

SEATING PLANE

0.08 C

0.05

0.00

1.3

1.1

(0.2) TYP

(0.13)

15X (0.18)

12X (0.25)

2X (1.415)

2X (0.915)

2X 0.675

2X (0.415)

2.25

2.15

0.1

C A B

0.05

1.125

1.025

0.000 PKG

2X (0.085)

0.1

C A B

0.05

2X (0.24)

2X (45 X 0.377)

2X (1)

0.47

0.37

2X 1.3125

2X (1.5)

16X (0.2)

0.5

0.3

PIN 1 ID

(45 X 0.15)

0.625

0.27

0.17

0.525

1.445

1.245

0.1

0.05

C A B

2X 0.5

4229109/A 10/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

RDX0007A

QFN-FCMOD - 2.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3X (0.6)

3X (0.22)

(1.9)

2X (1.85)

2X (1.572)

12X (0.25)

2X (1.5)

2X (1.195)

2X (1)

(0.62)

KEEP OUT

AREA

(1.295)

2X (0.775)

(0.4) KEEP OUT AREA

METAL UNDER

SOLDER MASK

TYP

2X (0.425)

2X (0.085)

0.000 PKG

4X (0.165)

2X (0.415)

4X (0.665)

2X (0.915)

4X (1.165)

2X (1.415)

SOLDER MASK

OPENING

TYP

(R0.05) TYP

2X (1.775)

(

0.2) TYP

VIA

LAND PATTERN EXAMPLE

SCALE: 25X

0.05 MIN

ALL AROUND

0.05 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

PADS: 1-4

SOLDER MASK DETAILS

PADS: 5-8

4229109/A 10/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RDX0007A

QFN-FCMOD - 2.1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

3X (0.22)

3X (0.6)

(1.9)

2X (1.84)

2X (1.575)

4X (0.25)

2X (1.5)

EXPOSED METAL

2X (1.185)

2X (1)

2X (0.785)

EXPOSED METAL

2X (0.375)

2X (0.085)

0.000 PKG

2X (0.065)

2X (0.415)

4X (0.3)

8X (0.25)

2X (0.915)

2X (1.265)

2X (1.415)

(R0.05) TYP

2X (1.705)

METAL UNDER

SOLDER MASK

TYP

SOLDER MASK

OPENING

TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 25X

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

PADS: 1, 2, 3 & 4: 75%

4229109/A 10/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TPSM863252 相关器件

型号	制造商	描述	价格	文档
TPSM863253	TI	3-V to 17-V input, 3-A synchronous buck module with?3.3-V fixed?output in QFN package	获取价格
TPSM863257	TI	3-V to 17-V input voltage, 3-A forced-CCM synchronous buck module	获取价格
TPSM86637	TI	采用 QFN 封装的 4.5V 至 28V 输入电压、6A ECO 模式、同步降压模块	获取价格
TPSM86638	TI	采用 QFN 封装的 4.5V 至 28V 输入电压、6A FCCM 模式、同步降压模块	获取价格
TPSM86837	TI	采用 QFN 封装的 4.5V 至 28V 输入电压、8A ECO 模式、同步降压模块	获取价格
TPSM86838	TI	采用 HotRod QFN 封装的4.5V 至28V 输入、8A FCCM 模式、同步降压模块	获取价格
TPSM8A28	TI	TPSM8A28, TPSM8A29 2.7-V to 16-V Input, 12-A, 15-A Buck Power Modules with Differential Remote Sense	获取价格
TPSM8A28RDGR	TI	TPSM8A28, TPSM8A29 2.7-V to 16-V Input, 12-A, 15-A Buck Power Modules with Differential Remote Sense	获取价格
TPSM8A29	TI	TPSM8A28, TPSM8A29 2.7-V to 16-V Input, 12-A, 15-A Buck Power Modules with Differential Remote Sense	获取价格
TPSM8A29RDGR	TI	TPSM8A28, TPSM8A29 2.7-V to 16-V Input, 12-A, 15-A Buck Power Modules with Differential Remote Sense	获取价格