UCC3776DP

更新时间:2024-12-03 13:11:20
品牌:TI
描述:Quad FET Driver 16-SOIC 0 to 70

UCC3776DP 概述

Quad FET Driver 16-SOIC 0 to 70 MOSFET 驱动器

UCC3776DP 规格参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete包装说明:SOP, SOP16,.25
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.9
Is Samacsys:N高边驱动器:NO
接口集成电路类型:BUFFER OR INVERTER BASED MOSFET DRIVERJESD-30 代码:R-PDSO-G16
长度:9.89 mm功能数量:4
端子数量:16最高工作温度:70 °C
最低工作温度:标称输出峰值电流:2 A
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:12 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:MOSFET Drivers
最大供电电压:18 V最小供电电压:4.5 V
标称供电电压:12 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
断开时间:0.1 µs接通时间:0.1 µs
宽度:3.9 mmBase Number Matches:1

UCC3776DP 数据手册

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UCC1776  
UCC2776  
UCC3776  
PRELIMINARY  
Quad FET Driver  
FEATURES  
DESCRIPTION  
The UCC3776 is a four output BCDMOS buffer/driver designed to drive highly  
capacitive loads such as power MOSFET gates at high speeds. The device  
can be configured as either an inverting or non-inverting driver via the POL  
pin. The outputs are enabled by ENBL. When disabled, all outputs are active  
low. The device incorporates thermal shutdown with hysteresis for stability.  
The device also includes an undervoltage lockout circuit (UVLO) with hystere-  
sis which disables the outputs when VDD is below a preset threshold. The  
outputs are held low during undervoltage lockout, even in the absence of  
VDD power to the device.This helps prevent MOSFET turn-on due to capaci-  
tive current through the gate-drain capacitance of the power MOSFET in the  
presence of high dV/dts. The logic input thresholds are compatible with  
standard 5V HCMOS logic.  
High Peak Output Current  
Each Output – 1.5A Source,  
2.0A Sink  
Wide Operating Voltage  
Range 4.5V to 18V  
Thermal Shutdown  
CMOS Compatible Inputs  
Outputs Are Active Low  
for Undervoltage Lockout  
Condition  
BLOCK DIAGRAM  
UDG-95129-2  
Note: Pin connections shown refer to 16-pin packages.  
3/97  
1
UCC1776  
UCC2776  
UCC3776  
ABSOLUTE MAXIMUM RATINGS  
Input Supply Voltage, VDD1, VDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V  
Maximum DC Voltage Difference, VDD1 vs.VDD2 . . . . . . . . . . . . . . . . . . . . . . .100mV  
Logic Input, IN1, IN4, ENBL  
Maximum forced voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 to VDD1 + 0.3V  
Logic Inputs, IN2, IN3, POL  
Maximum forced voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 to VDD2 + 0.3V  
Latch-up Protection withstand Reverse Current  
IREV, OUT1, OUT2, OUT3, OUT4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500mA  
Power Outputs, OUT1, OUT2, OUT3, OUT4  
Maximum pulsed current (10% duty max, 10µsec max pulse width) . . . . . . . . . .3A  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to +150°C  
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55°C to +150°C  
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300°C  
All currents are positive into, negative out of the specified terminal. Consult Packaging  
Section of Databook for thermal limitations and considerations of packages.  
CONNECTION DIAGRAMS  
DIL-16 (Top View)  
N or J, DP Packages  
PLCC-28 (Top View)  
Q Package  
ELECTRICAL CHARACTERISTICS Unless otherwise stated these specifications apply for TA = −55°C to +125°C for  
UCC1776;40°C to +85°C for UCC2776;0°C to +70°C for UCC3776;VPOL = 5V, VENBL = 5V, 4.5V < VDD < 18V, TJ = TA.  
PARAMETER  
Input Section  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
VIH, Logic 1 Input Voltage  
VIL, Logic 0 Input Voltage  
IINn, Input Current  
3
V
2
V
VINn = 5V  
VINn = 0V  
VENBL = 5V  
VENBL = 0V  
VPOL = 5V  
VPOL = 0V  
30  
+1  
30  
+1  
+1  
µA  
µA  
µA  
µA  
µA  
µA  
–1  
ENBL Input Current  
POL Input Current  
–1  
1  
30  
2
UCC1776  
UCC2776  
UCC3776  
ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated these specifications apply for TA = −55°C to +125°C  
for UCC1776;40°C to +85°C for UCC2776;0°C to +70°C for UCC3776;VPOL = 5V, VENBL = 5V, 4.5V < VDD < 18V, TJ = TA.  
PARAMETERTEST CONDITIONS  
Output Section  
MIN  
TYP  
MAX  
UNITS  
VOH, High Output Voltage  
IOUTn = -10mA, VDD1 = VDD2 = 12V, VINn = 5V VDD1.0  
IOUTn = 10mA, VDD1 = VDD2 = 12V, VINn = 0V  
IOUTn = 10mA, VDD1 = VDD2 = 12V, VINn = 0V  
V
V
A
VOL, Low Output Voltage  
Output Resistance  
0.15  
6
Output High Peak Current  
VDD1 = VDD2 = 12V, OUTn = 5V, VINn = 5V,  
TJ = 25°C (Note 1)  
1.5  
Output Low Peak Current  
VDD1 = VDD2 = 12V, OUTn = 5V, VINn = 0V,  
TJ = 25°C (Note 1)  
2.0  
0.8  
A
V
UVLO Output Pull-down Voltage  
Switching Time Section  
Output Rise Time  
VDD1 = VDD2 = 3V, IOUTn = −10mA  
1.5  
50  
COUTn = 1nF, VOUTn = 1V to 9V,  
VDD1 = VDD2 = 12V  
25  
nsec  
Output Fall Time  
COUTn = 1nF, VOUTn = 9V to 1V,  
VDD1 = VDD2 = 12V  
10  
40  
50  
nsec  
nsec  
IN−>OUT Delay Time (Rising Output) VINn = 2.5V, VOUTn = 0.1 • VDD,  
VDD1 = VDD2 = 12, COUTn = 0nF  
100  
IN−>OUT Delay Time (Falling Output) VINn = 2.5V, VOUTn = 0.9 • VDD,  
VDD1 = VDD2 = 12V, COUTn = 0nF  
50  
100  
nsec  
mA  
Power Supply Section  
Power Supply Current  
V(IN1IN4) = 0V, VENBL = 0V,  
VDD1 = VDD2 = 12V  
2
UVLO Threshold  
UVLO Hysteresis  
4.5  
V
V
0.5  
Note 1: Guaranteed by design. Not 100% tested in production.  
PIN DESCRIPTIONS  
ENBL: Logic level input to enable the drivers.When ENBL OUT1 - OUT4: Outputs to each driver (1-4). The outputs  
is low, the drivers outputs will be at GND potential, regard- are totem pole DMOS circuits. In the absence of VDD on  
less of the status of POL. The input threshold is designed the device, the outputs will stay off, even with a capacitive  
to be 5 volt CMOS compatible, independent of the VDD displacement current into the output node.  
voltage used on the device. There is a slight hysteresis in  
POL: Polarity selection for the drivers. A logic 0 selects  
the input circuit to help reduce sensitivity to noise on the  
inverting operation. A logic 1 selects non-inverting opera-  
input signal or input ground.  
tion. The input threshold is designed to be 5 volt CMOS  
GND: Ground for the device, the supply return for the compatible, independent of the VDD voltage used on the  
VDDs.There are four GND pads on the device.  
device. There is a slight hysteresis in the input circuit to  
help reduce sensitivity to noise.  
IN1 - IN4: Inputs to each driver (1-4).The input threshold  
is designed to be 5 volt CMOS compatible, independent VDD1: Supply Voltage for drivers 1 and 4. Tied internally  
of the VDD voltage used on the device. There is a slight to VDD2.  
hysteresis in the input circuit to help reduce sensitivity  
to noise.  
VDD2: Supply Voltage for drivers 2 and 3. Tied internally  
to VDD1.  
APPLICATION INFORMATION  
Figure 1 depicts a block diagram of the UCC3776 Quad tion flexibility, while power packaging and high speed  
FET Driver. Four high current, high speed gate drivers drive circuitry allow for driving high power MOSFET  
with CMOS compatible input stages are provided. gates in high speed applications.  
Polarity select and enable inputs provide circuit integra-  
3
UCC1776  
UCC2776  
UCC3776  
APPLICATION INFORMATION (cont.)  
UDG-96006  
Figure 1.Typical FET Driver Application  
Input Stage  
tify speed performance. While these specifications are  
important, they do not provide all the required informa-  
tion. The UCC3776 specifies rise and fall times of 25ns  
and 10ns respectively into a load of 1nF. This specifica-  
tion can be used to calculate the average slew rate capa-  
bility of the driver stage over the output voltage range.  
Each of the four UCC3776 FET driver circuits provides  
an independent, CMOS compatible input stage. The  
allowable input voltage range extends from ground to  
VDD, allowing for easy interface to a wide variety of  
PWM and power supply support circuitry. The POL and  
ENBL inputs are tied to all four drivers, and all drivers  
must be configured as either inverting or noninverting,  
and all must be either enabled or not enabled.  
However, the gate of a power MOSFET cannot be mod-  
eled accurately with a simple capacitor. The voltage/cur-  
rent requirements of the gate vary widely over several  
distinct phases of FET turn-on and turn-off. The most  
accurate way to calculate the switching times of power  
MOSFETs is to determine the total gate charge require-  
ment (Qg), which is usually specified by the MOSFET  
manufacturer, and determine the peak current capability  
of the MOSFET gate driver. Ideally the driver’s peak cur-  
rent can be delivered while the MOSFET gate is transi-  
tioning through its plateau or “Miller” level, when current  
demands are highest.  
To prevent oscillations in noisy PWM environments, any  
unused drivers should have their input stages tied to  
either VDD or ground. Unlike other CMOS FET drivers,  
quiescent power current is not significantly affected by  
the polarity of the driver input signal.  
Output Stage/Gate Driver Considerations  
Many power FET driver data sheets rely solely on rise  
and fall time specifications into a capacitive load to quan-  
4
UCC1776  
UCC2776  
UCC3776  
APPLICATION INFORMATION (cont.)  
The UCC3776 specifies peak source and sink currents gate drive energy (WGD) is computed as:  
for a driver output voltage of 5V. This output voltage  
QG  
V
WGD = 2 • 0.5 • CG • V2 =  
• V = QG • V  
2
1)  
approximately coincides with the average gate plateau  
voltage of a power MOSFET. Outside of the plateau  
region the gate drive waveform is primarily limited by the  
slew rate capability of the driver.Through proper analysis  
of the MOSFET’s gate drive requirements and the speci-  
fications for the UCC3776, an accurate model of AC per-  
formance can be created. For a detailed description of  
MOSFET AC gate drive requirements please see  
Unitrode Application Notes U-118 and U-137. Although  
the Unitrode power drivers referenced in these applica-  
tion notes are bipolar devices, the information relating to  
MOSFET gate drive characteristics is applicable.  
Where QG is the MOSFET’s total gate charge, and V is  
the gate voltage. The factor of two results from the fact  
that the gate drive circuit must charge and discharge the  
gate every electrical cycle. Each time the gate is charged  
or discharged, the gate drive dissipates an amount of  
energy equal to the energy supplied to the gate. Power  
lost due to driving the gate is:  
WGD  
Q • V  
T
2)  
PLGD =  
=
= QG • V • F  
T
Where F is the operating frequency of the MOSFET.This  
is a worst case assumption since the power loss is  
shared by the output driver and the gate resistor. If a rel-  
atively large value series gate resistor is used, the power  
loss in the gate driver is reduced. The penalty for this is  
slower switching speed, and therefore more loss in the  
MOSFET. For high power MOSFETs this power loss can  
be significant.  
Power Supply Decoupling/Grounding  
The high peak currents required to charge high capaci-  
tance MOSFET gates make proper power supply decou-  
pling and grounding essential. The UCC3776 provides  
two power supply inputs (VDD1 and VDD2) to allow for  
optimum internal circuit layout and minimum resistive  
voltage drop with high peak current loads. VDD1 pro-  
vides the drive current for outputs 1 and 4, while VDD2  
provides drive current for outputs 2 and 3. Both of these  
pins must be externally connected to the source power  
supply, and the DC potential difference between these  
two points should be limited to 100mV. Under no circum-  
stances should an output driver be used with only one  
supply input connected.  
To illustrate a typical example of driver loss, consider a  
MOSFET with 70nC of gate charge and a 15V gate volt-  
age.The power loss at 200kHz is:  
3)  
PLGD = 70nC • 15V • 200kHz = 210mW  
This analysis applies to one of the four drivers on the  
UCC3776. Four drivers operating under the same condi-  
tions results in a total power loss of 840mW. At higher  
frequencies the dissipation will be proportionally greater.  
This example demonstrates the need for power packag-  
ing which is available on the UCC3776, and not available  
on many other FET drivers.  
To guarantee a low impedance current path over a wide  
frequency range, each supply input should be separately  
bypassed to ground with both a high value tantalum or  
electrolytic capacitor in parallel with a 0.1µF ceramic  
capacitor. The exact value of the tantalum or electrolytic  
capacitor will depend on the charge requirements of the  
MOSFET gate. For most applications a value between  
1µF and 10µF should suffice. Connections for ground  
leads should be kept as short as possible. The driver  
chip and support electronics should be located over a  
large copper ground plane if layout conditions allow it.  
After device power dissipation has been estimated, prop-  
er heat sinking must be provided to ensure that the  
device junction temperature does not exceed the speci-  
fied maximum. Refer to the packaging section of the  
databook for package thermal impedance information.  
Application Circuits  
Power Dissipation/Thermal Considerations  
Figure 1 depicts a typical gate drive application circuit.  
Four independent, noninverting low side FET drivers are  
shown. Although series gate drive resistors are not  
required because all FET drivers have a finite peak current  
capability, it is good practice to include some series resis-  
tance to limit peak current and to prevent oscillations due  
to parasitic inductance and capacitance.The parallel diode  
and resistor allow for a faster gate turn off than turn on.  
This characteristic is often desirable for bridge driver appli-  
cations to prevent MOSFET cross conduction in the power  
stage.  
Being a CMOS device, the standby power dissipation of  
the UCC3776 is quite low. For a 15V supply, the maxi-  
mum quiescent current of 2mA results in a maximum  
power loss of only 30mW. However, driving high frequen-  
cy MOSFETs at high peak currents results in additional  
power dissipation. This is because each time the MOS-  
FET gate is charged or discharged, the energy transfer is  
only 50% efficient. The same amount of energy that is  
transferred to the gate is lost in the drive stage.  
In order to determine the average output stage loss, the  
5
UCC1776  
UCC2776  
UCC3776  
APPLICATION INFORMATION (cont.)  
Figure 2 shows an applications circuit with paralleled out- a single MOSFET, then four separate gate drive resistor  
put drivers. If it is required to drive high gate charge  
MOSFETs, the UCC3776 output drivers can be combined  
for higher peak current capability. It is good practice to pro-  
vide separate gate resistor networks to each individual  
MOSFET as shown. This will ensure that each driver cir-  
cuit will not see excessive current during the high gate  
charge portion of the switching waveform. This practice  
also tends to isolate driver circuits to reduce the possibility  
of ringing and crosstalk. If all four drivers are used to drive  
networks should be used.  
Figure 3 shows a transformer coupled full bridge power  
stage. The UCC3776 is ideally suited for interfacing  
between low power PWM outputs and high power output  
stages. Although the UC3879 phase shift controller is  
shown in this example, the UCC3776 can be used in  
many PWM controller applications where high power FET  
drivers are required.  
UDG-96007  
Figure 2. Parallel Output Drivers  
UDG-96008-1  
Figure 3. Full Bridge Driver Application  
UNITRODECORPORATION  
7 CONTINENTAL BLVD. MERRIMACK, NH 03054  
TEL. (603) 424-2410 FAX (603) 424-3460  
6
IMPORTANT NOTICE  
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
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In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
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Copyright 1999, Texas Instruments Incorporated  

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