AD5724AREZ [ADI]
Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs; 完整的四通道, 12位/ 14位/ 16位,串行输入,单极性/双极性电压输出DAC型号: | AD5724AREZ |
厂家: | ADI |
描述: | Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs |
文件: | 总32页 (文件大小:1216K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Complete, Quad, 12-/14-/16-Bit, Serial Input,
Unipolar/Bipolar Voltage Output DACs
AD5724/AD5734/AD5754
GENERAL DESCRIPTION
FEATURES
Complete, quad, 12-/14-/16-bit digital-to-analog converter
(DAC)
The AD5724/AD5734/AD5754 are quad, 12-/14-/16-bit, serial
input, voltage output digital-to-analog converters. They operate
from single-supply voltages from +4.5 V up to +16.5 V or dual-
supply voltages from 4.5 V up to 16.5 V. Nominal full-scale
output range is software-selectable from +5 V, +10 V, +10.8 V,
5 V, 10 V, or 10.8 V. Integrated output amplifiers, reference
buffers, and proprietary power-up/power-down control circuitry
are also provided.
Operates from single/dual supplies
Software programmable output range
+5 V, +10 V, +10.8 V, 5 V, 10 V, 10.8 V
INL error: 16 LSB maximum, DNL error: 1 LSB maximum
Total unadjusted error (TUE): 0.1% FSR maximum
Settling time: 10 μs typical
Integrated reference buffers
Output control during power-up/brownout
Simultaneous updating via LDAC
Asynchronous CLR to zero scale or midscale
DSP-/microcontroller-compatible serial interface
24-lead TSSOP
Operating temperature range: −40°C to +85°C
iCMOS process technology1
The parts offer guaranteed monotonicity, integral nonlinearity
(INL) of 16 LꢀB maximum, low noise, and 10 μs maximum
settling time.
The AD5724/AD5734/AD5754 use a serial interface that operates
at clock rates up to 30 MHz and are compatible with DꢀP and
microcontroller interface standards. Double buffering allows
the simultaneous updating of all DACs. The input coding is
user-selectable twos complement or offset binary for a bipolar
APPLICATIONS
2sComp
output (depending on the state of Pin BIN/
), and straight
Industrial automation
binary for a unipolar output. The asynchronous clear function
clears all DAC registers to a user-selectable zero-scale or midscale
output. The parts are available in a 24-lead TꢀꢀOP and offer
guaranteed specifications over the −40°C to +85°C industrial
temperature range.
Closed-loop servo control, process control
Automotive test and measurement
Programmable logic controllers
FUNCTIONAL BLOCK DIAGRAM
SS
AV
AV
DD
REFIN
DV
CC
AD5724/AD5734/AD5754
REFERENCE BUFFERS
n
n
INPUT
DAC
DAC A
SDIN
SCLK
SYNC
SDO
V
A
REGISTER A
REGISTER A
OUT
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
n
INPUT
REGISTER B
DAC
REGISTER B
DAC B
V
V
V
B
C
D
OUT
OUT
OUT
n
INPUT
REGISTER C
DAC
REGISTER C
DAC C
CLR
BIN/2sCOMP
n
INPUT
REGISTER D
DAC
REGISTER D
DAC D
AD5724: n = 12-BIT
AD5734: n = 14-BIT
AD5754: n = 16-BIT
DAC_GND (2)
SIG_GND (2)
GND
LDAC
Figure 1.
1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS® is a technology
platform that enables the development of analog ICs capable of 30 V and operating at 15 V supplies while allowing dramatic reductions in power consumption and
package size, as well as increased ac and dc performance.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
rights of third parties that may result from its use. Specifications subject to change without notice. No
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
AD5724/AD5734/AD5754
TABLE OF CONTENTS
Features .............................................................................................. 1
Transfer Function....................................................................... 20
Input ꢀhift Register .................................................................... 24
DAC Register .............................................................................. 24
Output Range ꢀelect Register ................................................... 25
Control Register ......................................................................... 25
Power Control Register ............................................................. 26
Features............................................................................................ 27
Analog Output Control ............................................................. 27
Power-Down Mode.................................................................... 27
Overcurrent Protection ............................................................. 27
Thermal ꢀhutdown .................................................................... 27
Applications Information.............................................................. 28
+5 V/ 5 V Operation ................................................................ 28
Layout Guidelines....................................................................... 28
Galvanically Isolated Interface ................................................. 28
Voltage Reference ꢀelection...................................................... 28
Microprocessor Interfacing....................................................... 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
ꢀpecifications..................................................................................... 3
AC Performance Characteristics................................................ 5
Timing Characteristics ................................................................ 5
Timing Diagrams.......................................................................... 6
Absolute Maximum Ratings............................................................ 8
EꢀD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 18
Architecture................................................................................. 18
ꢀerial Interface ............................................................................ 18
LDAC
Load DAC (
)..................................................................... 20
CLR
Asynchronous Clear (
)....................................................... 20
Configuring the AD5724/AD5734/AD5754 .......................... 20
REVISION HISTORY
8/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD5724/AD5734/AD5754
SPECIFICATIONS
AVDD = 4.5 V1 to 16.5 V; AVꢀꢀ = −4.5 V1 to −16.5 V, or 0 V; GND = 0 V; REFIN= 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ;
C
LOAD = 200 pF; all specifications TMIN to TMAX
.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ACCURACY
Outputs unloaded
Resolution
AD5754
AD5734
AD5724
16
14
12
Bits
Bits
Bits
Total Unadjusted Error (TUE)
A Version
B Version
Relative Accuracy (INL)2
−0.3
−0.1
+0.3
+0.1
% FSR
% FSR
AD5754
AD5734
AD5724
Differential Nonlinearity (DNL)
Bipolar Zero Error
−16
−4
−1
−1
−6
+16
+4
+1
+1
+6
LSB
LSB
LSB
LSB
mV
All models, all versions, guaranteed monotonic
TA = 25°C, error at other temperatures obtained
using bipolar zero error TC
Bipolar Zero Error TC3
Zero-Scale Error
4
4
4
ppm FSR/°C
mV
−6
−6
6
TA = 25°C, error at other temperatures
obtained using zero-scale error TC
Zero-Scale Error TC3
Offset Error
ppm FSR/°C
mV
+6
TA = 25°C, error at other temperatures
obtained using offset error TC
Offset Error TC3
Gain Error
ppm FSR/°C
+0.025 % FSR
−0.025
−0.065
0
10 V range, TA = 25°C, error at other
temperatures obtained using gain error TC
+10 V and +5 V ranges, TA = 25°C, error at other
temperatures obtained using gain error TC
5 V range, TA = 25°C, error at other
Gain Error3
Gain Error3
0
% FSR
% FSR
+0.08
temperatures obtained using gain error TC
Gain Error TC3
DC Crosstalk3
8
ppm FSR/°C
μV
120
REFERENCE INPUT3
Reference Input Voltage
DC Input Impedance
Input Current
2.5
5
0.5
V
1% for specified performance
1
−2
2
MΩ
μA
V
+2
3
Reference Range
OUTPUT CHARACTERISTICS3
Output Voltage Range
−10.8
−12
+10.8
+12
0.ꢀ
V
V
V
AVDD/AVSS = 11.7 V min, REFIN = +2.5 V
AVDD/AVSS = 12.ꢀ V min, REFIN = +3 V
Headroom Required
Output Voltage TC
Short-Circuit Current
Load
Capacitive Load Stability
DC Output Impedance
0.5
4
20
ppm FSR/°C
mA
kΩ
pF
Ω
2
For specified performance
4000
0.5
Rev. 0 | Page 3 of 32
AD5724/AD5734/AD5754
Parameter
DIGITAL INPUTS3
Min
Typ
Max
Unit
Test Conditions/Comments
DVCC = 2.7 V to 5.5 V, JEDEC compliant
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current
2
V
V
μA
pF
0.8
1
Per pin
Per pin
Pin Capacitance
5
DIGITAL OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH
High Impedance Leakage Current
High Impedance Output Capacitance
POWER REQUIREMENTS
AVDD
0.4
0.4
+1
V
V
V
V
μA
pF
DVCC = 5 V 10%, sinking 200 μA
DVCC = 5 V 10%, sourcing 200 μA
DVCC = 2.7 V to 3.6 V, sinking 200 μA
DVCC = 2.7 V to 3.6 V, sourcing 200 μA
DVCC − 1
DVCC − 0.5
−1
5
4.5
−4.5
2.7
16.5
−16.5
5.5
V
V
V
AVSS
DVCC
Power Supply Sensitivity3
∆VOUT/∆ΑVDD
−65
dB
AIDD
2.5
1.75
2.2
3
mA/channel
mA/channel
mA/channel
μA
Outputs unloaded
AVSS = 0 V, outputs unloaded
Outputs unloaded
AISS
DICC
0.5
VIH = DVCC, VIL = GND
Power Dissipation
310
115
mW
mW
16.5 V operation, outputs unloaded
16.5V operation, AVSS = 0 V, outputs unloaded
Power-Down Currents
AIDD
AISS
DICC
40
40
300
μA
μA
nA
1 For specified performance, maximum headroom requirement is 0.ꢀ V.
2 INL is measured from Code 512, Code 128, and Code 32 for the AD5754, the AD5734, and the AD5724, respectively.
3 Guaranteed by characterization; not production tested.
Rev. 0 | Page 4 of 32
AD5724/AD5734/AD5754
AC PERFORMANCE CHARACTERISTICS
AVDD = 4.5 V1 to 16.5 V; AVꢀꢀ = −4.5 V1 to −16.5 V, or 0 V; GND = 0 V; REFIN= 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ;
LOAD = 200 pF; all specifications TMIN to TMAX
C
.
Table 2.
A, B Version
Parameter2
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
10
7.5
12
8.5
5
μs
μs
μs
20 V step to 0.03% FSR
10 V step to 0.03% FSR
512 LSB step settling (16-bit resolution)
Slew Rate
3.5
13
35
10
10
0.6
V/μs
nV-sec
mV
nV-sec
nV-sec
nV-sec
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Crosstalk
DAC-to-DAC Crosstalk
Digital Feedthrough
Output Noise
0.1 Hz to 10 Hz Bandwidth)
100 kHz Bandwidth
Output Noise Spectral Density
15
80
320
μV p-p
μV rms
nV/√Hz
0x8000 DAC code
Measured at 10 kHz, 0x8000 DAC code
1 For specified performance, maximum headroom requirement is 0.ꢀ V.
2 Guaranteed by design and characterization. Not production tested.
TIMING CHARACTERISTICS
AVDD = 4.5 V to 16.5 V; AVꢀꢀ = −4.5 V to −16.5 V, or 0 V; GND = 0 V; REFIN = 2.5 V; DVCC = 2.7 V to 5.5 V; RLOAD = 2 kΩ; CLOAD = 200 pF;
all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2, 3
Limit at tMIN, tMAX
Unit
Description
t1
t2
t3
t4
33
13
13
13
13
100
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs typ
ns min
μs max
ns min
ns max
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (write mode)
Data setup time
t5
t6
t7
t8
tꢀ
0
Data hold time
20
20
20
10
20
2.5
13
40
200
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
t10
t11
t12
t13
t14
DAC output settling time
CLR pulse width low
CLR pulse activation time
4
t15
SYNC rising edge to SCLK rising edge
SCLK rising edge to SDO valid (CL SDO5 = 15 pF)
Minimum SYNC high time (readback/daisy-chain mode)
4
t16
t17
1 Guaranteed by characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to ꢀ0% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 Daisy-chain and readback mode.
5 CL SDO = capacitive load on SDO output.
Rev. 0 | Page 5 of 32
AD5724/AD5734/AD5754
TIMING DIAGRAMS
t1
SCLK
1
2
24
t3
t2
t6
t5
t4
SYNC
SDIN
t8
t7
DB23
DB0
t11
t9
t10
LDAC
t12
V
V
x
OUT
OUT
t12
x
t13
CLR
t14
V
x
OUT
Figure 2. Serial Interface Timing Diagram
t1
SCLK
24
48
t3
t2
t5
t17
t15
t4
SYNC
SDIN
t8
t7
D32B
D0B
D32B
D0B
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N – 1
INPUT WORD FOR DAC N
t16
DB23
DB0
SDO
t10
UNDEFINED
t11
LDAC
Figure 3. Daisy-Chain Timing Diagram
Rev. 0 | Page 6 of 32
AD5724/AD5734/AD5754
SCLK
1
24
24
1
t17
SYNC
SDIN
DB23
DB0
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB23
DB0
DB23
DB0
SDO
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Readback Timing Diagram
Rev. 0 | Page 7 of 32
AD5724/AD5734/AD5754
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause ꢀCR latch-up.
Table 4.
Parameter
AVDD to GND
AVSS to GND
DVCC to GND
Digital Inputs to GND
ꢀtresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +17 V
+0.3 V to −17 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
Digital Outputs to GND
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
ESD CAUTION
REFIN to GND
VOUTA, VOUTB, VOUTC, VOUTD to GND
DAC_GND to GND
−0.3 V to +5 V
AVSS to AVDD
−0.3 V to +0.3 V
−0.3 V to +0.3 V
SIG_GND to GND
Operating Temperature Range, TA
Industrial
−40°C to +85°C
−65°C to +150°C
105°C
Storage Temperature Range
Junction Temperature, TJ max
24-Lead TSSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Power Dissipation
42°C/W
ꢀ°C/W
(TJ max − TA)/ θJA
JEDEC industry standard
J-STD-020
Lead Temperature
Soldering
ESD (Human Body Model)
3.5 kV
Rev. 0 | Page 8 of 32
AD5724/AD5734/AD5754
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AV
AV
1
24
23
22
21
DD
SS
2
NC
A
V
V
C
OUT
AD5724/
AD5734/
AD5754
3
D
V
V
OUT
OUT
4
B
SIG_GND
OUT
5
20 SIG_GND
BIN/2sCOMP
NC
TOP VIEW
(Not to Scale)
6
19
18
17
16
15
14
13
DAC_GND
DAC_GND
REFIN
7
SYNC
SCLK
SDIN
8
9
SDO
10
11
12
LDAC
CLR
GND
DV
CC
NC
NC
NOTES
1. NC = NO CONNECT.
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE
THERMALLY CONNECTED TO A COPPER PLANE
FOR ENHANCED THERMAL PERFORMANCE.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
AVSS
Negative Analog Supply. Voltage ranges from −4.5 V to −16.5 V. This pin can be connected to 0 V if output
ranges are unipolar.
2, 6, 12, 13 NC
Do not connect to these pins.
3
4
5
VOUT
VOUT
BIN/2sCOMP
A
B
Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Determines the DAC coding for a bipolar output range. This pin should be hardwired to either DVCC or GND.
When hardwired to DVCC, input coding is offset binary. When hardwired to GND, input coding is twos
complement. (For unipolar output ranges, coding is always straight binary).
7
8
SYNC
SCLK
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 30 MHz.
ꢀ
SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
10
LDAC
Load DAC, Logic Input. This is used to update the DAC registers and consequently, the analog outputs. When
this pin is tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is
held high during the write cycle, the DAC input register is updated, but the output update is held off until the
falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of
LDAC. The LDAC pin should not be left unconnected.
11
14
15
16
CLR
Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user-selectable).
Digital Supply. Voltage ranges from 2.7 V to 5.5 V.
Ground Reference.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is
clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
DVCC
GND
SDO
17
REFIN
DAC_GND
SIG_GND
External Reference Voltage Input. Reference input range is 2 V to 3 V. REFIN = 2.5 V for specified performance.
Ground Reference for the Four Digital-to-Analog Converters.
Ground Reference for the Four Output Amplifiers.
Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Positive Analog Supply. Voltage ranges from 4.5 V to 16.5 V.
Negative Analog Supply Connection. Voltage ranges from −4.5 V to −16.5 V. This paddle can be connected to
0 V if output ranges are unipolar. The paddle can be left electrically unconnected provided that a supply
connection is made at the AVSS pin. It is recommended that the paddle be thermally connected to a copper
plane for enhanced thermal performance.
18, 1ꢀ
20, 21
22
23
24
VOUT
VOUT
D
C
AVDD
AVSS
Exposed
Paddle
Rev. 0 | Page ꢀ of 32
AD5724/AD5734/AD5754
TYPICAL PERFORMANCE CHARACTERISTICS
6
0.6
0.4
AV /AV = +12V/0V, RANGE = +10V
DD SS
AV /AV = ±12V, RANGE = ±10V
DD SS
AV /AV = ±6.5V, RANGE = ±5V
DD SS
4
2
AV /AV = +6.5V/0V, RANGE = +5V
DD
SS
0.2
0
0
–2
–4
–6
–8
–0.2
–0.4
–0.6
–0.8
AV /AV = +12V/0V, RANGE = +10V
DD SS
AV /AV = ±12V, RANGE = ±10V
DD SS
AV /AV = ±6.5V, RANGE = ±5V
DD SS
AV /AV = +6.5V/0V, RANGE = +5V
DD
SS
0
10,000
20,000
30,000
40,000
50,000
60,000
0
10,000
20,000
30,000
CODE
40000
50,000
60,000
CODE
Figure 6. AD5754 Integral Nonlinearity Error vs. Code
Figure 9. AD5754 Differential Nonlinearity Error vs. Code
0.15
1.5
1.0
AV /AV = +12V/0V, RANGE = +10V
DD SS
AV /AV = ±12V, RANGE = ±10V
DD SS
AV /AV = ±6.5V, RANGE = ±5V
DD SS
AV /AV = +6.5V/0V, RANGE = +5V
DD SS
0.10
0.05
0
0.5
0
–0.05
–0.10
–0.15
–0.20
–0.5
–1.0
–1.5
–2.0
AV /AV = +12V/0V, RANGE = +10V
DD SS
AV /AV = ±12V, RANGE = ±10V
DD SS
AV /AV = ±6.5V, RANGE = ±5V
DD SS
AV /AV = +6.5V/0V, RANGE = +5V
DD SS
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
0
2000 4000 6000 8000 10,000 12,000 14,000 16,000
CODE
Figure 7. AD5734 Integral Nonlinearity Error vs. Code
Figure 10. AD5734 Differential Nonlinearity Error vs. Code
0.3
0.2
0.04
AV /AV = +12V/0V, RANGE = +10V
AV /AV = +12V/0V, RANGE = +10V
DD SS
DD
SS
AV /AV = ±12V, RANGE = ±10V
AV /AV = ±12V, RANGE = ±10V
DD SS
DD
SS
AV /AV = ±6.5V, RANGE = ±5V
0.03
0.02
AV /AV = ±6.5V, RANGE = ±5V
DD
SS
DD SS
AV /AV = +6.5V/0V, RANGE = +5V
DD SS
AV /AV = +6.5V/0V, RANGE = +5V
DD
SS
0.1
0.01
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.01
–0.02
–0.03
–0.04
–0.05
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
Figure 8. AD5724 Integral Nonlinearity Error vs. Code
Figure 11. AD5724 Differential Nonlinearity Error vs. Code
Rev. 0 | Page 10 of 32
AD5724/AD5734/AD5754
8
6
10
8
6
4
4
MAX INL ±10V
MAX INL ±5V
MIN INL ±10V
MIN INL ±5V
MAX INL +10V
MIN INL +10V
MAX INL +5V
MIN INL +5V
2
2
BIPOLAR 5V MIN
UNIPOLAR 5V MIN
BIPOLAR 5V MAX
UNIPOLAR 5V MAX
0
0
–2
–4
–6
–8
–10
–2
–4
–6
–8
5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 12. AD5754 Integral Nonlinearity Error vs. Temperature
Figure 15. AD5754 Integral Nonlinearity Error vs. Supply Voltage
0.1
0
1.0
BIPOLAR 10V MIN
UNIPOLAR 10V MIN
0.8
BIPOLAR 10V MAX
UNIPOLAR 10V MAX
0.6
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
MAX DNL ±10V
MAX DNL ±5V
MIN DNL ±10V
MIN DNL ±5V
MAX DNL +10V
MIN DNL +10V
MAX DNL +5V
MIN DNL +5V
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–40
–20
0
20
40
60
80
11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 13. AD5754 Differential Nonlinearity Error vs. Temperature
Figure 16. AD5754 Differential Nonlinearity Error vs. Supply Voltage
10
8
1.0
BIPOLAR 5V MIN
UNIPOLAR 5V MIN
0.8
BIPOLAR 5V MAX
UNIPOLAR 5V MAX
6
0.6
4
0.4
0.2
2
BIPOLAR 10V MIN
UNIPOLAR 10V MIN
0
0
BIPOLAR 10V MAX
UNIPOLAR 10V MAX
–2
–0.2
–0.4
–0.6
–0.8
–4
–6
–8
–10
–1.0
11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
SUPPLY (V)
SUPPLY VOLTAGE (V)
Figure 14. AD5754 Integral Nonlinearity Error vs. Supply Voltage
Figure 17. AD5754 Differential Nonlinearity Error vs. Supply Voltage
Rev. 0 | Page 11 of 32
AD5724/AD5734/AD5754
0.02
0.01
0
10
9
BIPOLAR 10V MIN
UNIPOLAR 10V MIN
BIPOLAR 10V MAX
UNIPOLAR 10V MAX
8
7
–0.01
–0.02
–0.03
–0.04
6
5
4
4.5
11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
6.5
8.5
10.5
AV (V)
12.5
14.5
16.5
SUPPLY VOLTAGE (V)
DD
Figure 18. AD5754 Total Unadjusted Error vs. Supply Voltage
Figure 21. Supply Current vs. Supply Voltage (Single Supply)
0.04
0.03
0.02
4
+10V
3
2
0.01
0
BIPOLAR 5V MIN
UNIPOLAR 5V MIN
BIPOLAR 5V MAX
UNIPOLAR 5V MAX
1
±10V
–0.01
–0.02
–0.03
–0.04
–0.05
0
–1
–2
±5V
–3
–40
5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 14.5 15.5 16.5
–20
0
20
40
60
80
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 19. AD5754 Total Unadjusted Error vs. Supply Voltage
Figure 22. Zero-Scale Error vs. Temperature
0.8
8
6
0.6
0.4
I
(mA)
DD
4
2
±5V RANGE
0.2
0
0
±10V RANGE
–0.2
–0.4
–0.6
–0.8
–1.0
–2
–4
–6
–8
I
(mA)
SS
4.5
6.5
8.5
10.5
12.5
14.5
16.5
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
AV /AV (V)
DD SS
Figure 23. Bipolar Zero Error vs. Temperature
Figure 20. Supply Current vs. Supply Voltage (Dual Supply)
Rev. 0 | Page 12 of 32
AD5724/AD5734/AD5754
0.06
0.04
0.02
0
15
10
5
±5V
0
±10V
+10V
–0.02
–0.04
–0.06
–5
–10
–15
–3
–1
1
3
5
7
9
11
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
TIME (µs)
Figure 24. Gain Error vs. Temperature
Figure 27. Full-Scale Settling Time, 10 V Range
1000
900
800
700
600
500
400
300
200
100
0
7
5
3
1
–1
–3
–5
–7
DV
= 5V
CC
DV
2
= 3V
CC
–100
0
1
3
4
5
6
–3
–1
1
3
5
7
9
11
V
(V)
TIME (µs)
LOGIC
Figure 25. Digital Current vs. Logic Input Voltage
Figure 28. Full-Scale Settling Time, 5 V Range
0.010
0.005
0
12
10
8
±5V RANGE, CODE = 0xFFFF
±10V RANGE, CODE = 0xFFFF
+10V RANGE, CODE = 0xFFFF
+5V RANGE, CODE = 0xFFFF
±5V RANGE, CODE = 0x0000
±10V RANGE, CODE = 0x0000
–0.005
–0.010
–0.015
–0.020
6
4
2
0
–25 –20 –15 –10
–5
0
5
10
15
20
25
–3
–1
1
3
5
7
9
11
OUTPUT CURRENT (mA)
TIME (µs)
Figure 29. Full-Scale Settling Time, +10 V Range
Figure 26. Output Source and Sink Capability
Rev. 0 | Page 13 of 32
AD5724/AD5734/AD5754
6
5
4
3
2
1
0
1
RANGE = ±5V
RANGE = +5V
RANGE = +10V
RANGE = ±10V
–3
–1
1
3
5
7
9
11
CH1 5µV
M5s
LINE
73.8V
TIME (µs)
Figure 30. Full-Scale Settling Time, +5 V Range
Figure 33. Peak-to-Peak Noise, 100 kHz Bandwidth
0.10
0.020
AV /AV = ±16.5V
±
DD
DD
SS
±10V RANGE, 0x7FFF TO 0x8000
±10V RANGE, 0x8000 TO 0x7FFF
AV
= +16.5V, AVSS = 0V
±
±5V RANGE, 0x7FFF TO 0x8000
0.08
0.06
0.04
0.02
0
0.015
0.010
0.005
0
±5V RANGE, 0x8000 TO 0x7FFF
+10V RANGE, 0x7FFF TO 0x8000
+10V RANGE, 0x8000 TO 0x7FFF
+5V RANGE, 0x7FFF TO 0x8000
+5V RANGE, 0x8000 TO 0x7FFF
–0.005
–0.010
–0.015
–0.02
–0.04
–0.06
–50
–30
–10
10
30
TIME (µs)
50
70
90
–1
0
1
2
3
4
5
TIME (µs)
Figure 34. Output Glitch on Power-Up
Figure 31. Digital-to-Analog Glitch Energy
15
10
AV /AV = +12V/0V, RANGE = +10V
DD SS
AV /AV = ±12V, RANGE = ±10V
DD SS
AV /AV = ±6.5V, RANGE = ±5V
DD SS
AV /AV = +6.5V/0V, RANGE = +5V
DD
SS
5
0
–5
–10
–15
–20
–25
–30
–35
1
RANGE = ±5V
RANGE = +5V
RANGE = +10V
RANGE = ±10V
0
1000
2000
3000
CODE
4000
5000
6000
CH1 5µV
M 5s
LINE
73.8V
Figure 32. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth
Figure 35. AD5754 Total Unadjusted Error vs. Code
Rev. 0 | Page 14 of 32
AD5724/AD5734/AD5754
4
2
1.0
0.5
AV /AV = +12V/0V, RANGE = +10V
DD SS
AV /AV = +12V/0V, RANGE = +10V
DD SS
AV /AV = ±12V, RANGE = ±10V
DD SS
AV /AV = ±12V, RANGE = ±10V
DD SS
AV /AV = ±6.5V, RANGE = ±5V
DD SS
AV /AV = +6.5V/0V, RANGE = +5V
DD SS
AV /AV = ±6.5V, RANGE = ±5V
DD SS
AV /AV = +6.5V/0V, RANGE = +5V
DD
SS
0
0
–2
–4
–6
–8
–10
–0.5
–1.0
–1.5
–2.0
–2.5
0
2000 4000 6000 8000 10,000 12,000 14,000 16,000
CODE
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
Figure 36. AD5734 Total Unadjusted Error vs. Code
Figure 37. AD5724 Total Unadjusted Error vs. Code
Rev. 0 | Page 15 of 32
AD5724/AD5734/AD5754
TERMINOLOGY
Slew Rate
Relative Accuracy or Integral Nonlinearity (INL)
The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltage output
DAC is usually limited by the slew rate of the amplifier used at
its output. ꢀlew rate is measured from 10% to 90% of the output
signal and is given in V/μs.
For the DAC, relative accuracy, or integral nonlinearity, is a
measure of the maximum deviation in LꢀBs from a straight line
passing through the endpoints of the DAC transfer function. A
typical INL vs. code plot can be seen in Figure 6.
Differential Nonlinearity (DNL)
Gain Error
Differential nonlinearity is the difference between the measured
change and the ideal 1 LꢀB change between any two adjacent
codes. A specified differential nonlinearity of 1 LꢀB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 9.
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from
the ideal and is expressed in % FꢀR. A plot of gain error vs.
temperature can be seen in Figure 24.
Gain TC
Monotonicity
Gain TC is a measure of the change in gain error with changes
in temperature. Gain TC is expressed in ppm FꢀR/°C.
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5724/
AD5734/AD5754 are monotonic over their full operating
temperature range.
Total Unadjusted Error (TUE)
Total unadjusted error is a measure of the output error taking
all the various errors into account, namely INL error, offset
error, gain error, and output drift over supplies, temperature,
and time. TUE is expressed in % FꢀR.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (straight binary coding) or 0x0000 (twos complement
coding). A plot of bipolar zero error vs. temperature can be seen
in Figure 23.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state, but the output voltage remains constant. It is normally
specified as the area of the glitch in nV-sec and is measured
when the digital input code is changed by 1 LꢀB at the major
carry transition (0x7FFF to 0x8000). ꢀee Figure 31.
Bipolar Zero TC
Bipolar zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in ppm FꢀR/°C.
Zero-Scale Error or Negative Full-Scale Error
Glitch Impulse Peak Amplitude
Zero-scale error is the error in the DAC output voltage when
0x0000 (straight binary coding) or 0x8000 (twos complement
coding) is loaded to the DAC register. Ideally, the output voltage
should be negative full-scale− 1 LꢀB. A plot of zero-scale error
vs. temperature can be seen in Figure 22.
Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in
the DAC register changes state. It is specified as the amplitude
of the glitch in mV and is measured when the digital input code
is changed by 1 LꢀB at the major carry transition (0x7FFF to
0x8000). ꢀee Figure 31.
Zero-Scale TC
Zero-scale TC is a measure of the change in zero-scale error with a
change in temperature. Zero-scale TC is expressed in ppm FꢀR/°C.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated.
It is specified in nV-sec and measured with a full-scale code
change on the data bus.
Output Voltage Settling Time
Output voltage settling time is the amount of time required for
the output to settle to a specified level for a full-scale input change.
A plot for full-scale settling time can be seen in Figure 27.
Power Supply Sensitivity
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage. It is measured
by superimposing a 50 Hz/60 Hz, 200 mV p-p sine wave on the
supply voltages and measuring the proportion of the sine wave
that transfers to the outputs.
Rev. 0 | Page 16 of 32
AD5724/AD5734/AD5754
DC Crosstalk
DAC-to-DAC Crosstalk
This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in LꢀBs.
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and a subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s and vice versa) with
Digital Crosstalk
LDAC
low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-sec.
Digital crosstalk is a measure of the impulse injected into the
analog output of one DAC from the digital inputs of another
DAC, but is measured when the DAC output is not updated.
It is specified in nV-sec and measured with a full-scale code
change on the data bus.
Rev. 0 | Page 17 of 32
AD5724/AD5734/AD5754
THEORY OF OPERATION
REFIN
R
The AD5724/AD5734/AD5754 are quad, 12-/14-/16-bit, serial
input, unipolar/bipolar, voltage output DACs. They operate
from unipolar supply voltages of +4.5 V to +16.5 V or bipolar
supply voltages of 4.5 V to 16.5 V. In addition, the parts have
software-selectable output ranges of +5 V, +10 V, +10.8 V, 5 V,
10 V, and 10.8 V. Data is written to the AD5724/AD5734/
AD5754 in a 24-bit word format via a 3-wire serial interface.
The devices also offer an ꢀDO pin to facilitate daisy-chaining
or readback.
R
R
TO OUTPUT
AMPLIFIER
The AD5724/AD5734/AD5754 incorporate a power-on reset
circuit to ensure that the DAC registers power up loaded with
0x0000. When powered on, the outputs are clamped to 0 V via
a low impedance path.
R
R
ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 38 shows a block diagram of the DAC
architecture. The reference input is buffered before being
applied to the DAC.
Figure 39. Resistor String Structure
REFIN
Output Amplifiers
The output amplifiers are capable of generating both unipolar
and bipolar output voltages. They are capable of driving a load
of 2 kΩ in parallel with 4000 pF to GND. The source and sink
capabilities of the output amplifiers can be seen in Figure 26.
The slew rate is 3.5 V/μs with a full-scale settling time of 10 μs.
REF (+)
RESISTOR
STRING
DAC REGISTER
V
x
OUT
CONFIGURABLE
OUTPUT
REF (–)
AMPLIFIER
GND
OUTPUT
RANGE CONTROL
Reference Buffers
The AD5724/AD5734/AD5754 require an external reference
source. The reference input has an input range of 2 V to 3 V,
with 2.5 V for specified performance. This input voltage is then
buffered before it is applied to the DAC cores.
Figure 38. DAC Architecture Block Diagram
The resistor string structure is shown in Figure 39. It is a string
of resistors, each of value R. The code loaded to the DAC
register determines the node on the string where the voltage is
to be tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
SERIAL INTERFACE
The AD5724/AD5734/AD5754 are controlled over a versatile
3-wire serial interface that operates at clock rates up to 30 MHz.
It is compatible with ꢀPI, QꢀPI™, MICROWIRE™, and DꢀP
standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MꢀB first as a 24-bit word under the control of a serial
clock input, ꢀCLK. The input register consists of a read/write
bit, three register select bits, three DAC address bits, and 16 data
bits. The timing diagram for this operation is shown in Figure 2.
Rev. 0 | Page 18 of 32
AD5724/AD5734/AD5754
Standalone Operation
Daisy-Chain Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous ꢀCLK source can be used
For systems that contain several devices, the ꢀDO pin can be
used to daisy-chain several devices together. Daisy-chain mode
can be useful in system diagnostics and in reducing the number
ꢀYNC
only if
In gated clock mode, a burst clock containing the exact number
ꢀYNC
is held low for the correct number of clock cycles.
ꢀYNC
of serial interface lines. The first falling edge of
write cycle. ꢀCLK is continuously applied to the input shift
ꢀYNC
starts the
of clock cycles must be used, and
must be taken high
register when
is low. If more than 24 clock pulses are
after the final clock to latch the data. The first falling edge of
ꢀYNC
applied, the data ripples out of the shift register and appears on
the ꢀDO line. This data is clocked out on the rising edge of
ꢀCLK and is valid on the falling edge. By connecting the ꢀDO
of the first device to the ꢀDIN input of the next device in the
chain, a multidevice interface is constructed. Each device in the
system requires 24 clock pulses. Therefore, the total number of
clock cycles must equal 24 × N, where N is the total number of
AD5724/AD5734/AD5754 devices in the chain. When the serial
starts the write cycle. Exactly 24 falling clock edges must
ꢀYNC
be applied to ꢀCLK before
ꢀYNC
is brought high again. If
th
is brought high before the 24 falling ꢀCLK edge, the
data written is invalid. If more than 24 falling ꢀCLK edges are
ꢀYNC
applied before
invalid. The input register addressed is updated on the rising
ꢀYNC ꢀYNC
is brought high, the input data is also
edge of
. For another serial transfer to take place,
must be brought low again. After the end of the serial data
transfer, data is automatically transferred from the input shift
register to the addressed register.
ꢀYNC
transfer to all devices is complete,
is taken high. This
latches the input data in each device in the daisy chain and
prevents any further data from being clocked into the input shift
register. The serial clock can be a continuous or a gated clock.
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
updated by taking
ꢀYNC
A continuous ꢀCLK source can only be used if
is held
LDAC
ꢀYNC
low while
is high.
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
AD5724/
AD5734/
AD5754*
*
68HC11
ꢀYNC
be used, and
latch the data.
Readback Operation
must be taken high after the final clock to
SDIN
MOSI
SCK
PC7
PC6
SCLK
SYNC
LDAC
W
Readback mode is invoked by setting the R/ bit = 1 in the
serial input shift register write. (If the ꢀDO output is disabled
via the ꢀDO disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
SDO
MISO
SDIN
W
disabled again). With R/ = 1, Bit A2 to Bit A0 in association
AD5724/
AD5734/
AD5754*
with Bit REG2 to Bit REG0, select the register to be read. The
remaining data bits in the write sequence are don’t care bits.
During the next ꢀPI write, the data appearing on the ꢀDO
output contains the data from the previously addressed register.
For a read of a single register, the NOP command can be used
in clocking out the data from the selected register on ꢀDO. The
readback diagram in Figure 4 shows the readback sequence. For
example, to read back the DAC register of Channel A, the
following sequence should be implemented:
SCLK
SYNC
LDAC
SDO
SDIN
AD5724/
AD5734/
AD5754*
1. Write 0x800000 to the AD5724/AD5734/AD5754 input
register. This configures the part for read mode with the
DAC register of Channel A selected. Note that all the data
bits, DB15 to DB0, are don’t care bits.
SCLK
SYNC
LDAC
SDO
2. Follow this with a second write, a NOP condition, 0x180000.
During this write, the data from the register is clocked out
on the ꢀDO line.
*
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 40. Daisy Chaining the AD5724/AD5734/AD5754
Rev. 0 | Page 1ꢀ of 32
AD5724/AD5734/AD5754
LOAD DAC (LDAC)
CONFIGURING THE AD5724/AD5734/AD5754
When the power supplies are applied to the AD5724/AD5734/
AD5754, the power-on reset circuit ensures that all registers
default to 0. This places all channels in power-down mode. The
first communication to the AD5724/AD5734/AD5754 should be
to set the required output range on all channels (the default range
is the 5 V unipolar range) by writing to the output range select
register. The user should then write to the power control register to
power on the required channels. To program an output value on
a channel, that channel must first be powered up; any writes to a
channel while it is in power-down mode are ignored. The AD5724/
AD5734/AD5754 operate with a wide power supply range. It is
important that the power supply applied to the parts provides
adequate headroom to support the chosen output ranges.
After data has been transferred into the input register of the
DACs, there are two ways to update the DAC registers and DAC
ꢀYNC
LDAC
outputs. Depending on the status of both
and
, one
of two update modes is selected: individual DAC updating or
simultaneous updating of all DACs.
OUTPUT
AMPLIFIER
12-/14-/16-BIT
DAC
REFIN
LDAC
V
OUT
DAC
REGISTER
INPUT
REGISTER
TRANSFER FUNCTION
Table 7 to Table 15 show the relationships of the ideal input code
to output voltage for the AD5754, AD5734, and AD5724, respec-
tively, for all output voltage ranges. For unipolar output ranges,
the data coding is straight binary. For bipolar output ranges, the
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
Figure 41. Simplified Diagram of Input Loading Circuitry for One DAC
2sCOMP
data coding is user-selectable via the BIN/
be either offset binary or twos complement.
pin and can
Individual DAC Updating
LDAC
In this mode,
the input shift register. The addressed DAC output is updated
ꢀYNC
is held low while data is being clocked into
For a unipolar output range, the output voltage expression is
given by
on the rising edge of
Simultaneous Updating of All DACs
LDAC
.
D
2
⎡
⎤
VOUT =VREFIN ×Gain
N
⎢
⎣
⎥
⎦
In this mode,
into the input shift register. All DAC outputs are asynchronously
LDAC ꢀYNC
has been taken high.
is held high while data is being clocked
For a bipolar output range, the output voltage expression is given by
updated by taking
low after
Gain ×VREFIN
D
2
⎡
⎤
VOUT =VREFIN ×Gain
−
N
LDAC
The update now occurs on the falling edge of
.
⎢
⎣
⎥
⎦
2
ASYNCHRONOUS CLEAR (CLR)
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
VREFIN is the reference voltage applied at the REFIN pin.
Gain is an internal gain whose value depends on the output
range selected by the user, as shown in Table 6.
CLR
is an active low clear that allows the outputs to be cleared
to either zero-scale code or midscale code. The clear code value is
user-selectable via the CLR select bit of the control register (see
CLR
the Control Register section). It is necessary to maintain
for a minimum amount of time to complete the operation (see
CLR
low
Figure 2). When the
signal is returned high, the output
Table 6. Internal Gain Values
remains at the cleared value until a new value is programmed.
Output Range (V)
Gain Value
CLR
The outputs cannot be updated with a new value while the
pin is low. A clear operation can also be performed via the clear
command in the control register.
+5
2
+10
+10.8
5
4
4.32
4
10
8
10.8
8.64
Rev. 0 | Page 20 of 32
AD5724/AD5734/AD5754
Ideal Output Voltage to Input Code Relationship—AD5754
Table 7. Bipolar Output, Offset Binary Coding
Digital Input
Analog Output
10 V Output Range
+4 × REFIN × (32,767/32,768)
+4 × REFIN × (32,766/32,768)
…
MSB
1111
1111
…
LSB
1111
1110
…
5 V Output Range
+2 × REFIN × (32,767/32,768)
+2 × REFIN × (32,766/32,768)
…
10.8 V Output Range
+4.32 × REFIN × (32,767/32,768)
+4.32 × REFIN × (32,766/32,768)
…
1111
1111
…
1111
1111
…
1000
1000
0111
…
0000
0000
1111
…
0000
0000
1111
…
0001
0000
1111
…
+2 × REFIN × (1/32,768)
0 V
−2 × REFIN × (1/32,768)
…
+4 × REFIN × (1/32,768)
0 V
−4 × REFIN × (1/32,768)
…
+4.32 × REFIN × (1/32,768)
0 V
−4.32 × REFIN × (32,766/32,768)
…
0000
0000
0000
0000
0000
0000
0001
0000
−2 × REFIN × (32,766/32,768)
−2 × REFIN × (32,767/32,768
−4 × REFIN × (32,766/32,768)
−4 × REFIN × (32,767/32,768)
−4.32 × REFIN × (32,766/32,768)
−4.32 × REFIN × (32,767/32,768)
Table 8. Bipolar Output, Twos Complement Coding
Digital Input
Analog Output
10 V Output Range
+4 × REFIN × (32,767/32,768)
+4 × REFIN × (32,766/32,768)
…
MSB
0111
0111
…
LSB
1111
1110
…
5 V Output Range
+2 × REFIN × (32,767/32,768)
+2 × REFIN × (32,766/32,768)
…
10.8 V Output Range
+4.32 × REFIN × (32,767/32,768)
+4.32 × REFIN × (32,766/32,768)
…
1111
1111
…
1111
1111
…
0000
0000
1111
…
0000
0000
1111
…
0000
0000
1111
…
0001
0000
1111
…
+2 × REFIN × (1/32,768)
0 V
−2 × REFIN × (1/32,768)
…
+4 × REFIN × (1/32,768)
0 V
−4 × REFIN × (1/32,768)
…
+4.32 × REFIN × (1/32,768)
0 V
−4.32 × REFIN × (1/32,768)
…
1000
1000
0000
0000
0000
0000
0001
0000
−2 × REFIN × (32,766/32,768)
−2 × REFIN × (32,767/32,768)
−4 × REFIN × (32,766/32,768)
−4 × REFIN × (32,767/32,768)
−4.32 × REFIN × (32,766/32,768)
−4.32 × REFIN × (32,767/32,768)
Table 9. Unipolar Output, Straight Binary Coding
Digital Input
Analog Output
+10 V Output Range
+4 × REFIN × (65,535/65,536)
+4 × REFIN × (65,534/65,536)
…
MSB
1111
1111
…
LSB
1111
1110
…
+5 V Output Range
+2 × REFIN × (65,535/65,536)
+2 × REFIN × (65,534/65,536)
…
+10.8 V Output Range
+4.32 × REFIN × (65,535/65,536)
+4.32 × REFIN × (65,534/65,536)
…
1111
1111
…
1111
1111
…
1000
1000
0111
…
0000
0000
1111
…
0000
0000
1111
…
0001
0000
1111
…
+2 × REFIN × (32,76ꢀ/65,536)
+2 × REFIN × (32,768/65,536)
+2 × REFIN × (32,767/65,536)
…
+4 × REFIN × (32,76ꢀ/65,536)
+4 × REFIN × (32,768/65,536)
+4 × REFIN × (32,767/65,536)
…
+4.32 × REFIN × (32,76ꢀ/65,536)
+4.32 × REFIN × (32,768/65,536)
+4.32 × REFIN × (32,767/65,536)
…
0000
0000
0000
0000
0000
0000
0001
0000
+2 × REFIN × (1/65,536)
0 V
+4 × REFIN × (1/65,536)
0 V
+4.32 × REFIN × (1/65,536)
0 V
Rev. 0 | Page 21 of 32
AD5724/AD5734/AD5754
Ideal Output Voltage to Input Code Relationship—AD5734
Table 10. Bipolar Output, Offset Binary Coding
Digital Input
Analog Output
10 V Output Range
+4 × REFIN × (81ꢀ1/81ꢀ2)
+4 × REFIN × (81ꢀ0/81ꢀ2)
…
MSB
11
11
…
LSB
1111
1110
…
5 V Output Range
+2 × REFIN × (81ꢀ1/81ꢀ2)
+2 × REFIN × (81ꢀ0/81ꢀ2)
…
10.8 V Output Range
+4.32 × REFIN × (81ꢀ1/81ꢀ2)
+4.32 × REFIN × (81ꢀ0/81ꢀ2)
…
1111
1111
…
1111
1111
…
10
10
01
…
0000
0000
1111
…
0000
0000
1111
…
0001
0000
1111
…
+2 × REFIN × (1/81ꢀ2)
0 V
−2 × REFIN × (1/81ꢀ2)
…
+4 × REFIN × (1/81ꢀ2)
0 V
−4 × REFIN × (1/81ꢀ2)
…
+4.32 × REFIN × (1/81ꢀ2)
0 V
−4.32 × REFIN × (1/81ꢀ2)
…
00
00
0000
0000
0000
0000
0001
0000
−2 × REFIN × (81ꢀ0/81ꢀ2)
−2 × REFIN × (81ꢀ1/81ꢀ1)
−4 × REFIN × (81ꢀ0/81ꢀ2)
−4 × REFIN × (81ꢀ1/81ꢀ2)
−4.32 × REFIN × (81ꢀ0/81ꢀ2)
−4.32 × REFIN × (81ꢀ1/81ꢀ2)
Table 11. Bipolar Output, Twos Complement Coding
Digital Input
Analog Output
10 V Output Range
+4 × REFIN × (81ꢀ1/81ꢀ2)
+4 × REFIN × (81ꢀ0/81ꢀ2)
…
MSB
01
01
…
LSB
1111
1110
…
5 V Output Range
+2 × REFIN × (81ꢀ1/81ꢀ2)
+2 × REFIN × (81ꢀ0/81ꢀ2)
…
10.8 V Output Range
+4.32 × REFIN × (81ꢀ1/81ꢀ2)
+4.32 × REFIN × (81ꢀ0/81ꢀ2)
…
1111
1111
…
1111
1111
…
00
00
11
…
0000
0000
1111
…
0000
0000
1111
…
0001
0000
1111
…
+2 × REFIN × (1/81ꢀ2)
0 V
−2 × REFIN × (1/81ꢀ2)
…
+4 × REFIN × (1/81ꢀ2)
0 V
−4 × REFIN × (1/81ꢀ2)
…
+4.32 × REFIN × (1/81ꢀ2)
0 V
−4.32 × REFIN × (1/81ꢀ2)
…
10
10
0000
0000
0000
0000
0001
0000
−2 × REFIN × (81ꢀ0/81ꢀ2)
−2 × REFIN × (81ꢀ1/81ꢀ2)
−4 × REFIN × (81ꢀ0/81ꢀ2)
−4 × REFIN × (81ꢀ1/81ꢀ2)
−4.32 × REFIN × (81ꢀ0/81ꢀ2)
−4.32 × REFIN × (81ꢀ1/81ꢀ2)
Table 12. Unipolar Output, Straight Binary Coding
Digital Input
Analog Output
MSB
11
11
…
LSB
1111
1110
…
+5 V Output Range
+10 V Output Range
+10.8 V Output Range
+4.32 × REFIN × (16,383/16,384)
+4.32 × REFIN × (16,382/16,384)
…
1111
1111
…
1111
1111
…
+2 × REFIN × (16,383/16,384) +4 × REFIN × (16,383/16,384)
+2 × REFIN × (16,382/16,384) +4 × REFIN × (16,382/16,384)
…
…
10
10
01
…
0000
0000
1111
…
0000
0000
1111
…
0001
0000
1111
…
+2 × REFIN × (81ꢀ3/16,384)
+2 × REFIN × (81ꢀ2/16,384)
+2 × REFIN × (81ꢀ1/16,384)
…
+4 × REFIN × (81ꢀ3/16,384)
+4 × REFIN × (81ꢀ2/16,384)
+4 × REFIN × (81ꢀ1/16,384)
…
+4.32 × REFIN × (81ꢀ3/16,384)
+4.32 × REFIN × (81ꢀ2/16,384)
+4.32 × REFIN × (81ꢀ1/16,384)
…
00
00
0000
0000
0000
0000
0001
0000
+2 × REFIN × (1/16,384)
0 V
+4 × REFIN × (1/16,384)
0 V
+4.32 × REFIN × (1/16,384)
0 V
Rev. 0 | Page 22 of 32
AD5724/AD5734/AD5754
Ideal Output Voltage to Input Code Relationship—AD5724
Table 13. Bipolar Output, Offset Binary Coding
Digital Input
Analog Output
10 V Output Range
MSB
1111
1111
…
LSB
1111
1110
…
5 V Output Range
+2 × REFIN × (2047/2048)
+2 × REFIN × (2046/2048)
…
10.8 V Output Range
+4.32 × REFIN × (2047/2048)
+4.32 × REFIN × (2046/2048)
…
1111
1111
…
+4 × REFIN × (2047/2048)
+4 × REFIN × (2046/2048)
…
1000
1000
0111
…
0000
0000
1111
…
0001
0000
1111
…
+2 × REFIN × (1/2048)
0 V
−2 × REFIN × (1/2048)
…
+4 × REFIN × (1/2048)
0 V
−4 × REFIN × (1/2048)
…
+4.32 × REFIN × (1/2048)
0 V
−4.32 × REFIN × (1/2048)
…
0000
0000
0000
0000
0001
0000
−2 × REFIN × (2046/2048)
−2 × REFIN × (2047/2047)
−4 × REFIN × (2046/2048)
−4 × REFIN × (2047/2048)
−4.32 × REFIN × (2046/2048)
−4.32 × REFIN × (2047/2048)
Table 14. Bipolar Output, Twos Complement Coding
Digital Input
Analog Output
10 V Output Range
+4 × REFIN × (2047/2048)
+4 × REFIN × (2046/2048)
…
MSB
0111
0111
…
LSB
1111
1110
…
5 V Output Range
+2 × REFIN × (2047/2048)
+2 × REFIN × (2046/2048)
…
10.8 V Output Range
+4.32 × REFIN × (2047/2048)
+4.32 × REFIN × (2046/2048)
…
1111
1111
…
0000
0000
1111
…
0000
0000
1111
…
0001
0000
1111
…
+2 × REFIN × (1/2048)
0 V
−2 × REFIN × (1/2048)
…
+4 × REFIN × (1/2048)
0 V
−4 × REFIN × (1/2048)
…
+4.32 × REFIN × (1/2048)
0 V
−4.32 × REFIN × (1/2048)
…
1000
1000
0000
0000
0001
0000
−2 × REFIN × (2046/2048)
−2 × REFIN × (2047/2048)
−4 × REFIN × (2046/2048)
−4 × REFIN × (2047/2048)
−4.32 × REFIN × (2046/2048)
−4.32 × REFIN × (2047/2048)
Table 15. Unipolar Output, Straight Binary Coding
Digital Input
Analog Output
+10 V Output Range
+4 × REFIN × (40ꢀ5/40ꢀ6)
+4 × REFIN × (40ꢀ4/40ꢀ6)
…
MSB
1111
1111
…
LSB
1111
1110
…
+5 V Output Range
+2 × REFIN × (40ꢀ5/40ꢀ6)
+2 × REFIN × (40ꢀ4/40ꢀ6)
…
+10.8 V Output Range
+4.32 × REFIN × (40ꢀ5/40ꢀ6)
+4.32 × REFIN × (40ꢀ4/40ꢀ6)
…
1111
1111
…
1000
1000
0111
…
0000
0000
1111
…
0001
0000
1111
…
+2 × REFIN × (204ꢀ/40ꢀ6)
+2 × REFIN × (2048/40ꢀ6)
+2 × REFIN × (2047/40ꢀ6)
…
+4 × REFIN × (204ꢀ/40ꢀ6)
+4 × REFIN × (2048/40ꢀ6)
+4 × REFIN × (2047/40ꢀ6)
…
+4.32 × REFIN × (204ꢀ/40ꢀ6)
+4.32 × REFIN × (2048/40ꢀ6)
+4.32 × REFIN × (2047/40ꢀ6)
…
0000
0000
0000
0000
0001
0000
+2 × REFIN × (1/40ꢀ6)
0 V
+4 × REFIN × (1/40ꢀ6)
0 V
+4.32 × REFIN × (1/40ꢀ6)
0 V
Rev. 0 | Page 23 of 32
AD5724/AD5734/AD5754
INPUT SHIFT REGISTER
W
The input shift register is 24 bits wide and consists of a read/write bit (R/ ), a reserved bit (zero) that must always be set to 0, three
register select bits (REG0, REG1, REG2), three DAC address bits (A2, A1, A0), and 16 data bits (data). The register data is clocked in MꢀB
first on the ꢀDIN pin. Table 16 shows the register format and Table 17 describes the function of each bit in the register. All registers are
read/write registers.
Table 16. Input Register Format
MSB
DB23
R/W
LSB
DB15 to DB0
Data
DB22
DB21
DB20
DB19
DB18
DB17
DB16
Zero
REG2
REG1
REG0
A2
A1
A0
Table 17. Input Register Bit Functions
Bit Mnemonic
Description
R/W
Indicates a read from or a write to the addressed register.
REG2, REG1, REG0
Used in association with the address bits to determine if a write operation is to the DAC register, the output range
select register, the power control register, or the control register.
REG2
REG1
REG0
Function
0
0
0
0
0
0
1
1
0
1
0
1
DAC register
Output range select register
Power control register
Control register
A2, A1, A0
These DAC address bits are used to decode the DAC channels.
A2
A1
0
A0
0
Channel Address
DAC A
0
0
0
1
DAC B
0
1
0
DAC C
0
1
1
DAC D
1
0
0
All four DACs
DB15 to DB0
Data bits.
DAC REGISTER
The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel where the data transfer
is to take place (see Table 17). The data bits are in positions DB15 to DB0 for the AD5754 (see Table 18), DB15 to DB2 for the AD5734
(see Table 19), and DB15 to DB4 for the AD5724 (see Table 20).
Table 18. Programming the AD5754 DAC Register
MSB
R/W
0
LSB
Zero
REG2
REG1
REG0
A2
A1
A0
DB15 to DB0
0
0
0
0
DAC address
16-bit DAC data
Table 19. Programming the AD5734 DAC Register
MSB
LSB
R/W
Zero
REG2
REG1
REG0
A2
A1
A0
DB15 to DB2
DB1
DB0
0
0
0
0
0
DAC address
14-bit DAC data
X
X
Table 20. Programming the AD5724 DAC Register
MSB
LSB
DB0
X
R/W
Zero
REG2
REG1
REG0
A2
A1
A0
DB15 to DB4
DB3
DB2 DB1
0
0
0
0
0
DAC address
12-bit DAC data
X
X
X
Rev. 0 | Page 24 of 32
AD5724/AD5734/AD5754
OUTPUT RANGE SELECT REGISTER
The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel and the
range bits (R2, R1, R0) select the required output range (see Table 21 and Table 22).
Table 21. Programming the Required Output Range
MSB
R/W
0
LSB
DB0
R0
Zero
REG2
REG1
REG0
A2
A1
A0
DB15 to DB3 DB2
Don’t care R2
DB1
0
0
0
1
DAC address
R1
Table 22. Output Range Options
R2
R1
R0
0
Output Range (V)
0
0
+5
0
0
0
0
1
1
1
0
1
+10
+10.8
5
1
0
0
10
1
0
1
10.8
CONTROL REGISTER
The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the
control function selected. The control register options are shown in Table 23 and Table 24.
Table 23. Programming the Control Register
MSB
LSB
R/W
Zero
REG2 REG1 REG0 A2 A1 A0 DB15 to DB4 DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
1
0
1
NOP, data = don’t care
Clamp enable
Don’t care
TSD enable
CLR select
SDO disable
Clear, data = don’t care
Load, data = don’t care
Table 24. Explanation of Control Register Options
Option
Description
NOP
No operation instruction used in readback operations.
Clear
Load
SDO Disable
CLR Select
Clamp Enable
Addressing this function sets the DAC registers to the clear code and updates the outputs.
Addressing this function updates the DAC registers and, consequently, the DAC outputs.
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
See Table 25 for a description of the CLR select operation.
Set by the user to enable the current-limit clamp. The channel does not power down upon detection of an
overcurrent; the current is clamped at 20 mA (default).
Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent.
TSD Enable
Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown
feature (default).
Table 25. CLR Select Options
Output CLR Value
Bipolar Output Range
CLR Select Setting
Unipolar Output Range
0
1
0 V
Midscale
0 V
Negative full scale
Rev. 0 | Page 25 of 32
AD5724/AD5734/AD5754
POWER CONTROL REGISTER
The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the
power and thermal status of the AD5724/AD5734/AD5754. The power control register options are shown in Table 26 and Table 27.
Table 26. Programming the Power Control Register
MSB
LSB
DB15 to
W
R/
Zero REG2 REG1 REG0 A2 A1 A0 DB11
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
1
0
0
0
0
X
OCD
OCC
OCB
OCA
0
TSD
0
PUD
PUC
PUB
PUA
Table 27. Power Control Register Functions
Option Description
PUA
PUB
PUC
PUD
TSD
DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down
mode (default). If the clamp enable bit of the control register is cleared, DAC A powers down automatically upon detection of an
overcurrent and PUA is cleared to reflect this.
DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down
mode (default). If the clamp enable bit of the control register is cleared, DAC B powers down automatically upon detection of an
overcurrent and PUB is cleared to reflect this.
DAC C power-up. When set, this bit places DAC C in normal operating mode. When cleared, this bit places DAC C in power-down
mode (default). If the clamp enable bit of the control register is cleared, DAC C powers down automatically upon detection of an
overcurrent and PUC is cleared to reflect this.
DAC D power-up. When set, this bit places DAC D in normal operating mode. When cleared, this bit places DAC D in power-down
mode (default). If the clamp enable bit of the control register is cleared, DAC D powers down automatically upon detection of an
overcurrent and PUD is cleared to reflect this.
Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, the four DACs are powered down and this
bit is set.
OCA
OCB
OCC
OCD
DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set.
DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set.
DAC C overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC C, this bit is set.
DAC D overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC D, this bit is set.
Rev. 0 | Page 26 of 32
AD5724/AD5734/AD5754
FEATURES
ANALOG OUTPUT CONTROL
OVERCURRENT PROTECTION
Each DAC channel of the AD5724/AD5734/AD5754 incorporates
individual overcurrent protection. The user has two options for
the configuration of the overcurrent protection: constant current
clamp or automatic channel power-down. The configuration of
the overcurrent protection is selected via the clamp enable bit in
the control register.
In many industrial process control applications, it is vital that the
output voltage be controlled during power-up. When the supply
voltages change during power-up, the VOUT pins are clamped to 0 V
via a low impedance path (approximately 4 kΩ). To prevent the
output amplifiers from being shorted to 0 V during this time,
Transmission Gate G1 is also opened (see Figure 42). These
conditions are maintained until the power supplies have
stabilized and a valid word is written to a DAC register. At this
time, G2 opens and G1 closes.
Constant Current Clamp (Clamp Enable = 1)
If a short circuit occurs in this configuration, the current is
clamped at 20 mA. This event is signaled to the user by the
setting of the appropriate overcurrent (OCX) bit in the power
control register. Upon removal of the short-circuit fault, the
OCX bit is cleared.
VOLTAGE
MONITOR
AND
CONTROL
G1
Automatic Channel Power-Down (Clamp Enable = 0)
V
A
OUT
G2
If a short circuit occurs in this configuration, the shorted
channel powers down and its output is clamped to ground via a
resistance of approximately 4 kΩ. At this time, the output of the
amplifier is disconnected from the output pin. The short-circuit
event is signaled to the user via the overcurrent (OCX) bits, and
the power-up (PUX) bits indicate which DACs have powered
down. After the fault is rectified, the channels can be powered
up again by setting the PUX bits.
Figure 42. Analog Output Control Circuitry
POWER-DOWN MODE
Each DAC channel of the AD5724/AD5734/AD5754 can be
individually powered down. By default, all channels are in
power-down mode. The power status is controlled by the power
control register (see Table 26 and Table 27 for details). When a
channel is in power-down mode, its output pin is clamped to
ground through a resistance of approximately 4 kΩ and the
output of the amplifier is disconnected from the output pin.
THERMAL SHUTDOWN
The AD5724/AD5734/AD5754 incorporate a thermal shutdown
feature that automatically shuts down the device if the core
temperature exceeds approximately 150°C. The thermal shutdown
feature is disabled by default and can be enabled via the TꢀD
enable bit of the control register. In the event of a thermal
shutdown, the TꢀD bit of the power control register is set.
Rev. 0 | Page 27 of 32
AD5724/AD5734/AD5754
APPLICATIONS INFORMATION
+5 V/ 5 V OPERATION
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler® family of products from Analog Devices, Inc., provides
voltage isolation in excess of 2.5 kV. The serial loading structure
of the AD5724/AD5734/AD5754 makes them ideal for isolated
interfaces because the number of interface lines is kept to a
minimum. Figure 43 shows a 4-channel isolated interface to the
AD5724/AD5734/AD5754 using an ADuM1400. For further
information, visit http://www.analog.com/icouplers.
When operating from a single +5 V supply or a dual 5 V supply,
an output range of +5 V or 5 V is not achievable because
sufficient headroom for the output amplifier is not available.
In this situation, a reduced reference voltage can be used. For
example, a 2 V reference voltage produces an output range of
+4 V or 4 V, and the 1 V of headroom is more than enough for
full operation. A standard value voltage reference of 2.048 V can
be used to produce output ranges of +4.096 V and 4.096 V.
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5724/AD5734/AD5754 are mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5724/AD5734/AD5754
are in a system where multiple devices require an AGND-to-
DGND connection, the connection should be made at one
point only. The star ground point should be established as close
as possible to the device.
MICROCONTROLLER
ADuM1400*
V
V
V
V
V
V
V
V
OA
OB
OC
OD
IA
IB
IC
ID
SERIAL CLOCK OUT
ENCODE
DECODE
DECODE
DECODE
DECODE
TO SCLK
TO SDIN
TO SYNC
TO LDAC
SERIAL DATA OUT
SYNC OUT
ENCODE
ENCODE
ENCODE
CONTROL OUT
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 43. Isolated Interface
The AD5724/AD5734/AD5754 should have ample supply bypass-
ing of a 10 μF capacitor in parallel with a 0.1 μF capacitor on
each supply located as close to the package as possible, ideally
right up against the device. The 10 μF capacitor is the tantalum
bead type. The 0.1 μF capacitor should have low effective series
resistance (EꢀR) and low effective series inductance (EꢀI), such
as the common ceramic types, which provide a low impedance
path to ground at high frequencies to handle transient currents
due to internal logic switching.
VOLTAGE REFERENCE SELECTION
To achieve optimum performance from the AD5724/AD5734/
AD5754 over their full operating temperature range, a precision
voltage reference must be used. Thought should be given to the
selection of a precision voltage reference. The voltage applied to
the reference inputs are used to provide a buffered positive and
negative reference for the DAC cores. Therefore, any error in
the voltage reference is reflected in the outputs of the device.
There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, temperature coefficient of the output voltage,
long-term drift, and output voltage noise.
The power supply lines of the AD5724/AD5734/AD5754 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals, such as a data clock, should be shielded with
digital ground to avoid radiating noise to other parts of the
board, and they should never be run near the reference inputs.
A ground line routed between the ꢀDIN and ꢀCLK lines helps
reduce crosstalk between them (this is not required on a multilayer
board that has a separate ground plane, but separating the lines
does help). It is essential to minimize noise on the REFIN line
because any unwanted signals will couple through to the DAC
outputs.
•
Initial accuracy error on the output voltage of an external
reference can lead to a full-scale error in the DAC.
Therefore, to minimize these errors, a reference with low
initial accuracy error specification is preferred. Choosing a
reference with an output trim adjustment, such as the
ADR421, allows a system designer to trim out system
errors by setting the reference voltage to a voltage other
than the nominal. The trim adjustment can also be used to
trim out temperature-induced errors.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough on the board. A microstrip
technique is by far the best method, but it is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to a ground plane, and signal
traces are placed on the solder side.
•
•
The temperature coefficient of a reference output voltage
affects INL, DNL, and TUE. A reference with a tight
temperature coefficient specification should be chosen to
reduce the dependence of the DAC output voltage on
ambient conditions.
Long-term drift is a measure of how much the reference
output voltage drifts over time. A reference with a tight
long-term drift specification ensures that the overall
solution remains relatively stable over its entire lifetime.
Rev. 0 | Page 28 of 32
AD5724/AD5734/AD5754
AD5724/AD5734/AD5754 to Blackfin® DSP Interface
•
Reference output voltage noise needs to be considered in
high accuracy applications that have relatively low noise
budgets. It is important to choose a reference with as low
an output noise voltage as practical for the required system
resolution. Precision voltage references such as the ADR431
(XFET® design) produce low output noise in the 0.1 Hz to
10 Hz range. However, as the circuit bandwidth increases,
filtering the output of the reference may be required to
minimize the output noise.
Figure 44 shows how the AD5724/AD5734/AD5754 can be inter-
faced to the Analog Devices Blackfin DꢀP. The Blackfin has an
integrated ꢀPI port that can be connected directly to the ꢀPI pins
of the AD5724/AD5734/AD5754 and the programmable I/O pins
that can be used to set the state of a digital input such as the
LDAC
pin.
SPISELx
SYNC
SCK
SCLK
SDIN
MOSI
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5724/AD5734/AD5754 is
via a serial bus that uses standard protocol compatible with
microcontrollers and DꢀP processors. The communications
channel is a 3-wire (minimum) interface consisting of a clock
signal, a data signal, and a synchronization signal. The AD5724/
AD5734/AD5754 require a 24-bit data-word with data valid on
the falling edge of ꢀCLK.
AD5724/
AD5734/
AD5754
ADSP-BF531
PF10
LDAC
Figure 44. AD5724/AD5734/AD5754 to Blackfin Interface
For all interfaces, the DAC output update can be initiated
automatically when all the data is clocked in, or it can be
LDAC
performed under the control of
. The contents of the
registers can be read using the readback function.
Table 28. Some Precision References Recommended for Use with the AD5724/AD5734/AD5754
Part No. Initial Accuracy (mV max) Long-Term Drift (ppm typ) Temp Drift (ppm/°C max) 0.1 Hz to 10 Hz Noise (μV p-p typ)
ADR431
ADR421
ADR03
ADR2ꢀ1
AD780
1
1
2.5
2
1
40
50
50
50
20
3
3
3
8
3
3.5
1.75
6
8
4
Rev. 0 | Page 2ꢀ of 32
AD5724/AD5734/AD5754
OUTLINE DIMENSIONS
5.02
5.00
4.95
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
3.25
3.20
3.15
EXPOSED
PAD
(Pins Up)
6.40 BSC
1
BOTTOM VIEW
TOP VIEW
1.05
1.00
0.80
1.20 MAX
PLANE
8°
0°
0.20
0.09
0.15
0.05
0.30
0.19
0.65
BSC
0.75
0.60
0.45
SEATING
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-ADT
Figure 45. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]
(RE-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5724AREZ1
AD5724AREZ-REEL71
AD5734AREZ1
AD5734AREZ-REEL71
AD5754AREZ1
AD5754AREZ-REEL71
AD5754BREZ1
AD5754BREZ-REEL71
Resolution (Bits)
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
TUE
INL
1 LSB
1 LSB
4 LSB
4 LSB
Package Description
24-Lead TSSOP_EP
24-Lead TSSOP_EP
24-Lead TSSOP_EP
24-Lead TSSOP_EP
Package Option
RE-24
RE-24
12
12
14
14
16
16
16
16
0.3% FSR
0.3% FSR
0.3% FSR
0.3% FSR
0.3% FSR
0.3% FSR
0.1% FSR
0.1% FSR
RE-24
RE-24
16 LSB 24-Lead TSSOP_EP
16 LSB 24-Lead TSSOP_EP
16 LSB 24-Lead TSSOP_EP
16 LSB 24-Lead TSSOP_EP
RE-24
RE-24
RE-24
RE-24
1 Z = RoHS Compliant Part.
Rev. 0 | Page 30 of 32
AD5724/AD5734/AD5754
NOTES
Rev. 0 | Page 31 of 32
AD5724/AD5734/AD5754
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06468-0-8/08(0)
Rev. 0 | Page 32 of 32
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