AD6432 [ADI]
GSM 3 V Transceiver IF Subsystem; GSM 3 V收发器IF子系统
| 型号： | AD6432 |
| 厂家： | 
ADI |
| 描述： | GSM 3 V Transceiver IF Subsystem |
| 文件： | 总20页 (文件大小：336K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
GSM 3 V Transceiver IF Subsystem
AD6432
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Fully Compliant with Standard and Enhanced GSM
Specification
BP
DC-350 MHz RF Bandwidths
80 dB Gain Control Range
SAW
I/Q Modulation and Demodulation
Onboard Phase Locked Tunable Oscillator
On-Chip Noise Roofing IF Filters
Ultralow Power Design
PLO
IF
SYNTH
RF
SYNTH
2.7 V–3.6 V Operating Voltage
User-Selectable Power-Down Modes
Small 44-Lead TQFP Package
Interfaces Directly with AD20msp410 and AD20msp415
GSM Baseband Chipsets
PA
AD6432
OP AMP
APPLICATIONS
I/Q Modulated Digital Wireless Systems
GSM Mobile Radios
GSM PCMCIA Cards
GENERAL DESCRIPTION
This reference signal is normally provided by an external
VCTCXO under the control of the radio’s digital signal
processor. The transmit path consists of an I/Q modulator
and buffer amplifier, suitable for carrier frequencies up to
300 MHz and provides an output power of –17.5 dBm in
a 50 Ω system. The quadrature LO signals driving the
I and Q modulator are generated internally by dividing by
two the frequency of the signal presented at the differential
LO port of the AD6432. In both the transmit and receive
paths, onboard filters provide 30 dB of stopband attenuation.
The AD6432 IF IC provides the complete transmit and receive
IF signal processing, including I/Q modulation and demodula-
tion, necessary to implement a digital wireless transceiver such
as a GSM handset. The AD6432 may also be used for other
wireless TDMA standards using I/Q modulation.
The AD6432’s receive signal path is based on the proven archi-
tecture of the AD607 and the AD6459. It consists of a mixer,
gain-controlled amplifiers, integrated roofing filter and I/Q
demodulators based on a PLL. The low noise, high-intercept
variable-gain mixer is a doubly-balanced Gilbert-cell type. It has
a nominal –13 dBm input-referred 1 dB compression point and
a 0 dBm input-referred third-order intercept.
The AD6432 comes in a 44-lead plastic thin quad flatpack
(TQFP) surface mount package.
The gain-control input accepts an external control voltage input
from an external AGC detector or a DAC. It provides an 80 dB
gain range with 27.5 mV/dB gain scaling, where the mixer and
the IF gains vary together.
The I and Q demodulators provide inphase and quadrature
baseband outputs to interface with Analog Devices’ AD7015
and AD6421 (GSM, DCS1800, PCS1900) baseband convert-
ers. An onboard quadrature VCO, externally phase-locked to
the IF signal, drives the I and Q demodulators. The quadrature
phase-locked oscillator (QPLO) requires no external compo-
nents for frequency control or quadrature generation, and de-
modulates signals at standard GSM system IFs of 13 MHz, or
26 MHz with a reference input frequency of 13 MHz; or, in
general, 1X or 2X the reference frequency. Maximum reference
frequency is 25 MHz.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1997
(T = +25؇C, V = 3.0 V, GREF = 1.25 V unless otherwise noted)
AD6432–SPECIFICATIONS
A
P
Parameter
Conditions
Min
Typ
Max
Units
RX RF MIXER
RF Input Frequency
350
MHz
dB
dBm
dBm
AGC Conversion Gain Variation
Input 1 dB Compression Point
Input Third-Order Intercept
SSB Noise Figure
Z
IN = 150 Ω: 0.2 V < VGAIN < 2.4 V
–3 to +15
–13
0
At VGAIN = 2.4 V, ZIN = 150 Ω
At VGAIN = 0.2 V, RFIN = –25 dBm
At ZIN = 150 Ω, FRF = 246 MHz,
FLO = 272 MHz, VGAIN = 0.2 V
10
dB
RX IF AMPLIFIER
AGC Gain Variation
Input Resistance
0.2 V < VGAIN < 2.4 V
at VGAIN = 0.2 V
–14 to 48
5
dB
kΩ
MHz
Operating Frequency Range
10
50
GAIN CONTROL
Total Gain Control Range
Control Voltage Range at GAIN
Gain Scaling
Gain Law Conformance
Bias Current at GREF
Input Resistance at Gain
Mixer+IF+Demod, 0.2 V < VGAIN < 2.4 V
80
dB
V
mV/dB
dB
µA
kΩ
0.2
2.4
27.5
±0.1
–0.5
20
INTEGRATED IF FILTER
BPF Center Frequency
IFS0 = 1
f
REF = 13 MHz
“0” = Connect to Ground, “1” = Connect to VP
“0” = Connect to Ground, “1” = Connect to VP
13
26
MHz
MHz
IFS0 = 0
BPF –3 dB BW
IFS0 = 1
IFS0 = 0
fREF = 13 MHz
“0” = Connect to Ground, “1” = Connect to VP
“0” = Connect to Ground, “1” = Connect to VP
5
10
MHz
MHz
I AND Q DEMODULATOR
Demodulation Gain
Output Voltage Range
17
dB
V
Differential
0.3
VPOS – 0.2
Output Voltage Common-Mode Level Not Power Supply Independent
1.5
V
Output Offset Voltage
Error in Quadrature
Amplitude Match
I/Q Output BW
Differential, VGAIN = GREF
Differential from I to Q, IF = 13 MHz
–150
+150
3.5
mV
Degrees
dB
MHz
kΩ
1
0.25
3
C
LOAD = 10 pF
Output Resistance
Each Pin
4.7
QUADRATURE IF PLL
Operating Frequency Range
Reference Frequency Voltage Level
Reference Frequency Range
Acquisition Time
10
50
25
MHz
mV p-p
MHz
µs
200
80
Using 1 kΩ, 1 nF Loop Filter
TRANSMIT MODULATOR
Carrier Output Frequency
Output Power
300
MHz
R
F
LOAD = 150 Ω, Power at Final 50 Ω,
IF = 272 MHz
RLOAD = 150 Ω (Differential)
–17.5
14
2.056
1.2
1
dBm
dBm
V p-p
V
MHz
kΩ
Input 1 dB Compression Point
I/Q Input Signal Amplitude
I/Q Input Signal Required DC Bias
I/Q Input BW
Differential
I/Q Input Resistance
100
I/Q Phase Balance
With LOs 2nd Harmonic 30 dBc
Bellow Fundamental
±1.5
Degrees
I/Q Amplitude Balance
With LOs 2nd Harmonic 30 dBc
Bellow Fundamental
±0.1
dB
Output Harmonic Content
R
LOAD = 150 Ω
–45 (3rd)
–65 (5th)
–33
dBc
dBc
dBc
dBc
Carrier Feedthrough
Sideband Suppression
FCARRIER = 272 MHz
I and Q Inputs Driven In Quadrature
–37
REV. 0
–2–
AD6432
Parameter
Conditions
Min
Typ Max
Units
LO PORT (LOLO and LOHI)
Input Frequency
Input Signal Voltage Range
Input Resistance
200
200
600
500
MHz
mV p-p
Ω
Differential
Input Pull-Up Resistors to VPOS (Each Pin)
AUXILIARY OP AMPLIFIER
Small Signal –3 dB Bandwidth
Input Signal Voltage Range
Input Offset Voltage
Input Bias Current
Output Signal Voltage Range
50
MHz
V
mV
nA
V
0.1
V
POS – 2.1
±4
–150
With RLOAD > 4 kΩ
0.1
2.7
VPOS – 0.2
3.6
POWER CONSUMPTION
Supply Voltage
3
V
Transmit Mode
Receive Mode
Sleep Mode
13
13
< 5
mA
mA
µA
At VGAIN = 1.2 V
OPERATING TEMPERATURE RANGE
–25
+85
°C
NOTES
All reference to dBm is relative to 50 Ω.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
PIN CONFIGURATION
Supply Voltage VPDV, VPPX, VPDM, VPFL, VPPC, VPRX,
to CMTX, CMRX, CMIF, CMD . . . . . . . . . . . . . . +3.6 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . 600 mW
Operating Temperature Range . . . . . . . . . . . –25°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering (60 sec) . . . . . . . . . . . +300°C
44 43 42 41 40 39 38 37 36
34
35
1
2
33
32
31
GND
MODO
VPDV
CMTX
LOLO
LOHI
FREF
GND
IFS0
3
NOTES
4
30 CMDM
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Thermal Characteristics: 44-lead TQFP package: θJA = 126°C.
FLTR
VPFL
VPDM
5
29
28
27
AD6432
TOP VIEW
(Pins Down)
6
7
CMRX
GND
26 IRXP
25 IRXN
8
9
RFLO
RFHI
GND
10
11
24
23
QRXP
QRXN
20
14 15 16 17 18 19
13
21 22
12
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option*
Model
AD6432AST –25°C to +85°C
44-Pin Plastic ST-44
TQFP
*ST = Thin Quad Flatpack.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6432 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD6432
PIN FUNCTION DESCRIPTIONS
Function
Pin
Label
Description
1
2
3
4
5
6
7
8
GND
PCB Ground
TX Modulator Output
Not Bonded to IC
AC Coupled, Drives 150 Ω into 50 Ω
VPOS
MODO
VPDV
CMTX
LOLO
LOHI
CMRX
GND
LO2 Divided by 2 Supply Voltage
On-Chip TX Mixer Common
Differential RX Mixer LO2 Input Negative
Differential RX Mixer LO2 Input Positive
On-Chip RX Mixer Common
PCB Ground
Ground
AC Coupled, VPOS to VPOS – 100 mV
AC Coupled, VPOS – 100 mV to VPOS
Ground
Not Bonded to IC
9
RFLO
RFHI
GND
Differential RX Mixer IF1 Input Negative
Differential RX Mixer IF1 Input Positive
PCB Ground
AC Coupled
AC Coupled
Not Bonded to IC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VPRX
MXHI
MXLO
CMIF
IFLO
RX Section Supply Voltage
VPOS
See Figure 30
See Figure 30
Ground
AC Coupled
AC Coupled
Ground
Off = Low < 0.6 V, On = High > 2.5 V
0.2 V–2.4 V Using 3 V Supply. Max Gain at 0.2 V
1.2 V typ
Differential RX IF1/IF2 Mixer Output Positive
Differential RX IF1/IF2 Mixer Output Negative
On-Chip RX IF2 Common
Differential RX IF2 Input Negative
Differential RX IF2 Input Positive
On-Chip RX IF2 Common
RX Enable (Power-Up)
RX VGA Gain Control Input
RX VGA Reference Voltage
IFHI
CMIF
RXPU
GAIN
GREF
GND
QRXN
QRXP
IRXN
IRXP
VPDM
VPFL
FLTR
CMDM
IFS0
PCB Ground
Not Bonded to IC
Differential Demodulator Q Output Negative
Differential Demodulator Q Output Positive
Differential Demodulator I Output Negative
Differential Demodulator I Output Positive
Demodulator Supply Voltage
I/Q LO PLL Filter Cap. Supply Voltage
I/Q LO PLL Filter
On-Chip Demodulator Common
IF2 Frequency Select Bit
Internal 4.7 kΩ Resistor in Series with the Output
Internal 4.7 kΩ Resistor in Series with the Output
Internal 4.7 kΩ Resistor in Series with the Output
Internal 4.7 kΩ Resistor in Series with the Output
VPOS
To VPOS with Good Decoupling
Referenced to VPFL
Ground
“0” = Low < 0.6 V, “1” = High > 2.5 V
Not Bonded to IC
AC Coupled. Use 200 mV p-p Input Signal
VPOS
Active when TXPU Is High
Not Bonded to IC
0.1 V to VPOS – 2.1 V
0.1 V to VPOS – 2.1 V
Low < 0.6 V, High > 2.5 V
DC Coupled, 1.2 V ± 514 mV
DC Coupled, 1.2 V ± 514 mV
DC Coupled, 1.2 V ± 514 mV
DC Coupled, 1.2 V ± 514 mV
VPOS
GND
PCB Ground
FREF
VPPC
PCAO
GND
PCAM
PCAP
TXPU
QTXN
QTXP
ITXN
ITXP
Reference Input (13 MHz for GSM)
Auxiliary Op Amp Supply Voltage
Auxiliary Op Amp Output
PCB Ground
Differential Auxiliary Op Amp Input Negative
Differential Auxiliary Op Amp Input Positive
TX Enable (Power-Up)
Differential Modulator Q Input Negative
Differential Modulator Q Input Positive
Differential Modulator I Input Negative
Differential Modulator I Input Positive
TX Section Supply Voltage
VPTX
REV. 0
–4–
AD6432
R30
49.9Ω
PCAP
TXPU
QTXN
C9
F
0
R11
1kΩ
VS1
R10
500Ω
QTXP
ITXN
PCAM
R39
OPEN
R12
0Ω
VS1
R25
1kΩ
R34
0Ω
C28
0
C5
0.0F
F
VPTX
PCAO
DECOUPLING
R8
0Ω
ITXP
VS2
VPPC
C11
0.0
C32
0
F
F
MODO
DECOUPLING
R9
84Ω
R23
123Ω
R2
0Ω
C15
VS1
100pF
44 43 42 41 40 39 38
36
34
35
37
C36
1000pF
C29
0
C14
0.0F
F
1
33
32
31
VPDV
GND
FREF
FREF
VS1
DECOUPLING
R32
2
3
GND
IFS0
MODO
49.9Ω
IFS0
VPDV
CMTX
LOLO
LOHI
C10
1000pF
R7
0Ω
R1
1kΩ
T1
6
C18
4
30 CMDM
1
2
3
LOLO
0
F
FLTR
VPFL
VPDM
5
29
28
27
R14
249Ω
AD6432
TOP VIEW
C23
0.0
6
4
F
7
CMRX
GND
(Pins Down)
26 IRXP
25 IRXN
8
R6
C1
100pF
9
0Ω
RFLO
RFHI
GND
RFHI
10
11
24
23
QRXP
QRXN
C41
0.0
C17
0F
C2
100pF
R3
49.9Ω
F
20
13
21 22
12
14 15 16 17 18 19
IRXP
IRXN
QRXP
C6
47pF
J1
GREF
GAIN
VS2
C39
0.0
TXPU
C7
4
F
VS1
F
R31
C3
0.0
C30
0
C8
47pF
0Ω
F
F
J3
J4
QXRN
C40
0.0
C43
0.04
IFS0
GREF
GAIN
GND
F
F
MXHI
RXPU
RXPU
IFHI
C44
0.04
F
J5
VS1
MXLO
C7
F
C4
0.04
C7
0.04
4
F
F
IFLO
R5
49.9Ω
R4
49.9Ω
Figure 1. Characterization Board
REV. 0
–5–
AD6432
QTXN
QTXP
R9 R10
25Ω 10kΩ
R17
10kΩ
14
13
1
2
3
4
5
6
7
R11
10kΩ
R2
R1
10kΩ
10kΩ
QTX
VDC
ITX
R15 R20
R22
10kΩ 25Ω
50Ω
12
R3
R8
C2 1pF
C1 0.1µF
VP
AD824
20kΩ
20kΩ
VDC
VP
VN 11
10
R16 R19
10kΩ 25Ω
R6
20kΩ
R4
20kΩ
VN
9
R5
10kΩ
R21
50Ω
R14
R7
10kΩ
10kΩ
8
R18
10kΩ
R12 R13
25Ω 10kΩ
VDC
VP
ITXP
ITXN
VGREF
R29
10kΩ
1
2
V+
AD1580
NC
C13
0.1µF
AD830
Gm
3
4
3
2
1
5
VN
V
N
C4
0.1µF
V–
6
R23
50Ω
A=1
7
IRXN
IRXP
IRX
INTERFACE BOX TO TEST INSTR
ITX
Gm
8
C3
V
P
VP
IFIN
0.1µF
QTX
FREF
IRX
AD830
4
3
2
1
5
VN
VP
V
N
MODO
LOIP
C5
Gm
0.1µF
6
R24
A=1
QRX
50Ω
7
QRXN
QRXP
QRX
Gm
RFHI
PCAP
PCAO
8
C6
V
P
0.1µF
MXOUT
AD830
VS1
2
4
3
2
1
5
VN
VP
V
N
TXPU
RXPU
C8
Gm
3
0.1µF
VS2
GND
VP
6
R30
20kΩ
R25
50Ω
A=1
1
7
MXLO
MXHI
MXOUT
Gm
2
1
8
C7
V
P
VN
3
R31
20kΩ
0.1µF
GAIN
V
P
C9
0.1µF
1
2
3
4
8
7
R27
Gm
50Ω
INTERFACE BOX TO CHAR BOARD
IFHI
ITXP
RFHI
MXHI
MXLO
IFLO
IFHI
IRXP
A=1
6
5
Gm
AD830
ITXN
IRXN
V
V
N
C11
IFIN
0.1µF
R26
50Ω
QTXP
QTXN
MODO
LOIP
QRXP
QRXN
PCAP
PCAO
P
C10
0.1µF
V
1
2
3
4
8
7
6
5
R28
50Ω
P
Gm
Gm
IFLO
A=1
FREF
V
V
N
N
AD830
C12
0.1µF
J1
VS2
IFS1
GND
TXPU
GAIN
GREF
GND
IFS0
NOTES:
VP
VP = +5V
VN = –5V
RXPU
VS1
IFS0
Figure 2. Characterization Test Set
–6–
REV. 0
AD6432
11
10.5
10
9.5
9
20
15
10
5
R
R
= 50Ω, IF = 45MHz
= 50Ω, IF = 26MHz
IN
V
= 0.2V
GAIN
IN
8.5
8
R
= 400Ω, IF = 13MHz
R
= 50Ω, IF = 13MHz
IN
IN
V
= 1.5V
= 2.4V
GAIN
7.5
7
0
V
6.5
6
GAIN
–5
150
200
250
300
350
400
450
10
14
18
22
26
30
34
38
42
46
50
IF FREQUENCY – MHz
RF FREQUENCY – MHz
Figure 6. Mixer Conversion Gain vs. IF Frequency,
TA = +25°C, VPOS = 3 V, VGREF = 1.2 V, FRF = 250 MHz
Figure 3. Rx Mixer Noise Figure vs. RF Frequency,
TA = +25°C, VPOS = 3 V, VGREF = 1.2 V, VGAIN = 0.2 V
900
800
700
600
500
400
300
200
100
70
5.0
4.5
4.0
3.5
R
V
S
= 2.4V
C
V
AMP/DEMOD, V
POS
= 2.7V TO 3.6V
GAIN
S
60
50
40
30
20
10
= 0.2V
GAIN
R
S
V
= 1.2V
GAIN
C
S
V
= 1.2V
GAIN
R
S
V
= 0.2V
GAIN
C
V
S
= 2.4V
GAIN
3.0
2.5
MIXER, V
POS
= 2.7V TO 3.6V
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
50
100 150 200 250 300 350 400 450 500 550
FREQUENCY – MHz
TEMPERATURE
C
Figure 7. Rx Mixer Conversion Gain and IF Amplifier/
Demodulator Gain vs. Temperature, VGAIN = 0.2 V,
Figure 4. Rx Mixer Input Impedance vs. RF Frequency,
VPOS = 3 V, TA = +25°C, VGREF = 1.2 V
VGREF = 1.2 V, FIF = 26 MHz, FRF = 250 MHz
–10
16
14
–11
–12
–13
–14
–15
–16
V
= 2.7V, T = +8C
A
V
= 0.2V
POS
12
10
8
GAIN
V
= 2.7V, T = +2C
POS
A
6
V
= 3.6V, T = +8C
A
POS
4
V
= 1.5V
= 2.4V
2
GAIN
V
= 2.7V, T = –2C
A
POS
0
–2
–4
–6
V
= 3.6V, T = –4C
A
POS
V
GAIN
275
RF FREQUENCY – MHz
0
0.5
1.0
1.5
– Volts
2.0
2.5
150
175
200
225
250
300
325
350
V
GAIN
Figure 8. Rx Mixer Input 1 dB Compression Point vs.
VGAIN, VGREF = 1.2 V, FRF = 250 MHz, FIF = 26 MHz
Figure 5. Rx Mixer Conversion Gain vs. RF Frequency,
TA = +25°C, VPOS = 3 V, VGREF = 1.2 V, FIF = 26 MHz
REV. 0
–7–
AD6432
0.4
0.3
0.2
0.1
0
70
60
50
40
30
20
10
0
V
= 0.2V
= 0.5V
GAIN
V
GAIN
IF AMP/DEMOD
V
= 1.5V
= 2.4V
GAIN
MIXER
–0.1
–0.2
V
GAIN
–10
10
0
0.5
1.0
V
1.5
– Volts
2.0
2.5
15
20
25
30
35
40
45
INTERMEDIATE FREQUENCY – MHz
GAIN
Figure 9. IF Amplifier and Demodulator Gain vs. IF
Frequency, TA = +25°C, VPOS = 3 V, VGREF = 1.2 V
Figure 12. Gain Error vs. Gain Control Voltage, TA = +25°C,
VPOS = 3 V, VGREF = 1.2 V, FRF = 250 MHz, FIF = 26 MHz
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
13000
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
0.6
0.4
R
V
S
0.2
C
V
= 2.4V
S
GAIN
= 0.2V
GAIN
0
C
V
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
S
= 1.2V
GAIN
C
V
S
R
V
S
= 2.4V
= 0.2V
GAIN
= 1.2V
GAIN
R
S
V
GAIN
10
15
20
25
30
35
40
45
50
10
15
20
25
30
35
40
45
IF INPUT FREQUENCY – MHz
DEMODULATOR VCO FREQUENCY – MHz
Figure 10. IF Amplifier Input Impedance vs. Frequency,
TA = +25°C, VPOS = 3 V, VGREF = 1.2 V
Figure 13. Demodulator Quadrature Error vs. FREF
Frequency, TA = +25°C, VPOS = 3 V
0
–10
–20
–30
–40
–50
–60
–80
–85
–90
IF = 26MHz
–95
–100
–105
IF = 13MHz
–110
0
0.5
1.0
V
1.5
– Volts
2.0
2.5
0.1
1.0
10
100
1000
FREQUENCY OFFSET – kHz
GAIN
Figure 14. PLL Phase Noise vs. Frequency, VPOS = 3 V,
FLTR =1 nF, RFLTR =1 kΩ, FREF = 13 MHz
Figure 11. IF Amplifier/Demodulator Input 1 dB
Compression Point vs. VGAIN , FIF = 26 MHz,
C
VGREF = 1.2 V, TA = +25°C, VPOS = 3 V
REV. 0
–8–
AD6432
16
14
12
10
8
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
T
= –4C
A
6
T
A
= +2C
4
2
T
= +8C
A
0
–2
–4
0
0.5
1.0
V
1.5
– Volts
2.0
2.5
10
15
20
25
30
35
40
45
50
GAIN
FREQUENCY OF VCO – MHz
Figure 18. Rx Mixer Conversion Gain vs VGAIN, TA = +25°C,
VPOS = 3 V, FRF = 250 MHz, FIF = 26 MHz, VGREF = 1.2 V
Figure 15. PLL Loop Voltage at FLTR Pin (KVCO) vs.
Frequency
–10
–20
–30
–40
–50
–60
–70
70
60
50
40
30
20
10
0
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
V
1.5
– Volts
2.0
2.5
GAIN VOLTAGE – Volts
GAIN
Figure 16. System (Mixer + IF LC Filter + IF Amplifier +
Demodulator) 1 dB Compression Point vs. VGAIN, TA = +25°C,
VPOS = 3 V, FRF = 250 MHz, FIF = 26 MHz, VGREF = 1.2 V
Figure 19. IF Amplifier/Demodulator Gain vs. VGAIN,
TA = +25°C, VPOS = 3 V, FRF = 250 MHz, FIF = 26 MHz,
VGREF = 1.2 V
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
–70
0
0
0.5
1.0
1.5
2.0
2.5
0
0.5
1.0
1.5
2.0
2.5
GAIN VOLTAGE – Volts
GAIN VOLTAGE – Volts
Figure 17. System (Mixer + IF LC Filter + IF Amplifier +
Demodulator) IP3 vs. VGAIN, TA = +25°C, VPOS = 3 V,
FIF = 26 MHz, FRF = 250 MHz, VGREF = 1.2 V
Figure 20. System (Mixer + IF LC Filter + IF Amplifier +
Demodulator) Gain vs. VGAIN, TA = +25°C, VPOS = 3 V,
F
IF =26 MHz, FRF = 250 MHz, VGREF = 1.2 V
REV. 0
–9–
AD6432
–16.0
–16.5
–17.0
–17.5
–18.0
–18.5
–19.0
–19.5
–20.0
–35.0
–35.5
–36.0
–36.5
–37.0
–37.5
–38.0
–38.5
–39.0
–39.5
–40.0
–40
–20
0
20
40
60
80
100
100 120 140 160 180 200 220 240 260 280 300
TEMPERATURE
C
CARRIER FREQUENCY – MHz
Figure 21. Tx Desired Sideband Gain vs. Temperature,
TA = +25°C, VPOS = 3 V, FCARRIER = 280 MHz, I and Q Inputs
Driven in Quadrature
Figure 24. Tx Typical Undesired Sideband Suppression
vs. FCARRIER, TA = +25°C, VPOS = 3 V
–13.5
–14.0
–14.5
–15.0
–15.5
–16.0
–16.5
–17.0
–17.5
–18.0
–18.5
22
V
= 3.6V, T = +8C
A
POS
20
18
16
14
12
10
V
= 2.7V, T = +8C
POS
A
V
= 3.6V, T = +2C
A
POS
V
= 3V, T = +2C
A
POS
V
= 2.7V, T = +2C
POS
A
V
T
= 3.6V
POS
V
= 2.7V
= –4C
POS
A
T
= –4C
A
–19.0
100 120 140 160 180 200 220 240 260 280 300
0
0.5
1.0
1.5
2.0
2.5
GAIN VOLTAGE – Volts
CARRIER FREQUENCY – MHz
Figure 22. Tx Desired Sideband Gain vs. FCARRIER
,
Figure 25. Rx Mode Supply Current vs. VGAIN, VGREF = 1.2 V
TA = +25°C, VPOS = 3 V
–35.0
–35.5
–36.0
–36.5
–37.0
–37.5
–38.0
–38.5
–39.0
–39.5
–40.0
15.0
14.5
V
= 3.6V
POS
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
V
= 3V
POS
V
= 2.7V
POS
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE
C
TEMPERATURE
C
Figure 23. Tx Typical Undesired Sideband Suppression
vs. Temperature, TA = +25°C, VPOS = 3 V
Figure 26. Tx Mode Supply Current vs. Temperature
REV. 0
–10–
AD6432
PRODUCT OVERVIEW
Figure 27 shows the main sections of the AD6432. In the re-
ceive path, it consists of a variable-gain UHF mixer and linear
two-stage IF strip, both of which together provide a calibrated
voltage-controlled gain range of more than 80 dB, followed by a
tunable IF bandpass filter and dual quadrature demodulators.
These are driven by inphase and quadrature clocks generated
by a Phase-Locked Loop (PLL) locked to a corrected external
reference. In the transmit path it consists of a quadrature modu-
lator followed by a low-pass filter. The quadrature modulator is
driven by quadrature frequencies that are generated internally
by dividing the external local oscillator frequency by two. A
CMOS-compatible power-down interface completes the AD6432.
The AD6432 provides most of the active circuitry required to
realize a complete low power, single-conversion superhetero-
dyne time division transceiver, or the latter part of a double-
conversion transceiver, at input receive frequencies up to
350 MHz with an IF from 10 MHz to 50 MHz and transmit
frequencies up to 300 MHz. The internal I/Q demodulators,
with their associated phase-locked loop and the internal I/Q
modulator, support a wide variety of modulation modes, includ-
ing n-PSK, n-QAM, and GMSK. A single positive supply volt-
age of 3 V is required (2.7 V minimum, 3.6 V maximum) at a
typical supply current of 13 mA at midgain in receive mode and
13 mA in transmit mode. In the following discussion, VPOS will
be used to denote the power supply voltage, which will be as-
sumed to be 3 V.
4.7kΩ
25
26
IRXN
IRXP
4.7kΩ
IFIP
IFIM
MXOP
10
9
13
14
16
17
RFHI
LC
3MHz
BANDPASS
FILTER
4.7kΩ
4.7kΩ
23
24
QRXN
QRXP
RFLO
MXOM
9
QUADRATURE
VCO
DIVIDE BY
1 OR 2
31
IFS0
33
29
FREF
FLTR
PHASE
DETECTOR
20
21
GAIN
GAIN TEMP. COMPENSATION
GREF
6
5
LOHI
19 RXPU
39 TXPU
2
RX, TX
BIAS
9
AD6432
LOLO
42
43
ITXN
ITXP
2
MODO
PCAO
40 QTXN
41
QTXP
38 PCAP
37 PCAM
35
Figure 27. Functional Block Diagram
REV. 0
–11–
AD6432
Receive Mixer
250Ω
MXOP
MXOM
The UHF mixer is an improved Gilbert-cell design that can
operate from low frequencies (it is internally dc-coupled) up to
an RF input of 350 MHz. The dynamic range at the input of the
mixer is determined, at the upper end, by the maximum input
signal level of ±71 mV (–13 dBm in 50 Ω between RFHI and
RFLO) up to which the mixer remains linear and, at the lower
end, by the noise level. It is customary to define the linearity of
a mixer in terms of the 1 dB gain-compression point and third-
order intercept, which for the AD6432 are –13 dBm and 0 dBm,
respectively, in a 50 Ω system.
VPRX
250Ω
Figure 30. Mixer Output Port
IF Amplifier
Most of the gain in the AD6432 receive section is provided by
the IF amplifier strip, which comprises two stages. Both are fully
differential and each has a gain span of 31 dB for the AGC volt-
age range of 0.2 V to 2.4 V. Thus, in conjunction with the vari-
able gain of the mixer, the total gain span is 80 dB. The overall IF
gain varies from –14 dB to +48 dB for the nominal AGC voltage of
0.2 V to 2.4 V. Maximum gain is at VGAIN = 0.2 V.
The mixer’s RF input port is differential, that is, pin RFLO is
functionally identical to RFHI, and these nodes are internally
biased. The RF port can be modeled as a parallel RC circuit as
shown in Figure 29. The local oscillator input of the receive
mixer is internally provided by the LO divided by two.
The IF input is differential, at IFHI and IFLO. Figure 32 shows
a simplified schematic of the IF interface modeled as parallel
RC network.
RFHI
R
C
SH
SH
The operative range of the IF amplifier is approximately 50 MHz
from IFHI and IFLO through the demodulator.
RFLO
IFHI
Figure 28. Mixer Port Modeled as a Parallel RC Network
At VGAIN = 1.2 V and FRF = 250 MHz, CSH = 3.5 pF and
RSH = 400 Ω (See Figure 4)
C
R
SH
SH
IFLO
The output of the mixer is differential. The nominal conversion
gain is specified for operation into a 26 MHz LC IF bandpass
filter, as shown in Figure 29 and Table I.
Figure 31. IF Amplifier Port Modeled as a Parallel RC
Network for VGAIN = 1.2 V and FIF = 26 MHz, CSH = 3 pF,
RSH = 8.5 kΩ (See Figure 10)
C1
IFIP
MXOP
Gain Scaling
The overall gain of the AD6432, expressed in decibels, is linear
with respect to the AGC voltage VGAIN at Pin GAIN. The gain
of all sections is maximum when VGAIN is 0.2, and falls off as the
bias is increased to VGAIN = 2.4 V and is independent of the
power supply voltage. The gain of all stages changes simulta-
neously. The AD6432’s gain scaling is also temperature-
compensated. Note that GAIN pin of the AD6432 is an input
driven by an external low impedance voltage source, normally a
DAC, under the control of radio’s digital processor.
C2
L1
C1
IFIM
MXOM
Figure 29. Suggested IF Filter Inserted Between the
Mixer’s Output Port and the Amplifier’s Input Port
The gain-control scaling is directly proportional to the reference
voltage applied to the Pin GREF and is independent of the
power supply voltage. When this input is set to the nominal
value of 1.2 V, the scale is nominally 27.5 mV/dB (36.4 dB/V).
Under these conditions, 80 dB of gain range (mixer plus IF)
corresponds to a control voltage of 0.2 V < = VG < = 2.4 V. The
final centering of this 2.2 V range depends on the insertion losses of
the IF filters used.
The conversion gain is measured between the mixer input and
the input of this filter, and varies between –3 dB and +15 dB.
Table I. Filter Component Values for Selected Frequencies
Frequency
C1
L1
C2
13 MHz
26 MHz
27 pF
22 pF
0.82 µH
0.39 µH
180 pF
82 pF
Pin GREF can be tied to an external voltage reference, VREF
,
provided, for example, by a AD1580 (1.21 V) voltage reference.
The maximum permissible signal level between MXOP and
MXOM is determined by the maximum gain control voltage.
The mixer output port, having pull-up resistors of 250 Ω to
VPRX, is shown in Figure 30.
When using the Analog Devices AD7013 (IS54, TETRA and
satellite receiver applications) and AD7015 or AD6421 (GSM,
DCS1800, PCS1900) baseband converters, the external refer-
ence may also be provided by the reference output of the
REV. 0
–12–
AD6432
integral sample-hold system ensures that the frequency-
baseband converters. The interface between the AD6432 and
the AD6421 baseband converter is shown in Figure 35. The
AD7015 baseband converter provides a VR of 1.23 V; an auxil-
iary DAC in the AD7015 can be used to generate the AGC
voltage. Since it uses the same reference voltage, the numerical
input to this DAC provides an accurate RSSI value in digital
form, no longer requiring the reference voltage to have high
absolute accuracy.
control voltage on Pin FLTR remains held during power-
down, so reacquisition of the carrier occurs in less than
80 µs.
In practice, the probability of a phase mismatch at power-
up is high, so the worst-case linear settling period to full
lock needs to be considered in making filter choices. This
is typically < 80 µs for a locking error of ±3° at an IF of
26 MHz. Note that the VFQO always provides quadrature
between its own I and Q outputs, but the phasing between
it and the reference carrier will swing around the final value
during the PLL’s settling time.
Tunable Filter and I/Q Demodulators
The demodulators (I and Q) receive their inputs internally from
the IF amplifier through a two-pole tunable-frequency bandpass
filter. This filter is centered on the IF frequency and its band-
width is approximately equal to forty per cent of the IF fre-
quency. The filter attenuates the amount of noise present at the
input of the demodulators.
I and Q Transmit Modulator
The transmit modulator uses two standard mixer cells
whose linear inputs are the differential voltages at the input
Pins ITXP/ITXN and QTXP/QTXN, respectively and whose
local oscillator inputs are derived from a divide-by-two cell,
driven from the input applied to pins LOHI/LOLO. The
outputs of the mixers are summed and converted to single-
sided form. The output stage also filters the higher harmon-
ics, minimizing the need for filtering before this signal is
presented to the up-converter in a typical transmitter
configuration.
Each demodulator comprises a full-wave synchronous detector
followed by a 3 MHz, two-pole low-pass filter, producing differ-
ential outputs at pins IRXP and IRXN, and QRXP and QRXN.
Using the I and Q demodulators for IFs above 50 MHz is pre-
cluded by the 10 MHz to 50 MHz range of the PLL used in the
Demodulator section.
The I and Q outputs are differential and can swing up to 2 V p-p
at the low supply voltage of 2.7 V. They are nominally centered
at 1.5 V independent of power supply. They can therefore
directly drive the receive ADCs in the AD7015 or AD6421
baseband converters, which require an amplitude of 1.23 V to
fully load them when driven by a differential signal. The conver-
sion gain of the I and Q demodulators is 17 dB.
The I and Q inputs are intended to be driven using a
fully-differential drive (for example from an AD7015 or
AD6421) and need to be biased to a common-mode dc
level of 1.2 V, with a typical differential amplitude of
±1.028 V (that is, ±514 mV at each input). Some small
variation in the drive conditions is allowable, but will result
in nonoptimal performance. The minimum instantaneous
input should not go below 0.6 V and the maximum voltage
should not exceed 1.8 V using a 2.7 V supply (in general,
VP – 0.9 V). The impedance at these inputs is several MΩ
in parallel with approximately 1 pF; the bias currents flow
out of the pins and are ~100 nA. These conditions permit
the use of a high impedance low-pass filter if desired ahead
of the modulator inputs.
A simple 1-pole RC filter at the I and Q outputs, with its corner
above the modulation bandwidth is sufficient to attenuate un-
desired outputs. The design of the RC filter is eased by the
4.7 kΩ resistor integrated into each I and Q output pin.
Phase-Locked Loop
The demodulators are driven by quadrature signals that are
provided by a variable-frequency quadrature oscillator (VFQO),
phase-locked to the reference frequency. This frequency is equal
or double the frequency of the signal applied to Pin FREF.
When the quadrature signals are at the IF, inphase and quadra-
ture baseband outputs are generated at the I output (IRXP
and IRXN) and Q output (QRXP and QRXN), respectively.
The quadrature accuracy of the VFQO is typically within ±1° at
26 MHz. A simplified diagram of the FREF input is shown in
The dc modulator output is at a constant dc level of 1.5 V,
independent of temperature and supply voltage. It is de-
signed to drive a 150 Ω load and should either be matched
into a 50 Ω load, using a simple LC network, or padded to
150 Ω with a series 100 Ω resistor (Figure 33). The output
is short-circuit-proof. The output modulated signal at pin
MODO has a power of –16 dBm when driving a 50 Ω load
with a 100 Ω series resistor, as shown in Figure 33. This
power is specified at a carrier frequency of 272 MHz with a
maximum dc differential signal applied to the I or Q chan-
nel while the other channel has no differential signal ap-
plied. The transmit modulator is enabled only when the
TXPU input (Pin 39) is taken HI.
Figure 32.
VPOS
5kΩ
20kΩ
FREF
5kΩ
100pF
100Ω
MODO
A PTAT
50Ω
Figure 32. Simplified Schematic of the FREF Interface
Figure 33. Output Impedance of Pin MODO Is
Designed to Drive a 50 Ω Load with a 100 Ω Series
Resistor
The VFQO is controlled by the voltage between VPOS and
FLTR. In normal operation, a series RC network, forming the
PLL loop filter, is connected from FLTR to VPOS. The use of an
REV. 0
–13–
AD6432
Local Oscillator Input
USING THE AD6432
The Local Oscillator (LO) input port is differential and consists
of two functionally identical pins, LOHI and LOLO. It accepts
a signal of 200 mV p-p at a frequency between 200 MHz and
600 MHz. Inputs LOHI and LOLO are internally biased to the
positive supply (Pin 3) through 500 Ω resistors. While not usu-
ally needed, these inputs may be driven through a simple match-
ing network to lower the LO power required from a 50 Ω source.
Single-sided drives are not recommended. The most noticeable
effects will be degradation of phase balance and an increase in
phase noise.
In this section, we will focus on a few areas of special impor-
tance through the real life example of interfacing the AD6432
to the AD6421 Base Band converter. As is true of any wideband
high gain components, great care is needed in PC board layout.
The location of the particular grounding points must be considered
with due regard for the possibility of unwanted signal coupling.
The high sensitivity of the AD6432 leads to the possibility
that unwanted local EM signals may have an effect on the per-
formance. During system development, carefully-shielded test
assemblies should be used. The best solution is to use a fully
enclosed box enclosing all components, with the minimum
number of needed signal connectors (RF, LO, I and Q outputs)
in miniature coax form.
This signal is fed internally to a divider by two that generates the
mixing signals for the receive mixer and the transmit modulator.
In order to meet the phase and amplitude balance of the trans-
mit quadrature modulator, as stated in the specification table,
the duty cycle of the LO signal must be such that the second
harmonic is at least 30 dBc below the fundamental.
Interfacing the AD6432 to the AD6421 Baseband Converter
The AD6421 Baseband Converter contains all the necessary
elements to drive the AD6432.
I/Q Convention
Receive Interface
The AD6432 is a complete IF subsystem. Although not a re-
quirement for using the AD6432, most applications will use a
high side LO injection on the receive mixer. The I and Q con-
vention on the receive section is such that when a spectrum with
I leading Q is presented to the input of the receive mixer and a
high side LO is presented to the receive mixer, I still leads Q at
the baseband output of the AD6432.
The interface between the two devices provides for quadrature
I and Q channels that can be driven either differentially or in the
single-ended configuration. Figure 35 shows the interface be-
tween the AD6432 and the AD6421 for the differential configu-
ration. The respective pins (IRXP, IRXN, QRXP and QRXN)
are dc coupled through 4.7 kΩ resistors, which are integrated
within the AD6432. Balanced coupling may be used with a
single 50 pF capacitor between the complementary signals as
illustrated in Figure 35. This low-pass filter is the only external
filter required to prevent aliasing of the baseband analog signal
prior to sampling within the AD6421.
Likewise, the I and Q convention on the transmit section is
such that when a spectrum with I leading Q is presented at the
baseband input of the modulator, I still leads Q at the output of
the modulator.
Auxiliary Op Amp
The AD6421 has an external autocalibration mode that can
calibrate out any offsets resulting from the IF demodulation
circuitry.
An auxiliary operational amplifier is available although it is im-
portant to remember that it is active only when TXPU is high.
The positive and negative input terminals are PCAP and PCAM
with PCAO being the output pin. The inputs are the bases of
PNP transistors with a typical bias current of approximately
150 nA. The input offset voltage is typically < 4 mV and the
open loop gain of the amplifier is 60 dB. The amplifier is unity
gain stable with a –3 dB Bandwidth greater than 40 MHz. The
input signal voltage range is from 0.1 V to VPOS – 2.1 V.
Transmit Interface
The corresponding transmit (ITXP, ITXN, QTXP and QTXN)
pins of the AD6421 and AD6432 are directly connected as these
have compatible bias levels for dc coupling. To meet the more
stringent phase two filter mask requirements, an external low-
pass filter may be required, depending on the filtering capabili-
ties of the radio section. A passive second order low-pass
filter network with a cutoff frequency to 600 kHz is suggested
as shown in Figure 34. Resistor values should range from
1.5 kΩ–3.0 kΩ to minimize AD6432 offsets.
Bias System
The AD6432 operates from a single supply, VPOS, usually 3 V, at
a typical supply current in receive mode of 13 mA at midgain
and TA = +25°C, corresponding to a power consumption of
39 mW. Any voltage from 2.7 V to 3.6 V may be used.
ITXP
ITXN
ITXP
ITXN
The bias system includes a fast-acting active high CMOS-com-
patible power-up switch, allowing the part to idle at less than
100 µA when disabled. Biasing is generally proportional-to-
absolute temperature (PTAT) to ensure stable gain with tem-
perature. Other special biasing techniques are used to ensure
very accurate gain, stable over the full temperature range.
AD6432
AD6421
QTXP
QTXN
QTXP
QTXN
Figure 34. GSM Phase II Transmit Interface
REV. 0
–14–
AD6432
Gain Control
ITXP
ITXP
ITXN
QTXP
QTXN
IRXP
IRXN
The AD6432 contains a Gain TC Compensation circuit that
provides a nominal 80 dB dynamic range of automatic gain
control. The GAIN input pin of the gain circuit is driven by
the AD6421 Automatic Gain Control DAC (AGCDAC), an
integrated auxiliary DAC of the AD6421, controllable by the
radio’s digital processor. This connection should be made
through a single pole RC to reduce high frequency noise into
the gain control circuit. The values shown in Figure 35 provide
a –3 dB point at approximately 1 MHz, sufficient for the gain
control.
ITXN
QTXP
QTXN
IRXP
50pF
50pF
IRXN
QRXP
QRXN
AD6432
AD6421
QRXP
QRXN
MCLK
1nF
1kΩ
FREF
VCTCXO
AFCDAC
100nF
0
BREFCAP
LOHI
FREQUENCY
SYNTHESIZER
Gain control scaling is directly proportional to the reference
voltage applied to Pin GREF and is independent of the power
supply voltage. A nominal 1.2 V reference for GREF can be
provided by the AD6421 through BREFOUT. BREFOUT is
a buffered output version of BREFCAP reference. This refer-
ence output feature is enabled on the AD6421 by setting Bit 2
in control register BCRB (BCRB2). See AD6421 data sheet.
F
LOLO
GREF
GAIN
BREFOUT
AGCDAC
RAMDAC
160Ω
1nF
POWER CONTROL
LC
BAND-
PASS
FILTER
The VGAIN input range for this control signal is 0.2 V– 2.4 V where
gain is maximum at 0.2 V and falls off as VGAIN is increased to
2.4 V. To avoid saturating the input to the baseband converter,
the automatic gain control function of the receiver must limit
the output signal swing of the AD6432 to ±1.2 V, the full signal
range of the input.
Figure 35. AD6432 to AD6421 Interface
Transmit Power Control
A general purpose amplifier is available on the AD6432, which
may be useful as part of an automatic control circuit for the
power amplifier. Open ended, this amplifier will swing full scale
from rail to rail. It is recommended that this amplifier be con-
nected in the unity feedback configuration when not being used
by connecting PCAO to PCAM.
Phase-Lock Loop Control
The AD6432 PLL/QVCO circuits require an external frequency
reference for coherent modulation and demodulation of the
baseband and IF signal. The external frequency reference con-
trol for the AD6432 PLL/QVCOs is typically generated through
a 13 MHz voltage controlled temperature compensated crystal
oscillator (VCTCXO). The control voltage for the VCTCXO is
generated by an auxiliary DAC in the AD6421 designated as
the Automatic Frequency Control DAC (AFCDAC). The PLL
loop is closed through the radio’s algorithm signal processor,
which drives the AD6421 AFCDAC.
AD6432 EVALUATION BOARD
The AD6432 Evaluation Board is designed to enable measure-
ments of key parameters on the AD6432 IFIC, a device that
provides the complete transmit and receive IF signal processing,
including I/Q modulation and demodulation, necessary to imple-
ment a digital wireless transceiver.
The AD6432 FREF pin provides the VCTCXO reference sig-
nal to the AD6432 RX quadrature VCO (QVCO) circuit.
The AD6432 FREF input must be an ac coupled signal
200 mV p-p or greater. The reference for the UHF TX QVCO
and RX IF down converter is synthesized from the VCTCXO
output reference signal through an external frequency synthe-
sizer and VCO. This UHF reference is an ac coupled input into
AD6432 LOHI and LOLO pins.
Many of the signal paths into and out of the AD6432 are differ-
ential, which is the preferred interface to and from single supply
CODECS. To facilitate an interface to traditional lab equip-
ment, the following interface circuitry is included on the board.
A 20-pin Berg strip for bias, gain and Inphase and Quadrature
signal interface. End Launch SMA connectors for RF, LO,
MODO and FREF signals and provisions for breaking out
MXOP and IFHI with RF transformers.
An external series RC network connected between FLTR (Pin
29) and the VPOS supply pin provides the proper loop filter for
the VCO/PLL as shown in Figure 35.
A single-ended to differential RF transformer provides a bal-
anced LO drive.
An onboard 1.2 V dc reference IC is provided for application to
GREF.
REV. 0
–15–
AD6432
Evaluation Board Description
Interface Connector (Berg Strip) Pin Description
Building up a simple IDC connector/ribbon cable breakout to a
vector board or box with banana plugs will facilitate testing.
Figure 37 shows the signal’s placement and Table II describes
each signal.
This four layer board demonstrates both the transmit and
receive functions of the AD6432. The top internal layer is a
ground plane and the bottom internal layer is a strategically
partitioned power plane with DUT power and bipolar support
device power.
A 20-pin Berg strip connector provides the external power and
dc signal interface, which includes power-up, gain and external
reference bias options. The various high frequency IF, LO, TX
Modulation output (MODO) and the Demodulator Reference
(FREF) are brought in and out of the board via end-launch
SMA connectors. Appropriate terminations are provided for
each signal. Several hardware jumpers are provided for bias and
IF selection options. Figure 36 shows the placement of the
different connectors used on the evaluation board.
BOARD
EDGE
Figure 37. Evaluation Board Interface Connector
MODO
FREF
LOINP
1
J21
J26
J24
U1
OPTLO
T1
J23
J25
Q1
J22
RFHI
AD6432 EVAL.
REV. B
MXOP
IFIP
Figure 36. Evaluation Board Layout (Top View)
Note: MXOP, IFHI, OPTLO are optional SMA connectors not
supplied with the evaluation board.
REV. 0
–16–
AD6432
Table II. Connector Signal Description
Description
Table III. SMA End-Launch Connectors
Pin
Name
SMA
Connector Description
MODO
Transmit Modulator Output. This pin, which is
designed to drive a 150 Ω filter, has been resistively
matched (loss) onboard to drive a 50 Ω instrument
such as a spectrum analyzer.
Local Oscillator Input pin. This is actually fed with
twice the LO frequency from a generator for both
transmit and receive. The nominal LO level is
–16 dBm (50 Ω).
GND
ITXP
ITXN
QTXP
QTXN
TXPU
Analog and Power Ground.
I Channel Transmit Plus Modulation Input.
I Channel Transmit Minus Modulation Input.
Q Channel Transmit Plus Modulation Input.
Q Channel Transmit Minus Input.
Transmit Section Power-Up. This function is
also jumper selectable with J21.
Auxiliary Op Amp Minus Input.
Auxiliary Op Amp Plus Input.
Power control op amp supply 2.7 V dc–3.6 V dc.
The jumper, J26, connects VS1 and VS2 together.
AD6432 main supply 2.7 V dc–3.6 V dc.
Auxiliary Op Amp Output.
Selects IF Pin. This function is also jumper pro-
grammable with J25.
I Channel Receive Plus Modulation Output.
I Channel Receive Minus Modulation Output.
Q Channel Receive Plus Modulation Output.
Q Channel Receive Plus Modulation Output.
The AD6432 gain reference bias which is optimized
for 1.2 V dc. This may be externally supplied; or by
shorting J23, supplied directly from the AD1580
SOT-23 onboard, 1.2 V reference.
LOIP
OPTLO Optional differential minus local oscillator input
(transformer can be removed).
PCAM
PCAP
VS2
RFHI
MXOP
RF input
Mixer Output (optional output that may be converted
to single ended output with an RF transformer).
IF Input (optional single ended input that may be
converted to differential with an RF transformer).
Frequency Reference for phase locked receive de-
modulator. The internal VCO frequency is equal to
FREF in the 1X mode and equal to two times FREF
in the 2X mode.
VS1
PCAO
IFS0
IFHI
FREF
IRXP
IRXN
QRXP
QRXN
GREF
GAIN
RXPU
Max RX gain occurs at 0.2 V dc. Minimum gain
occurs at 2.4 V dc.
Receive Section Power-Up. This function is also
jumper selectable with J22.
Power Requirements
The evaluation board uses two supplies, VS1 and VS2.
VS1—2.7 V dc–3.6 V dc, 13 mA typical. This is the main sup-
ply for the AD6432.
VS2—2.7 V dc–3.6 V dc, 2 mA typical. This is the supply for
the on-chip op amp which is normally used in RF power control
circuits.
The op amp is active only in the Transmit mode.
REV. 0
–17–
AD6432
TXPU
VS1
PCAP
R19
20kΩ
R30
1kΩ
J21
QTXN
QTXP
ITXN
ITXP
PCAM
R39
OPEN
R34
0Ω
R25
1kΩ
R12
0Ω
PCAO
FREF
VS1
R8
0Ω
C5
C28
0
VS2 VS1
J26
VPTX
0.0
F
F
DECOUPLING
C11
C32
0
0.0
F
F
MODO
R9
84Ω
R23
123Ω
J24
R2
0Ω
R18
20kΩ
C15
100pF
VS1
C36
1nF
44 43 42 41 40 39 38
36
34
35
37
C29
0
C14
0.0
IFS1
IFS0
VPDV
DECOUPLING
F
F
R17
20kΩ
1
2
33
32
31
GND
MODO
VPDV
CMTX
LOLO
LOHI
FREF
GND
IFS0
J25
3
C10
1nF
R1
1kΩ
T1
R7
0Ω
R35
125Ω
C18
0F
6
1
2
3
4
30 CMDM
LOIP
AD6432
FLTR
VPFL
VPDM
VS1
5
29
28
27
C23
0.0
6
4
R20
OPEN
F
F
R14
125Ω
TOP VIEW
(Pins Down)
7
CMRX
GND
R6
0Ω
OPTLO
26 IRXP
25 IRXN
8
C1
100pF
R21
0Ω
9
RFLO
RFHI
GND
C17
0
C41
0.0
F
RFHI
10
11
24
23
QRXP
QRXN
C2
R3
49.9Ω
100pF
IRXP
20
14 15 16 17 18 19
13
21 22
12
C6
47pF
TX
IRXN
GND
QRXP
ITXP
C8
GREF
47pF
RXPU
ITXN
QTXP
QTXP
TXPU
PCAM
PCAP
R31
0Ω
QXRN
C21
VS1
0
F
J23
F
C3
0.0
C30
Q1
TP1580
GAIN
F
0
F
C44
0.0
R16
10kΩ
J22
R15
20kΩ
VS1
VS1
VS2
VS1
C50
4
F
C16
22pF
L2
SHORT
PCAO
GND
C12
4
F
C20
82pF
R13
OPEN
L4
0.3
R6
OPEN
L1
OPEN
C18
OPEN
C19
22pF
L3
SHORT
H
IFS0
IRXP
C43
0.0
C42
0.0
F
F
IRXN
QRXP
QRXN
GREF
GAIN
RXPU
1
2
3
4
1
2
3
4
T2
T3
6
6
IFIP
MXOP
20B
20A
Figure 38. Evaluation Board Schematics
REV. 0
–18–
AD6432
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Thin Quad Flatpack (TQFP)
(ST-44)
0.063 (1.60)
MAX
0.472 (12.00) SQ
0.030 (0.75)
0.018 (0.45)
33
23
34
22
SEATING
PLANE
0.394
(10.0)
SQ
TOP VIEW
(PINS DOWN)
44
12
1
11
0.006 (0.15)
0.002 (0.05)
0.018 (0.45)
0.012 (0.30)
0.031 (0.80)
BSC
0.057 (1.45)
0.053 (1.35)
REV. 0
–19–
–20–
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