AD8383 [ADI]
Low Cost 10-Bit, 6-Channel Output Decimating LCD DecDriver; 低成本10位， 6声道输出抽取LCD DecDriver
| 型号： | AD8383 |
| 厂家： | 
ADI |
| 描述： | Low Cost 10-Bit, 6-Channel Output Decimating LCD DecDriver |
| 文件： | 总16页 (文件大小：474K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost 10-Bit, 6-Channel Output
Decimating LCD DecDriver®
AD8383
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High voltage drive to within 1.3 V of supply rails
Output short-circuit protection
High update rates
Fast, 100 Ms/s, 10-bit input data update rate
Low static power dissipation: 0.7 W
Includes STBY function
Voltage-controlled video reference (brightness) and
full-scale (contrast) output levels
INV bit reverses polarity of video signal
3.3 V logic, 9 V to 18 V analog supplies
High accuracy voltage outputs
Laser trimming eliminates the need for adjustments
Flexible logic
STSQ/XFR allow parallel AD8383 operation at various
resolutions
Fast settling into capacitive loads
30 ns settling time to 0.25% into 150 pF load
Slew rate 460 V/µs
10
10
10
10
10
10
10
10
10
10
10
10
10
10
2-STAGE
LATCH
DAC
DAC
DAC
DAC
DAC
DAC
DB(0:9)
VID0
VID1
VID2
VID3
VID4
VID5
2-STAGE
LATCH
AD8383
2-STAGE
LATCH
STBY
BYP
BIAS
2-STAGE
LATCH
2-STAGE
LATCH
R/L
E/O
2-STAGE
LATCH
CLK
STSQ
XFR
SEQUENCE
CONTROL
SCALING
CONTROL
VREFHI
VREFLO
INV
V1 V2
Available in 48-lead 7 mm × 7 mm LFCSP package
Figure 1
APPLICATIONS
LCD analog column driver
PRODUCT DESCRIPTION
The AD8383 provides a fast, 10-bit latched decimating digital
input that drives six high voltage outputs. 10-bit input words are
sequentially loaded into six separate, high speed, bipolar DACs.
Flexible digital input format allows several AD8383s to be used
in parallel for higher resolution displays. STSQ synchronizes
sequential input loading, XFR controls synchronous output
updating, and R/L controls the direction of loading as either
left-to-right or right-to-left. Six channels of high voltage output
drivers drive to within 1.3 V of the rail. For maximum flexibility,
the output signal can be adjusted for dc reference, signal
inversion.
The AD8383 is fabricated on the 26 V, fast bipolar XFHV
process developed by Analog Devices, Inc. This process
provides fast input logic, bipolar DACs with trimmed accuracy
and fast settling, high voltage, precision drive amplifiers on the
same chip.
The AD8383 dissipates 0.7 W nominal static power. The STBY
pin reduces power to a minimum with fast recovery.
The AD8383 is offered in a 48-lead, 7 mm × 7 mm × 0.85 mm
LFCSP package and operates over the commercial temperature
range of 0°C to 85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD8383
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Maximum Power Dissipation ..................................................... 5
Pin Configuration and Function Descriptions............................. 6
Timing Diagrams.............................................................................. 7
Theory of Operation ........................................................................ 8
Transfer Function and Analog Output Voltage ........................ 8
Applications....................................................................................... 9
External VBIAS Generation........................................................ 9
PCB Design for Good Thermal Performance ........................ 10
Thermal Pad Design .................................................................. 10
Thermal Via Structure Design.................................................. 11
Solder Masking........................................................................... 11
Reference PCB Design............................................................... 11
Estimated Junction Temperature ............................................. 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8383
SPECIFICATIONS
Table 1. @25°C, AVCC = 15.5 V, DVCC = 3.3 V, TMIN = 0°C, TMAX = 75°C, VFS = 5 V, VREFLO = V1 = V2 = 7 V,
unless otherwise noted
Parameter
VIDEO DC PERFORMANCE1
Conditions
Min
Typ
Max
Unit
TMIN to TMAX, DAC Code 450 to 800
VDE
VCME
–7.5
–3.5
+7.5
+3.5
mV
mV
REFERENCE INPUTS
V1, V2 Range
5
AVCC – 4
V
V2 to V1 Range
V1 Input Current
V2 Input Current
VREFHI Range
VREFLO Range
VREFHI Input Resistance
VREFLO Bias Current
VREFHI Input Current
VFS Range2
–0.25
V
+0.2
–7.5
µA
µA
V
VREFHI ≥ VREFLO
VREFHI ≥ VREFLO
To VREFLO
VREFLO
V1 – 0.5
AVCC
AVCC – 1.3
V
20
–0.2
125
kΩ
µA
µA
V
0
5.5
RESOLUTION
Coding
Binary
10
Bits
DIGITAL INPUT CHARACTERISTICS
Maximum Input Data Update Rate3
CLK to Data Setup Time
CLK to STSQ Setup Time
CLK to XFR Setup Time
CLK to Data Hold Time
CLK to STSQ Hold Time
CLK to XFR Hold Time
CLK High Time
CLK Low Time
100
0
1
1
3
3
3
3
2.5
Ms/s
ns
ns
ns
ns
ns
ns
ns
ns
pF
µA
µA
µA
V
CIN
IIH
IIL
IIL, CLK
3
0.05
0.6
1.2
VIH
2
VIL
0.8
V
VTH
1.5
V
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
CLK to VID Delay4
INV to VID Delay
Output Current
Output Resistance
AVCC – VOH, VOL – AGND
50% of VIDx
50% of VIDx
1.1
1.3
14.0
14.4
V
10.0
10.4
12.0
12.4
100
22
ns
ns
mA
Ω
1 VDE = Differential Error Voltage = Common-Mode Error Voltage. See Theory of Operation section.
2 VFS = 2 × (VREFHI – VREFLO).
3 Maximum input transition time (10% to 90%) = 0.8/(2f) where f is the operating CLK rate.
4 Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV.
Rev. 0 | Page 3 of 16
AD8383
SPECIFICATIONS (continued)
Parameter
Conditions
Min
Typ
Max
Unit
VIDEO OUTPUT DYNAMIC PERFORMANCE
Data Switching Slew Rate
Invert Switching Slew Rate
Data Switching Settling Time to 1%
Data Switching Settling Time to 0.25%
Invert Switching Settling Time to 1%
Invert Switching Settling Time to 0.25%
Invert Switching Overshoot
CLK and Data Feedthrough5
All-Hostile Crosstalk6
TC, MIN to TC, MAX, VO = 5 V Step, CL = 150 pF
20% to 80%
20% to 80%
460
560
19
30
75
250
100
10
V/µs
V/µs
ns
ns
ns
ns
mV
mV p-p
24
50
120
500
200
VO = 10 V Step
VO = 10 V Step
VO = 10 V Step
Amplitude
Duration
DAC Transition Glitch Energy
POWER SUPPLY
40
20
0.3
mV p-p
ns
nV-s
Code 511 to Code 512
DVCC, Operating Range
DVCC, Quiescent Current
AVCC, Operating Range
3
9
3.3
20
3.6
28
18
V
mA
V
Total AVCC Quiescent Current
STBY AVCC Current STBY = H
STBY DVCC Current STBY = H
OPERATING TEMPERATURE RANGE, TA
AMBIENT TEMPERATURE RANGE7
OPERATING TEMPERATURE RANGE, TJ
40
0.15
3.5
48
0.45
5
mA
mA
mA
°C
Ambient Temperature
100% tested
0
75
0
85
°C
25
125
°C
5 Measured on two outputs differentially as CLK and DB(0:9) are driven and STSQ and XFR are held low.
6 Measured on two outputs differentially as the other four outputs make a full-scale transition for both states of INV.
7 Operation at 85°C ambient temperature requires a thermally optimized PCB layout (see Application Notes), minimum airflow of 200 lfm, input clock rate not
exceeding 100 MHz, black-to-white transition ≤4 V, CL ≤150 pF.
Rev. 0 | Page 4 of 16
AD8383
ABSOLUTE MAXIMUM RATINGS
Table 2. AD8383 Stress Ratings
Parameter
MAXIMUM POWER DISSIPATION
Junction Temperature
Rating
Supply Voltages
The maximum power that can be safely dissipated by the
AD8383 is limited by its junction temperature. The maximum
safe junction temperature for plastic encapsulated devices as
determined by the glass transition temperature of the plastic is
approximately 150°C. Exceeding this limit temporarily may
cause a shift in the parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can
result in device failure.
AVCCx – AGNDx
DVCC – DGND
Input Voltages
18 V
4.5 V
Maximum Digital Input Voltages
Minimum Digital Input Voltages
Maximum Analog Input Voltages
Minimum Analog Input Voltages
Internal Power Dissipation8
LFCSP Package @ 25°C Ambient
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 10 sec)
DVCC + 0.5 V
DGND – 0.5 V
AVCC + 0.5 V
AGND – 0.5 V
3.8 W
Overload Protection
0°C to 85°C
–65°C to +125°C
300°C
The AD8383 employs a 2-stage overload protection circuit that
consists of an output current limiter and a thermal shutdown.
The maximum current at any one output of the AD8383 is
internally limited to 100 mA, average. In the event of a momen-
tary short-circuit between a video output and a power supply
rail (AVCC or AGND), the output current limit is sufficiently
low to provide temporary protection.
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the
absolute maximum ratings for extended periods may reduce
device reliability.
The thermal shutdown debiases the output amplifier when the
junction temperature reaches the internally set trip point. In the
event of an extended short-circuit between a video output and a
power supply rail, the output amplifier current continues to
switch between 0 mA and 100 mA typical with a period
determined by the thermal time constant and the hysteresis of
the thermal trip point. The thermal shutdown provides long-
term protection by limiting the average junction temperature to
a safe level.
8 48-Lead LFCSP Package:
θJA = 26°C/W (Still Air): JEDEC STD, 4-layer board with 0 CFM airflow
θJC = 20°C/W
ψJB = 11.0°C/W in Still Air
Operating Temperature Range
Production testing guarantees a minimum thermal shutdown
junction temperature (TJ) of at least 125°C.
To ensure operation at TJ < 125°C, it is necessary to limit the
maximum power dissipation as described in the Applications
section.
Exposed Paddle
The die paddle must be soldered to AVCC for reliable electrical
operation.
See the Applications section for details regarding use of the
exposed paddles to dissipate excess heat.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 16
AD8383
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
1
2
3
4
5
6
7
8
9
36 VID0
PIN 1
INDICATOR
35 AVCC0,1
34 VID1
33 AGND1,2
32 VID2
AD8383
TOP VIEW
7mm × 7mm
(Not to Scale)
31 AVCC2,3
30 VID3
29 AGND3,4
28 VID4
DB8 10
DB9 11
NC 12
27 AVCC4,5
26 VID5
25 AGND5
NC = NO CONNECT
Figure 2. 48-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin Name
DB(0:9)
CLK
Function
Data Input
Clock
Description
10-Bit Data Input. MSB = DB(0:9).
Clock Input.
STSQ
Start Sequence
The state of STSQ is detected on the active edge of CLK. A new data loading sequence begins on
the next active edge of CLK after STSQ is detected HIGH.
The active CLK edge is the rising edge when E/O is held HIGH. It is the falling edge when E/O is
held LOW.
R/L
Right/Left Select
Even/Odd Select
A new data loading sequence begins on the left with Channel 0 when this input is LOW, and on
the right with Channel 5 when this input is HIGH.
E/O
The active CLK edge is the rising edge when this input is held HIGH and the falling edge when
this input is held LOW. Data is loaded sequentially on the rising edges of CLK when this input is
HIGH and on the falling edges when this input is LOW.
XFR
Data Transfer
XFR is detected and a data transfer is initiated on a rising CLK edge when this input is held HIGH.
Data is transferred to the video outputs on the next rising CLK edge after XFR is detected.
VID0–VID5
V1, V2
Analog Outputs
These pins are directly connected to the analog inputs of the LCD panel.
The voltage applied between these pins set the reference levels of the analog outputs.
The voltage applied between these pins sets the full-scale output voltage.
Reference Voltages
Full-Scale References
VREFHI,
VREFLO
INV
Invert
When this pin is HIGH, the analog output voltages are above VMID. When LOW, the analog
output voltages are below VMID. VMID is a hypothetical reference level set by the voltages
applied to V1 and V2. VMID is equal to (V1 + V2)/2.
DVCC
DGND
AVCCx
AGNDx
BYP
Digital Power Supply
Digital Supply Return
Analog Power Supplies
Analog Supply Returns
Bypass
Digital Power Supply.
This pin is normally connected to the analog ground plane.
Analog Power Supplies.
Analog Supply Returns.
A 0.1 µF capacitor connected between this pin and AGND ensures optimum settling time.
When HIGH, the internal circuits are debiased and the power dissipation drops to a minimum.
STBY
Standby
Rev. 0 | Page 6 of 16
AD8383
TIMING DIAGRAMS
tCLK HIGH
tCLK LOW
V
= 1.65V
TH
CLK
tSKEW
tSETUP
tHOLD
= 1.65V
V
TH
DB(0:9)
tSETUP
V
V
= 1.65V
= 1.65V
TH
STSQ
XFR
TH
tHOLD
Figure 3. Timing Diagram, Even Mode (E/O = HIGH)
tCLK LOW
tCLK HIGH
V
= 1.65V
TH
CLK
tSKEW
tSETUP
tHOLD
= 1.65V
V
TH
DB(0:9)
tSETUP
tHOLD
V
V
= 1.65V
= 1.65V
STSQ
XFR
TH
TH
tSETUP
tHOLD
Figure 4. Timing Diagram, Odd Mode (E/O = LOW)
Rev. 0 | Page 7 of 16
AD8383
THEORY OF OPERATION
TRANSFER FUNCTION AND ANALOG OUTPUT VOLTAGE
The DecDriver has two regions of operation: where the video
output voltages are either above or below a reference voltage
VMID, and where VMID = (V1 + V2)/2. The transfer function
defines the analog output voltage as the function of the digital
input code as follows:
To best correlate transfer function errors to image artifacts, the
overall accuracy of the DecDriver is defined by two parameters,
VDE and VCME.
VDE, the differential error voltage, measures the difference
between the rms value of the output and the rms value of the
ideal. The defining expression is
n
⎛
⎞
⎟
⎠
VIDx(n) = V1–VFS× 1–
for INV = LOW
for INV = HIGH
⎜
1023
⎝
VOUTN(n)−V 2
]
−
2
[
VOUTP(n) −V1
]
n
1023
⎛
⎝
⎞
⎟
⎠
VDE(n) =
− 1−
×VFS
⎜
n
1023
⎛
⎝
⎞
⎠
VIDx(n) = V 2 +VFS× 1–
⎜
⎟
VCME, the common-mode error voltage, measures ½ the dc
bias of the output. The defining expression is
where n = input code
VFS = 2 × (VREFHI – VREFLO)
1 1
2 2
⎣
V1+V 2
⎡
⎤
VCME(n) =
(
VOUTN(n)+VOUTP(n) –
)
A number of internal limits define the usable range of the
analog output voltages, VIDx, as shown in Figure 5.
⎢
⎥
⎦
2
AVCC
≥ 1.3V
2V
–V
REFHI REFLO
V2 + V
FS
INV = HIGH
9V ≤ AVCC ≤ 18V
0 ≤ V ≤ 5.5V
FS
V2
V
= (V1+V2)/2
MID
V
MID
5V ≤ V2 ≤ (AVCC – 4)
V1
0 ≤ V ≤ 5.5V
5V ≤ V1 ≤
(AVCC – 4)
FS
INV = LOW
V1 – V
FS
≥ 1.3V
AGND
0
1023
INTERNAL LIMITS AND
USABLE VOLTAGE RANGES
INPUT CODE
Figure 5. Transfer Function, VIDx vs. Input Code, Internal Limits and Usable Output Voltage Range
Rev. 0 | Page 8 of 16
AD8383
APPLICATIONS
The V1 and V2 inputs in these systems are tied together and are
normally connected to VCOM, as shown in Figure 6.
AVCC = 15.5V
VZ = 5.1V
AD8383
V2
AD8383
3
VCOM
1
V2 = 8V
V1 = 6V
V1
5
–IN
V+
V2
2
8
VCOM = 7V
R2 = 1kΩ
VCOM
+IN
AD8132
V–
4
Figure 6. Standard Connection Diagram
V1
6
R1 = 6kΩ
The transfer function of the AD8383 is shown in Figure 7 for
V2 = V1 = VCOM.
DVCC = 3.3V
Figure 8. High Accuracy Reference Circuit
VFS = 5V
VFS = 4V
VBIAS = 1V
VCOM
VBIAS = 1V
820 1023
V2
VBIAS = 1V
VCOM
VBIAS = 1V 1023
V1
RESERVED
CODE
VFS = 5V
RANGE
VFS = 4V
Figure 7. Output Transfer Function for Standard Connection
THE AD8383, IN THE APPLICATIONS
CIRCUIT SHOWN, TYPICALLY PRODUCES
A SYMMETRICAL OUTPUT AT 85°C WHEN
ITS SUPPLY, (V+) – (V–), IS AT 7.2V.
EXTERNAL VBIAS GENERATION
In systems that require improved brightness resolution and
higher accuracy, the V1 and V2 inputs, connected to external
voltage references, provide the necessary VBIAS while allowing
the full code range to be used for gamma correction.
Figure 9. Transfer Function for High Accuracy Reference Applications
8.75
7.50
6.25
5.00
3.75
V1 sets the white drive voltage while INV = LOW and V2 sets
the white drive voltage while INV = HIGH. V1 and V2 are
defined as
T
= 25°C
T
= 85°C
A
A
2.50
1.25
V1 = VCOM – VBIAS
V2 = VCOM + VBIAS
0.00
–1.25
–2.50
–3.75
–5.00
–6.25
–7.50
–8.75
To ensure a symmetrical ac driving voltage, the difference
between V2 and VCOM must be equal to the difference
between VCOM and V1.
TYPICAL ASYMMETRY AT THE OUTPUTS OF THE
AD8383 VERSUS ITS POWER SUPPLY FOR THE
APPLICATION CIRCUIT
5.7
6.2
6.7
7.2
7.7
8.2
8.7
9.2
9.7 10.2 10.7
(V2 – VCOM) = (VCOM – V1)
+
–
V
– V (V)
The circuit in Figure 8 ensures symmetry to within 1 mV with a
minimum component count. Bypass capacitors are not shown
for clarity.
Figure 10. Accuracy for High Accuracy Reference Applications
The transfer function and the input symmetry error of the
AD8383 are shown in Figure 9 when the circuit of Figure 8 is
used to generate VBIAS.
Rev. 0 | Page 9 of 16
AD8383
PCB DESIGN FOR GOOD THERMAL PERFORMANCE
THERMAL PAD DESIGN
The total maximum power dissipation of the AD8383 is partly
dependent on load. In a 6-channel 60 Hz XGA system running
at a 65 MHz clock rate, the total maximum power dissipation is
1.08 W at an LCD panel input capacitance of 150 pF.
Thermal performance of the AD8383 varies logarithmically
with the contact area between the exposed thermal paddle and
the thermal pad on the top layer of the PCB. See Figure 11.
The θJA (of the AD8383 mounted on a standard JEDEC PCB) is
reduced by approximately 40% as the contact area increases
from 0% (no thermal pad) to 50%. It approaches its specified
value as the contact area (on the JEDEC standard PCB)
approaches 100%.
At the maximum specified clock rate of 100 Ms/s, the total
maximum power dissipation can exceed 2 W for large capacitive
loads, as shown in Table 4.
Although the maximum safe operating junction temperature is
higher, the AD8383 is 100% tested at a junction temperature of
125°C. Consequently, the maximum guaranteed operating
junction temperature is 125°C. To limit the maximum junction
temperature at or below the guaranteed maximum, the package,
in conjunction with the PCB, must effectively conduct heat
away from the junction.
In order to minimize thermal performance degradation of
production PCBs, the contact area between the thermal pad and
the PCB should be maximized. Therefore, the size of the
thermal pad should match the exposed 5.25 mm × 5.25 mm
paddle size. However, if the PCB design rules require a pad-to-
pad clearance of more than 0.3 mm, the size of the thermal pad
may be reduced to 5 mm × 5 mm. Additionally, a second
thermal pad of the same size should be placed on the bottom
side of the PCB. At least one thermal pad should be in direct
thermal (and electrical) contact with the AVCC plane.
The AD8383’s LFCSP package is designed to provide superior
thermal characteristics, partly achieved by an exposed die
paddle on the bottom surface of the package. In order to take
full advantage of this feature, the exposed paddle must be in
direct thermal contact with the PCB, which then serves as a
heat sink.
50
45
40
35
30
25
A thermally effective PCB must incorporate a thermal pad and
a thermal via structure. The thermal pad provides a solderable
contact surface on the top surface of the PCB. The thermal via
structure provides a thermal path to the inner and bottom
layers of the PCB to remove heat.
0
25
50
75
100
CONTACT AREA (%)
Figure 11. Thermal Performance vs. Contact Area (on a JEDEC PCB)
Table 4. Power Dissipation vs. Load Capacitance and VFS at 100 Ms/s Clock Rate
VFS = 5 V
VFS = 4 V
PTOTAL (W)
CLOAD (pF)
150
200
250
300
PQUIESCENT (W)
PDYNAMIC (W)
0.72
0.96
1.20
1.44
PTOTAL (W)
1.42
1.66
1.90
2.14
PDYNAMIC (W)
0.58
0.77
0.96
1.15
0.7
0.7
0.7
0.7
1.28
1.47
1.66
1.85
Rev. 0 | Page 10 of 16
AD8383
THERMAL VIA STRUCTURE DESIGN
REFERENCE PCB DESIGN
The top copper layer is shown in Figure 13.
7 mm
Effective heat transfer from the top to the inner and bottom
layers of the PCB requires thermal vias incorporated into the
thermal pad design. Thermal performance increases logarithmi-
cally with the number of vias, as shown in Figure 12. With the
AD8383 on a standard JEDEC PCB, θJA reaches its specified
value when a total of 16 vias are used. At a via count above 36,
θJA approaches its optimum value as the slope of the curve
approaches zero.
32
30
28
26
24
22
Figure 13. Recommended PCB Landing
The bottom thermal pad forms AVCC plane.
Thermal Pads
Top PCB Layer:
5.25 mm × 5.25 mm
5.25 mm × 5.25 mm
0
10
20
30
40
Bottom PCB Layer:
NUMBER OF VIAS
Figure 12. Thermal Performance vs. Number of Vias (on a JEDEC PCB)
Thermal via structure
Diameter:
0.25 mm
41
0.5 mm
Number of vias:
Via Grid Pitch:
Near optimum thermal performance of production PCBs is
attained when the number of vias is at least 36.
Miscellaneous
Perimeter Pads:
Solder Mask Swell:
SOLDER MASKING
0.5 mm × 0.25 mm
0.02 mm
To minimize the formation of solder voids due to solder flowing
into the via holes (solder wicking), the via diameter should be
small. Solder masking of the via holes on the top layer of the
PCB plugs the via holes, inhibiting solder flow into the holes. To
optimize the thermal pad coverage, the solder mask diameter
should be no more than 0.1 mm larger than the via diameter.
Rev. 0 | Page 11 of 16
AD8383
θ
θ
, ψ
JB JB
θ, ψ
θ
θ
AIR-CASE
JC
AD8383
C
T
C
JC
CASE
AIR-CASE
θ
θ
θ
AIR-PCB
JC-BOTTOM
PCB
T
T
A
AMBIENT
P
C
T
J
C
JC-BOTTOM
C
C
PCB
AIR-PCB
T
PCB
PCB
Figure 14. Thermal Equivalent Circuit
ESTIMATED JUNCTION TEMPERATURE
Junction Temperature and Maximum Power Dissipation
Assuming no heat flows through the sides of the AD8383 pack-
age, heat flow from the AD8383 is through two paths. While
part of the total heat generated dissipates through the top of the
case, the remainder flows into the PCB to be dissipated.
In a thermal steady state represented by the simplified schema-
tic shown in Figure 15, heat flow from the die is partly through
the top of the case, causing a temperature drop (TJ – TCASE), and
partly through the PCB, causing a temperature drop (TJ – TPCB).
The junction temperature is calculated as follows:
Assuming there is no other heat-generating component near the
AD8383, the thermal equivalent circuit of a system that consists
of one AD8383 mounted on a PCB is shown in Figure 14.
(T
J
−TCASE
)
(T −TPCB)
J
P = PCASE + PPCB
=
+
θ
JC
θ
PCB
The thermal resistance of the top of the case, θJC, is constant,
independent of the system variables, and well defined. θJC
depends on the thermal resistance of the molding compound.
θJCθPCBP +θPCB TCASE +θJCTPCB
TJ =
θJC +θPCB
The thermal resistance of the system, θJA, is system dependent
and therefore cannot be properly estimated. Although it is tra-
ditional to provide the thermal resistance of a JEDEC reference
system in the data sheet, its value may not be appropriate for all
systems and may result in large errors (>>25%).
where:
TJ is the junction temperature
T
CASE is the temperature of the top of the case (near the output
pins for the AD8383)
PCB is the PCB temperature on the solder side (directly under
T
The thermal resistance of production PCBs, θJC, depends largely
on the particular PCB design, and, to some extent, the environ-
mental conditions specific to the particular system. Although θJB
is traditionally not provided on data sheets, a thermal character-
ization parameter, ψJB, of a JEDEC reference system is gaining
increasing acceptance. When the PCB thermal design near the
AD8383 closely approximates the PCB of the JEDEC reference
system, θJA approaches ψJB.
the AD8383)
P is the total power dissipated by the AD8383
θ
θ
JC is the thermal resistance of the top of the case
PCB is the thermal resistance of the PCB
At a given maximum allowed junction temperature, the
maximum allowed power dissipation is
(
θJC +θPCB
θJCθPCB
)
TCASE TPCB
⎡
⎤
PMAX =
TJMAX −
−
⎢
⎣
⎥
⎦
For thermally enhanced packages, the thermal resistance of the
exposed thermal paddle, θJC-BOTTOM, is very low and may
therefore be ignored.
θJC
θPCB
For a thermally optimized PCB, θJC can be replaced with ψPCB
and the equation can be rewritten as
⎡
⎢
⎣
⎤
⎥
⎦
θJC + ψPCB
θJCψPCB
)
TCASE TPCB
PMAX =
TJMAX −
−
θJC
ψPCB
Rev. 0 | Page 12 of 16
AD8383
P
Power-Up and Power-Down Sequencing
P
P
C
PCB
As indicated in the Absolute Maximum Ratings, the voltage at
any input pin cannot exceed its supply voltage by more than
0.5 V. To ensure compliance with the Absolute Maximum
Ratings, power-up and power-down sequencing may be
required.
T
J
θ
θ
θ
PCB
JC
T
T
PCB
CASE
During power-up, initial application of nonzero voltages to any
of the input pins must be delayed until the supply voltage ramps
up to at least the highest maximum operational input voltage.
θ
AIR-PCB
AIR-CASE
During power-down, the voltage at any input pin must reach
zero during a period not exceeding the hold-up time of the
power supply.
T
A
P
Failure to comply with the Absolute Maximum Ratings may
result in functional failure or damage to the internal ESD
diodes.
Figure 15. Simplified Thermal Equivalent Circuit
Verification of the Maximum Operating Junction
Temperature
Damaged ESD diodes may cause temporary parametric failures,
which may result in image artifacts. Damaged ESD diodes
cannot provide full ESD protection, thus reducing reliability.
In order to verify the system thermal design for compliance
with the maximum operating junction temperature specifica-
tion, temperature measurements TCASE and TPCB are required at
the maximum possible total power dissipation in a complete,
fully assembled LCD projection system.
The recommended sequence is
Power ON
Maximum possible total power dissipation of the AD8383
occurs when the video input to the projector is a pattern with
1-pixel-wide white and black vertical lines. An alternative
pattern that results in the maximum possible total power
dissipation is a 1-pixel checkerboard pattern. The expected total
power dissipation of the AD8383 in a 60 Hz, 6-channel XGA
projector displaying the 1-pixel-wide vertical line or checker-
board pattern is 1.08 W (at AVCC = 15.5 V, VCOM = 7 V, and
LCD capacitance = 150 pF).
1. Apply power to supplies.
2. Apply power to other I/Os.
Power OFF
1. Remove power from I/Os.
2. Remove power from supplies.
VBIAS Generation—V1, V2 Input Pin Functionality
Although the case and PCB temperatures are highly dependent
on the PCB design, their measured values are expected to be
similar at approximately 40°C above the ambient (on a typical
PCB with a minimal airflow whose thermal design follows the
recommendations described in this note). The junction temper-
ature then calculates to approximately 10°C above the case and
PCB temperatures. At a 70°C ambient temperature, the junction
temperature is expected to be at approximately 120°C.
In order to avoid image flicker, a bias voltage of approximately
1 V minimum must be maintained across the pixels of HTPS
LCDs. The AD8383 provides two methods of maintaining this
bias voltage.
Internal Bias Voltage Generation
Standard systems that internally generate the bias voltage
reserve the upper-most code range for the bias voltage and use
the remaining code range to encode the video for gamma
correction.
The AD8383 has a relatively small thermal mass. In order to
minimize measurement errors due to the thermal mass of the
measuring device, a small-gauge thermocouple or a thermal
probe with a very small thermal mass is required for the mea-
surement of TCASE and TPCB
.
Rev. 0 | Page 13 of 16
AD8383
OUTLINE DIMENSIONS
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
5.25
5.10 SQ
4.95
6.75
BSC SQ
TOP
VIEW
BOTTOM
VIEW
0.50
0.40
0.30
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 16. 48-Lead Frame Chip Scale Package [LFCSP]
(CP-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8383ACPZ9
Temperature Range
Package Description
Package Option
0°C to 85°C
48-Lead LFCSP
CP-48
9 Z = Pb-free part.
Rev. 0 | Page 14 of 16
AD8383
NOTES
Rev. 0 | Page 15 of 16
AD8383
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03191–0–1/04(0)
Rev. 0 | Page 16 of 16
相关型号：
AD8383ACPZ
LIQUID CRYSTAL DISPLAY DRIVER, QCC48, 7 X 7 MM, 0.85 MM HEIGHT, MO-220VKKD-2, LFCSP-48
ROCHESTER
©2020 ICPDF网 联系我们和版权申明