AD841_17 [ADI]
Wideband, Unity-Gain Stable, Fast Settling Op Amp;
| 型号： | AD841_17 |
| 厂家： | 
ADI |
| 描述： | Wideband, Unity-Gain Stable, Fast Settling Op Amp |
| 文件： | 总17页 (文件大小：377K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wideband, Unity-Gain Stable,
Fast Settling Op Amp
Data Sheet
AD841
FEATURES
CONNECTION DIAGRAMS
AC performance
NC
NC
1
2
3
4
5
6
7
14 NC
AD841
Unity-gain bandwidth: 40 MHz
Fast settling time: 110 ns to 0.01%
Slew rate: 300 V/µs
Full power bandwidth: 4.7 MHz for 20 V p-p into a 500 Ω load
DC performance
13 NC
BALANCE
–INPUT
+INPUT
12 BALANCE
11 +V
S
10 OUTPUT
–V
9
8
NC
NC
S
TOP VIEW
(Not to Scale)
NC
Input offset voltage: 1 mV maximum
Input voltage noise: 15 nV/√Hz typical
Open-loop gain: 45 V/mV into a 1 kΩ load
Output current: 50 mA minimum
Supply current: 12 mA maximum
NOTES
1. NC = NO CONNECT.
Figure 1. PDIP (N-14) Package and CERDIP (Q-14) Package
APPLICATIONS
High speed signal conditioning
Video and pulse amplifiers
Data acquisition systems
Line drivers
Active filters
Available in 14-pin plastic PDIP, 14-pin hermetic CERDIP, and
20-pin LCC packages
Chips and MIL-STD-883B parts available
3
2
1
20 19
18
17
16
15
14
4
5
6
7
8
NC
+V
NC
–INPUT
NC
S
NC
+INPUT
NC
OUTPUT
NC
AD841
9
10 11 12 13
NOTES
1. NC = NO CONNECT.
Figure 2. LCC (E-20-1) Package
GENERAL DESCRIPTION
The AD841 is a member of the Analog Devices, Inc., family of
wide bandwidth operational amplifiers. This high speed/high
precision family includes the AD842, which is stable at a gain of
two or greater and has 100 mA minimum output current drive.
These devices are fabricated using Analog Devices’ junction
isolated complementary bipolar (CB) process. This process
permits a combination of dc precision and wideband ac perfor-
mance previously unobtainable in a monolithic op amp. In
addition to its 40 MHz unity-gain bandwidth product, the
AD841 offers extremely fast settling characteristics, typically
settling to within 0.01% of final value in 110 ns for a 10 V step.
use in high frequency signal conditioning circuits and wide
bandwidth active filters. The extremely rapid settling time of
the AD841 makes it the preferred choice for data acquisition
applications that require 12-bit accuracy. The AD841 is also
appropriate for other applications such as high speed DAC and
ADC buffer amplifiers and other wide bandwidth circuitry.
PRODUCT HIGHLIGHTS
1. The high slew rate and fast settling time of the AD841
make it ideal for DAC and ADC buffers, and all types of
video instrumentation circuitry.
2. The AD841 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth performance
previously available only in hybrids.
3. The AD841’s thermally balanced layout and the speed of
the CB process allow the AD841 to settle to 0.01% in 110 ns
without the long tails that occur with other fast op amps.
4. Laser wafer trimming reduces the input offset voltage to
1 mV maximum on the K grade, thus eliminating the need
for external offset nulling in many applications. Offset null
pins are provided for additional versatility.
Unlike many high frequency amplifiers, the AD841 requires no
external compensation. It remains stable over its full operating
temperature range. It also offers a low quiescent current of
12 mA maximum, a minimum output current drive capability
of 50 mA, a low input voltage noise of 15 nV/√Hz, and low
input offset voltage of 1 mV maximum.
The 300 V/µs slew rate of the AD841, along with its 40 MHz
gain bandwidth, ensures excellent performance in video and
pulse amplifier applications. This amplifier is well suited for
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
AD841* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DESIGN RESOURCES
• AD841 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DOCUMENTATION
Application Notes
• AN-402: Replacing Output Clamping Op Amps with Input
Clamping Amps
DISCUSSIONS
View all AD841 EngineerZone Discussions.
• AN-417: Fast Rail-to-Rail Operational Amplifiers Ease
Design Constraints in Low Voltage High Speed Systems
• AN-581: Biasing and Decoupling Op Amps in Single
Supply Applications
SAMPLE AND BUY
Visit the product page to see pricing options.
Data Sheet
• AD841: Military Data Sheet
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• AD841: Wideband, Unity-Gain Stable, Fast Settling Op
Amp Data Sheet
TOOLS AND SIMULATIONS
• Power Dissipation vs Die Temp
• VRMS/dBm/dBu/dBV calculators
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
REFERENCE MATERIALS
Tutorials
• MT-032: Ideal Voltage Feedback (VFB) Op Amp
• MT-033: Voltage Feedback Op Amp Gain and Bandwidth
• MT-047: Op Amp Noise
• MT-048: Op Amp Noise Relationships: 1/f Noise, RMS
Noise, and Equivalent Noise Bandwidth
• MT-049: Op Amp Total Output Noise Calculations for
Single-Pole System
• MT-050: Op Amp Total Output Noise Calculations for
Second-Order System
• MT-052: Op Amp Noise Figure: Don't Be Misled
• MT-053: Op Amp Distortion: HD, THD, THD + N, IMD,
SFDR, MTPR
• MT-056: High Speed Voltage Feedback Op Amps
• MT-058: Effects of Feedback Capacitance on VFB and CFB
Op Amps
• MT-059: Compensating for the Effects of Input
Capacitance on VFB and CFB Op Amps Used in Current-to-
Voltage Converters
• MT-060: Choosing Between Voltage Feedback and
Current Feedback Op Amps
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
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AD841
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 10
Offset Nulling ............................................................................. 10
Input Considerations ................................................................. 10
AD841 Settling Time ................................................................. 10
Grounding and Bypassing......................................................... 11
Capacitive Load Driving Ability............................................... 11
Terminated Line Driver............................................................. 12
Overdrive Recovery ................................................................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
Connection Diagrams...................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
2/13—Rev. B to Rev. C
Removed TO-8 Package.....................................................Universal
Changed Input Voltage Noise 13 nV/√Hz to 15 nV/√Hz and
Changes to General Description Section ...................................... 1
Changes to Endnote 1, Table 1........................................................ 4
Added Operating Temperature Range, Table 2 ............................ 5
Deleted Using a Heat Sink Section............................................... 11
Updated Outline Dimensions....................................................... 13
Added Ordering Guide .................................................................. 14
11/88—Rev. A to Rev. B
Rev. C | Page 2 of 16
Data Sheet
AD841
SPECIFICATIONS
TA = 25°C and 15 V dc, unless otherwise noted. All minimum and maximum specifications are guaranteed.
Table 1.
AD841J
Min Typ
AD841K
Max Min Typ
AD841S1
Max Min Typ
Test Conditions/
Comments
Parameter
Max Unit
INPUT OFFSET VOLTAGE2
0.8
2.0
5.0
0.5
1.0
3.3
0.5
5.5
35
2.0
mV
mV
µV/°C
µA
TMIN − TMAX
Offset Drift
35
35
INPUT BIAS CURRENT
3.5
8
3.5
5
3.5
8
TMIN – TMAX
10
0.4
0.5
6
0.2
0.3
12
0.4
0.6
µA
µA
µA
Input Offset Current
0.1
0.1
0.1
TMIN − TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Differential mode
200
2
200
2
200
2
kΩ
pF
INPUT VOLTAGE RANGE
Common Mode
10 12
10 12
10 12
V
Common-Mode Rejection
VCM = 10 V
TMIN – TMAX
86
80
100
103 109
100
15
86
80
110
dB
dB
INPUT VOLTAGE NOISE
Wideband Noise
f = 1 kHz
15
47
15
47
nV/√Hz
µV rms
10 Hz to 10 MHz
VOUT = 10 V
RLOAD ≥ 500 Ω
TMIN − TMAX
47
OPEN-LOOP GAIN
25
12
45
25
20
45
25
12
45
V/mV
V/mV
OUTPUT CHARACTERISTICS
Voltage
RLOAD ≥ 500 Ω
TMIN − TMAX
10
10
10
V
Current
VOUT = 10 V
Open loop
50
50
50
mA
Ω
OUTPUT RESISTANCE
FREQUENCY RESPONSE
Unity Gain Bandwidth
Full Power Bandwidth3
5
5
5
VOUT = 90 mV p-p
VOUT = 20 V p-p
RLOAD ≥ 500 Ω
AV = −1
AV = −1
AV = −1
40
40
40
MHz
3.1
4.7
10
10
3.1
4.7
10
10
3.1
4.7
10
10
MHz
ns
%
Rise Time4
Overshoot4
Slew Rate4
200 300
200 300
200 300
V/µs
Settling Time 10 V Step
AV = −1
to 0.1%
90
00
90
ns
to 0.01%
110
200
700
0.03
0.022
110
200
700
0.03
0.022
110
200
700
0.03
0.022
ns
OVERDRIVE RECOVERY
−Overdrive
+Overdrive
f = 4.4 MHz
f = 4.4 MHz
ns
ns
DIFFERENTIAL GAIN
Differential Phase
POWER SUPPLY
%
Degree
Rated Performance
Operating Range
Quiescent Current
15
15
15
V
V
mA
mA
dB
dB
5
18
12
14
5
18
12
14
5
18
12
16
11
11
11
TMIN − TMAX
Power Supply Rejection Ratio VS = 5 V to 18 V
TMIN − TMAX
86
80
100
90
86
100
86
80
100
Rev. C | Page 3 of 16
AD841
Data Sheet
AD841J
Min Typ
AD841K
Max Min Typ
AD841S1
Max Min Typ
Test Conditions/
Comments
Parameter
Max Unit
TEMPERATURE RANGE
Rated Performance5
0
70
0
70
−55
+125 °C
1 Standard military drawing available: 5962-89641012A – (SE/883B).
2 Input offset voltage specifications are guaranteed after 5 minutes at TA = 25°C.
3 Full power bandwidth = slew rate/2 π VPEAK
4 Refer to Figure 22 to Figure 24.
.
5 S grade TMIN – TMAX specifications are tested with automatic test equipment at TA = −55°C and TA = +125°C.
Rev. C | Page 4 of 16
Data Sheet
AD841
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL CHARACTERISTICS
Table 3.
Parameter
Rating
Supply Voltage (VS)
Internal Power Dissipation1
PDIP (N-14)
CERDIP (Q-14)
Input Voltage
1ꢀ V
Package Type
14-Lead CERDIP
14-Lead PDIP
20-Lead LCC
θJC
35
30
35
θJA
θSA
Unit
°C/W
°C/W
°C/W
110
100
150
3ꢀ
1.5 W
1.3 W
VS
Differential Input Voltage
Storage Temperature Range
Q-14
6 V
ESD CAUTION
−65°C to +150°C
−65°C to +125°C
N-14
Operating Temperature Range
ADꢀ41J/ADꢀ41K
ADꢀ41S
Junction Temperature
Lead Temperature Range (Soldering 60 sec)
0°C to 70°C
−55°C to +125°C
+175°C
+300°C
1 Maximum internal power dissipation is specified so that TJ does not exceed
175°C at an ambient temperature of 25°C.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
0.099
(2.5)
BALANCE
+V
S
BALANCE
–V
IN
0.067
(1.7)
OUTPUT
+V
–V
S
IN
SUBSTRATE CONNECTED TO +V
S
Figure 3. Metalization Photograph
Contact factory for latest dimensions
Dimensions shown in inches and (millimeters)
Rev. C | Page 5 of 16
AD841
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C and VS = 15 V, unless otherwise noted.
20
12
10
8
15
V
IN
10
5
6
0
4
0
5
10
SUPPLY VOLTAGE (±V)
15
20
0
5
10
15
20
SUPPLY VOLTAGE (±V)
Figure 4. Input Common-Mode Range vs. Supply Voltage
Figure 7. Quiescent Current vs. Supply Voltage
20
15
10
5
6
5
4
3
V
OUT
0
0
5
10
SUPPLY VOLTAGE (±V)
15
20
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 5. Output Voltage Swing vs. Supply Voltage
Figure 8. Input Bias Current vs. Temperature
30
25
20
15
10
5
100
10
±15V SUPPLIES
1
0.1
0.01
0
10
100
1k
10k
10k
100k
1M
10M
100M
LOAD RESISTANCE (Ω)
FREQUENCY (Hz)
Figure 6. Output Voltage Swing vs. Load Resistance
Figure 9. Output Impedance vs. Frequency
Rev. C | Page 6 of 16
Data Sheet
AD841
15
14
13
12
11
10
9
100
80
60
40
20
0
100
80
60
40
20
0
8
500Ω LOAD
1k
7
–20
100
–20
100M
–60 –40 –20
0
20
40
60
80
100 120 140
10k
100k
1M
10M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 10. Quiescent Current vs. Temperature
Figure 13. Open-Loop Gain and Phase Margin vs. Frequency
140
130
120
110
100
90
98
96
94
92
90
+OUTPUT CURRENT
–OUTPUT CURRENT
80
70
500Ω LOAD
60
–60 –40 –20
0
20
40
60
80
100 120 140
0
5
10
15
20
TEMPERATURE (°C)
SUPPLY VOLTAGE (±V)
Figure 11. Short-Circuit Current Limit vs. Temperature
Figure 14. Open-Loop Gain vs. Supply Voltage
50
45
40
35
30
120
100
80
60
40
20
0
+SUPPLY
–SUPPLY
100
1k
10k
100k
1M
10M
100M
–60 –40 –20
0
20
40
60
80
100 120 140
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 12. Gain Bandwidth Product vs. Temperature
Figure 15. Power Supply Rejection vs. Frequency
Rev. C | Page 7 of 16
AD841
Data Sheet
120
V
–70
–80
3V rms
= 1kΩ
= ±15V
= 1V p-p
= 25°C
S
R
V
L
CM
T
A
100
80
60
40
20
–90
SECOND HARMONIC
–100
–110
–120
–130
THIRD HARMONIC
1k
10k
100k
1M
10M
100M
100
1k
10k
FREQUENCY (Hz)
100k
FREQUENCY (Hz)
Figure 16. Common-Mode Rejection vs. Frequency
Figure 19. Harmonic Distortion vs. Frequency
30
25
20
15
10
5
500
450
400
350
300
250
200
V
R
= ±15V
= 1kΩ
= 25°C
S
L
T
A
0
1M
10M
100M
–60 –40 –20
0
20
40
60
80
100 120 140
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 17. Large Signal Frequency Response
Figure 20. Slew Rate vs. Temperature
10
30
25
20
15
10
5
8
6
4
2
0.1%
0.1%
0.01%
0.01%
0
–2
–4
–6
–8
–10
30
40
50
60
70
80
90
100
110
10
100
1k
10k
100k
1M
10M
SETTLING TIME (ns)
FREQUENCY (Hz)
Figure 18. Output Swing and Error vs. Settling Time
Figure 21. Input Voltage Noise Spectral Density
Rev. C | Page 8 of 16
Data Sheet
AD841
R
1kΩ
R
B
120Ω
F
0.1µF
2.2µF
0.1µF
2.2µF
+V
+V
S
S
HP3314A
FUNCTION
GENERATOR
OR
R
1kΩ
IN
4
4
–
–
11
11
EQUIVALENT
49.9Ω
10
0.1µF
2.2µF
10
0.1µF
2.2µF
V
V
HP3314A
FUNCTION
GENERATOR
OR
AD841
OUT
AD841
OUT
R
100Ω
IN
499Ω
499Ω
V
IN
6
6
5
5
+
+
EQUIVALENT
R
499Ω
B
49.9Ω
–V
–V
S
S
Figure 22. Inverting Amplifier Configuration (PDIP Pinout)
Figure 25. Unity-Gain Buffer Amplifier Configuration (PDIP Pinout)
2V
50ns
2V
50ns
100
90
100
90
10
10
0%
0%
Figure 23. Inverter Large Signal Pulse Response
Figure 26. Buffer Large Signal Pulse Response
50mV
50ns
50mV
50ns
100
90
100
90
10
10
0%
0%
Figure 24. Inverter Small Signal Pulse Response
Figure 27. Buffer Small Signal Pulse Response
Rev. C | Page 9 of 16
AD841
Data Sheet
THEORY OF OPERATION
OFFSET NULLING
10mV
5V
20ns
The input offset voltage of the AD841 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 28 can be used.
100
90
+V
S
OUTPUT ERROR:
0.02%/DIV
100Ω
100Ω
3
4
5
–
12
10
11
OUTPUT:
5V/DIV
0%
10
OUTPUT
INPUT
AD841
R
L
6
0.1µF
2.2µF
+
Figure 29. AD841 0.01% Settling Time
–V
S
Figure 28. Offset Nulling (PDIP Pinout)
TEK
7A13
ERROR
AMP
(×10)
INPUT CONSIDERATIONS
TEK
An input resistor (RIN in Figure 25) is recommended in circuits
where the input to the AD841 is subjected to transient or
continuous overload voltages exceeding the 6 V maximum
differential limit. This resistor provides protection for the input
transistors by limiting the maximum current that can be forced
into the input.
7A18
HP6263
1kΩ
1kΩ
1kΩ
1kΩ
DDD5109
FLAT-TOP
PULSE
0.1µF
2.2µF
+15V
11
GENERATOR
50Ω
For high performance circuits it is recommended that a resistor
(RB in Figure 22 and Figure 25) be used to reduce bias current
errors by matching the impedance at each input. The output
voltage error caused by the offset current is more than an order
of magnitude less than the error present if the bias current error
is not removed.
4
–
FET PROBE
TEK P6201
10
0.1µF
2.2µF
AD841
499Ω
6
5
+
499Ω
AD841 SETTLING TIME
–15V
Figure 29 and Figure 31 show the settling performance of the
AD841 in the test circuit shown in Figure 30.
Figure 30. Settling Time Test Circuit
Settling time is defined as the interval of time from the
application of an ideal step function input until the closed-loop
amplifier output has entered and remains within a specified
error band.
Measurement of the 0.01% settling in 110 ns was accomplished
by amplifying the error signal from a false summing junction
with a very high speed proprietary hybrid error amplifier
specially designed to enable testing of small settling errors.
The device under test was driving a 500 Ω load. The input to
the error amp is clamped to avoid possible problems associated
with the overdrive recovery of the oscilloscope input amplifier.
The error amp gains the error from the false summing junction
by 10, and it contains a gain vernier to fine trim the gain.
This definition encompasses the major components, which
comprise settling time. They include
•
•
•
Propagation delay through the amplifier
Slewing time to approach the final output value
The time of recovery from the overload associated
with slewing
•
Linear settling to within the specified error band
Expressed in these terms, the measurement of settling time
is obviously a challenge and needs to be done accurately to
assure the user that the amplifier is worth consideration for
the application.
Rev. C | Page 10 of 16
Data Sheet
AD841
Figure 31 shows the long-term stability of the settling charac-
teristics of the AD841 output after a 10 V step. There is no
evidence of settling tails after the initial transient recovery
time. The use of a junction isolated process, together with
careful layout, avoids these problems by minimizing the effects
of transistor isolation capacitance discharge and thermally
induced shifts in circuit operating points. These problems
do not occur even under high output current conditions.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD841 is sensitive to capaci-
tive loading. The AD841 is designed to drive capacitive loads
of up to 20 pF without degradation of its rated performance.
Capacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF (for a unity-gain follower). A
resistor in series with the output can be used to decouple larger
capacitive loads.
Figure 32 shows a typical configuration for driving a large
capacitive load. The 51 Ω output resistor effectively isolates the
high frequency feedback from the load and stabilizes the circuit.
Low frequency feedback is returned to the amplifier summing
junction via the low-pass filter formed by the 51 Ω resistor and
the load capacitance, CL.
OUTPUT ERROR:
100
0.02%/DIV
90
OUTPUT:
5V/DIV
1kΩ
10
15pF
0.1µF
2.2µF
+V
S
0%
500ns
1kΩ
4
INPUT
–
11
Figure 31. AD841 Settling Demonstrating No Settling Tails
51Ω
V
L
OUT
10
0.1µF
2.2µF
AD841
C
R
L
GROUNDING AND BYPASSING
6
5
+
In designing practical circuits with the AD841, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Avoid sockets because the increased interlead
capacitance can degrade bandwidth.
499Ω
–V
S
Figure 32. Circuit for Driving a Large Capacitive Load
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kΩ are recommended. If a larger resistor must be used, a
small (<10 pF) feedback capacitor in parallel with the feed-
back resistor, RF, may be used to compensate for these stray
capacitances and optimize the dynamic performance of the
amplifier in the particular application.
Bypass power supply leads to ground as close as possible to
the amplifier pins. A 2.2 µF capacitor in parallel with a 0.1 µF
ceramic disk capacitor is recommended.
Rev. C | Page 11 of 16
AD841
Data Sheet
TERMINATED LINE DRIVER
OVERDRIVE RECOVERY
The AD841 functions very well as a high speed line driver of
either terminated or unterminated cables. Figure 33 shows the
AD841 driving a doubly terminated cable in a follower config-
uration. The AD841 maintains a typical slew rate of 300 V/µs,
which means it can drive a 10 V, 4.7 MHz signal or a 3 V,
15.9 MHz signal.
Figure 34 shows the overdrive recovery capability of the AD841.
Typical recovery time is 200 ns from negative overdrive and
700 ns from positive overdrive.
10V
200ns
OVERDRIVEN
OUTPUT: 10V/DIV
100
90
The termination resistor, RT, (when equal to the characteristic
impedance of the cable) minimizes reflections from the far end
of the cable. A back-termination resistor, RBT, (also equal to the
characteristic impedance of the cable) may be placed between
the AD841 output and the cable to damp any stray signals
caused by a mismatch between RT and the cable’s characteristic
impedance. This results in a cleaner signal, but because half the
output voltage is dropped across RBT, the op amp must supply
double the output signal required if there is no back termina-
tion. Therefore, the full power bandwidth is cut in half.
INPUT SQUARE
WAVE: 1V/DIV
10
0%
1V
Figure 34. Overdrive Recovery
If termination is not used, cables appear as capacitive loads. If
this capacitive load is large, it should be decoupled from the
AD841 by a resistor in series with the output (see Figure 32).
0.1µF
+V
S
2.2µF
R
B
0.1µF
2.2µF
+V
S
4
–
11
OUTPUT
10
0.1µF
2.2µF
AD841
HP3314A
4
5
–
PULSE GENERATOR
OR EQUIVALENT
1kΩ
11
50Ω OR
6
75Ω CABLE
5
+
10
0.1µF
2.2µF
V
OUT
1µs ± 1V SQUARE
WAVE INPUT
AD841
R
BT
R
T
(OPTIONAL)
100Ω
50Ω
6
V
+
IN
–V
S
TERMINATION
RESISTOR
FOR INPUT
SIGNAL
Figure 35. Overdrive Recovery Test Circuit
–V
S
R
= R = CABLE CHARACTERISTIC IMPEDANCE
BT
T
Figure 33. Line Driver Configuration
Rev. C | Page 12 of 16
Data Sheet
AD841
OUTLINE DIMENSIONS
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14
1
8
7
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 36. 14-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-14)
Dimensions shown in inches and (millimeters)
0.098 (2.49) MAX
8
0.005 (0.13) MIN
14
0.310 (7.87)
0.220 (5.59)
1
7
PIN 1
0.100 (2.54) BSC
0.785 (19.94) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
15°
0°
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 37. 14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Dimensions shown in inches and (millimeters)
Rev. C | Page 13 of 16
AD841
Data Sheet
0.200 (5.08)
REF
0.075 (1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.100 (2.54) REF
0.095 (2.41)
0.075 (1.90)
0.015 (0.38)
MIN
3
19
18
20
4
8
0.028 (0.71)
0.022 (0.56)
1
0.358 (9.09)
0.342 (8.69)
SQ
0.358
0.011 (0.28)
0.007 (0.18)
R TYP
(9.09)
MAX
SQ
BOTTOM
VIEW
0.050 (1.27)
BSC
14
0.075 (1.91)
13
9
REF
45° TYP
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
0.150 (3.81)
BSC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 38. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
AD841JNZ
0°C to +70°C
0°C to +70°C
14-Lead Plastic Dual In-Line Package [PDIP]
14-Lead Plastic Dual In-Line Package [PDIP]
Die
N-14
N-14
AD841KNZ
AD841JCHIPS
AD841SCHIPS
AD841SE
AD841SE/883B
AD841SQ
Die
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
−55°C to +125°C
20-Terminal Ceramic Leadless Chip Carrier [LCC]
20-Terminal Ceramic Leadless Chip Carrier [LCC]
14-Lead Ceramic Dual In-Line Package [CERDIP]
14-Lead Ceramic Dual In-Line Package [CERDIP]
E-20-1
E-20-1
Q-14
AD841SQ/883B
Q-14
1 Z = RoHS Compliant Part.
Rev. C | Page 14 of 16
Data Sheet
NOTES
AD841
Rev. C | Page 15 of 16
AD841
NOTES
Data Sheet
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11340-0-2/13(C)
Rev. C | Page 16 of 16
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