AD9575ARUZPEC [ADI]
Network Clock Generator, Two Outputs; 网络时钟发生器，两路输出
| 型号： | AD9575ARUZPEC |
| 厂家： | 
ADI |
| 描述： | Network Clock Generator, Two Outputs |
| 文件： | 总16页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Network Clock Generator, Two Outputs
AD9575
FEATURES
GENERAL DESCRIPTION
Fully integrated VCO/PLL core
0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz
The AD9575 provides a highly integrated, dual output clock
generator function including an on-chip PLL core that is
0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz
0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz
Input crystal frequency of 19.44 MHz, 25 MHz, or
25.78125 MHz
optimized for network clocking. The integer-N PLL design is
based on the Analog Devices, Inc., proven portfolio of high
performance, low jitter frequency synthesizers to maximize line
card performance. Other applications with demanding phase
noise and jitter requirements also benefit from this part.
Pin selectable divide ratios for 33.33 MHz, 62.5 MHz,
100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz,
159.375 MHz, 161.13 MHz, and 312.5 MHz outputs
LVDS/LVPECL/LVCMOS output format
The PLL section consists of a low noise phase frequency detector
(PFD), a precision charge pump, a low phase noise voltage
controlled oscillator (VCO), and pin selectable feedback and
output dividers.
Integrated loop filter
By connecting an external crystal, popular network output
frequencies can be locked to the input reference. The output
divider and feedback divider ratios are pin programmable for the
required output rates. No external loop filter components are
required, thus conserving valuable design time and board space.
Space saving 4.4 mm × 5.0 mm TSSOP
100 mW power dissipation (LVDS output)
120 mW power dissipation (LVPECL output)
3.3 V operation
APPLICATIONS
The AD9575 is available in a 16-lead, 4.4 mm × 5.0 mm TSSOP
and can be operated from a single 3.3 V supply. The temperature
range is −40°C to +85°C.
GbE/FC/SONET line cards, switches, and routers
CPU/PCI-e applications
Low jitter, low phase noise clock generation
FUNCTIONAL BLOCK DIAGRAM
VDD × 5
LVDS OR
LVPECL
LDO
VCO
100MHz
TO 312.5MHz
XTAL
OSC
LVCMOS
33.33MHz/
62.5MHz/SEL1
SEL
AD9575
GND × 5
SEL0
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
AD9575
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................7
Thermal Resistance.......................................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions..............................8
Typical Performance Characteristics ..............................................9
Terminology.................................................................................... 11
Theory of Operation ...................................................................... 12
Phase Frequency Detector (PFD) and Charge Pump............ 12
Power Supply............................................................................... 12
LVPECL Clock Distribution..................................................... 12
LVDS Clock Distribution.......................................................... 13
LVCMOS Clock Distribution ................................................... 13
Typical Applications................................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
PLL Characteristics ...................................................................... 3
LVDS Clock Output Jitter (Typ/Max)........................................ 4
LVPECL Clock Output Jitter (Typ/Max)................................... 4
Output Frequency Select ............................................................. 5
Clock Outputs............................................................................... 5
Timing Characteristics ................................................................ 5
Power.............................................................................................. 6
Crystal Oscillator.......................................................................... 6
Timing Diagrams.......................................................................... 6
REVISION HISTORY
1/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD9575
SPECIFICATIONS
Typical (typ) value is given for VDD = 3.3 V 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are
given over full VDD and TA (−40°C to +85°C) variation.
PLL CHARACTERISTICS
Table 1.
LVDS
Typ
LVCMOS
Typ
LVPECL
Typ
Parameter
Min
Max
Min
Max
Min
Max
Unit
PHASE NOISE CHARACTERISTICS
PLL Noise (100 MHz Output)
At 1 kHz
−123
−128
−131
−150
−156
−156
−122
−129
−131
−151
−158
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
At 10 kHz
At 100 kHz
At 1 MHz
At 10 MHz
At 30 MHz
PLL Noise (106.25 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
−121
−127
−130
−149
−156
−156
−121
−128
−130
−150
−158
−159
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
At 10 MHz
At 30 MHz
PLL Noise (125 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
−120
−126
−128
−148
−155
−156
−120
−127
−129
−150
−157
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
At 10 MHz
At 30 MHz
PLL Noise (155.52 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
−118
−123
−125
−147
−155
−156
−118
−123
−125
−149
−157
−157
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
At 10 MHz
At 30 MHz
PLL Noise (156.25 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
−118
−124
−126
−146
−155
−155
−118
−125
−127
−148
−157
−157
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
At 10 MHz
At 30 MHz
PLL Noise (159.375 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
−118
−124
−126
−146
−155
−155
−118
−125
−126
−147
−156
−157
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
At 10 MHz
At 30 MHz
Rev. 0 | Page 3 of 16
AD9575
LVDS
Typ
LVCMOS
Typ
LVPECL
Typ
Parameter
Min
Max
Min
Max
Min
Max
Unit
PLL Noise (312.5 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
−112
−119
−120
−140
−152
−153
−112
−119
−120
−142
−154
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
At 10 MHz
At 30 MHz
PLL Noise (33.33 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
−131
−138
−140
−155
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
At 5 MHz
PLL Noise (62.5 MHz Output)
At 1 kHz
At 10 kHz
At 100 kHz
At 1 MHz
At 5 MHz
Spurious Content
PLL Figure of Merit
−126
−133
−134
−150
−152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
−70
−217
−70
−217
dBc/Hz
LVDS CLOCK OUTPUT JITTER (TYP/MAX)
Typical (typ) value is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 2.
Jitter Integration Bandwidth
100 MHz 106.25 MHz 125 MHz 155.52 MHz 156.25 MHz 159.375 MHz 312.5 MHz Unit
12 kHz to 20 MHz
1.875 MHz to 20 MHz
0.637 MHz to 10 MHz
0.38/0.50 0.40/0.54
0.37/0.47 0.41/0.54
0.39/0.51
0.15/0.27
0.38/0.51
0.36/0.48
ps rms
ps rms
ps rms
0.15/0.21
LVPECL CLOCK OUTPUT JITTER (TYP/MAX)
Typical (typ) value is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 3.
Jitter Integration Bandwidth
100 MHz 106.25 MHz 125 MHz 155.52 MHz 156.25 MHz 159.375 MHz 312.5 MHz Unit
12 kHz to 20 MHz
1.875 MHz to 20 MHz
0.637 MHz to 10 MHz
0.36/0.46 0.44/0.68
0.36/0.45 0.40/0.52
0.39/0.64
0.19/0.54
0.41/0.62
0.38/0.49
ps rms
ps rms
ps rms
0.22/0.35
Rev. 0 | Page 4 of 16
AD9575
OUTPUT FREQUENCY SELECT
Typical (typ) value is given for VS = 3.3 V, TA = 25°C, unless otherwise noted
Table 4.
Parameter
Min
Typ
Max
Unit Test Conditions/Comments
Select Pins (SEL0/SEL1)
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
0.83 × VS + 0.2
V
V
μA
μA
0.33 × VS − 0.2
190
150
Pull-down to GND, pull-up to VDD, pull-up to VDD via 15 kΩ,
do not connect
CLOCK OUTPUTS
Typical (typ) value is given for VS = 3.3 V, TA = 25°C, unless otherwise noted.
Table 5.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVDS CLOCK OUTPUT
Output Frequency
Differential Output Voltage (VOD)
Delta VOD
Output Offset Voltage (VOS)
Delta VOS
Short-Circuit Current (ISA, ISB)
Duty Cycle
Termination = 100 Ω differential; default
312.5
450
25
1.375
25
MHz
mV
mV
V
mV
mA
%
250
340
Refer to Figure 2 for definition
Output shorted to GND
1.125
1.25
14
50
24
55
45
LVPECL CLOCK OUTPUT
Output Frequency
Output High Voltage (VOH)
Output Low Voltage (VOL)
Differential Output Voltage (VOD)
Duty Cycle
312.5
VS –1.05 VS – 0.8
VS –1.75 VS – 1.7
MHz
V
V
mV
%
VS – 1.5
VS – 2.5
430
640
50
800
55
Refer to Figure 2 for definition
45
LVCMOS CLOCK OUTPUT
Output Frequency
Output High Voltage (VOH)
Output Low Voltage (VOL)
Duty Cycle
62.5
MHz
V
V
VS − 0.1
45
0.1
55
50
%
TIMING CHARACTERISTICS
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVDS
Termination = 100 Ω differential; CLOAD = 0 pF
20% to 80%, measured differentially
80% to 20%, measured differentially
Termination = 200 Ω differential; CLOAD = 0 pF
20% to 80%, measured differentially
80% to 20%, measured differentially
Termination = 50 Ω to 0 V; CLOAD = 5 pF
20% to 80%; CLOAD = 5 pF
Output Rise Time, tRL
Output Fall Time, tFL
LVPECL
Output Rise Time, tRL
Output Fall Time, tFL
LVCMOS
150
150
200
200
300
300
ps
ps
180
180
250
250
300
300
ps
ps
Output Rise Time, tRC
Output Fall Time, tFC
0.50
0.50
0.70
0.70
1.10
1.10
ns
ns
80% to 20%; CLOAD = 5 pF
Rev. 0 | Page 5 of 16
AD9575
POWER
Table 7.
Parameter
POWER SUPPLY
POWER DISSIPATION
LVDS
Min
Typ
Max
Unit
3.0
3.3
3.6
V
100
120
130
160
mW
mW
LVPECL
CRYSTAL OSCILLATOR
Table 8.
Parameter
CRYSTAL SPECIFICATION
Frequency
Min
Typ
Max
Unit
Test Conditions/Comments
Parallel resonant/fundamental mode
19.44
25
25.78125 MHz
ESR
40
Ω
Load Capacitance
Phase Noise
Stability
18
−138
pF
dBc/Hz
ppm
At 1 kHz offset
−30
+30
TIMING DIAGRAMS
DIFFERENTIAL
SIGNAL
SINGLE-ENDED
80%
80%
50%
LVCMOS
5pF LOAD
V
OD
20%
20%
tRL
tFL
tRC
tFC
Figure 3. LVCMOS Timing
Figure 2. LVDS or LVPECL, Timing and Differential Amplitude
Rev. 0 | Page 6 of 16
AD9575
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 9.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
VDD, VDDA, VDDX, VDD_CMOS to GND
XO1, XO2 to GND
LVDS/LVPECL OUT, LVDS/LVPECL OUT,
CMOS OUT/SEL1 to GND
Junction Temperature1
−0.3 V to +3.6 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
Table 10. Thermal Resistance1
Package Type
θJA
Unit
16-Lead TSSOP
90.3
°C/W
150°C
1 Thermal impedance measurements were taken on a 4-layer board in still air
in accordance with EIA/JESD51-7.
Storage Temperature Range
Lead Temperature (10 sec)
−65°C to +150°C
300°C
1 See Table 10 for θJA
.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 16
AD9575
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDA
VDDA
VDDX
XO1
SEL0
GND
LVDS/LVPECL OUT
LVDS/LVPECL OUT
VDD
AD9575
TOP VIEW
XO2
(Not to Scale)
GNDX
GNDA
VDDA
VDD_CMOS
CMOS OUT/SEL1
GND_CMOS
Figure 4. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
1, 7
2, 8
3
4, 5
6
Mnemonic
Description
Analog Ground.
Analog Power Supply (3.3 V).
Crystal Oscillator Power Supply.
External Crystal.
GNDA
VDDA
VDDX
XO1, XO2
GNDX
Crystal Oscillator Ground.
9
10
11
12
GND_CMOS
CMOS OUT/SEL1
VDD_CMOS
VDD
LVDS/LVPECL OUT
LVDS/LVPECL OUT
GND
Ground for LVCMOS Output.
LVCMOS Output/Output Frequency Select.
Power Supply for LVCMOS Output.
Power Supply for LVDS or LVPECL Output.
Complementary LVDS or LVPECL Output.
LVDS or LVPECL Output.
13
14
15
16
Ground for LVDS or LVPECL Output.
Output Frequency Select.
SEL0
Table 12. Output Frequency Selection1
Mode
XTAL
SEL0
SEL1
X2
GND
GND
X2
VDD
GND
VDD
LVDS/LVPECL Output
100 MHz
156.25 MHz
161.132812 MHz
125 MHz
159.375 MHz
312.5 MHz
106.25 MHz
155.52 MHz
LVCMOS Output
33.33 MHz
High-Z
High-Z
62.5 MHz
High-Z
High-Z
High-Z
High-Z
1
2
3
4
5
6
7
8
25 MHz
25 MHz
25.78125 MHz
25 MHz
25 MHz
25 MHz
25 MHz
19.44 MHz
GND
VDD
VDD
NC
15 kΩ pull-up
15 kΩ pull-up
VDD
VDD
No connect
1 The AD9575 must be power-cycled if the select pin voltages are altered.
2 X = in Mode 1 and Mode 4, Pin 10 is configured as a LVCMOS output by forcing Pin16 to GND.
Rev. 0 | Page 8 of 16
AD9575
TYPICAL PERFORMANCE CHARACTERISTICS
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5. Phase Noise at LVPECL, 100 MHz Clock Output
Figure 8. Phase Noise at LVPECL, 155.52 MHz Clock Output
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Phase Noise at LVPECL, 106.25 MHz Clock Output
Figure 9. Phase Noise at LVPECL, 156.25 MHz Clock Output
–110
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Phase Noise at LVPECL, 125 MHz Clock Output
Figure 10. Phase Noise at LVPECL, 159.375 MHz Clock Output
Rev. 0 | Page 9 of 16
AD9575
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
M2
–160
1k
M2 100mV 1ns
M3 100mV 1ns
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 14. 312.5 MHz LVPECL Output
Figure 11. Phase Noise at LVPECL, 312.5 MHz Clock Output
140
130
120
110
100
90
LVDS POWER
M2
LVPECL POWER
80
M2 100mV 10ns
M3 100mV 10ns
1
2
3
4
5
6
7
8
MODE
Figure 15. 62.5 MHz LVCMOS Output
Figure 12. Typical Power Dissipation vs. Mode
M2
M2 50mV 2ns
M3 50mV 2ns
Figure 13. 156.25 MHz LVDS Output
Rev. 0 | Page 10 of 16
AD9575
TERMINOLOGY
Phase Jitter
Time Jitter
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount of
variation from ideal phase progression over time. This phenome-
non is called phase jitter. Although many causes can contribute
to phase jitter, one major cause is random noise, which is
characterized statistically as Gaussian (normal) in distribution.
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings is
seen to vary. In a square wave, the time jitter is seen as a
displacement of the edges from their ideal (regular) times of
occurrence. In both cases, the variations in timing from the
ideal are the time jitter. Because these variations are random in
nature, the time jitter is specified in units of seconds root mean
square (rms) or 1 sigma of the Gaussian distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in fre-
quency from the sine wave (carrier). The value is a ratio (expressed
in dB) of the power contained within a 1 Hz bandwidth with
respect to the power at the carrier frequency. For each measure-
ment, the offset from the carrier frequency is also given.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured. The
phase noise of any external oscillators or clock sources has been
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise.
Phase Noise
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable
to the device or subsystem being measured. The time jitter of
any external oscillators or clock sources has been subtracted.
This makes it possible to predict the degree to which the device
impacts the total system time jitter when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own time jitter to the total. In many cases, the
time jitter of the external oscillators and clock sources
dominates the system time jitter.
Phase noise has a detrimental effect on error rate performance
by increasing eye closure at the transmitter output and reducing
the jitter tolerance/sensitivity of the receiver.
Rev. 0 | Page 11 of 16
AD9575
THEORY OF OPERATION
VDDA GNDA
VDDA GNDA
VDD_CMOS GND_CMOS
LVCMOS
1/k
PHASE
FREQUENCY
DETECTOR
XTAL
OSC
1/n
CMOS OUT/SEL1
SEL0
LDO
SEL
LVDS/LVPECL OUT
LVDS/LVPECL OUT
CHARGE
PUMP
1/m
2.5GHz TO
2.55GHz VCO
LVDS
100MHz
AD9575
V
LDO
Figure 16. Detailed Block Diagram
POWER SUPPLY
Figure 16 shows a block diagram of the AD9575. The chip
features a PLL core, which is configured to generate the specific
clock frequencies via pin programming. By appropriate connec-
tion of the select pins, SEL0 and SEL1, as described in Table 12,
the divide ratios of the feedback divider (n), LVDS output
divider (m), and LVCMOS output divider (k) can be programmed.
In Mode 1 and Mode 4, Pin 10 is configured as a LVCMOS
output by forcing Pin 16 to GND. In conjunction with a band-
select VCO that operates over the range of 2.488 GHz to 2.55 GHz,
a wide range of popular network reference frequencies can
be generated. This PLL is based on proven Analog Devices
synthesizer technology, noted for its exceptional phase noise
performance. The AD9575 is highly integrated and includes
the loop filter, a regulator for supply noise immunity, all the
necessary dividers, output buffers, and a crystal oscillator. A
user need only supply an external crystal to implement a
clocking solution, which does not require any processor
intervention.
The AD9575 requires a 3.3 V 10% power supply for VDD. The
Specifications section gives the performance expected from the
AD9575 with the power supply voltage within this range. The
absolute maximum range of −0.3 V to +3.6 V, with respect to
GND, must never be exceeded on the VDDX, VDD_CMOS,
and VDDA pins.
Good engineering practice should be followed in the layout of
power supply traces and the ground plane of the PCB. The
power supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9575 should be bypassed with
adequate capacitors (0.1 μF) at all power pins as close as
possible to the part. The layout of the AD9575 evaluation board
is a good example.
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs (because they are open emitter) require a
dc termination to bias the output transistors. The simplified
equivalent circuit in Figure 19 shows the LVPECL output stage.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 18. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the desired switching threshold (1.3 V).
The PFD takes inputs from the reference clock and feedback
divider to produce an output proportional to the phase and
frequency difference between them. Figure 17 shows a
simplified schematic.
3.3V
V
3.3V
3.3V
P
127Ω
127Ω
50Ω
CHARGE
PUMP
UP
SINGLE-ENDED
(NOT COUPLED)
HIGH
D1 Q1
CLR1
LVPECL
LVPECL
REFCLK
50Ω
83Ω
83Ω
V
= V – 1.3V
DD
T
CP
Figure 18. LVPECL Far-End Termination
CLR2
D2 Q2
DOWN
HIGH
FEEDBACK
DIVIDER
GND
Figure 17. PFD Simplified Schematic and Timing (in Lock)
Rev. 0 | Page 12 of 16
AD9575
3.3V
3.3V
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver (see
Figure 21). The value of the resistor is dependent on the board
design and timing requirements (typically 10 Ω to 100 Ω is
used). LVCMOS outputs are limited in terms of the capacitive
load or trace length that they can drive. Typically, trace lengths
less than 6 inches are recommended to preserve signal rise/fall
times and preserve signal integrity.
0.1nF
DIFFERENTIAL
(COUPLED)
100Ω
LVPECL
LVPECL
0.1nF
200Ω
200Ω
Figure 19. LVPECL with Parallel Transmission Line
LVDS CLOCK DISTRIBUTION
60.4Ω
The AD9575 is also available with low voltage differential
signaling (LVDS) outputs. LVDS uses a current mode output
stage with a factory programmed current level. The normal
value (default) for this current is 3.5 mA, which yields a 350 mV
output swing across a 100 Ω resistor. The LVDS outputs meet or
exceed all ANSI/TIA/EIA-644 specifications.
1.0 INCH
10Ω
CMOS
MICROSTRIP
5pF
GND
Figure 21. Series Termination of LVCMOS Output
Termination at the far end of the PCB trace is a second option.
The LVCMOS output of the AD9575 does not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 22. The far-end
termination network should match the PCB trace impedance
and provide the desired switching point.
A recommended termination circuit for the LVDS outputs is
shown in Figure 20.
50Ω
100Ω
LVDS
LVDS
50Ω
Figure 20. LVDS Output Termination
The reduced signal swing may still meet receiver input
requirements in some applications. This can be useful when
driving long trace lengths on less critical nets.
See the AN-586 Application Note on the Analog Devices
website at www.analog.com for more information about LVDS.
V
= 3.3V
PULLUP
LVCMOS CLOCK DISTRIBUTION
The AD9575 provides a 33.33 or 62.5 MHz clock output, which
is a dedicated LVCMOS level. Whenever single-ended LVCMOS
clocking is used, some of the following general guidelines
should be followed.
100Ω
50Ω
10Ω
LVCMOS
3pF
100Ω
Point-to-point nets should be designed such that a driver has
one receiver only on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
Figure 22. LVCMOS Output with Far-End Termination
TYPICAL APPLICATIONS
AD9575
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
GNDA
VDDA
SEL0
GND
0.1µF
1nF
V
S
V
50Ω
VDDX LVDS/LVPECL OUT
S
R
100Ω
=
T
Cx
Cx
0.1µF
50Ω
XO1
LVDS/LVPECL OUT
VDD
0.1µF
V
XO2
S
S
V
GNDX
VDD_CMOS
0.1µF
GNDA CMOS OUT/SEL1
VDDA
GND CMOS
0.1µF
V
S
Figure 23. Typical Application (in LVDS configuration)
Rev. 0 | Page 13 of 16
AD9575
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 24. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range Package Description
Package Option
AD9575ARUZLVD
−40°C to +85°C
16-Lead Thin Shrink Small Outline Package (TSSOP), 96 pcs per Tube,
LVDS Output Format
RU-16
AD9575ARUZPEC
−40°C to +85°C
16-Lead Thin Shrink Small Outline Package (TSSOP), 96 pcs per Tube,
LVPECL Output Format
RU-16
AD9575-EVALZ-LVD
AD9575-EVALZ-PEC
LVDS Outputs, Evaluation Board
LVPECL Outputs, Evaluation Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 14 of 16
AD9575
NOTES
Rev. 0 | Page 15 of 16
AD9575
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08462-0-1/10(0)
Rev. 0 | Page 16 of 16
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