ADA4937-2YCPZ-RL [ADI]
Ultralow Distortion Differential ADC Driver;
| 型号： | ADA4937-2YCPZ-RL |
| 厂家： | 
ADI |
| 描述： | Ultralow Distortion Differential ADC Driver |
| 文件： | 总28页 (文件大小：591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Distortion
Differential ADC Driver
ADA4937-1/ADA4937-2
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
ADA4937-1
Extremely low harmonic distortion (HD)
−112 dBc HD2 at 10 MHz
−84 dBc HD2 at 70 MHz
−77 dBc HD2 at 100 MHz
−102 dBc HD3 at 10 MHz
−91 dBc HD3 at 70 MHz
−84 dBc HD3 at 100 MHz
–FB
+IN
1
2
3
4
12
PD
11 –OUT
10
9
–IN
+OUT
+FB
V
OCM
Low input voltage noise: 2.2 nV/√Hz
High speed
−3 dB bandwidth of 1.9 GHz, G = 1
Slew rate: 6000 V/μs, 25% to 75%
Fast overdrive recovery of 1 ns
0.5 mV typical offset voltage
Externally adjustable gain
Figure 1. ADA4937-1
ADA4937-2
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Single-supply operation: 3.3 V to 5 V
1
2
3
4
5
6
18
17
16
15
14
–IN1
+OUT1
+FB1
V
OCM1
–V
–V
+V
S1
S2
S2
+V
S1
–FB2
+IN2
PD2
APPLICATIONS
13 –OUT2
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Figure 2. ADA4937-2
–55
–60
Line drivers
HD2, V = 5.0V
S
HD3, V = 5.0V
S
GENERAL DESCRIPTION
HD2, V = 3.3V
S
–65
HD3, V = 3.3V
S
The ADA4937-1/ADA4937-2 are low noise, ultralow distortion,
high speed differential amplifiers. They are an ideal choice for
driving high performance ADCs with resolutions up to 16 bits
from dc to 100 MHz. The adjustable level of the output common
mode allows the ADA4937-1/ADA4937-2 to match the input
of the ADC. The internal common-mode feedback loop also
provides exceptional output balance as well as suppression of
even-order harmonic distortion products.
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
With the ADA4937-1/ADA4937-2, differential gain configurations
are easily realized with a simple external feedback network of
four resistors that determine the closed-loop gain of the amplifier.
1
10
FREQUENCY (MHz)
100
Figure 3. Harmonic Distortion vs. Frequency
The ADA4937-1/ADA4937-2 are fabricated using Analog Devices,
Inc., proprietary silicon-germanium (SiGe), complementary
bipolar process, enabling them to achieve very low levels of
distortion with an input voltage noise of only 2.2 nV/√Hz.
The low dc offset and excellent dynamic performance of the
ADA4937-1/ADA4937-2 make them well-suited for a wide
variety of data acquisition and signal processing applications.
The ADA4937-1/ADA4937-2 are available in a Pb-free, 3 mm ×
3 mm, 16-lead LFCSP (ADA4937-1, single) or a Pb-free, 4 mm ×
4 mm, 24-lead LFCSP (ADA4937-2, dual). The pinout has been
optimized to facilitate PCB layout and minimize distortion.
The ADA4937-1/ADA4937-2 are specified to operate over the
automotive (−40°C to +105°C) temperature range and between
3.3 V and 5 V supplies.
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADA4937-1/ADA4937-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analyzing an Application Circuit ............................................ 18
Setting the Closed-Loop Gain .................................................. 18
Estimating the Output Noise Voltage...................................... 18
Impact of Mismatches in the Feedback Networks................. 19
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Operation ............................................................................... 3
3.3 V Operation ............................................................................ 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 16
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
Calculating the Input Impedance for an Application Circuit
....................................................................................................... 19
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 20
Setting the Output Common-Mode Voltage.......................... 20
Power-Down Operation ............................................................ 20
Layout, Grounding, and Bypassing.............................................. 22
High Performance ADC Driving ................................................. 23
3.3 V Operation .......................................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
6/2016—Rev. E to Rev. F
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 26
Changes to Figure 5 and Figure 6....................................................8
Added EP Row to Table 7 and EP Row to Table 8 ........................8
Added Figure 46, Figure 47, and Figure 48; Renumbered
Sequentially ..................................................................................... 15
Changes to Table 9.......................................................................... 18
Changes to Input Common-Mode Voltage Range in Single-
Supply Applications Section.......................................................... 20
Changes to Ordering Guide.......................................................... 26
5/2015—Rev. D to Rev. E
Changes to Table 6............................................................................ 7
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide .......................................................... 26
8/2013—Rev. C to Rev. D
11/2007—Rev. 0 to Rev. A
Changes to Input Bias Current Parameter, Table 1...................... 3
Changes to Input Bias Current Parameter, Table 3...................... 5
Updated Outline Dimensions....................................................... 26
Added the ADA4937-2......................................................Universal
Changes to Features ..........................................................................1
Changes to Specifications.................................................................3
Changes to Figure 4...........................................................................7
Changes to Typical Performance Characteristics..........................9
Inserted Figure 44........................................................................... 15
Added the Terminating a Single-Ended Input Section ............. 19
Changes to Table 10 and Table 11 ................................................ 21
Changes to Layout, Grounding, and Bypassing Section ........... 22
Inserted Figure 59, Figure 60, and Figure 61.............................. 22
Updated Outline Dimensions....................................................... 26
Changes to Ordering Guide.......................................................... 26
3/2010—Rev. B to Rev. C
Changes to Table 2, Power Supply Parameter............................... 4
Changes to Table 4, Power Supply Parameter............................... 6
Changes to Figure 43...................................................................... 15
Added the Power-Down Operation Section ............................... 20
10/2009—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changes to Table 1............................................................................ 3
Changes to Operating Temperature Range Parameter, Table 2.. 4
Changes to Table 3............................................................................ 5
Changes to Figure 4.......................................................................... 7
5/2007—Revision 0: Initial Version
Rev. F | Page 2 of 28
Data Sheet
ADA4937-1/ADA4937-2
SPECIFICATIONS
5 V OPERATION
TA = 25°C, +VS = 5 V, −V S = 0 V, V OCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, Gain (G) = +1, RL, dm = 1 kΩ, unless otherwise noted. All
specifications refer to single-ended input and differential outputs, unless otherwise noted.
±±IN to ±OUT Performance
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
VOUT, dm = 0.1 V p-p
VOUT, dm = 0.1 V p-p
VOUT, dm = 2 V p-p
VOUT, dm = 2 V p-p; 25% to 75%
VOUT, dm = 2 V p-p
1900
200
1700
6000
7
MHz
MHz
MHz
V/µs
ns
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
VIN = 0 V to 1.5 V step; G = 3.16
See Figure 51 for distortion test circuit
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p; 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p; 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
f1 = 70 MHz; f2 = 70.1 MHz; VOUT, dm = 2 V p-p
f = 100 kHz
<1
ns
−112
−84
−77
−102
−91
−84
−91
2.2
dBc
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
dB
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Noise Figure
Crosstalk (ADA4937-2)
INPUT CHARACTERISTICS
Offset Voltage
f = 100 kHz
4
15
−72
G = 4; RT = 136 Ω; RF = 200 Ω; RG = 37 Ω; f = 100 MHz
f = 100 MHz
dB
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = 2.5 V
TMIN to TMAX variation
−2.5
−50
−2
0.5
1
−30
0.01
+0.5
6
3
1
+2.5
−10
+2
mV
µV/°C
µA
µA/°C
µA
MΩ
MΩ
pF
Input Bias Current
TMIN to TMAX variation
Input Offset Current
Input Resistance
Differential
Common mode
Input Capacitance
Input Common-Mode Voltage
CMRR
0.3 to 3.0
−80
V
dB
∆VOUT, dm/∆VIN, cm; ∆VIN, cm
=
1 V
−69
0.9
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
Maximum ∆VOUT; single-ended output; RF = RG = 10 kΩ
Per amplifier; RL, dm = 20 Ω; f = 10 MHz
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V; f = 10 MHz;
see Figure 50 for test circuit
4.1
V
mA
dB
70
−61
Rev. F | Page 3 of 28
ADA4937-1/ADA4937-2
Data Sheet
VOCM to ±OUT Performance
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
440
1150
7.5
MHz
V/µs
nV/√Hz
VIN = 1.5 V to 3.5 V; 25% to 75%
f = 100 kHz
1.2
8
3.8
12
7.1
V
10
2
0.5
−75
0.98
kΩ
mV
µA
dB
V/V
VOS, cm = VOUT, cm; VDIN+ = VDIN− = +VS/2
ΔVOUT, dm/ΔVOCM; ΔVOCM
ΔVOUT, cm/ΔVOCM; ΔVOCM
=
=
1 V
1 V
−70
0.97
Gain
1.00
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
3.0
38.0
5.25
42.0
V
Enabled
TMIN to TMAX variation
Powered down
39.5
17
0.3
mA
µA/°C
mA
dB
0.02
−70
0.5
Power Supply Rejection Ratio
POWER-DOWN (PD)
ΔVOUT, dm/ΔVS; ΔVS = 1 V
−90
PD Input Voltage
Powered down
Enabled
≤1
≥2
1
V
V
µs
ns
Turn-Off Time
Turn-On Time
200
PD Bias Current per Amplifier
Enabled
PD = 5 V
PD = 0 V
10
30
50
µA
µA
°C
Powered Down
−300
−40
−200
−150
+105
OPERATING TEMPERATURE RANGE
Rev. F | Page 4 of 28
Data Sheet
ADA4937-1/ADA4937-2
3.3 V OPERATION
TA = 25°C, +VS = 3.3 V, −VS = 0 V, V OCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, G = 1, RL, dm = 1 kΩ, unless otherwise noted. All
specifications refer to single-ended input and differential outputs, unless otherwise noted.
±±IN to ±OUT Performance
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
VOUT, dm = 0.1 V p-p
VOUT, dm = 0.1 V p-p
VOUT, dm = 2 V p-p
VOUT, dm = 2 V p-p; 25% to 75%
VOUT, dm = 2 V p-p
1800
200
1300
4000
7
MHz
MHz
MHz
V/µs
ns
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
VIN = 0 V to 1.0 V step; G = 3.16
See Figure 51 for distortion test circuit
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p; 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
VOUT, dm = 2 V p-p; 10 MHz
VOUT, dm = 2 V p-p; 70 MHz
VOUT, dm = 2 V p-p; 100 MHz
f1 = 70 MHz; f2 = 70.1 MHz; VOUT, dm = 2 V p-p
f = 100 kHz
<1
ns
−113
−85
−77
−95
−77
−71
−87
2.2
dBc
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
dB
Third Harmonic
IMD
Voltage Noise (RTI)
Input Current Noise
Noise Figure
Crosstalk (ADA4937-2)
INPUT CHARACTERISTICS
Offset Voltage
f = 100 kHz
4
15
−72
G = 4; RT = 136 Ω; RF = 200 Ω; RG = 37 Ω; f = 100 MHz
f = 100 MHz
dB
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = +VS/2
TMIN to TMAX variation
−2.5
−50
0.5
1
−30
0.01
6
3
1
+2.5
−10
mV
µV/°C
µA
µA/°C
MΩ
MΩ
pF
Input Bias Current
Input Resistance
TMIN to TMAX variation
Differential
Common mode
Input Capacitance
Input Common-Mode Voltage
CMRR
0.3 to 1.2
−80
V
dB
∆VOUT, dm/∆VIN, cm; ∆VIN, cm
=
1 V
−67
0.8
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
Maximum ∆VOUT; single-ended output; RF = RG = 10 kΩ
Per amplifier; RL, dm = 20 Ω; f = 10 MHz
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V; f = 10 MHz;
see Figure 50 for test circuit
2.5
V
mA
dB
47
−61
Rev. F | Page 5 of 28
ADA4937-1/ADA4937-2
Data Sheet
VOCM to ±OUT Performance
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
440
900
7.5
MHz
V/µs
nV/√Hz
VIN = 0.9 V to 2.4 V; 25% to 75%
f = 100 kHz
1.2
2.1
7.1
V
10
2
0.5
−75
0.98
kΩ
mV
µA
dB
V/V
VOS, cm = VOUT, cm; VDIN+ = VDIN− = 1.67 V
∆VOUT, dm/∆VOCM; ∆VOCM
∆VOUT, cm/∆VOCM; ∆VOCM
=
=
1 V
1 V
−70
0.97
Gain
1.00
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
3.0
36
5.25
40
V
Enabled
TMIN to TMAX variation
Powered down
38
17
0.2
−90
mA
µA/°C
mA
dB
0.02
−70
0.5
Power Supply Rejection Ratio
POWER-DOWN (PD)
∆VOUT, dm/∆VS; ∆VS = 1 V
PD Input Voltage
Powered down
Enabled
≤1
≥2
1
V
V
µs
ns
Turn-Off Time
Turn-On Time
200
PD Bias Current per Amplifier
Enabled
PD = 3.3 V
PD = 0 V
10
20
30
µA
µA
°C
Powered Down
−200
−40
−120
−100
+105
OPERATING TEMPERATURE RANGE
Rev. F | Page 6 of 28
Data Sheet
ADA4937-1/ADA4937-2
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Table 5.
Parameter
Rating
Supply Voltage
5.5 V
Power Dissipation
See Figure 4
−65°C to +125°C
−40°C to +105°C
300°C
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through holes, ground,
and power planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the ADA4937-1 single
16-lead LFCSP (95°C/W), and the ADA4937-2 dual 24-lead
LFCSP (67°C/W) on a JEDEC standard 4-layer board.
3.5
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD51-7.
3.0
2.5
Table 6. Thermal Resistance
ADA4937-2
Package Type
θJA
95
67
θJC
Unit
°C/W
°C/W
2.0
16-Lead LFCSP (Exposed Pad)
24-Lead LFCSP (Exposed Pad)
12.6
8.78
1.5
ADA4937-1
1.0
Maximum Power ±issipation
The maximum safe power dissipation in the ADA4937-1/
0.5
ADA4937-2 packages is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which is
the glass transition temperature, the plastic changes the properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4937-1/
ADA4937-2. Exceeding a junction temperature of 150°C for
an extended period can result in changes in the silicon devices,
potentially causing failure.
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 110
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature, 4-Layer Board
ESD CAUTION
Rev. F | Page 7 of 28
ADA4937-1/ADA4937-2
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
18
17
–IN1
+OUT1
–FB
+IN
–IN
1
2
3
4
12 PD
+FB1
V
OCM1
ADA4937-1
TOP VIEW
(Not to Scale)
ADA4937-2
11 –OUT
16 –V
+V
S1
S2
S2
TOP VIEW
15
14
13
–V
+V
S1
10
9
+OUT
(Not to Scale)
–FB2
+IN2
PD2
+FB
V
OCM
–OUT
2
NOTES
1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT
ELECTRICALLY CONNECTED TO THE DEVICE. IT IS
TYPICALLY SOLDERED TO GROUND OR A POWER
PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE.
NOTES
1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT
ELECTRICALLY CONNECTED TO THE DEVICE. IT IS
TYPICALLY SOLDERED TO GROUND OR A POWER
PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE.
Figure 5. ADA4937-1 Pin Configuration
Figure 6. ADA4937-2 Pin Configuration
Table 7. ADA4937-1 Pin Function Descriptions
Pin No. Mnemonic Description
Table 8. ADA4937-2 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
−FB
Negative Output for Feedback
Component Connection.
1
2
3, 4
5
6
7
8
9, 10
11
12
−IN1
+FB1
+VS1
−FB2
+IN2
−IN2
+FB2
+VS2
VOCM2
+OUT2
−OUT2
PD2
Negative Input Summing Node 1.
Positive Output Feedback Pin 1.
Positive Supply Voltage 1.
Negative Output Feedback Pin 2.
Positive Input Summing Node 2.
Negative Input Summing Node 2.
Positive Output Feedback Pin 2.
Positive Supply Voltage 2.
Output Common-Mode Voltage 2.
Positive Output 2.
2
3
4
+IN
−IN
+FB
Positive Input Summing Node.
Negative Input Summing Node.
Positive Output for Feedback
Component Connection.
5 to 8
9
10
11
12
+VS
Positive Supply Voltage.
VOCM
+OUT
−OUT
PD
Output Common-Mode Voltage.
Positive Output for Load Connection.
Negative Output for Load Connection.
Power-Down Pin.
13
14
Negative Output 2.
Power-Down Pin 2.
13 to 16 −VS
EP
Negative Supply Voltage.
Exposed Paddle. The exposed pad is not
electrically connected to the device. It is
typically soldered to ground or a power
plane on the PCB that is thermally
conductive.
15, 16
17
18
19
20
−VS2
Negative Supply Voltage 2.
Output Common-Mode Voltage 1.
Positive Output 1.
Negative Output 1.
Power-Down Pin 1.
VOCM1
+OUT1
−OUT1
PD1
21, 22
23
24
−VS1
−FB1
+IN1
Negative Supply Voltage 1.
Negative Output Feedback Pin 1.
Positive Input Summing Node 1.
EP
Exposed Paddle. The exposed pad is
not electrically connected to the
device. It is typically soldered to
ground or a power plane on the PCB
that is thermally conductive.
Rev. F | Page 8 of 28
Data Sheet
ADA4937-1/ADA4937-2
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, +VS = 5 V, −VS = 0 V, VOUT, dm = 2 V p-p, VOCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, G = 1, RL, dm = 1 kꢀ, unless otherwise
noted. Refer to Figure 49 for the test setup circuit.
6
6
3
3
0
0
–3
–6
–9
–12
–15
–3
–6
–9
–12
–15
G = +1, R = 200Ω
G = +1, R = 200Ω
F
F
G = +2, R = 402Ω
G = +2, R = 402Ω
F
F
G = +5, R = 402Ω
G = +5, R = 402Ω
F
F
1
10
100
FREQUENCY (MHz)
1000
1
10
100
FREQUENCY (MHz)
1000
Figure 7. Small Signal Frequency Response for Various Gains,
VOUT, dm = 100 mV p-p
Figure 10. Large Signal Frequency Response for Various Gains
6
6
V
V
= 3.3V
= 5.0V
V
V
= 3.3V
= 5.0V
S
S
S
S
3
0
3
0
–3
–3
–6
–6
–9
–9
–12
–15
–12
–15
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. Large Signal Frequency Response for Various Supplies
Figure 8. Small Signal Frequency Response for Various Supplies,
VOUT, dm = 100 mV p-p
6
6
+105°C
+105°C
+25°C
+25°C
–40°C
–40°C
3
3
0
–3
0
–3
–6
–6
–9
–9
–12
–12
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Small Signal Frequency Response for Various Temperatures,
VOUT, dm = 100 mV p-p
Figure 12. Large Signal Frequency Response for Various Temperatures
Rev. F | Page 9 of 28
ADA4937-1/ADA4937-2
Data Sheet
6
6
3
R
R
R
= 1kΩ
= 100Ω
= 200Ω
R
R
R
= 1kΩ
= 100Ω
= 200Ω
L
L
L
L
L
L
3
0
0
–3
–6
–9
–3
–6
–9
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 13. Small Signal Frequency Response for Various Loads,
VOUT, dm = 100 mV p-p
Figure 16. Large Signal Frequency Response for Various Loads
6
3
6
3
0
0
–3
–6
–9
–12
–3
–6
–9
–12
V
V
V
= 3.3V, G = +1, R = 200Ω
V
V
V
= 3.3V, G = +1, R = 200Ω
S
S
S
F
S
S
S
F
= 3.3V, G = +2, R = 402Ω
= 3.3V, G = +2, R = 402Ω
F
F
= 3.3V, G = +5, R = 402Ω
= 3.3V, G = +5, R = 402Ω
F
F
–15
–15
1
10
100
FREQUENCY (MHz)
1000
1
10
100
FREQUENCY (MHz)
1000
Figure 17. Large Signal Frequency Response for Various Gains, VS = 3.3 V
Figure 14. Small Signal Frequency Response for Various Gains,
VS = 3.3 V, VOUT, dm = 100 mV p-p
6
6
3
3
0
0
–3
–6
–9
–3
–6
–9
–12
–12
–15
G = +1, R = 348Ω
G = +1, R = 348Ω
F
F
G = +2, R = 348Ω
G = +2, R = 348Ω
F
F
G = +5, R = 348Ω
G = +5, R = 348Ω
F
F
–15
1
10
100
1000
1
10
100
FREQUENCY (MHz)
1000
FREQUENCY (MHz)
Figure 18. Large Signal Frequency Response for Various Gains, RF = 348 Ω
Figure 15. Small Signal Frequency Response for Various Gains,
VOUT, dm = 100 mV p-p, RF = 348 Ω
Rev. F | Page 10 of 28
Data Sheet
ADA4937-1/ADA4937-2
3
–50
–60
HD2, G = +1, R = 200Ω
V
V
V
= 1.0V
= 2.5V
= 3.9V
F
OCM
HD3, G = +1, R = 200Ω
F
OCM
OCM
HD2, G = +2, R = 402Ω
F
HD3, G = +2, R = 402Ω
0
–3
F
–70
–80
–90
–6
–100
–110
–120
–9
–12
1
10
100
1000
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 19. Small Signal Frequency Response for Various VOCM
Figure 22. Harmonic Distortion vs. Frequency and Gain
1.5
–50
HD2, R = 1kΩ
L
R
R
R
R
= 1kΩ, ADA4937-1
= 100Ω, ADA4937-1
= 1kΩ, ADA4937-2
= 100Ω, ADA4937-2
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
L
L
L
L
HD3, R = 1kΩ
L
HD2, R = 200Ω
–60
–70
L
HD3, R = 200Ω
L
–80
–90
–100
–110
–120
–0.1
–0.2
–0.3
–0.4
–0.5
1
10
100
1000
1
10
FREQUENCY (MHz)
100
FREQUENCY (MHz)
Figure 20. 0.1 dB Flatness Response for Various Loads
Figure 23. Harmonic Distortion vs. Frequency and Load
–55
–60
–50
HD2, V = 5.0V
HD2, V = 3.3V
S
S
HD3, V = 5.0V
HD3, V = 3.3V
S
S
–60
–70
HD2, V = 3.3V
HD2, V = 5.0V
S
S
–65
HD3, V = 3.3V
HD3, V = 5.0V
S
S
–70
–75
–80
–80
–85
–90
–90
–100
–110
–120
–130
–95
–100
–105
–110
–115
1
10
100
–1
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
V
(V)
OUT
Figure 21. Harmonic Distortion vs. Frequency and Supply Voltage
Figure 24. Harmonic Distortion vs. VOUT and Supply Voltage
Rev. F | Page 11 of 28
ADA4937-1/ADA4937-2
Data Sheet
–30
0
–20
HD2, f = 10MHz
HD3, f = 10MHz
HD2, f = 75MHz
HD3, f = 75MHz
–40
–50
–60
–70
–40
–60
–80
–90
–80
–100
–110
–120
–100
–120
1.0
1.5
2.0
2.5
3.0
3.5
4.0
69.4
69.6
69.8
70.0
70.2
70.4
70.6
1000
1000
V
(V)
FREQUENCY (MHz)
OCM
Figure 25. Harmonic Distortion vs. VOCM and Frequency
Figure 28. 70 MHz Intermodulation Distortion
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
HD2, f = 30MHz
HD3, f = 30MHz
HD2, f = 75MHz
HD3, f = 75MHz
R
= 200Ω
L
1.1
1.2
1.3
1.4
1.5
1.6
(V)
1.7
1.8
1.9
2.0
1
10
100
V
FREQUENCY (MHz)
OCM
Figure 26. Harmonic Distortion vs. VOCM and Frequency, VS = 3.3 V
Figure 29. CMRR vs. Frequency
–50
–10
–20
–30
–40
–50
–60
HD2, 1V p-p
HD3, 1V p-p
HD2, 2V p-p
R
= 200Ω
L
–60
HD3, 2V p-p
–70
–80
–90
–100
–110
–120
–130
1
10
100
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 27. Harmonic Distortion vs. Frequency and VOUT, VS = 3.3 V
Figure 30. Output Balance vs. Frequency
Rev. F | Page 12 of 28
Data Sheet
ADA4937-1/ADA4937-2
–30
V
28
26
24
22
20
18
16
14
12
10
PSRR, V = 3.3V
G = +1
G = +2
G = +4
OUT, dm
S
V
PSRR, V = 5.0V
S
OUT, dm
–40
–50
–60
–70
–80
–90
–100
1
10
100
1000
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 31. PSRR vs. Frequency, RL = 200 Ω
Figure 34. Noise Figure vs. Frequency
0
5
4
S11
S22
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
V
V
× 3.16
IN
OUT, dm
3
2
1
0
–1
–2
–3
–4
–5
1
10
100
1000
TIME (4ns/DIV)
FREQUENCY (MHz)
Figure 32. Return Loss (S11, S22) vs. Frequency
Figure 35. Overdrive Recovery Time (Pulse Input)
–55
–60
5
4
SFDR, R = 1kΩ
L
V
V
× 3
IN
OUT, dm
SFDR, R = 200Ω
L
–65
3
–70
2
–75
1
–80
–85
0
–90
–1
–2
–3
–4
–5
–95
–100
–105
–110
–115
+V = +2.5V
S
–V = –2.5V
S
0
100
200
300
400
500
600
1
10
FREQUENCY (MHz)
100
TIME (ns)
Figure 33. Spurious-Free Dynamic Range vs. Frequency and Load
Figure 36. Overdrive Amplitude Characteristics (Triangle Wave Input)
Rev. F | Page 13 of 28
ADA4937-1/ADA4937-2
Data Sheet
60
55
50
45
40
35
60
55
50
45
40
35
30
25
20
15
10
5
+105°C
+55°C
+25°C
0°C
30
+25°C
+105°C
25
+55°C
20
0°C
15
–40°C
–40°C
10
5
0
1.0
0
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
POWER-DOWN VOLTAGE (V)
POWER-DOWN VOLTAGE (V)
PD
PD
for Various Temperatures, VS = 3.3 V
Figure 37. Supply Current vs.
for Various Temperatures
Figure 40. Supply Current vs.
0.20
3.5
3.0
+V = +2.5V
+V = +2.5V
S
S
V
V
= 4V p-p
= 2V p-p
OUT, dm
OUT, dm
–V = –2.5V
–V = –2.5V
S
S
0.15
0.10
0.05
0
V
= 0V
V = 0V
OCM
OCM
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–0.05
–0.10
–0.15
–0.20
TIME (1ns/DIV)
TIME (1ns/DIV)
Figure 41. Large Signal Pulse Response
Figure 38. Small Signal Pulse Response
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
2.60
2.58
2.56
2.54
2.52
2.50
2.48
2.46
2.44
2.42
2.40
V
= +5V
S
V
= +5V
S
G = 1
G = 1
R
= 1kΩ
L, dm
R
= 1kΩ
L, dm
TIME (2ns/DIV)
TIME (2ns/DIV)
Figure 42. Large Signal VOCM Pulse Response
Figure 39. Small Signal VOCM Pulse Response
Rev. F | Page 14 of 28
Data Sheet
ADA4937-1/ADA4937-2
10
9
8
7
6
5
4
3
2
1
0
10
G = 1
POWER-DOWN PULSE
1
OUTPUT
0.1
0.01
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
0.1
1
10
100
1k
TIME (ms)
FREQUENCY (MHz)
PD
Figure 46. Closed-Loop Output Impedance
Figure 43.
Response vs. Time
2
1
1.0
–40
–50
–60
V
IN
INPUT2, OUTPUT1
0.5
0.1
–70
SETTLING ERROR
–80
0
0
–0.1
–90
–100
–110
–120
–130
–140
INPUT1, OUTPUT2
–1
–2
–0.5
–1.0
0.3
1
10
FREQUENCY (MHz)
100
1000
TIME (1ns/DIV)
Figure 44. Crosstalk vs. Frequency for ADA4937-2
Figure 47. 0.1% Settling Time
100
10
1
70
50
PHASE
60
50
0
GAIN
–50
–100
–150
–200
–250
–300
40
30
20
10
0
–10
–20
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k 100k 1M 10M 100M 1G 10G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 45. Voltage Spectral Noise Density, RTI
Figure 48. Open-Loop Gain and Phase vs. Frequency
Rev. F | Page 15 of 28
ADA4937-1/ADA4937-2
TEST CIRCUITS
Data Sheet
200Ω
5V
50Ω
200Ω
V
V
IN
OCM
61.9Ω
ADA4937
1kΩ
200Ω
27.5Ω
200Ω
Figure 49. Equivalent Basic Test Circuit
200Ω
5V
50Ω
200Ω
50Ω
V
V
IN
OCM
61.9Ω
ADA4937
200Ω
50Ω
27.5Ω
200Ω
Figure 50. Test Circuit for Output Balance
200Ω
5V
0.1µF
50Ω
200Ω
412Ω
FILTER
FILTER
61.9Ω
V
V
IN
OCM
ADA4937
0.1µF
200Ω
412Ω
27.5Ω
200Ω
Figure 51. Test Circuit for Distortion Measurements
Rev. F | Page 16 of 28
Data Sheet
ADA4937-1/ADA4937-2
TERMINOLOGY
–FB
Common-Mode Voltage
Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as
R
F
R
G
+IN
–OUT
+D
IN
V
R
V
OUT, dm
OCM
L, dm
ADA4937
V
OUT, cm = (V+OUT + V−OUT)/2
–D
IN
–IN
+OUT
R
G
R
F
Output Balance
+FB
Output balance is a measure of how close the differential signals
are to being equal in amplitude and opposite in phase. Output
balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the midpoint of the
divider with the magnitude of the differential signal (see Figure 50).
By this definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage.
Figure 52. Circuit Definitions
Differential Voltage
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as
V
OUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
VOUT, cm
Output Balance Error
VOUT , dm
Rev. F | Page 17 of 28
ADA4937-1/ADA4937-2
Data Sheet
THEORY OF OPERATION
The ADA4937-1/ADA4937-2 differ from conventional
operational amplifiers in that they have two outputs whose voltages
move in opposite directions. Like an operational amplifier, they
rely on open-loop gain and negative feedback to force these
outputs to the desired voltages. The ADA4937-1/ADA4937-2
behave much like standard voltage feedback operational amplifiers,
which makes it easier to perform single-ended-to-differential
conversions, common-mode level shifting, and amplifications
of differential signals. Also like an operational amplifier, the
ADA4937-1/ADA4937-2 have high input impedance and low
output impedance.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 52 can be
determined by
VOUT, dm
RF
RG
VIN, dm
This assumes that the input resistors (RG) and feedback resistors
(RF) on each side are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
To estimate the differential output noise of the ADA4937-1/
ADA4937-2 use the noise model in Figure 53. The input-referred
noise voltage density, vnIN, is modeled as a differential input, and
the noise currents, inIN− and inIN+, appear between each input and
ground. The noise currents are assumed to be equal and produce
a voltage across the parallel combination of the gain and feedback
resistances. vn, cm is the noise voltage density at the VOCM pin. Each
of the four resistors contributes (4kTRx)1/2. Table 9 summarizes
the input noise sources, the multiplication factors, and the output-
referred noise density terms.
Two feedback loops control the differential and common-mode
output voltages. The differential feedback loop, set with external
resistors, controls only the differential output voltage. The
common-mode feedback loop controls only the common-mode
output voltage. This architecture makes it easy to set the output
common-mode level to any arbitrary value. It is forced, by internal
common-mode feedback, to be equal to the voltage applied to
the VOCM input without affecting the differential output voltage.
The ADA4937-1/ADA4937-2 architecture results in outputs
that are highly balanced over a wide frequency range without
requiring tightly matched external components. The common-
mode feedback loop forces the signal component of the output
common-mode voltage to zero. This results in nearly perfectly
balanced differential outputs that are identical in amplitude and
are exactly 180° apart in phase.
V
V
nRG1
nRF1
R
R
F1
G1
inIN+
+
V
nIN
V
nOD
inIN–
ADA4937
V
OCM
ANALYZING AN APPLICATION CIRCUIT
V
nCM
The ADA4937-1/ADA4937-2 use open-loop gain and negative
feedback to force their differential and common-mode output
voltages in such a way as to minimize the differential and
common-mode error voltages. The differential error voltage is
defined as the voltage between the differential inputs labeled
+IN and −IN (see Figure 52). For most purposes, this voltage
can be assumed to be zero. Similarly, the difference between the
actual output common-mode voltage and the voltage applied to
R
R
F2
G2
V
V
nRG2
nRF2
Figure 53. ADA4937-1/ADA4937-2 Noise Model
VOCM can also be assumed to be zero. Starting from these two
assumptions, any application circuit can be analyzed.
Table 9. Output Noise Voltage Density Calculations
Output Noise Voltage
Density Term
vnO1 = GN(vnIN
vnO2 = GN[inIN− × (RG2||RF2)]
vnO3 = GN[inIN+ × (RG1||RF1)]
Input Noise Contribution Input Noise Term Input Noise Voltage Density Output Multiplication Factor
Differential Input
Inverting Input
Noninverting Input
VOCM Input
vnIN
inIN−
inIN+
vn, cm
vnRG1
vnRG2
vnRF1
vnRF2
vnIN
GN
GN
GN
)
inIN− × (RG2||RF2)
inIN+ × (RG1||RF1)
vn, cm
GN(β1 − β2)
vnO4 = GN(β1 − β2)(vn, cm)
Gain Resistor RG1
Gain Resistor RG2
Feedback Resistor RF1
Feedback Resistor RF2
(4kTRG1)1/2
(4kTRG2)1/2
(4kTRF1)1/2
(4kTRF2)1/2
GN(1 − β1)
GN(1 − β2)
1
1
vnO5 = GN(1 − β1)(4kTRG1)1/2
vnO6 = GN(1 − β2)(4kTRG2)1/2
vnO7 = (4kTRF1)1/2
vnO8 = (4kTRF2)1/2
Rev. F | Page 18 of 28
Data Sheet
ADA4937-1/ADA4937-2
R
F
Similar to the case of a conventional operational amplifier, the
output noise voltage densities can be estimated by multiplying
the input-referred terms at +IN and −IN by the appropriate output
factor, where:
ADA4937
+V
S
R
R
G
+IN
+D
–D
IN
V
OCM
V
2
OUT, dm
GN
is the circuit noise gain.
IN
β1 β2
RG1
F1 RG1
–IN
G
RG2
R
F
and
are the feedback factors.
β1
β2
R
RF2 RG2
Figure 54. ADA4937-1/ADA4937-2 Configured for Balanced (Differential) Inputs
When RF1/RG1 = RF2/RG2, then β1 = β2 = β, and the noise gain
becomes
For an unbalanced, single-ended input signal (see Figure 55),
the input impedance is
1
β
RF
RG
GN
1
RG
RF
RG RF
RIN, cm
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
1
2
R
F
+V
8
S
vnOD
v2
nOi
R
R
G
S
i1
R
V
OCM
T
IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
V
ADA4937
OUT, dm
R
G
As previously mentioned in the Setting the Closed-Loop Gain
section), even if the external feedback networks (RF/RG) are
mismatched, the internal common-mode feedback loop still
forces the outputs to remain balanced. The amplitudes of the
signals at each output remain equal and 180° out of phase. The
input-to-output differential mode gain varies proportionately to
the feedback mismatch, but the output balance is unaffected.
R
R
T
S
R
F
Figure 55. ADA4937-1/ADA4937-2 Configured for Unbalanced
(Single-Ended) Input
The input impedance of the circuit is effectively higher than it is
for a conventional operational amplifier connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the Input Gain Resistor RG.
As well as causing a noise contribution from VOCM, ratio matching
errors in the external resistors result in a degradation of the
ability of the circuit to reject input common-mode signals, much
the same as for a four-resistor difference amplifier made from a
conventional operational amplifier.
Terminating a Single-Ended Input
This section explains how to properly terminate a single-ended
input to the ADA4937-1/ADA4937-2. Using a simple example
with an input source of 2 V and a source resistor of 50 ꢀ, four
simple steps must be followed.
In addition, if the dc levels of the input and output common-
mode voltages are different, matching errors result in a small
differential-mode output offset voltage. When G = 1, with a
ground referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-
case input CMRR of approximately 40 dB, a worst-case
1. The input impedance must be calculated using the formula
RG
RF
200
200
2 (200 200)
RIN
267 Ω
1
1
2 (RG RF )
R
F
differential-mode output offset of 25 mV due to 2.5 V level
shift, and no significant degradation in output balance error.
R
200Ω
+V
IN
267Ω
S
CALCULATING THE INPUT IMPEDANCE FOR AN
APPLICATION CIRCUIT
R
S
R
G
50Ω
200Ω
V
2V
S
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 54, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
V
OCM
ADA4937
R
V
O
L
R
G
200Ω
–V
S
R
F
200Ω
Figure 56. Single-Ended Input Impedance RIN
Rev. F | Page 19 of 28
ADA4937-1/ADA4937-2
Data Sheet
R
F
2. For the source termination to be 50 Ω, the termination
resistor (RT) is calculated using RT||RIN = 50 Ω, which
makes RT equal to 61.9 Ω.
+V
S
R
R
S
G
R
F
50Ω
200Ω
R
61.9Ω
T
200Ω
+V
V
2V
S
50Ω
V
OCM
ADA4937
R
V
O
L
S
R
G
R
R
S
G
200Ω
R
TS
27.4Ω
50Ω
200Ω
R
61.9Ω
T
V
S
V
OCM
ADA4937
–V
S
R
V
O
2V
L
R
F
R
G
200Ω
Figure 60. Complete Single-Ended-to-Differential System
–V
S
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
R
F
200Ω
Figure 57. Adding Termination Resistor RT
The ADA4937-1/ADA4937-2 are optimized for level-shifting
ground-referenced input signals. As such, the center of the input
common-mode range is shifted approximately 1 V down from
midsupply. For 5 V single-supply operation, the input common-
mode range at the summing nodes of the amplifier is 0.3 V to
3.0 V, and 0.3 V to 1.2 V with a 3.3 V supply. To avoid clipping
at the outputs, the voltage swing at the +IN and −IN terminals
must be confined to these ranges.
3. To compensate for the imbalance of the gain resistors,
a correction resistor (RTS) is added in series with the
inverting Input Gain Resistor RG. RTS is equal to the
Thevenin equivalent of the Source Resistance RS||RT.
R
R
S
TH
50Ω
R
61.9Ω
27.4Ω
T
V
V
S
2V
TH
1.1V
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the ADA4937-1/ADA4937-2 is internally biased
at a voltage approximately equal to the midsupply point, [(+VS) +
(−VS)]/2. Relying on this internal bias results in an output
common-mode voltage that is within about 100 mV of the
expected value.
Figure 58. Calculating Thevenin Equivalent
RTS = RTH = RS||RT = 27.4 Ω. Note that VTH is not equal to VS/2,
which is the case if the termination is not affected by the
amplifier circuit.
R
F
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external source,
or resistor divider (10 kΩ or greater resistors), be used. The output
common-mode offset listed in Table 2 and Table 4 assumes that the
200Ω
+V
S
R
R
TH
G
27.4Ω
200Ω
V
TH
1.1V
V
O
V
VOCM input is driven by a low impedance voltage source.
OCM
ADA4937
R
0.97V
L
R
G
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
ensure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 10 kΩ. If multiple
ADA4937-1/ADA4937-2 devices share one reference output, it is
recommended that a buffer be used.
200Ω
R
TS
27.4Ω
–V
S
R
F
200Ω
Figure 59. Balancing Gain Resistor RG
4. The feedback resistor is calculated to adjust the output
voltage.
Table 10 and Table 11 list several common gain settings, asso-
ciated resistor values, input impedances, and output noise density
values for both balanced and unbalanced input configurations.
a. To make the output voltage VOUT = 1 V, RF must be
calculated using the following formula:
POWER-DOWN OPERATION
The ADA4937-1/ADA4937-2 power-down pin features an
internal 25 kꢀ pull-up resistor to the positive supply (+VS).
This ensures that, with the power-down pin left unconnected
(floating), the ADA4937-1/ADA4937-2 turn on. Applying a
voltage of ≤1 V turns the ADA4937-1/ADA4937-2 off.
VOUT (RG RTS )
1 (200 27.4)
RF
207 ꢀ
VTH
1.1
To make VO = VS = 2 V to recover the loss due to the input
termination, RF must be
VOUT (RG RTS )
2 (200 27.4)
RF
414 ꢀ
VTH
1.1
Rev. F | Page 20 of 28
Data Sheet
ADA4937-1/ADA4937-2
Table 10. Differential Ground-Referenced Input, DC-Coupled, 1 kΩ Load; See Figure 54
Nominal Gain (dB)
RF (Ω)
RG (Ω) RIN, dm (Ω) Differential Output Noise Density (nV/√Hz)
0
6
10
14
200
402
402
402
200
200
127
80.6
400
400
254
161
5.8
9.6
12.1
16.2
Table 11. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω, RL = 1 kΩ; See Figure 55
Nominal Gain (dB)
RF (Ω) RG1 (Ω)
RT (Ω) RIN, cm (Ω)
RG2 (Ω)1
226
228
155
Differential Output Noise Density (nV/√Hz)
0
6
10
14
200
402
402
402
200
200
127
80.6
61.9
60.4
66.5
76.8
267
301
205
138
5.5
8.6
10.1
12.2
111
1 RG2 = RG1 + (RS||RT)
Rev. F | Page 21 of 28
ADA4937-1/ADA4937-2
Data Sheet
LAYOUT, GROUNDING, AND BYPASSING
As high speed devices, the ADA4937-1/ADA4937-2 are sensitive
to the PCB environment in which they operate. Realizing their
superior performance requires attention to the details of high
speed PCB design. This section shows a detailed example of
how the design issues of the ADA4937-1 is addressed.
Bypass the power supply pins as close to the device as possible
and directly to a nearby ground plane. Use high frequency ceramic
chip capacitors. It is recommended that two parallel bypass capaci-
tors (1000 pF and 0.1 μF) be used for each supply with the 1000 pF
capacitor placed closer to the device; further away, provide low
frequency bypassing using 10 μF tantalum capacitors from each
supply to ground.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4937-1 as possible.
However, the area near the feedback resistors (RF), input gain
resistors (RG), and the input summing nodes (Pin 2 and Pin 3)
must be cleared of all ground and power planes (see Figure 61).
Clearing the ground and power planes minimizes any stray capa-
citance at these nodes and prevents peaking of the response of
the amplifier at high frequencies.
Signal routing must be short and direct to avoid parasitic
effects. Wherever complementary signals exist, provide a sym-
metrical layout to maximize balanced performance. When
routing differential signals over a long distance, keep PCB
traces close together and twist any differential wiring to mini-
mize loop area. Doing this reduces radiated energy and makes
the circuit less susceptible to interference.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD 51-7.
1.30
0.80
1.30 0.80
Figure 62. Recommended PCB Thermal Attach Pad Dimensions (mm)
Figure 61. Ground and Power Plane Voiding in Vicinity of RF and RG
1.30
TOP METAL
GROUND PLANE
0.30
PLATED
VIA HOLE
POWER PLANE
BOTTOM METAL
Figure 63. Cross-Section of 4-layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in mm)
Rev. F | Page 22 of 28
Data Sheet
ADA4937-1/ADA4937-2
HIGH PERFORMANCE ADC DRIVING
The ADA4937-1/ADA4937-2 are ideally suited for broadband IF
applications. The circuit in Figure 64 shows a front-end connection
for an ADA4937-1 driving an AD9445, 14-bit, 105 MSPS ADC.
The AD9445 achieves optimum performance when driven
differentially. The ADA4937-1/ADA4937-2 eliminate the need for
a transformer to drive the ADC and performs a single-ended-
to-differential conversion and buffering of the driving signal.
The signal generator has a symmetric, ground-referenced
bipolar output. The VOCM pin of the ADA4937-1/ADA4937-2
remains unconnected allowing the internal divider to set the
output common-mode voltage at midsupply; one half of the
common-mode voltage is fed back to the summing nodes, biasing
−IN and +IN at 1.25 V. For a common-mode voltage of 2.5 V,
each ADA4937-1/ADA4937-2 output swings between 2.0 V and
3.0 V, providing a 2 V p-p differential output.
The ADA4937-1/ADA4937-2 are configured with a single 5 V
supply and unity gain for a single-ended input to differential
output. The 61.9 ꢀ termination resistor, in parallel with the single-
ended input impedance of 267 ꢀ, provides a 50 ꢀ termination
for the source. The additional 26 ꢀ (226 ꢀ total) at the inverting
input balances the parallel impedance of the 50 ꢀ source and the
termination resistor driving the noninverting input.
The output of the amplifier is ac-coupled to the ADC through a
second-order, low-pass filter with a cutoff frequency of 100 MHz.
This reduces the noise bandwidth of the amplifier and isolates
the driver outputs from the ADC inputs.
The AD9445 is configured for a 2 V p-p full-scale input by
connecting the SENSE pin to AGND, as shown in Figure 64.
5V (A) 3.3V (A) 3.3V (D)
200Ω
5V
AVDD2 AVDD1 DRVDD
30nH
0.1µF
0.1µF
200Ω
50Ω
VIN–
47pF
VIN+
AD9445
+
BUFFER T/H
24.3Ω
24.3Ω
V
61.9Ω
OCM
ADA4937-1
14
ADC
SIGNAL
GENERATOR
30nH
226Ω
CLOCK/
TIMING
REF
200Ω
AGND
SENSE
Figure 64. Driving an AD9445, 14-Bit, 105 MSPS ADC
Rev. F | Page 23 of 28
ADA4937-1/ADA4937-2
Data Sheet
The circuit in Figure 66 shows a simplified front-end connection
for an ADA4937-1 driving an AD9246, 14-bit, 125 MSPS ADC.
The AD9246 achieves optimum performance when driven
differentially. The ADA4937-1/ADA4937-2 perform the single-
ended-to-differential conversion, eliminating the need for a
transformer to drive the ADC.
The AD9246 is set for a 2 V p-p full-scale input by connecting
the SENSE pin to AGND. The inputs of the AD9246 are biased
at 1 V by connecting the CML output, as shown in Figure 66.
The circuit was tested with a −1 dBFS signal at various frequencies.
Figure 65 shows a plot of the second- and third-order harmonic
distortion (HD2/HD3) vs. frequency.
The ADA4937-1/ADA4937-2 are configured with a single 5 V
supply and a gain of ~2 V/V for a single-ended input to
differential output. The 76.8 ꢀ termination resistor, in parallel
with the single-ended input impedance of 137 ꢀ, provides a 50 ꢀ
ac termination for the source. The additional 30 ꢀ (120 ꢀ total) at
the inverting input balances the parallel ac impedance of the
50 ꢀ source and the termination resistor driving the
noninverting input.
–75
G = +2
–80
HD3
–85
HD2
–90
The signal generator has a symmetric, ground-referenced bipolar
output. The VOCM pin of the ADA4937-1/ADA4937-2 remains
unconnected; therefore, the internal pull-ups set the output
common-mode voltage to midsupply. A portion of this is fed back
to the summing nodes, biasing −IN and +IN at 0.55 V. For a
common-mode voltage of 2.5 V, each ADA4937-1/ADA4937-2
output swings between 2.0 V and 3.0 V, providing a 2 V p-p
differential output.
–95
–100
0
20
40
60
80
100
120
FREQUENCY (MHz)
Figure 65. HD2/HD3 for Combination of ADA4937-1/ADA4937-2 and
AD9246 ADC
The output is ac-coupled to a single-pole, low-pass filter. This
reduces the noise bandwidth of the amplifier and provides some
level of isolation from the switched capacitor inputs of the ADC.
200Ω
1.8V
5V
76.8Ω
10µF
10µF
50Ω
33Ω
10pF
90Ω
AVDD DRVDD
VIN–
+
200Ω
200Ω
D13 TO
V
IN
AD9246
D0
ADA4937-1
10µF
90Ω
VIN+
AGND SENSE CML
33Ω
10µF
50Ω
76.8Ω
200Ω
Figure 66. Driving an AD9246, 14-Bit, 125 MSPS ADC
Rev. F | Page 24 of 28
Data Sheet
ADA4937-1/ADA4937-2
ended input impedance of 306 ꢀ, provides a 50 ꢀ termination for
the source. The additional 26 ꢀ (226 ꢀ total) at the inverting input
balances the parallel impedance of the 50 ꢀ source and the
termination resistor that drives the noninverting input. The signal
generator has a symmetric, ground-referenced bipolar output. The
VOCM pin is connected to the CML output of the AD9230, and sets
the output common mode of the ADA4937-1/ADA4937-2 at 1.4 V.
One third of the output common-mode voltage of the amplifier is
fed back to the summing nodes, biasing −IN and +IN at ~0.5 V.
For a common-mode voltage of 1.4 V, each ADA4937-1/
ADA4937-2 output swings between 1.09 V and 1.71 V,
providing a 1.25 V p-p differential output.
3.3 V OPERATION
The ADA4937-1/ADA4937-2 provide excellent performance in
3.3 V single-supply applications. Significant power savings can
be realized when the ADA4937-1/ADA4937-2 are used in
combination with a low voltage ADC.
The circuit in Figure 67 is an example of the ADA4937-1 driving
an AD9230, 12-bit, 250 MSPS ADC that is specified to operate with
a single 1.8 V supply. The performance of the ADC is optimized
when it is driven differentially, making the best use of the signal
swing available within the 1.8 V supply. The ADA4937-1/
ADA4937-2 perform the single-ended-to-differential conversion,
common-mode level-shifting, and buffering of the driving signal.
A third-order, 125 MHz, low-pass filter between the ADA4937-1/
ADA4937-2 and the AD9230 reduces the noise bandwidth of
the amplifier and isolates the driver outputs from the ADC inputs.
The ADA4937-1/ADA4937-2 are configured with a single 3.3 V
supply and a gain of 2 V/V for a single-ended input to differential
output. The 59 ꢀ termination resistor, in parallel with the single-
453Ω
1.8V
3.3V
56nH
50Ω
33Ω
200Ω
AVDD DRVDD
+
VIN–
V
D11 TO
D0
59Ω
OCM
V
AD9230
10pF
30pF
ADA4937-1
IN
VIN+
AGND
CML
33Ω
56nH
226Ω
453Ω
Figure 67. Driving an AD9230, 12-Bit, 250 MSPS ADC
Rev. F | Page 25 of 28
ADA4937-1/ADA4937-2
OUTLINE DIMENSIONS
Data Sheet
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
12
1
4
EXPOSED
PAD
1.45
1.30 SQ
1.15
9
0.25 MIN
8
5
0.50
0.40
0.30
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-21)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR
24
19
18
0.50
BSC
1
6
EXPOSED
PAD
2.20
2.10 SQ
2.00
13
12
7
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
Figure 69. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
24-Lead LFCSP
Package Option
Ordering Quantity
Branding
H1S
H1S
ADA4937-1YCPZ-R2
ADA4937-1YCPZ-RL
ADA4937-1YCPZ-R7
ADA4937-2YCPZ-R2
ADA4937-2YCPZ-RL
ADA4937-2YCPZ-R7
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
CP-16-21
CP-16-21
CP-16-21
CP-24-10
CP-24-10
CP-24-10
250
5,000
1,500
250
5,000
1,500
H1S
1 Z = RoHS Compliant Part.
Rev. F | Page 26 of 28
Data Sheet
NOTES
ADA4937-1/ADA4937-2
Rev. F | Page 27 of 28
ADA4937-1/ADA4937-2
NOTES
Data Sheet
©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06591-0-6/16(F)
Rev. F | Page 28 of 28
相关型号：
©2020 ICPDF网 联系我们和版权申明