ADL5353ACPZ-WP [ADI]
SPECIALTY TELECOM CIRCUIT, QCC20, 5 X 5 MM, ROHS COMPLIANT, MO-220VHHC, LFCSP_VQ-20;
| 型号： | ADL5353ACPZ-WP |
| 厂家： | 
ADI |
| 描述： | SPECIALTY TELECOM CIRCUIT, QCC20, 5 X 5 MM, ROHS COMPLIANT, MO-220VHHC, LFCSP_VQ-20 电信 信息通信管理 电信集成电路 |
| 文件： | 总24页 (文件大小：610K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2200 MHz to 2700 MHz Balanced Mixer,
LO Buffer, IF Amplifier, and RF Balun
ADL5353
FEATURES
FUNCTIONAL BLOCK DIAGRAM
IFGM
IFOP
IFON
PWDN
LEXT
Frequency ranges of 2200 MHz to 2700 MHz (RF) and 30 MHz
to 450 MHz (IF)
20
19
18
17
16
Power conversion gain: 8.7 dB
Input IP3 of 24.5 dBm and Input P1dB of 10.4 dBm
SSB noise figure of 9.8 dB
ADL5353
1
2
3
4
5
15
14
13
12
11
VPIF
RFIN
LOI2
Typical LO drive of 0 dBm
VPSW
VGS1
VGS0
LOI1
Single-ended, 50 Ω RF and LO input ports
High isolation SPDT LO input switch
Single-supply operation: 3.3 V to 5 V
Exposed pad, 5 mm × 5 mm 20-lead LFCSP
1500 V HBM/500 V FICDM ESD performance
RFCT
COMM
COMM
BIAS
GENERATOR
APPLICATIONS
Cellular base station receivers
Transmit observation receivers
Radio link downconverters
6
7
LGM3
8
9
10
GENERAL DESCRIPTION
VLO3
VLO2
LOSW
NC
NC = NO CONNECT
The ADL5353 uses a highly linear, doubly balanced passive
mixer core along with integrated RF and local oscillator (LO)
balancing circuitry to allow for single-ended operation. The
ADL5353 incorporates an RF balun to provide optimal perfor-
mance over a 2200 MHz to 2700 MHz input frequency range
using high-side LO. The balanced passive mixer arrangement
provides good LO-to-RF leakage, typically better than −36 dBm,
and excellent intermodulation performance.
Figure 1.
The ADL5353 provides two switched LO paths that can be used
in TDD applications where it is desirable to rapidly switch between
two local oscillators. LO current can be externally set using a
resistor to minimize dc current commensurate with the desired
level of performance. For low voltage applications, the ADL5353 is
capable of operation at voltages down to 3.3 V with substantially
reduced current. For low voltage operation, an additional logic
pin is provided to power down (<200 µA) the circuit when desired.
The balanced mixer core also provides extremely high input
linearity, allowing the device to be used in demanding cellular
applications where in-band blocking signals might otherwise
result in the degradation of dynamic performance. A high
linearity IF buffer amplifier follows the passive mixer core to yield a
typical power conversion gain of 8.8 dB and can be used with a
wide range of output impedances.
The ADL5353 is fabricated using a BiCMOS high performance
IC process. The device is available in a 5 mm × 5 mm, 20-lead
LFCSP and operates over a −40°C to +85°C temperature range.
An evaluation board is also available.
Table 1. Passive Mixers
Single
Single Mixer Dual Mixer
RF Frequency (MHz) Mixer
and IF Amp
and IF Amp
ADL5358
ADL5356
ADL5354
500 to 1700
1200 to 2500
2200 to 2700
ADL5367 ADL5357
ADL5365 ADL5355
ADL5353
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADL5353
TABLE OF CONTENTS
Features .............................................................................................. 1
3.3 V Performance...................................................................... 14
Spur Tables ...................................................................................... 15
Circuit Description......................................................................... 16
RF Subsystem.............................................................................. 16
LO Subsystem ............................................................................. 16
Applications Information.............................................................. 18
Basic Connections...................................................................... 18
Bias Resistor Selection ............................................................... 18
Mixer VGS Control DAC.......................................................... 18
Evaluation Board ............................................................................ 19
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Performance Specifications.................................................. 3
3.3 V Performance Specifications............................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
5 V Performance........................................................................... 7
REVISION HISTORY
10/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADL5353
SPECIFICATIONS
5 V PERFORMANCE SPECIFICATIONS
RF Interface
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, ZO = 50 Ω, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Tunable to >20 dB over a limited bandwidth
18
50
dB
Ω
MHz
Input Impedance
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
IF Frequency Range
DC Bias Voltage1
LO INTERFACE
2200
2700
Differential impedance, f = 200 MHz
Externally generated
230||1.5
5.0
Ω||pF
MHz
V
30
3.3
450
5.5
LO Power
−6
0
+10
3150
0.4
dBm
dB
Ω
Return Loss
15
50
Input Impedance
LO Frequency Range
POWER-DOWN (PWDN) INTERFACE2
PWDN Threshold
Logic 0 Level
2230
MHz
1.0
V
V
Logic 1 Level
1.4
V
PWDN Response Time
Device enabled, IF output to 90% of its final level
Device disabled, supply current <5 mA
Device enabled
160
220
0.0
70
ns
ns
µA
µA
PWDN Input Bias Current
Device disabled
1 Apply the supply voltage from the external circuit through the choke inductors.
2 The power-down function is intended for use with VS ≤ 3.6 V only.
Rev. 0 | Page 3 of 24
ADL5353
RF Dynamic Performance
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, VGS0 = VGS1 = 0 V, and ZO = 50 Ω, unless
otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Gain
Voltage Conversion Gain
SSB Noise Figure
Including 4:1 IF port transformer and PCB loss
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential
8.7
14.7
9.8
dB
dB
dB
Input Third-Order Intercept (IIP3)
Input Second-Order Intercept (IIP2)
fRF1 = 2534.5 MHz, fRF2 = 2535.5 MHz, fLO = 2738 MHz, each RF
tone at −10 dBm
fRF1 = 2535 MHz, fRF2 = 2585 MHz, fLO = 2738 MHz, each RF tone
at −10 dBm
21
24.5
47.5
dBm
dBm
Input 1 dB Compression Point (IP1dB)
LO-to-IF Leakage
LO-to-RF Leakage
RF-to-IF Isolation
IF/2 Spurious
IF/3 Spurious
10.4
−15
−38
−28
−70
−78
dBm
dBm
dBm
dBc
dBc
dBc
Unfiltered IF output
−10 dBm input power
−10 dBm input power
POWER SUPPLY
Positive Supply Voltage
Quiescent Current
4.5
5.0
100
90
5.5
V
LO supply, resistor programmable
IF supply, resistor programmable
VS = 5 V
mA
mA
mA
Total Quiescent Current
190
3.3 V PERFORMANCE SPECIFICATIONS
VS = 3.3 V, IS = 125 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
Table 4.
Parameter
Test Conditions/Comments
Min Typ Max Unit
DYNAMIC PERFORMANCE
Power Conversion Gain
Voltage Conversion Gain
SSB Noise Figure
Including 4:1 IF port transformer and PCB loss
ZSOURCE = 50 Ω, differential ZLOAD = 200 Ω differential
9
dB
dB
dB
dBm
15
8.95
19
Input Third-Order Intercept (IIP3)
fRF1 = 2534.5 MHz, fRF2 = 2535.5 MHz, fLO = 2738 MHz, each RF
tone at −10 dBm
Input Second-Order Intercept (IIP2)
fRF1 = 2535 MHz, fRF2 = 2585 MHz, fLO = 2738 MHz, each RF tone
at −10 dBm
41.5
7.5
dBm
dBm
Input 1 dB Compression Point (IP1dB)
POWER INTERFACE
Supply Voltage
3.0
3.3
3.6
V
Quiescent Current
Power-Down Current
Resistor programmable
Device disabled
125
150
mA
μA
Rev. 0 | Page 4 of 24
ADL5353
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
5.5 V
20 dBm
13 dBm
6.0 V
5.5 V
1.2 W
25°C/W
Supply Voltage, VS
RF Input Level
LO Input Level
IFOP, IFON Bias Voltage
VGS0, VGS1, LOSW, PWDN
Internal Power Dissipation
Thermal Resistance, θJA
Temperature
ESD CAUTION
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
150°C
−40°C to +85°C
−65°C to +150°C
260°C
Rev. 0 | Page 5 of 24
ADL5353
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
VPIF 1
RFIN 2
RFCT 3
COMM 4
COMM 5
15 LOI2
14 VPSW
13 VGS1
12 VGS0
11 LOI1
ADL5353
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD. MUST BE SOLDERED
TO GROUND.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
VPIF
RFIN
Positive Supply Voltage for IF Amplifier.
RF Input. Must be ac-coupled.
3
RFCT
COMM
RF Balun Center Tap (AC Ground).
Device Common (DC Ground).
4, 5
6, 8
7
9
10
VLO3, VLO2 Positive Supply Voltages for LO Amplifier.
LGM3
LOSW
NC
LO Amplifier Bias Control.
LO Switch. LOI1 selected for 0 V, and LOI2 selected for 3 V.
No Connect.
11, 15
12, 13
14
LOI1, LOI2
LO Inputs. Must be ac-coupled.
VGS0, VGS1 Mixer Gate Bias Controls. 3 V logic. Ground these pins for nominal setting.
VPSW
Positive Supply Voltage for LO Switch.
16
LEXT
IF Return. This pin must be grounded.
17
18, 19
20
PWDN
IFON, IFOP
IFGM
Power Down. Connect this pin to ground for normal operation and connect this pin to 3.0 V for disable mode.
Differential IF Outputs (Open Collectors). Each requires an external dc bias.
IF Amplifier Bias Control.
EPAD (EP)
Exposed Pad. The exposed pad must be soldered to ground.
Rev. 0 | Page 6 of 24
ADL5353
TYPICAL PERFORMANCE CHARACTERISTICS
5 V PERFORMANCE
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
220
210
200
190
180
170
160
70
60
50
40
30
20
10
T
T
= –40°C
= +85°C
A
T
= –40°C
A
A
T
T
= +25°C
= +85°C
A
T
= +25°C
A
A
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 3. Supply Current vs. RF Frequency
Figure 6. Input IP2 vs. RF Frequency
12
14
12
10
8
T
= +85°C
= +25°C
A
11
10
9
T
= –40°C
A
T
A
T
= –40°C
A
T
T
= +25°C
= +85°C
A
6
A
8
4
7
2
6
0
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 4. Power Conversion Gain vs. RF Frequency
Figure 7. Input P1dB vs. RF Frequency
28
26
24
22
20
18
16
14
12
10
12
T
= –40°C
A
11
10
9
T
T
= +85°C
= +25°C
A
T
= +25°C
A
A
T
= +85°C
A
T
= –40°C
A
8
7
6
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 5. Input IP3 vs. RF Frequency
Figure 8. SSB Noise Figure vs. RF Frequency
Rev. 0 | Page 7 of 24
ADL5353
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
52
240
51
220
50
V
V
= 5.25V
= 5.00V
S
200
180
160
140
120
100
V
= 5.25V
S
S
49
48
47
46
45
44
V
= 4.75V
S
V
= 5.00V
S
V
= 4.75V
40
S
–40
–20
0
20
40
60
80
–40
–20
0
20
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Input IP2 vs. Temperature
Figure 9. Supply Current vs. Temperature
14
13
12
11
10
9
9.8
9.6
9.4
9.2
9.0
8.8
8.6
8.4
8.2
V
= 4.75V
S
V
= 5.25V
S
V
= 5.00V
V
= 4.75V
S
S
V
S
= 5.00V
8
7
6
V
= 5.25V
40
S
5
4
–40
–20
0
20
40
60
80
–40
–20
0
20
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Input P1dB vs. Temperature
Figure 10. Power Conversion Gain vs. Temperature
12.0
11.5
11.0
10.5
10.0
9.5
28
27
26
25
24
23
22
21
20
V
= 5.25V
S
V
= 5.25V
S
V
= 4.75V
S
V
= 5.00V
S
9.0
8.5
V
= 5.00V
V
= 4.75V
S
S
8.0
7.5
7.0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 14. SSB Noise Figure vs. Temperature
Figure 11. Input IP3 vs. Temperature
Rev. 0 | Page 8 of 24
ADL5353
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
220
210
200
190
180
170
160
60
55
50
45
40
35
30
T
= –40°C
= +25°C
A
T
= –40°C
A
T
A
T
T
= +25°C
= +85°C
A
T
= +85°C
A
A
30
80
130
180
230
280
330
380
430
430
430
30
80
130
180
230
280
330
380
430
430
430
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 15.Supply Current vs. IF Frequency
Figure 18. Input IP2 vs. IF Frequency
12
11
10
16
14
12
10
T
= +85°C
= +25°C
A
T
T
= –40°C
A
9
8
7
6
T
= +25°C
A
T
= –40°C
A
T
A
8
6
4
= +85°C
A
30
80
130
180
230
280
330
380
30
80
130
180
230
280
330
380
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 16. Power Conversion Gain vs. IF Frequency
Figure 19. Input P1dB vs. IF Frequency
11.0
30
28
26
24
22
20
18
16
10.5
10.0
9.5
T
= –40°C
A
T
= +85°C
A
T
= +25°C
9.0
A
8.5
8.0
30
80
130
180
230
280
330
380
30
80
130
180
230
280
330
380
IF FREQUENCY (MHz)
IF FREQUENCY (MHz)
Figure 20. SSB Noise Figure vs. IF Frequency
Figure 17. Input IP3 vs. IF Frequency
Rev. 0 | Page 9 of 24
ADL5353
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
13
12
11
10
9
14
13
12
11
10
9
T
= +85°C
= –40°C
A
T
= –40°C
= +25°C
A
T
A
T
A
T
= +25°C
A
8
T
= +85°C
A
7
8
6
7
5
–6
6
–6
–4
–2
0
2
4
6
8
10
–4
–2
0
2
4
6
8
10
LO POWER (dBm)
LO POWER (dBm)
Figure 24. Input P1dB vs. LO Power
Figure 21. Power Conversion Gain vs. LO Power
–50
–55
–60
–65
–70
–75
30
28
26
24
22
20
18
16
14
T
= –40°C
= +85°C
A
T
A
T
= –40°C
A
T
= +25°C
A
T
= +85°C
A
T
= +25°C
A
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
–6
–4
–2
0
2
4
6
8
10
RF FREQUENCY (GHz)
LO POWER (dBm)
Figure 25. IF/2 Spurious vs. RF Frequency, RF Power = −10 dBm
Figure 22. Input IP3 vs. LO Power
60
55
50
45
40
35
30
–60
–65
–70
T
= –40°C
= +85°C
A
T
= –40°C
A
–75
–80
–85
–90
T
A
T
= +25°C
A
T
= +85°C
A
T
= +25°C
A
–6
–4
–2
0
2
4
6
8
10
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
LO POWER (dBm)
RF FREQUENCY (GHz)
Figure 23. Input IP2 vs. LO Power
Figure 26. IF/3 Spurious vs. RF Frequency, RF Power = −10 dBm
Rev. 0 | Page 10 of 24
ADL5353
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
100
80
60
40
20
0
500
400
300
200
100
0
10
8
6
4
2
0
8.70
8.75
8.80
8.85
8.90
30
80
130
180
230
280
330
380
430
CONVERSION GAIN (dB)
IF FREQUENCY (MHz)
Figure 27. Power Conversion Gain Distribution
Figure 30. IF Differential Output Impedance (R Parallel C Equivalent)
100
80
60
40
20
0
0
–5
–10
–15
–20
–25
–30
–35
–40
22
23
24
25
26
27
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
INPUT IP3 (dBm)
RF FREQUENCY (GHz)
Figure 28. Input IP3 Distribution
Figure 31. RF Port Return Loss, Fixed IF
100
80
60
40
20
0
0
–5
–10
SELECTED
–15
–20
UNSELECTED
–25
–30
2.0
9.0
9.4
9.8
10.2
10.6
11.0
11.4
11.8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
INPUT P1dB (dBm)
LO FREQUENCY (GHz)
Figure 29. Input P1dB Distribution
Figure 32. LO Return Loss, Selected and Unselected
Rev. 0 | Page 11 of 24
ADL5353
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
60
55
50
45
40
35
30
–20
–25
–30
–35
–40
–45
T
= –40°C
A
T
= –40°C
A
T
= +25°C
A
T
= +25°C
A
T
= +85°C
A
T
= +85°C
A
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
LO FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 33. LO Switch Isolation vs. LO Frequency
Figure 36. LO-to-RF Leakages vs. LO Frequency
0
–20
–22
–24
–26
–28
–30
–32
–34
–36
–10
2LO TO RF
2LO TO IF
–20
–30
–40
–50
–60
T
= +85°C
A
T
= –40°C
A
T
= +25°C
A
2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
LO FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 37. 2LO Leakage vs. LO Frequency
Figure 34. RF-to-IF Isolation vs. RF Frequency
–10
0
–11
–12
–13
–14
–15
–16
–17
–18
–19
–20
–5
T
= +85°C
= +25°C
A
3LO TO IF
3LO TO RF
–10
–15
–20
–25
–30
T
A
T
= –40°C
A
2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
LO FREQUENCY (GHz)
LO FREQUENCY (GHz)
Figure 35. LO-to-IF Leakage vs. LO Frequency
Figure 38. 3LO Leakage vs. LO Frequency
Rev. 0 | Page 12 of 24
ADL5353
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, R9 = 1.1 kΩ, R14 = 910 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
10
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
160
140
120
100
80
LO SUPPLY CURRENT
8
IF SUPPLY CURRENT
7
VGS = 00
VGS = 01
VGS = 10
VGS = 11
60
6
5
40
600
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
800
1000
1200
1400
1600
1800
RF FREQUENCY (GHz)
BIAS RESISTOR VALUE (Ω)
Figure 39. Power Conversion Gain and SSB Noise Figure vs. RF Frequency
Figure 42. LO and IF Supply Current vs. IF and LO Bias Resistor Value
12
11
10
9
30
25
20
15
10
5
15
14
13
12
11
10
9
28
26
24
22
20
18
INPUT IP3
SSB NOISE FIGURE
CONVERSION GAIN
8
VGS = 00
7
VGS = 01 16
VGS = 10
VGS = 11
6
0.6
0
1.6
8
14
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
IF BIAS RESISTOR VALUE (kΩ)
RF FREQUENCY (GHz)
Figure 43. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. IF Bias
Resistor Value
Figure 40. Input IP3 and Input P1dB vs. RF Frequency
12
30
INPUT IP3
11
10
9
25
20
15
10
5
SSB NOISE FIGURE
CONVERSION GAIN
8
7
6
0.6
0
1.8
0.8
1.0
1.2
1.4
1.6
LO BIAS RESISTOR VALUE (kΩ)
Figure 41. Power Conversion Gain, SSB Noise Figure, and Input IP3 vs. LO Bias
Resistor Value
Rev. 0 | Page 13 of 24
ADL5353
3.3 V PERFORMANCE
VS = 3.3 V, IS = 125 mA, TA = 25°C, fRF = 2535 MHz, fLO = 2738 MHz, LO power = 0 dBm, R9 = 226 Ω, R14 = 604 Ω, VGS0 = VGS1 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
138
136
134
132
130
128
126
124
60
55
50
45
40
35
30
T
= –40°C
= +25°C
A
A
T
= –40°C
A
T
T
= +25°C
A
T
= +85°C
A
T
= +85°C
A
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 44. Supply Current vs. RF Frequency at 3.3 V
Figure 47. Input IP2 vs. RF Frequency at 3.3 V
12
9
T
= +25°C
T
= +85°C
A
A
8
7
6
5
4
3
2
1
0
11
10
9
T
T
T
= –40°C
= +25°C
= +85°C
A
A
A
T
= –40°C
A
8
7
6
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 45. Power Conversion Gain vs. RF Frequency at 3.3 V
Figure 48. Input P1dB vs. RF Frequency at 3.3 V
14
24
22
13
12
11
10
9
T
T
= –40°C
= +85°C
A
20
18
16
14
12
10
T
= +85°C
A
A
T
= +25°C
A
T
= +25°C
A
8
T
= –40°C
7
6
A
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
RF FREQUENCY (GHz)
RF FREQUENCY (GHz)
Figure 49. SSB Noise Figure vs. RF Frequency at 3.3 V
Figure 46. Input IP3 vs. RF Frequency at 3.3 V
Rev. 0 | Page 14 of 24
ADL5353
SPUR TABLES
SPUR TABLES
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board. Mixer spurious products are measured
in dBc from the IF output power level. Data was measured for frequencies less than 6 GHz only. Typical noise floor of the measurement
system = −100 dBm.
5 V Performance
VS = 5 V, IS = 190 mA, TA = 25°C, fRF = 2600 MHz, fLO = 2803MHz, LO power = 0 dBm, RF power = −10 dBm, VGS0 = VGS1 = VGS2 = 0 V,
and ZO = 50 Ω, unless otherwise noted.
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−14.9
0.00
−33.1
−63.4
−66.8
<−100
<−100
1
−36.5
−80.2
−59.8
−86.8
−96.7
<−100
<−100
2
−87.8
<−100
3
<−100
<−100
<−100
<−100
4
<−100
<−100
<−100
<−100
5
<−100
<−100
<−100
<−100
6
<−100
N
7
<−100 <−100
<−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
8
9
10
11
12
13
14
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
3.3 V Performance
VS = 3.3 V, IS = 125 mA, TA = 25°C, fRF = 2600 MHz, fLO = 2803 MHz, LO power = 0 dBm, RF power = −10 dBm, R9 = 226 ꢀ, R14 =
604 ꢀ, VGS0 = VGS1 = 0 V, and ZO = 50 ꢀ, unless otherwise noted.
M
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
−20.2
0.00
−74.3
−45.0
−57.7
−63.7
1
−36.9
−81.7
−66.5
−81.9
−69.2
2
3
<−100 −97.9
<−100
4
<−100 <−100 <−100 <−100
5
<−100 <−100 <−100 <-100
<−100 <−100 <-100
6
<−100
7
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100 <−100
N
8
9
10
11
12
13
14
15
<−100 <−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100 <−100
<−100 <−100 <−100
<−100 <−100
Rev. 0 | Page 15 of 24
ADL5353
CIRCUIT DESCRIPTION
adds minimum noise to the frequency translation. The only
noise contribution from the mixer is due to the resistive loss
of the switches, which is in the order of a few ohms.
The ADL5353 consists of two primary components: the radio
frequency (RF) subsystem and the local oscillator (LO) subsystem.
The combination of design, process, and packaging technology
allows the functions of these subsystems to be integrated into a
single die, using mature packaging and interconnection technolo-
gies to provide a high performance, low cost design with excellent
electrical, mechanical, and thermal properties. In addition, the
need for external components is minimized, thereby optimizing
cost and size.
Because the mixer is inherently broadband and bidirectional, it
is necessary to properly terminate all the idler (M × N product)
frequencies generated by the mixing process. Terminating the
mixer avoids the generation of unwanted intermodulation pro-
ducts and reduces the level of unwanted signals at the input of
the IF amplifier, where high peak signal levels can compromise the
compression and intermodulation performance of the system. This
termination is accomplished by the addition of a sum network
between the IF amplifier and the mixer and also in the feedback
elements in the IF amplifier.
The RF subsystem consists of an integrated, low loss RF balun,
passive MOSFET mixer, sum termination network, and IF
amplifier.
The LO subsystem consists of an SPDT-terminated FET switch
and a three stage, limiting LO amplifier. The purpose of the LO
subsystem is to provide a large, fixed amplitude, balanced signal
to drive the mixer independent of the level of the LO input. A
block diagram of the device is shown in Figure 50.
The IF amplifier is a balanced feedback design that simultaneously
provides the desired gain, noise figure, and input impedance that
are required to achieve the overall performance. The balanced
open-collector output of the IF amplifier, with impedance mod-
ified by the feedback within the amplifier, permits the output to be
connected directly to a high impedance filter, differential amplifier,
or to an analog-to-digital input while providing optimum second-
order intermodulation suppression. The differential output
impedance of the IF amplifier is approximately 200 Ω. If operation
in a 50 Ω system is desired, the output can be transformed to
50 Ω by using a 4:1 transformer.
IFGM
IFOP
19
IFON
18
PWDN
17
LEXT
16
20
ADL5353
1
2
3
4
5
15
14
13
12
11
VPIF
RFIN
LOI2
VPSW
VGS1
VGS0
LOI1
The intermodulation performance of the design is generally
limited by the IF amplifier. The Input IP3 performance can be
optimized by adjusting the IF current with an external resistor.
Figure 41, Figure 42, and Figure 43 illustrate how various IF and
LO bias resistors affect the performance with a 5 V supply. Addi-
tionally, dc current can be saved by increasing either or both
resistors. It is permissible to reduce the dc supply voltage to as
low as 3.3 V, further reducing the dissipated power of the part.
(Note that no performance enhancement is obtained by reducing
the value of these resistors, and excessive dc power dissipation
may result.)
RFCT
COMM
COMM
BIAS
GENERATOR
6
7
8
9
10
VLO3
LGM3
VLO2
LOSW
NC
NC = NO CONNECT
LO SUBSYSTEM
Figure 50. Simplified Schematic
The ADL5353 has two LO inputs permitting multiple synthe-
sizers to be rapidly switched with extremely short switching
times (<40 ns) for frequency agile applications. The two inputs
are applied to a high isolation SPDT switch that provides a
constant input impedance, regardless of whether the port is
selected, to avoid pulling the LO sources. This multiple section
switch also ensures high isolation to the off input, minimizing
any leakage from the unwanted LO input that may result in
undesired IF responses.
RF SUBSYSTEM
The single-ended, 50 Ω RF input is internally transformed to a
balanced signal using a low loss (<1 dB) unbalanced-to-balanced
(balun) transformer. This transformer is made possible by an
extremely low loss metal stack, which provides both excellent
balance and dc isolation for the RF port. Although the port can
be dc connected, it is recommended that a blocking capacitor be
used to avoid running excessive dc current through the part.
The RF balun can easily support an RF input frequency range
of 2200 MHz to 2700 MHz.
The single-ended LO input is converted to a fixed amplitude
differential signal using a multistage, limiting LO amplifier.
This results in consistent performance over a range of LO input
power. Optimum performance is achieved from −6 dBm to
+10 dBm, but the circuit continues to function at considerably
lower levels of LO input power.
The resulting balanced RF signal is applied to a passive mixer
that commutates the RF input with the output of the LO subsystem.
The passive mixer is essentially a balanced, low loss switch that
Rev. 0 | Page 16 of 24
ADL5353
The performance of this amplifier is critical in achieving a high
intercept passive mixer without degrading the noise floor of the
system. This is a critical requirement in an interferer rich environ-
ment, such as cellular infrastructure, where blocking interferers can
limit mixer performance. The bandwidth of the intermodulation
performance is somewhat influenced by the current in the LO
amplifier chain. For dc current sensitive applications, it is per-
missible to reduce the current in the LO amplifier by raising the
value of the external bias control resistor. For dc current critical
applications, the LO chain can operate with a supply voltage as
low as 3.3 V, resulting in substantial dc power savings.
In addition, when operating with supply voltages below 3.6 V, the
ADL5353 has a power-down mode that permits the dc current to
drop to <200 μA.
All of the logic inputs are designed to work with any logic family
that provides a Logic 0 input level of less than 0.4 V and a Logic 1
input level that exceeds 1.4 V. All logic inputs are high impedance
up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection
circuitry permits operation of up to 5.5 V, although a small bias
current is drawn.
All pins, including the RF pins, are ESD protected and have been
tested to a level of 1500 V HBM and 500 V CDM.
Rev. 0 | Page 17 of 24
ADL5353
APPLICATIONS INFORMATION
need for a transformer. This results in a voltage conversion gain
that is approximately 6 dB higher than the power conversion gain,
as shown in Table 3. When a 50 Ω output impedance is needed,
use a 4:1 impedance transformer, as shown in Figure 51.
BASIC CONNECTIONS
The ADL5353 mixer is designed to downconvert radio frequen-
cies (RF) primarily between 2200 MHz and 2700 MHz to lower
intermediate frequencies (IF) between 30 MHz and 450 MHz.
Figure 51 depicts the basic connections of the mixer. To prevent
nonzero dc voltages from damaging the RF balun or LO input
circuit, ac couple the RF and LO input ports. The RFIN matching
network consists of a series 1.5 pF capacitor and a shunt 10 nH
inductor to provide the optimized RF input return loss for the
desired frequency band IF port.
BIAS RESISTOR SELECTION
Two external resistors, RBIAS IF and RBIAS LO, are used to adjust the
bias current of the integrated amplifiers at the IF and LO terminals.
It is necessary to have a sufficient amount of current to bias both
the internal IF and LO amplifiers to optimize dc current vs.
optimum IIP3 performance.
The mixer differential IF interface requires pull-up choke inductors
to bias the open-collector outputs and to set the output match.
The shunting impedance of the choke inductors used to couple
dc current into the IF amplifier should be selected to provide
the desired output return loss.
MIXER VGS CONTROL DAC
The ADL5353 features two logic control pins, VGS0 (Pin 12) and
VGS1 (Pin 13), that allow programmability for internal gate-to-
source voltages for optimizing mixer performance over desired
frequency bands. The evaluation board defaults both VGS0 and
VGS1 to ground.
The real part of the output impedance is approximately 200 Ω,
which matches many commonly used SAW filters without the
+5V
100pF
150pF
470nH
470nH
4:1
IF OUT
R
10kΩ
BIAS IF
+5V
20
19
18
17
16
10pF
4.7µF
22pF
ADL5353
+5V
1
2
3
4
5
15
14
13
12
11
LO2 IN
+5V
1.5pF
RF IN
10pF
10nH
10pF
0.1µF
BIAS
GENERATOR
22pF
LO1 IN
6
7
8
9
10
R
BIAS LO
10kΩ
+5V
10pF
10pF
Figure 51. Typical Application Circuit
Rev. 0 | Page 18 of 24
ADL5353
EVALUATION BOARD
An evaluation board is available for the family of double balanced
mixers. The standard evaluation board schematic is shown in
Figure 52. The evaluation board is fabricated using Rogers®
RO3003 material.
Table 7 describes the various configuration options of the
evaluation board. Evaluation board layout is shown in Figure 53 to
Figure 56.
L5
470nH
T1
IF1-OUT
V
S
C18
100pF
C19
100pF
L4
470nH
R1
0Ω
C17
150pF
R24
0Ω
R25
0Ω
PWR_UP
R21
10kΩ
R14
910Ω
L3
0Ω
C12
22pF
LO2_IN
V
S
V
VPIF
LOI2
VPSW
VGS1
VGS0
LOI1
S
C2
C21
C20
R22
10µF
10pF
10pF
10kΩ
RFIN
RF-IN
C1
1.5pF
Z1
10nH
C22
1nF
R23
15kΩ
ADL5353
RFCT
COMM
COMM
VGS1
C5
0.01µF
C4
10pF
VGS0
LO1_IN
C10
22pF
LOSEL
V
S
R9
1.1kΩ
C6
10pF
R4
10kΩ
V
S
C8
10pF
Figure 52. Evaluation Board Schematic
Rev. 0 | Page 19 of 24
ADL5353
Table 7. Evaluation Board Configuration
Components
Function
Description
Default Conditions
C2, C6, C8, C18, Power
Nominal supply decoupling consists of a 10 µF capacitor to
ground in parallel with a 10 pF capacitor to ground positioned
as close to the device as possible.
C2 = 10 µF (size 0603)
C19, C20, C21
C1, C4, C5, Z1
supply
C6, C8, C20, C21 = 10 pF (size 0402)
C18, C19 = 100 pF (size 0402)
C1 = 1.5 pF (size 0402)
decoupling
RF input
interface
The input channels are ac-coupled through C1. C4 and C5
provide bypassing for the center taps of the RF input baluns.
C4 = 10 pF (size 0402)
C5 = 0.01 µF (size 0402)
Z1 = 10 nH (size 0402)
T1, C17, L4, L5,
R1, R24, R25
IF output
interface
The open-collector IF output interfaces are biased through
pull-up choke inductors, L4 and L5. T1 is a 4:1 impedance
transformer used to provide a single-ended IF output interface,
with C17 providing center-tap bypassing. Remove R1 for
balanced output operation.
T1 = TC4-1W+ (Mini-Circuits )
C17 = 150 pF (size 0402)
L4, L5 = 470 nH (size 1008)
R1, R24, R25 = 0 Ω (size 0402)
C10, C12, R4
LO interface
C10 and C12 provide ac coupling for the LO1_IN and LO2_IN
local oscillator inputs. LOSEL selects the appropriate LO input
for both mixer cores. R4 provides a pull-down to ensure that
LO1_IN is enabled when the LOSEL test point is logic low. LO2_IN
is enabled when LOSEL is pulled to logic high.
C10, C12 = 22 pF (size 0402)
R4 = 10 kΩ (size 0402)
R21
PWDN
interface
R21 pulls the PWDN logic low and enables the device. The
PWR_UP test point allows the PWDN interface to be exercised
using the external logic generator. Grounding the PWDN pin
for nominal operation is allowed. Using the PWDN pin when
supply voltages exceed 3.3 V is not allowed.
R21 = 10 kΩ (size 0402)
C22, L3, R9, R14, Bias control
R22, R23, VGS0,
VGS1
R22 and R23 form a voltage divider to provide 3 V for logic
control, bypassed to ground through C22. VGS0 and VGS1
jumpers provide programmability at the VGS0 and VGS1 pins.
It is recommended to pull these two pins to ground for
nominal operation. R9 sets the bias point for the internal LO
buffers. R14 sets the bias point for the internal IF amplifier.
C22 = 1 nF (size 0402)
L3 = 0 Ω (size 0603)
R9 = 1.1 k Ω (size 0402)
R14 = 910 Ω (size 0402)
R22 = 10 k Ω (size 0402)
R23 = 15 kΩ (size 0402)
VGS0 = VGS1 = 3-pin shunt
Rev. 0 | Page 20 of 24
ADL5353
Figure 53. Evaluation Board Top Layer
Figure 55. Evaluation Board Power Plane, Internal Layer 2
Figure 56. Evaluation Board Bottom Layer
Figure 54. Evaluation Board Ground Plane, Internal Layer 1
Rev. 0 | Page 21 of 24
ADL5353
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.65
BSC
PIN 1
INDICATOR
4.75
BSC SQ
3.20
3.10 SQ
3.00
EXPOSED
PAD
(BOTTOM VIEW)
10
11
6
0.75
0.60
0.50
TOP VIEW
2.60 BSC
0.70
0.65
0.60
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.90
0.85
0.80
0.05 MAX
0.01 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.05
0.35
0.28
0.23
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHC
Figure 57. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-20-5)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Model1
Package Description
Ordering Quantity
1,500 7”Tape and Reel
36, Waffle Package
1
ADL5353ACPZ-R7
ADL5353ACPZ-WP
ADL5353-EVALZ
−40°C to +85°C
−40°C to +85°C
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
CP-20-5
CP-20-5
1 Z = RoHS Compliant Part.
Rev. 0 | Page 22 of 24
ADL5353
NOTES
Rev. 0 | Page 23 of 24
ADL5353
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09117-0-10/10(0)
Rev. 0 | Page 24 of 24
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