ADP3182JRQZ-REEL [ADI]
IC SWITCHING CONTROLLER, 3000 kHz SWITCHING FREQ-MAX, PDSO20, ROHS COMPLIANT, MO-137AD, QSOP-28, Switching Regulator or Controller;
| 型号： | ADP3182JRQZ-REEL |
| 厂家： | 
ADI |
| 描述： | IC SWITCHING CONTROLLER, 3000 kHz SWITCHING FREQ-MAX, PDSO20, ROHS COMPLIANT, MO-137AD, QSOP-28, Switching Regulator or Controller 开关 光电二极管 |
| 文件： | 总16页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Adjustable Output 1-/2-/3-Phase
Synchronous Buck Controller
Preliminary Technical Data
FEATURES
Selectable 1-, 2-, or 3-phase operation at up to 1 MHz per
phase
ADP3182
FUNCTIONAL BLOCK DIAGRAM
VCC
1
RAMPADJ RT
10
9
ADP3182
2ꢀ ꢁorst-case differential sensing error over temperature
Externally adjustable 0.8 V to 5 V output from a 12 V supply
Logic-level PꢁM outputs for interface to external high-
power drivers
Active current balancing between all output phases
Built-in power good/crowbar functions
Programmable short circuit protection with programmable
latch-off delay
UVLO
SHUTDOWN
& BIAS
6
EN
OSCILLATOR
SET
EN
+
20
19
CMP
RESET
PWM1
PWM2
14
GND
–
–
+
950mV
CURRENT
BALANCING
CIRCUIT
+
CMP
RESET
FB
–
2 / 3-PHASE
DRIVER LOGIC
+
18
+
–
CMP
RESET
PWM3
–
650mV
CROWBAR
CURRENT
LIMIT
5
PWRGD
DELAY
–
+
1.05V
FB
APPLICATIONS
Auxiliary supplies
DDR memory supplies
Point-of-load modules
17
16
15
SW1
SW2
SW3
10
ILIMIT
EN
12
11
–
+
CSSUM
CSREF
CURRENT
LIMIT
CIRCUIT
GENERAL DESCRIPTION
7
4
DELAY
COMP
The ADP3182 is a highly efficient multi-phase synchronous
buck switching regulator controller optimized for converting a
12 V main supply into a high-current low voltage supply for use
in point-of-load (POL) applications. It uses a multi-mode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VR size and
efficiency. The phase relationship of the output signals can be
programmed to provide 1-, 2-, or 3-phase operation, allowing
for the construction of up to three complementary buck
switching stages.
SOFT
START
13
3
CSCOMP
FB
–
+
800 mV
REFERENCE
2
FBRTN
Figure 1.
The ADP3182 also provides accurate and reliable short circuit
protection and adjustable current limiting.
ADP3182 is specified over the commercial temperature range of
0°C to +85°C and is available in a 20-lead QSOP package.
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology ꢁay, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADP3182
Preliminary Technical Data
TABLE OF CONTENTS
Specifications..................................................................................... 3
Current Limit, Short Circuit, and Latch-off Protection ...........9
Power Good Monitoring ........................................................... 10
Output Crowbar ......................................................................... 10
Output Enable and UVLO ........................................................ 10
Applications Information.............................................................. 12
Layout and Component Placement ......................................... 12
General Recommendations .................................................. 12
Power Circuitry Recommendations .................................... 12
Signal Circuitry Recommendations .................................... 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
NOTES:........................................................................................ 15
NOTES:........................................................................................ 16
Test Circuits ....................................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Description .............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 8
Start-Up Sequence........................................................................ 8
Master Clock Frequency.............................................................. 8
Output Voltage Differential Sensing .......................................... 8
Output Current Sensing .............................................................. 8
Current Control Mode and Thermal Balance ......................... 9
Voltage Control Mode.................................................................. 9
Soft Start ........................................................................................ 9
REVISION HISTORY
Revision PrA: Initial Version
Revision PrB: Updated electrical table, added theory of operation section and typical application circuit
Rev. PrB | Page 2 of 16
Preliminary Technical Data
ADP3182
SPECIFICATIONS
VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OSCILLATOR
2
Frequency Range
fOSC
fPHASE
0.25
155
3
245
MHz
kHz
kHz
kHz
V
Frequency Variation
200
400
600
2.0
TA = 25°C, RT = 332 kΩ, 3-phase
TA = 25°C, RT = 154 kΩ, 3-phase
TA = 25°C, RT = 100 kΩ, 3-phase
RT = 100 kΩ to GND
Output Voltage
VRT
1.9
−50
0
2.1
RAMPADJ Output Voltage
RAMPADJ Input Current Range
VRAMPADJ
IRAMPADJ
RAMPADJ – FB
+50
100
mV
µA
VOLTAGE ERROR AMPLIFIER
Output Voltage Range2
Accuracy
VCOMP
VFB
0.3
784
3.1
816
V
mV
%
Referenced to FBRTN
VCC = 10 V to 14 V
FB = 800 mV
800
0.05
Line Regulation
∆VFB
IFB
Input Bias Current
FBRTN Current
-4
+4
µA
µA
IFBRTN
IO(ERR)
GBW(ERR)
100
500
20
140
Output Current
FB forced to VOUT – 3%
COMP = FB
CCOMP = 10 pF
µA
MHz
Gain Bandwidth Product
Slew Rate
25
V/µs
CURRENT SENSE AMPLIFIER
Offset Voltage
Input Bias Current
Gain Bandwidth Product
Slew Rate
VOS(CSA)
IBIAS(CSSUM)
GBW(CSA)
CSSUM – CSREF, Figure 2
−5.5
−50
+5.5
+50
mV
nA
MHz
V/µs
V
10
10
CCSCOMP = 10 pF
Input Common-Mode Range
Output Voltage Range
Output Current
CSSUM and CSREF
0
0.05
VCC–2.5
VCC–2.5
V
ICSCOMP
500
µA
CURRENT BALANCE CIRCUIT
Common-Mode Range
Input Resistance
VSW(X)CM
RSW(X)
ISW(X)
−600
20
+200
40
mV
kΩ
µA
%
SW(X) = 0 V
SW(X) = 0 V
SW(X) = 0 V
30
7
Input Current
4
10
Input Current Matching
−7
+7
∆ISW(X)
CURRENT LIMIT COMPARATOR
Output Voltage
Normal Mode
VILIMIT(NM)
VILIMIT(SD)
IILIMIT(NM)
2.9
3
3.1
V
EN > 2 V, RILIMIT = 250 kΩ
EN < 0.8 V, IILIMIT = -100 µA
EN > 2 V, RILIMIT = 250 kΩ
In Shutdown Mode
400
mV
Output Current, Normal Mode
12
µA
µA
mV
2
Maximum Output Current
60
Current Limit Threshold Voltage
Current Limit Setting Ratio
DELAY Normal Mode Voltage
DELAY Overcurrent Threshold
Latch-Off Delay Time
VCL
105
125
10.4
3
145
VCSREF – VCSCOMP, RILIMIT = 250 kΩ
VCL/IILIMIT
mV/µA
V
VDELAY(NM)
VDELAY(OC)
tDELAY
2.9
1.7
3.1
1.9
RDELAY = 250 kΩ
1.8
1.5
V
RDELAY = 250 kΩ
RDELAY = 250 kΩ, CDELAY = 12 nF
ms
SOFT START
Output Current, Soft-Start Mode
Soft-Start Delay Time
IDELAY(SS)
tDELAY(SS)
During startup, DELAY < 2.4 V
15
20
25
µA
µs
500
RDELAY = 250 kΩ, CDELAY = 12 nF
Rev. PrB | Page 3 of 16
ADP3182
Preliminary Technical Data
Parameter
Symbol
Conditions
Min
Typ
Max
Units
ENABLE INPUT
Input Low Voltage
Input High Voltage
Input Current
VIL(EN)
VIH(EN)
IIN(EN)
0.8
V
V
2.0
-1
+1
µA
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Power Good Delay Time
Crowbar Trip Point
Crowbar Reset Point
Crowbar Delay Time
PWM OUTPUTS
VPWRGD(UV)
VPWRGD(OV)
VOL(PWRGD)
Relative to FBRTN
Relative to FBRTN
IPWRGD(SINK) = 4 mA
600
880
660
940
225
200
1.05
650
400
720
1000
400
mV
mV
mV
ns
V
mV
ns
VCROWBAR
tCROWBAR
Relative to FBRTN
Relative to FBRTN
Overvoltage to PWM going low
0.975
550
1.1
750
Output Low Voltage
Output High Voltage
VOL(PWM)
VOH(PWM)
160
5
500
mV
V
IPWM(SINK) = −400 µA
IPWM(SOURCE) = 400 µA
4.0
SUPPLY
DC Supply Current
UVLO Threshold Voltage
UVLO Hysteresis
5
6.9
0.9
10
7.3
1.1
mA
V
V
VUVLO
VCC rising
6.5
0.7
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2 Guaranteed by design or bench characterization, not tested in production.
TEST CIRCUITS
ADP3182
VCC
1
12V
CSCOMP
CSSUM
CSREF
GND
13
12
11
14
100nF
39kΩ
–
+
1kΩ
+
–
0.8V
CSCOMP - 0.8V
40
V
=
OS
Figure 2. Current Sense Amplifier VOS
Rev. PrB | Page 4 of 16
Preliminary Technical Data
ADP3182
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified all other
voltages re referenced to GND.
VCC
FBRTN
−0.3 V to +15 V
−0.3 V to +0.3 V
−0.3 V to 5.5 V
EN, DELAY, ILIMIT, CSCOMP, RT,
PWM1 – PWM3, COMP
SW1 – SW3
All Other Inputs and Outputs
Storage Temperature
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA)
Lead Temperature
−5 V to +25 V
−0.3 V to VCC + 0.3 V
−65°C to +150°C
0°C to 85°C
125°C
100°C/W
Soldering (10 sec)
Infrared (15 sec)
300°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 5 of 16
ADP3182
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
20
19
18
17
16
15
14
13
12
11
VCC
FBRTN
FB
PWM1
PWM2
PWM3
SW1
2
3
4
COMP
PWRGD
EN
ADP3182
5
SW2
TOP VIEW
(Not to Scale)
6
SW3
7
DELAY
RT
GND
8
CSCOMP
CSSUM
CSREF
9
RAMPADJ
ILIMIT
10
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
VCC
FBRTN
FB
Supply Voltage for the Device.
Feedback Return. Voltage error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor divider
between the output and FBRTN connected to this pin sets the output voltage point. This pin is also the
reference point for the power good and crowbar comparators.
4
5
COMP
PWRGD
Error Amplifier Output and Compensation Point.
Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating
range.
6
7
EN
DELAY
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
Soft-Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected
between this pin and GND sets the soft-start ramp-up time and the overcurrent latch-off delay time.
8
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
9
RAMPADJ
ILIMIT
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit threshold
of the converter. This pin is actively pulled low when the ADP3182 EN input is low, or when VCC is below its
UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low.
10
11
12
13
CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier. This pin should be connected to the common point of the output inductors.
Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determines the gain of the
current sense amplifier.
CSSUM
CSCOMP
14
GND
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
15 to 17
SW3 to SW1
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
18 to 20
PWM3 to
PMW1
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3418. Connecting the PWM3 output to GND causes that phase to turn off, allowing the ADP3182 to operate
as a 1- or 2-phase controller.
Rev. PrB | Page 6 of 16
Preliminary Technical Data
ADP3182
TYPICAL PERFORMANCE CHARACTERISTICS
3
2
1
0
0
50
100
150
200
250
300
R
VALUE – kΩ
T
Figure 4. Master Clock Frequency vs. RT
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
T
= 25ºC
A
3-PHASE OPERATION
0
0.5
1
1.5
2
2.5
3
OSCILLATOR FREQUENCY – MHz
Figure 5. Supply Current vs. Oscillator Frequency
Rev. PrB | Page 7 of 16
ADP3182
Preliminary Technical Data
THEORY OF OPERATION
cycle is possible. Also, more than one output can be on at the
same time for overlapping phases.
The ADP3182 combines a multi-mode, fixed frequency PWM
control with multi-phase logic outputs for use in 1-, 2-, and
3-phase synchronous buck point-of-load supply power
converters. Multiphase operation is important for producing the
high currents and low voltages demanded by auxiliary supplies
in desktop computers, workstations, and servers. Handling the
high currents in a single-phase converter would place high
thermal demands on the components in the system such as the
inductors and MOSFETs.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3182 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 4. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM3 is grounded, then divide the master clock by 2 for the
frequency of the remaining two phases.
The multimode control of the ADP3182 ensures a stable, high
performance topology for
It is important to note that if only one phase is used, the clock
will still be switching as if two phases were operating. This
means that the oscillator frequency needs to be set at twice the
expected value to program the desired PWM frequency.
•
•
Balancing currents and thermals between phases
High speed response at the lowest possible switching
frequency and output decoupling
OUTPUT VOLTAGE DIFFERENTIAL SENSING
•
Minimizing thermal switching losses due to lower
frequency operation
The ADP3182 uses a differential sensing low offset voltage error
amplifier. This maintains a worst-case specification of 2%
differential sensing error over its full operating output voltage
and temperature range. The output voltage is sensed between
the FB and FBRTN pins. FB should be connected through a
resistor to the regulation point, usually the local bypass
capacitor for the load. FBRTN should be connected directly to
the remote sense ground point. The internal precision reference
is referenced to FBRTN, which has a minimal current of 100 µA
to allow accurate remote sensing. The internal error amplifier
compares the output of the reference to the FB pin to regulate
the output voltage.
•
•
•
•
Tight load line regulation and accuracy
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
•
Flexibility in operation for tailoring design to low cost or
high performance
START-UP SEQUENCE
During start-up, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3182 operates as
a 3-phase PWM controller. Grounding the PWM3 pin programs
1/2-phase operation.
OUTPUT CURRENT SENSING
The ADP3182 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for current limit
detection. Sensing the load current at the output gives the total
average current being delivered to the load, which is an
inherently more accurate method than peak current detection
or sampling the current across a sense element such as the low-
side MOSFET. This amplifier can be configured several ways
depending on the objectives of the system:
When the ADP3182 is enabled, the controller outputs a voltage
on PWM3 which is approximately 675 mV. An internal
comparator checks the pin’s voltage versus a threshold of
300 mV. If the pin is grounded, it is below the threshold and the
phase is disabled. The output resistance of the PWM pin is
approximately 5 kΩ during this detection time. Any external
pull-down resistance connected to the PWM pin should not be
less than 25 kΩ to ensure proper operation. PWM1 and PWM2
are disabled during the phase detection interval, which occurs
during the first two clock cycles of the internal oscillator. After
this time, if the PWM output is not grounded, the 5 kΩ
resistance is removed. and it switches between 0 V and 5 V. If
the PWM output was grounded, it remains off.
•
•
•
Output inductor DCR sensing without a thermistor for
lowest cost
Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor temperature
Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Since each phase is
monitored independently, operation approaching 100% duty
Rev. PrB | Page 8 of 16
Preliminary Technical Data
ADP3182
gain of the amplifier is programmable by adjusting the feedback
resistor. The current information is then given as the difference
of CSREF – CSCOMP. This difference signal is used as a
differential input for the current limit comparator.
SOFT START
The power-on ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch off
time as explained in the following section. In UVLO or when
EN is a logic low, the DELAY pin is held at ground. After the
UVLO threshold is reached and EN is a logic high, the DELAY
capacitor is charged with an internal 20 µA current source. The
output voltage follows the ramping voltage on the DELAY pin,
limiting the inrush current. The soft-start time depends on the
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. Also, the sensing
gain is determined by external resistors so that it can be made
extremely accurate.
CURRENT CONTROL MODE AND
THERMAL BALANCE
value of CDLY, with a secondary effect from RDLY
.
The ADP3182 has individual inputs for each phase, which are
used for monitoring the current in each phase. This information
is combined with an internal ramp to create a current balancing
feedback system, which has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for positioning
described previously.
If either EN is taken low or VCC drops below UVLO, the
DELAY capacitor is reset to ground to be ready for another soft-
start cycle. Figure 6 shows a typical soft-start sequence for the
ADP3182.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It is also monitors the supply
voltage for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the RAMPADJ
pin determines the slope of the internal PWM ramp. External
resistors can be placed in series with individual phases to create,
if desired, an intentional current imbalance such as when one
phase may have better cooling and can support higher currents.
Resistors RSW1 through RSW3 (see the typical application circuit
in Figure 8) can be used for adjusting thermal balance. It is best
to have the ability to add these resistors during the initial design,
so make sure that placeholders are provided in the layout.
TO BE ADDED
Figure 6. Typical Start-Up Waveforms
Channel 1: PWRGD, Channel 2: CSREF,
Channel 3: DELAY, Channel 4: COMP
CURRENT LIMIT, SHORT CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3182 compares a programmable current limit set point
to the voltage from the output of the current sense amplifier.
The level of current limit is set with the resistor from the ILIMIT
pin to ground. During normal operation, the voltage on ILIMIT
is 3 V. The current through the external resistor is internally
scaled to give a current limit threshold of 10.4 mV/µA. If the
difference in voltage between CSREF and CSCOMP rises above
the current limit threshold, the internal current limit amplifier
controls the internal COMP voltage to maintain the average
output current at the limit.
To increase the current in any given phase, make RSW for that
phase larger (make RSW = 0 for the hottest phase and do not
change during balancing). Increasing RSW to only 500 Ω makes a
substantial increase in phase current. Increase each RSW value by
small amounts to achieve balance, starting with the coolest
phase first.
VOLTAGE CONTROL MODE
A high gain-bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is derived from the internal 800 mV reference.
The output of the amplifier is the COMP pin, which sets the
termination voltage for the internal PWM ramps.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops
below 1.8 V. The current limit latch-off delay time is therefore
set by the RC time constant discharging from 3 V to 1.8 V.
The negative input (FB) is tied to the center point of a resistor
divider from the output sense location. The main loop
compensation is incorporated into the feedback network
between FB and COMP.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
Rev. PrB | Page 9 of 16
ADP3182
Preliminary Technical Data
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if short circuit has caused
the output voltage to drop below the PWRGD threshold, a soft-
start cycle is initiated.
POꢁER GOOD MONITORING
The power good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified in the
electrical table. PWRGD goes low if the output voltage is
outside of this specified range or whenever the EN pin is pulled
low.
The latch-off function can be reset by either removing and
reapplying VCC to the ADP3182, or by pulling the EN pin low
for a short time. To disable the short circuit latch-off function,
the external resistor to ground should be left open, and a high-
value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached. The resistor has an impact
on the soft-start time because the current through it adds to the
internal 20 µA current source.
OUTPUT CROꢁBAR
As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
crowbar threshold. This crowbar action stops once the output
voltage falls below the release threshold of approximately 650 mV.
During start-up when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage to
the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry.
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over-
voltage is due to a short in the high-side MOSFET, this action
current-limits the input supply or blows its fuse, protecting the
microprocessor from being destroyed.
OUTPUT ENABLE AND UVLO
An inherent per phase current limit protects individual phases
if one or more phases stops functioning because of a faulty
component. This limit is based on the maximum normal mode
COMP voltage.
For the ADP3182 to begin switching, the input supply (VCC) to
the controller must be higher than the UVLO threshold, and the
EN pin must be higher than its logic threshold. If UVLO is less
than the threshold or the EN pin is a logic low, the ADP3182 is
disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be connected
OD
to the
pins of the ADP3418 drivers. The ILIMIT being
grounded disables the drivers such that both DRVH and DRVL
are grounded. This feature is important in preventing the
discharge of the output capacitors when the controller is shut
off. If the driver outputs were not disabled, a negative voltage
could be generated during output due to the high current
discharge of the output capacitors through the inductors.
Figure 7. Overcurrent Latch-Off Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: COMP, Channel 4: Phase 1 Switch Node
Rev. PrB | Page 10 of 16
Monday, May 24, 2004 8:57 PM /dslack
L1
1µH
D1
1N4148WS
V
IN
+
+
12 V
C5
4.7µF
V
RTN
D2
IN
U2
C4
1N4148WS
ADP3418 100nF
C2
2700µF
16V
C1
2700µF
16V
Q1
NTD40N02
1
2
3
4
8
7
6
5
BST
IN
DRVH
SW
L2
1200µF / 6.3V x 5
16mΩ ESR (each)
1µH / 1.5mΩ
V
OUT
1.8 V
55A
OD
PGND
DRVL
C6
4.7nF
+
+
VCC
C3
1µF
R1
2.2Ω
V
OUT RTN
C17
C21
Q2
NTD110N02
C9
4.7µF
D3
4.7µFx10
6.3V
MLCC
C8
U3
1N4148WS
ADP3418 100nF
Q3
NTD40N02
1
2
3
4
8
7
6
5
BST
IN
DRVH
SW
L3
1µH / 1.5mΩ
OD
PGND
DRVL
C10
4.7nF
VCC
R2
C7
2.2Ω
1µF
Q4
NTD110N02
C13
4.7µF
D4
C12
1N4148WS
U4
ADP3418 100nF
Q5
NTD40N02
1
2
3
4
8
7
6
5
BST
IN
DRVH
SW
L4
1µH / 1.5mΩ
OD
PGND
DRVL
C14
4.7nF
VCC
C11
1µF
R3
2.2Ω
Q6
NTD110N02
R4
10Ω
+
C15
1µF
C16
U1
ADP3182
R
R
33µF
412kΩ
1
2
20
19
18
17
16
15
14
13
12
11
VCC
PWM1
PWM2
PWM3
SW1
FBRTN
FB
R
B1
1.43kΩ
3
R
C
SW1
*
FB
470pF
4
COMP
PWRGD
EN
C
R
R
2.0kΩ
R
A
B2
A
SW2
*
680pF
1.00kΩ
POWER
GOOD
5
SW2
R
R
6
PH1
158kΩ
ENABLE
SW3
PH3
158kΩ
R
SW3
*
7
DELAY
RT
GND
R
CS
C
CS
3.3nF
200kΩ
C
DLY
33nF
R
DLY
390kΩ
8
CSCOMP
R
PH2
158kΩ
R
T
267kΩ
9
RAMPADJ CSSUM
10
ILIMIT
CSREF
R
LIM
150kΩ
Figure 8. 1.8 V, 55 A Application Circuit
ADP3182
Preliminary Technical Data
APPLICATIONS INFORMATION
LAYOUT AND COMPONENT PLACEMENT
Power Circuitry Recommendations
The switching power path should be routed on the PCB to
encompass the shortest possible length in order to minimize
radiated switching noise energy (i.e., EMI) and conduction
losses in the board. Failure to take proper precautions often
results in EMI problems for the entire PC system as well as
noise-related operational problems in the power converter
control circuitry. The switching power path is the loop formed
by the current path through the input capacitors and the power
MOSFETs including all interconnecting PCB traces and planes.
Using short and wide interconnection traces is especially critical
in this path for two reasons: it minimizes the inductance in the
switching loop, which can cause high energy ringing, and it
accommodates the high current demand with minimal voltage
loss.
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
General Recommendations
For good results, a PCB with at least four layers is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the remainder of the power delivery current paths.
Keep in mind that each square unit of 1 ounce copper trace
has a resistance of ~0.53 mΩ at room temperature.
Whenever high currents must be routed between PCB layers,
vias should be used liberally to create several parallel current
paths so that the resistance and inductance introduced by these
current paths is minimized and the via current rating is not
exceeded.
Whenever a power dissipating component, for example, a power
MOSFET, is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding it,
is recommended. Two important reasons for this are improved
current rating through the vias and improved thermal perform-
ance from vias extended to the opposite side of the PCB, where
a plane can more readily transfer the heat to the air. Make a
mirror image of any pad being used to heatsink the MOSFETs
on the opposite side of the PCB to achieve the best thermal
dissipation to the air around the board. To further improve
thermal performance, use the largest possible pad area.
If critical signal lines (including the output voltage sense lines of
the ADP3182) must cross through power circuitry, it is best if a
signal ground plane can be interposed between those signal lines
and the traces of the power circuitry. This serves as a shield to
minimize noise injection into the signals at the expense of
making signal ground a bit noisier.
An analog ground plane should be used around and under the
ADP3182 as a reference for the components associated with the
controller. This plane should be tied to the nearest output
decoupling capacitor ground and should not be tied to any other
power circuitry to prevent power currents from flowing in it.
The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.
The components around the ADP3182 should be located close
to the controller with short traces. The most important traces to
keep short and away from other traces are the FB and CSSUM
pins. The output capacitors should be connected as close as
possible to the load or connector. If the load is distributed, the
capacitors should also be distributed and generally be in
proportion to where the load tends to be more dynamic.
For best EMI containment, a solid power ground plane should
be used as one of the inner layers extending fully under all the
power components.
Signal Circuitry Recommendations
The output voltage is sensed and regulated between the FB pin
and the FBRTN pin, which connect to the signal ground at the
load. To avoid differential mode noise pickup in the sensed
signal, the loop area should be small. Thus, the FB and FBRTN
traces should be routed adjacent to each other on top of the
power ground plane back to the controller.
Avoid crossing any signal lines over the switching power path
loop, described in the following section.
The feedback traces from the switch nodes should be connected
as close as possible to the inductor. The CSREF signal should be
connected to the output voltage at the nearest inductor to the
controller.
Rev. PrB | Page 12 of 16
Preliminary Technical Data
OUTLINE DIMENSIONS
ADP3182
0.341
BSC
20
1
11
0.154
BSC
0.236
BSC
10
PIN 1
MO-137AD
0.065
0.049
0.069
0.053
8°
0°
0.010
0.004
0.012
0.008
0.025
BSC
0.050
0.016
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS
Figure 9. 20-Lead Shrink Small Outline Package [QSOP]
(RQ-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP3182JRQZ-REEL1
Temperature Range
Package Description
Package Option
Quantity per Reel
2500
0°C to 85°C
Shrink SOIC 13” Reel
RQ-20
1 Z = Pb-free part.
Rev. PrB | Page 13 of 16
ADP3182
Preliminary Technical Data
NOTES:
Rev. PrB | Page 14 of 16
Preliminary Technical Data
ADP3182
NOTES:
Rev. PrB | Page 15 of 16
ADP3182
Preliminary Technical Data
NOTES:
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR04938-0-5/04(PrB)
Rev. PrB | Page 16 of 16
相关型号：
ADP3189JCPZ-R7
SWITCHING CONTROLLER, 5000kHz SWITCHING FREQ-MAX, QCC40, 6 X 6 MM, LEAD FREE, MO-220VJJD-2, LFCSP-40
ONSEMI
ADP3189JCPZ-R7
SWITCHING CONTROLLER, 5000kHz SWITCHING FREQ-MAX, QCC40, 6 X 6 MM, LEAD FREE, MO-220VJJD-2, LFCSP-40
ROCHESTER
ADP3189JCPZ-RL
SWITCHING CONTROLLER, 5000kHz SWITCHING FREQ-MAX, QCC40, 6 X 6 MM, LEAD FREE, MO-220VJJD-2, LFCSP-40
ONSEMI
©2020 ICPDF网 联系我们和版权申明