ADP5003ACPZ-R7 [ADI]
Low Noise Micro PMU, 3 A Buck Regulator with 3 A LDO;型号: | ADP5003ACPZ-R7 |
厂家: | ADI |
描述: | Low Noise Micro PMU, 3 A Buck Regulator with 3 A LDO |
文件: | 总30页 (文件大小:988K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Low Noise Micro PMU,
3 A Buck Regulator with 3 A LDO
Data Sheet
ADP5003
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
:
PVIN1
4.2V TO 15V
Low noise, dc power supply system
PVIN1
PVIN1
High efficiency buck for first stage conversion
High PSRR, low noise LDO regulator to remove switching
ripple
Adaptive LDO regulator headroom control option for
optimal efficiency and PSRR across full load range
3 A, low noise, buck regulator
EN1
VOUT1
V
:
SW1
SW1
SW1
COMP1
PVOUT1
0.6V TO 5.0V
BUCK
REGULATOR
3A
VSET1
PGND1
PGND1
PGND1
Wide input voltage range: 4.2 V to 15 V
Programmable output voltage range: 0.6 V to 5.0 V
0.3 MHz to 2.5 MHz internal oscillator
VREG
RT
V
:
PVINSYS
4.2V TO 15V
PVINSYS
PWRGD
SYSTEM
0.3 MHz to 2.5 MHz SYNC frequency range
3 A, low noise, NFET LDO regulator (active filter)
Wide input voltage range: 0.65 V to 5 V
Programmable output voltage range: 0.6 V to 3.3 V
Differential point of load remote sensing
3 μV rms output noise (independent of output voltage)
PSRR > 50 dB (to 100 kHz) with 400 mV headroom at 3 A
Ultrafast transient response
SYNC
REFOUT
PVIN2
PVIN2
PVIN2
VSET2
VBUF
V
:
PVOUT2
PVOUT2
PVOUT2
PVOUT2
LOW NOISE
LDO ACTIVE
FILTER
0.6V TO 3.3V
Power-good output
3A
VREG_LDO
EN2
LOAD
Precision enable inputs for both the buck regulator and LDO
−40°C to +125°C operating junction temperature range
32-lead, 5 mm × 5 mm, LFCSP
VFB2P
VFB2N
APPLICATIONS
AGND1
AGND2
Low noise power for high speed analog-to-digital converter
(ADC) and digital-to-analog converter (DAC) designs
Powering RF agile transceivers and clocking ICs
Figure 1.
GENERAL DESCRIPTION
The ADP5003 integrates a high voltage buck regulator and an
ultralow noise low dropout (LDO) regulator in a small, 5 mm ×
5 mm, 32-lead LFCSP package to provide highly efficient and
quiet regulated supplies.
The LDO regulator output can be accurately controlled at the
point of load (POL) using remote sensing that compensates for the
printed circuit board (PCB) trace impedance while delivering
high output currents.
The buck regulator is optimized to operate at high output
currents up to 3 A. The LDO is capable of a maximum output
current of 3 A and operates efficiently with low headroom
voltage while maintaining high power supply rejection.
Each regulator is activated via a dedicated precision enable
input. The buck switching frequency can be synchronized to
an external signal, or programmed with an external resistor.
Safety features in the ADP5003 include thermal shutdown (TSD)
and input undervoltage lockout (UVLO). The ADP5003 is rated
for a −40°C to +125°C operating junction temperature range.
The ADP5003 can operate in one of two modes. Adaptive mode
allows the LDO to operate with a set headroom by adjusting the
buck output voltage internally. Alternatively, the ADP5003 can
operate in independent mode, where both regulators operate
separately from each other, and where the output voltages are
programmed using resistor dividers.
Rev. 0
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Last Content Update: 11/21/2017
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Data Sheet
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3 A LDO Data Sheet
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3 A Buck Regulator with 3 A LDO
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ADP5003
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Setting the Switching Frequency for the Buck Regulator ....... 21
Setting the Output Voltage for the Buck Regulator ................. 21
Selecting the Inductor for the Buck Regulator......................... 21
Selecting the Output Capacitor for the Buck Regulator.......... 21
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Buck Regulator Specifications .................................................... 4
LDO Specifications ...................................................................... 5
Adaptive Headroom Controller Specifications ........................ 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 14
Power Management Unit........................................................... 14
Buck Regulator............................................................................ 14
LDO Regulator............................................................................ 16
Power-Good ................................................................................ 17
Output Voltage of the Buck Regulator..................................... 17
Output Voltage of the LDO Regulator..................................... 17
Voltage Conversion Limitations............................................... 17
Component Selection................................................................. 18
Compensation Components Design........................................ 20
Junction Temperature ................................................................ 20
Buck Regulator Design Example .................................................. 21
Designing the Compensation Network for the Buck
Regulator ..................................................................................... 22
Selecting the Input Capacitor for the Buck Regulator............. 22
Adaptive Headroom Control Design Example .......................... 23
Setting the Switching Frequency for the Buck Regulator Using
Adaptive Headroom Control.................................................... 23
Setting the Output Voltage for the Buck Regulator Using
Adaptive Headroom Control.................................................... 23
Selecting the Inductor for the Buck Regulator Using Adaptive
Headroom Control..................................................................... 23
Selecting the Output Capacitors for the Buck Regulator Using
Adaptive Headroom Control.................................................... 23
Designing the Compensation Network for the Buck
Regulator Using Adaptive Headroom Control....................... 24
Selecting the Input Capacitor for the Buck Regulator Using
Adaptive Headroom Control.................................................... 24
Recommended Buck External Components for the Buck
Regulator ...................................................................................... 25
Buck Configurations ...................................................................... 26
Independent................................................................................ 26
Adaptive Headroom................................................................... 27
Layout Considerations................................................................... 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
11/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 29
Data Sheet
ADP5003
SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for
typical specifications, unless otherwise noted.
Table 1.
Parameter
Symbol
Min Typ Max Unit Test Conditions/Comments
INPUT VOLTAGE RANGE
VPVIN1, VPVINSYS 4.2
15
5
V
V
VPVIN2
0.65
THERMAL SHUTDOWN
Threshold
Hysteresis
TSD
TSD-HYS
155
15
°C
°C
TJ rising
SYNC INPUT
Input Logic
High
VIH
1.1
V
Low
VIL
VI-LEAKAGE
0.4
1
V
µA
Input Leakage Current
ADAPTIVE MODE INPUT (VSET1)
Input Rising Threshold
Input Hysteresis
VADPR
VADPH
2.5
16
V
mV
PRECISION ENABLING
High Level Threshold
Low Level Threshold
Shutdown Mode
EN1, EN2 Pull-Down Resistance
INPUT CURRENT
VTH_H
VTH_L
VTH_S
RENPD
1.125 1.15 1.175 V
1.025 1.05 1.075 V
0.4
V
1.5
MΩ
Both Channels Enabled
Both Channels Disabled
REFOUT CHARACTERISTICS
Output Voltage
ISTBY-NOSW
ISHUTDOWN
0.5
5
1
10
mA No load
µA TJ = −40°C to +125°C
VREFOUT
2.0
5
V
%
Accuracy
−0.5
+0.5
+2
VREG AND VREG_LDO CHARACTERISTICS
Output Voltage
Accuracy
Current Limit1
VREG, VREG_LDO
V
%
mA
−2
10
POWER-GOOD PIN (PWRGD)
Lower Limit
Lower Hysteresis
Output Voltage Level
Deglitch Time
PWRGDF
PWRGDFH
VOL
80
85 90
2.5
25 50
60
%
%
Nominal VOUT1 and nominal VFB2P/VFB2N low threshold
Nominal VOUT1 and nominal VFB2P/VFB2N low hysteresis
mV Sink current (ISINK) = 1 mA
µs
tPWRGDD
PVINSYS UNDERVOLTAGE LOCKOUT (UVLO)
Input Voltage
Rising
Falling
UVLOPVINSYSRISE
UVLOPVINSYSFALL 3.9
4.2
V
V
1 Do not use VREG and VREG_LDO to supply the external loads. This current limit protects against a pin short to ground.
Rev. 0 | Page 3 of 29
ADP5003
Data Sheet
BUCK REGULATOR SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted.
Table 2.
Parameter
Symbol
Min Typ
Max Unit Test Conditions/Comments
OUTPUT CHARACTERISTICS
Programmable Output Voltage Range1
Buck Regulator Gain
Error Amplifier Transconductance
Buck Output Voltage Accuracy2
Regulation
VVOUT1
ABUCK
gm1
0.6
2.5
5.0
V
509
−1
600
661
+1
µS
%
σVOUT1
Load 1 current (ILOAD1) = 10 mA
ILOAD1 = 10 mA
Line
Load
(ΔVVOUT1/VVOUT1)/ΔVPVIN1
(ΔVVOUT1/VVOUT1)/ΔIVOUT1
σBUCK
IIN
0.004
0.04
1.5
%/V
%/A 0 mA ≤ ILOAD1 ≤ 3 A, VPVIN1 = 12 V
%
Total Output Voltage Accuracy
OPERATING SUPPLY CURRENT
SW1 CHARACTERISTICS
SW1 On Resistance
4.2 V ≤ VPVIN1 ≤ 15 V, 1 mA ≤ ILOAD1 ≤ 3 A
ILOAD1 = 0 mA, LDO disabled
3.8
mA
RPFET
RNFET
ILIMIT1
130
60
200
100
mΩ
mΩ
A
VPVIN1 = 15 V (PVIN1 to SW1)
VPVIN1 = 15 V (SW1 to PGND1)
Negative channel field effect
transistor (NFET) switch valley
current limit
Current Limit 1
3.5
−1
A
Negative current limit
Slew Rate
Minimum On Time3
Minimum Off Time
SLEWSW1
tMIN_ON
tMIN_OFF
RPDWN-B
tSSBUCK
1.6
35
100
90
2
V/ns VPVIN1 = 15 V, IVOUT1 = 1 A
ns
ns
128
150
BUCK REGULATOR ACTIVE PULL DOWN
BUCK REGULATOR SOFT START (SS)
HICCUP TIME
Ω
Channel disabled
ms
ms
nA
tHICCUP
33
10
VSETx ADJUSTABLE INPUT BIAS CURRENT
OSCILLATOR
IVSET1, IVSET2
4.2 V ≤ VPVINSYS ≤ 15 V
Internal Switching Frequency 1
Internal Switching Frequency 2
SYNC
fSW1
fSW2
2.25 2.5
0.26 0.3
2.75 MHz RT current (IRT) = 10 µA
0.34 MHz IRT = 1 µA
Frequency Range
fSYNC
0.3
2.5
MHz
Minimum Pulse Width
Positive
Negative
20
10
ns
ns
1 The switching frequency, minimum on time, and minimum off time dictates the output voltage range.
2 The buck output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error.
3 The minimum on time indicates the minimum turn on time to ensure fixed frequency switching.
Rev. 0 | Page 4 of 29
Data Sheet
ADP5003
LDO SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, LDO headroom voltage (VHR) = 300 mV, TJ = −40°C to +125°C for
minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 3.
Parameter
Symbol
Min Typ
Max Unit
Test Conditions/Comments
OUTPUT CHARACTERISTICS
Programmable Output Voltage Range1
LDO Gain
Output Voltage Accuracy2
Regulation
VPVOUT2
ALDO
σPVOUT2
0.6
1.65
−1
3.3
+1
V
%
Load 2 current (ILOAD2) = 150 mA
Line
(ΔVPVOUT2/VPVOUT2)/ΔVPVIN2
0.007
%/V
(VPVOUT2 + VHR) ≤ VPVIN2 ≤ 6 V,
ILOAD2 = 100 mA
Load
(ΔVPVOUT2/VPVOUT2)/ΔIPVOUT2
σLDO
0.08
1.5
%/A
%
10 mA ≤ ILOAD2 ≤ 3 A
(VPVOUT2 + VHR) ≤ VPVIN2 ≤ 6 V,
10 mA ≤ ILOAD2 ≤ 3 A
Total Output Voltage Accuracy
OPERATING SUPPLY CURRENT
IGND
1.8
2.3
2.5
4.5
mA
mA
ILOAD2 = 0 μA
ILOAD2 = 3 A
ILOAD2 = 3 A
MINIMUM VOLTAGE REQUIREMENTS
PVINSYS to PVOUT23
VREG_LDO to PVOUT24
Dropout5
CURRENT-LIMIT THRESHOLD6
LDO SOFT START (SS) TIME
LDO ACTIVE PULL-DOWN
OUTPUT NOISE
VLDO-PVINSYS
VLDO-VREG_LDO
VDROPOUT
ILIMIT2
1.5
1.35
100
V
V
mV
A
Required to drive NFET
3.1
tSSLDO
400
µs
Ω
RPDWNLDO
NPVOUT2
300
Channel disabled
3
µV rms 10 Hz to 100 kHz, IOUT = 1 A
VPVIN2 = VPVOUT2 + 0.3 V, IOUT = 1 A
LDO POWER SUPPLY REJECTION RATIO
VPVOUT2 = 1.3 V
PSRRLDO
87
82
61
38
89
83
61
37
dB
dB
dB
dB
dB
dB
dB
dB
1 kHz
10 kHz
100 kHz
1000 kHz
1 kHz
10 kHz
100 kHz
1000 kHz
VPVOUT2 = 3.3 V
1 Limited by minimum PVINSYS to PVOUT2 and VREG_LDO to PVOUT2 voltage.
2 The LDO output voltage accuracy is relative to the nominal output voltage and accounts for reference voltage, gain, and offset error.
3 PVINSYS must be higher than PVOUT2 for VLDO-PVINSYS to keep the LDO regulating.
4 PVOUT2 must be lower than VREG_LDO for VLDO-VREG_LDO to keep the LDO regulating.
5 The dropout voltage is the input to output voltage differential when the input voltage is set to the nominal output voltage.
6 The current-limit threshold is the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V output
voltage is the current that causes the output voltage to drop to 90% of 1.0 V or 0.9 V.
ADAPTIVE HEADROOM CONTROLLER SPECIFICATIONS
VPVIN1 = VPVINSYS = 4.2 V to 15 V, VPVIN2 = 0.65 V to 5 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted.
Table 4.
Parameter
Symbol
Min
Typ
160
280
400
Max
Unit
mV
mV
mV
Test Conditions/Comments
ILOAD2 = 1 mA
ILOAD2 = 1.5 A
HEADROOM VOLTAGE (PVIN2 − PVOUT2)
VHR
ILOAD2 = 3 A
Rev. 0 | Page 5 of 29
ADP5003
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
Parameter
Rating
PVIN1/PVINSYS to AGND1/AGND2
PVIN2 to AGND1/AGND2
AGND1 to AGND2
PGND1 to AGND1/AGND2
PVOUT2 to AGND1/AGND2
VFB2N to AGND1/AGND2
VOUT1, VFB2P, EN1, EN2, SYNC, RT,
REFOUT, VBUF, VSET1, VSET2,
COMP1 to AGND1/AGND2
−0.3 V to +16 V
−0.3 V to +6.0 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to (PVIN2 + 0.3 V)
−0.3 V to +0.3 V
−0.3 V to (VREG + 0.3 V)
Table 6. Thermal Resistance
1
1
Package Type
θJA
θJC
20.95
Unit
CP-32-7
46.91
°C/W
1 θJA and θJC are based on a 4-layer PCB (two signal and two power planes)
with nine thermal vias connecting the exposed pad to the ground plane as
recommended in the Layout Considerations section.
SW1 to PGND1
−0.3 V to (PVIN1 + 0.3 V)
VREG, VREG_LDO to AGND1/AGND2 −0.3 V to the lower of
(PVINSYS + 0.3 V) or +6.0 V
ESD CAUTION
VREG to VREG_LDO
Storage Temperature Range
Operating Junction Temperature
Range
−0.3 V to +0.3 V
−65°C to +150°C
−40°C to +125°C
Soldering Conditions
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 6 of 29
Data Sheet
ADP5003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 AGND1
23
22 RT
PGND1
VOUT1
EN1
1
2
3
4
5
6
7
8
VREG
ADP5003
21 COMP1
EN2
TOP VIEW
20
19
18
PWRGD
VSET1
REFOUT
SYNC
PVIN2
PVIN2
PVIN2
(Not to Scale)
17 VSET2
NOTES
1. EXPOSED THERMAL PAD. CONNECT THE
EXPOSED THERMAL PAD TO AGND1.
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Description
1, 31, 32
2
3
PGND1
VOUT1
EN1
Buck Regulator Dedicated Power Ground.
Buck Regulator Feedback Input. Connect a short sense trace to the buck output capacitor.
Buck Regulator Precision Enable Pin. Drive the EN1 pin high to turn on the buck regulator, and drive the EN1 pin
low to turn off the buck regulator.
4
5
EN2
LDO Precision Enable Pin. Drive the EN2 pin high to turn on the LDO regulator, and drive the EN2 pin low to turn
off the LDO regulator.
Synchronization Input. To synchronize the switching frequency of the device to an external clock, connect this
pin to an external clock with a frequency from 300 kHz to 2.5 MHz.
SYNC
6 to 8
9 to 11
12
PVIN2
PVOUT2
VFB2P
LDO Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and AGND2.
LDO Regulator Power Output. Connect a 10 µF ceramic capacitor between this pin and AGND2.
LDO Regulator Positive Sense Feedback Input. Connect a sense trace to the LDO output at the load. Route this
pin with the VFB2N pin on the PCB.
13
VFB2N
LDO Regulator Ground Sense Feedback Input. Connect a sense trace to ground at the load. Route this pin with
the VFB2P pin on the PCB.
14
15
16
VBUF
AGND2
VREG_LDO
Output of the LDO Reference Buffer. Connect a 0.1 µF ceramic capacitor between this pin and VFB2N.
LDO Dedicated Analog Ground.
Internal Regulator Output for the LDO. Connect a 1 µF ceramic decoupling capacitor between this pin and
AGND2. Do not use this pin to power external devices.
17
18
VSET2
REFOUT
LDO Regulator Output Voltage Configuration Input.
Internal Reference Output Required for Driving the External Resistor Dividers for VSET1 and VSET2. Connect a
0.22 µF ceramic capacitor between this pin and AGND2.
19
VSET1
Buck Regulator Output Voltage Configuration Input. Connect this pin to VREG to enable adaptive headroom
control.
20
21
22
23
PWRGD
COMP1
RT
Power-Good Digital Output (Open-Drain NFET Pull-Down Driver).
Buck Regulator External Compensation Pin.
Resistor Adjustable Frequency Programming Input.
Internal Regulator Output. Connect a 1 µF ceramic decoupling capacitor between this pin and AGND1. Do not
use this pin to power external devices.
VREG
24
25
26, 27
28 to 30
AGND1
PVINSYS
PVIN1
SW1
Analog Ground.
System Power Supply for the ADP5003. Connect a 10 µF ceramic capacitor between this pin and AGND1.
Buck Regulator Power Input. Connect a 10 µF ceramic capacitor between this pin and PGND1.
Buck Regulator Switching Output.
EPAD
Exposed Thermal Pad. Connect the exposed thermal pad to AGND1.
Rev. 0 | Page 7 of 29
ADP5003
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
3.3V
3.3V
2.5V
1.8V
1.3V
1.1V
20
2.5V
1.8V
10
1.3V
1.1V
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 6. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 5 V at
Various Buck Output Voltages
Figure 3. Buck Efficiency vs. Load Current, VPVIN1 = 5 V, fSW = 600 kHz at
Various Buck Output Voltages
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
3.3V
3.3V
2.5V
1.8V
1.3V
1.1V
20
10
0
2.5V
1.8V
10
0
1.3V
1.1V
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 7. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 12 V at
Various Buck Output Voltages
Figure 4. Buck Efficiency vs. Load Current, VPVIN1 = 12 V, fSW = 600 kHz at
Various Buck Output Voltages
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
300kHz
600kHz
1MHz
300kHz
10
0
10
0
600kHz
1MHz
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
LOAD CURRENT (A)
Figure 8. Adaptive Mode Efficiency vs. Load Current, VPVIN1 = 12 V,
PVOUT2 = 3.3 V at Various Buck Switching Frequencies
Figure 5. Buck Efficiency vs. Load Current, VPVIN1 = 12 V, VVOUT1 = 3.3 V at
Various Buck Switching Frequencies
V
Rev. 0 | Page 8 of 29
Data Sheet
ADP5003
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.1A
0.1A
1A
1A
–10
2A
3A
2A
3A
–20
–30
–40
–50
–60
–70
–80
–90
–100
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. LDO PSRR vs. Frequency, VHR = 0.3 V, VPVOUT2 = 1.3 V at
Various LDO Load Currents
Figure 12. LDO PSRR vs. Frequency, VHR = 0.3 V, VPVOUT2 = 3.3 V at
Various LDO Load Currents
0
0
0.2V
0.2V
0.3V
0.4V
0.5V
0.3V
–10
–10
0.4V
0.5V
–20
–20
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. LDO PSRR vs. Frequency, VPVOUT2 = 3.3 V, IPVOUT2 = 1 A at
Various LDO Headroom Voltages
Figure 10. LDO PSRR vs. Frequency, VPVOUT2 = 1.3 V, IPVOUT2 = 1 A at
Various LDO Headroom Voltages
1000
1000
0.1A
1A
3A
0.9V
3.3V
100
10
1
100
10
1
V = 3.3V
PVOUT2
I
= 1A
PVOUT2
0.1
0.1
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. LDO Noise Spectral Density vs. Frequency, IPVOUT2 = 1 A at
Various LDO Output Voltages
Figure 14. LDO Noise Spectral Density vs. Frequency, VPVOUT2 = 3.3 V at
Various LDO Load Currents
Rev. 0 | Page 9 of 29
ADP5003
Data Sheet
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
–0.5
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
4.2 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0
INPUT VOLTAGE (V)
LOAD CURRENT (A)
Figure 18. Buck Line Regulation, VVOUT1 = 3.3 V, IVOUT1 = 1 A, fSW = 600 kHz
Figure 15. Buck Load Regulation, VPVIN1 = 12 V, VVOUT1 = 3.3 V, fSW = 600 kHz
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.5
1.0
1.5
2.0
2.5
3.0
HEADROOM (V)
LOAD CURRENT (A)
Figure 16. LDO Load Regulation, VPVOUT2 = 3.3 V, VHR = 0.3 V
Figure 19. LDO Line Regulation, VPVOUT2 = 3.3 V, IPVOUT2 = 1 A
1.0
3
0.8
0.6
2
1
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–50
–20
10
40
70
100
130
–50
–20
10
40
70
100
130
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. REFOUT Voltage (VREFOUT) vs. Temperature
Figure 20. Switching Frequency vs. Temperature
Rev. 0 | Page 10 of 29
Data Sheet
ADP5003
3.0
2.5
2.0
1.5
1.0
0.5
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
4
6
8
10
12
14
0
0.5
1.0
1.5
2.0
2.5
3.0
INPUT VOLTAGE (V)
LOAD CURRENT (A)
Figure 21. Buck Quiescent Current vs. Input Voltage
Figure 24. Adaptive Mode Headroom vs. Load Current
4.0
3.5
3.0
2.5
2.0
1.5
1,0
0.5
0
I
L
1
V
SW1
2
3
V
VOUT1
CH1 500mA CH2 5V
CH3 10mV Ω B
M200ns
94ns
A CH2
8V
0
0.5
1.0
1.5
2.0
2.5
3.0
T
W
LOAD CURRENT( A)
Figure 25. SW1 Waveform, VVOUT1 = 5 V, IVOUT1 = 100 mA
Figure 22. LDO Quiescent Current vs. Load Current
V
VOUT1
V
VOUT1
2
2
V
SW1
V
SW1
3
1
3
1
I
I
L
L
B
CH1 5.00AB CH2 500mV
M20.0ms
40.0080ms
A CH2
510mV
B
CH1 5.00AB CH2 500mV
M20.0ms
40.0080ms
A CH2
510mV
W
W
W
W
CH3 10.0V B
CH3 10.0V B
T
W
T
W
Figure 26. Exiting Hiccup Mode
Figure 23. Entering Hiccup Mode (VVOUT1 is the Voltage of the VOUT1 Pin, and
VSW1 is the Voltage of the SW1 Pin, and IL is Inductor Current)
Rev. 0 | Page 11 of 29
ADP5003
Data Sheet
I
= 1A
PVOUT2
V
/V
EN1 EN2
V
EN1
2
3
V
VOUT1
V
PVOUT2
V
VOUT1
3
1
4
I
VOUT1
4
2
1
I
VOUT1
V
SW1
B
CH1 1A
CH3 1V
CH2 2V
CH4 10V B
M400µs
A
CH2
1.56V
W
CH1 1.00A
CH3 2.00V
CH2 1.00V
CH4 1.00V
M1.00ms
A CH3
2.04V
B
W
W
T
3.00400ms
Figure 27. Buck Startup, VVOUT1 = 3.3V, IVOUT1 = 3 A
(VEN1 is the EN1 voltage, and IVOUT1 is the VOUT1 current.)
Figure 30. Adaptive Mode Startup, VPVOUT2 = 3.3 V, IPVOUT2 = 1 A
(VEN2 is the EN2 voltage.)
I
V
VOUT1
PVIN1
2.3A/µs
3.1A/µs
4
V
V
VOUT1
VOUT1
4
2
2
10V OFFSET
CH2 500mV B CH4 20.0mVΩ B M80µs
A CH2
12.4V
CH2 500mV
CH4 1A
M200µs
A
CH4
1.46A
W
W
T 25.50%
T
493.480µs
Figure 31. Buck Load Transient, VPVIN1 = 12 V, VVOUT1 = 1.2 V, IVOUT1 = 0.5 A to 3 A
Figure 28. Buck Line Transient, VPVIN1 = 12 V to 13 V, VVOUT1 = 1.2 V, IVOUT1 = 1 A
2.3A/µs
3A/µs
I
PVOUT2
V
PVIN2
4
2
1
2
3V OFFSET
V
PVOUT2
V
PVOUT2
B
CH2 20.0mV
CH4 1.00A
M8.00µs
A
CH4
1.34A
CH1 500mV CH2 1.00mV
M80.0µs
A
CH1
3.81V
W
T
18.4800µs
T
200.960µs
Figure 32. LDO Load Transient, VPVIN2 = 3.6 V, VPVOUT2 = 3.3 V,
PVOUT2 = 0.5 A to 3 A
Figure 29. LDO Line Transient, VPVIN2 = 3.6 V to 4.1 V, VPVOUT2 = 3.3 V,
PVOUT2 = 1 A
I
I
Rev. 0 | Page 12 of 29
Data Sheet
ADP5003
V
1.2A/µs
I
1.3A/µs
PVIN1
PVOUT2
3
4
V
PVOUT2
V
PVOUT2
4
10V OFFSET
2
CH2 500mV B CH4 1.00mV Ω B
M80µs
25.90%
A
CH2
12.5V
CH3 500mA
CH4 10.0mVΩ B M80µs
A
CH2
1.52V
W
W
W
T
T 24.70%
Figure 33. Adaptive Mode Line Transient, VPVIN1 = 11 V to 13 V, VPVOUT2 = 3.3 V,
PVOUT2 = 1 A
Figure 34 Adaptive Mode Load Transient, VPVIN1 = 12 V, VPVOUT2 = 3.3 V,
PVOUT2 = 1 A to 1.5 A
I
I
Rev. 0 | Page 13 of 29
ADP5003
Data Sheet
THEORY OF OPERATION
Active Pull Down
POWER MANAGEMENT UNIT
Both regulators have active pull-down resistors discharging the
respective output capacitors when the regulators are disabled.
The pull-down resistors are connected between VOUT1 to
AGND1 and PVOUT2 to AGND2. Active pull-down resistors
are disabled when the regulators are turned on.
The ADP5003 is a micropower management unit combing a
step-down (buck) dc-to-dc converter and an ultralow noise low
dropout linear (LDO)regulator. The high switching frequency
and 5 mm × 5 mm, 32-lead LFCSP package allow a compact
power management solution.
When the enable pins are asserted low, or a TSD or UVLO
event occurs, the active pull-down resistors enable to quickly
discharge the output capacitors. The pull-down resistors remain
engaged until the enable pins are asserted high, the fault event is
no longer present, or the VREG supply voltage falls to less than
1 V to guarantee that the pull-down resistor remains enabled.
Adaptive Headroom Control
The ADP5003 features a scheme to control the LDO headroom
voltage to ensure optimal operating efficiency while maintaining
the power supply rejection ratio (PSRR) performance across the
full range of the load current.
Precision Enable/Shutdown
Soft Start (SS)
The ADP5003 has individual enable pins (EN1 and EN2) to
control the regulators.
Both regulators have an internal soft start function that ramps
the output voltage in a controlled manner on startup, thereby
limiting the inrush current. The soft start function reduces the
risk of noise spikes and voltage drops on the upstream supplies.
The precision enable function allows a precise turn on point for
the regulators to allow the possibility of external sequencing. A
voltage level higher than VTH_H applied to the EN1 or EN2 pin
activates a regulator, whereas a level below VTH_L turns off a
regulator. The buck is controlled by EN1, and the LDO is
controlled by the EN2 pin. When both EN1 and EN2 fall below
Power-Good
The ADP5003 has a dedicated power-good, open-drain, output
(PWRGD). PWRGD indicates whether one or more regulators
are outside the voltage limits specified by the power-good lower
limit (PWRGDF) and the power-good upper limit (PWRGDF +
PWRGDFH). When either one or both of the regulator outputs
are outside the power-good limits, the PWRGD output pulls low.
V
TH_S, the ADP5003 enters shutdown mode.
Undervoltage Lockout (UVLO)
To protect against the input voltage being too low, UVLO
circuitry is integrated into the system. If the input voltage on
PVINSYS drops to less than the UVLOPVINSYSFALL threshold, all
channels shut down.
When in adaptive mode, PWRGD only monitors the LDO
output, and when in standalone mode, PWRGD only monitors
the regulator/regulators that are enabled.
The device is enabled again when the voltage on PVINSYS rises
more than UVLOPVINSYSRISE threshold if the enable pins remain
active.
BUCK REGULATOR
Control Scheme
The buck regulator operates with a fixed frequency, emulated
peak current mode, pulse-width modulation (PWM) control
architecture, where the duty cycle of the integrated switches is
adjusted and regulates the output voltage. At the start of each
oscillator cycle, the positive channel field effect transistor (PFET)
switch is turned on, sending a positive voltage across the inductor.
Current in the inductor increases until the emulated current
sense signal crosses the peak inductor current threshold, which
turns off the PFET switch and turns on the NFET synchronous
rectifier. Turning on the NFET synchronous rectifier creates a
negative voltage across the inductor, which causes the inductor
current to decrease. The synchronous rectifier stays on for the
remainder of the cycle. By adjusting the peak inductor current
threshold, the buck regulator can regulate the output voltage.
The emulated inductor current scheme senses the current in the
inductor during the off phase of the cycle, when the NFET is
conducting, and uses this inductor current to generate the
emulated current sense signal during the on time of the cycle.
This scheme allows the low duty cycles necessary for high input
voltage, VIN, to output voltage, VOUT, conversion ratios.
Thermal Shutdown (TSD)
In the event that the junction temperature rises above TSD, the
thermal shutdown circuit turns off all regulators. Extreme
junction temperatures can be the result of high current operation,
poor circuit board design, or a high ambient temperature. A
hysteresis value of TSD-HYS is included so that when thermal
shutdown occurs, the regulators do not return to operation until
the on-chip temperature drops below TSD − TSD-HYS. When
emerging from thermal shutdown, both regulators restart with
soft start control.
Rev. 0 | Page 14 of 29
Data Sheet
ADP5003
Oscillator Frequency Control
External Oscillator Synchronization
The ADP5003 buck regulator oscillator frequency is controlled
by using the RT pin or the SYNC pin. To define the buck
The SYNC pin is dedicated for oscillator synchronization and
allows the ADP5003 to lock to an external clock.
regulator internal switching frequency, connect the RT pin via a
resistor to AGND1. Figure 35 shows the relationship of the buck
oscillator frequency and the RT resistor.
When an applied external clock signal is present at the SYNC pin,
the buck regulator operates in sync with this signal.
When alternating between external clocks and the internal
oscillator, the presence of an external frequency causes a
multiplexer to switch between the internal oscillator and the
external SYNC frequency. The output of this multiplexer acts as
the frequency reference to an internal phase-lock loop (PLL),
which ensures that changing between the two modes of operation
results in a smooth transition between the different frequencies.
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Buck Startup
The buck regulator turns on with a controlled soft start ramp to
limit inrush current. The reference of the buck is ramped by
tSSBUCK, which is typically 2 ms (see Figure 36).
0
100
200
300
400
500
600
700
800
tSSBUCK
V
EN1
RT RESISTOR (kΩ)
2
Figure 35. Buck Oscillator Frequency vs. RT Resistor (RRT)
To determine the oscillator frequency (fSW), use the following
equation:
V
VOUT1
4
1
3
f
SW = (1.78 × 1011)/RRT
(1)
I
VOUT1
When there is no resistor present on the RT pin, the internal
oscillator operates at the lowest frequency. An upper limit
prevents out of range frequencies when the RT pin is shorted
to ground or connected with an incorrect resistor value.
V
SW1
CH1 1.00A B
CH3 5.00V
CH2 5.0V
CH4 1.0V
4.00µs
1.60ms
A
CH2
1.20V
B
B
W
W
W
W
B
T
Figure 36. Buck Startup
Rev. 0 | Page 15 of 29
ADP5003
Data Sheet
Current-Limit and Short-Circuit Protection
LDO Startup
The LDO regulator turns on with a controlled soft start ramp to
The buck regulator includes current-limit protection circuitry
to limit the amount of forward current through the metal oxide
semiconductor field effect transistor (MOSFET) switches.
When the valley inductor current exceeds the overcurrent limit
threshold for a number of clock cycles during an overload or
short-circuit condition, the regulator enters hiccup mode. The
regulator stops switching and then restarts with a new soft start
cycle after the hiccup time, tHICCUP, and repeats until the over-
current condition is removed. If the buck regulator output
voltage falls below 50% of the nominal output voltage, the
regulator immediately enters hiccup mode. When the valley
inductor current falls below the negative current-limit
threshold, the NFET remains on until the inductor current
returns to 0 A.
limit inrush current. This soft start ramp is dictated by tSSLDO
,
which is typically 400 µs.
4.0
0.1A
3.5
1A
3A
V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
EN2
2.5
1.5
0.5
–0.5
–1.5
–2.5
–3.5
–4.5
–0.4 –0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4 1.6
TIME (ms)
2
Figure 38. LDO Startup
Current Limit
The LDO reaches the current limit when the output load reaches
LIMIT2. When the output load exceeds ILIMIT2, the output voltage
3A
3
I
reduces to maintain a constant current limit.
tHICCUP
Differential Remote Sensing
1
The LDO can sense at the point of load by using VFB2P and
VFB2N as shown in Figure 39. Differential remote sensing
compensates for both the source drop and the return drop to
provide a more precise supply scheme at the point of load.
PVOUT2
LOW NOISE
PVOUT2
PVOUT2
LDO ACTIVE
FILTER
3A
V
VOUT1
–
+
2
VFB2P
VFB2N
+
3A
LOAD
–
I
L
3
1
AGND1
AGND2
–
+
V
SW1
Figure 39. Differential Remote Sensing
CH1 10.0V
CH3 2.0A
CH2 2.00V
20.0ms
A
CH2
1.08V
B
T
79.7600ms
W
Figure 37. Short-Circuit Response (Current Limit and Hiccup Mode)
LDO REGULATOR
The ADP5003 contains a single low noise, low dropout (LDO)
linear regulator that uses an NFET pass device to provide high
PSRR with low headroom voltage and an output current up to 3 A.
The LDO regulator can operate with an input voltage of 0.65 V
to 5 V while providing excellent line and load transient response
using 10 µF ceramic input and output capacitors.
Rev. 0 | Page 16 of 29
Data Sheet
ADP5003
POWER-GOOD
OUTPUT VOLTAGE OF THE LDO REGULATOR
An external pull-up resistor is necessary to drive the PWRGD
output high (see Figure 40). Through the value of the pull-up
resistor is not critical, it is recommended to use a 10 kΩ to
300 kΩ resistor. The resistor must be pulled to a voltage level
no greater than 5.5 V.
The output voltage on the LDO regulator is adjustable through
an external resistor divider. The LDO adjustable output voltage
configuration is shown in Figure 42.
PVOUT2
PVIN2
REFOUT
VFB2P
VFB2N
V
PULLUP
LDO
R
TOP
R
PULLUP
VSET2
PWRGD
GPIO
PWRGD
V
R
BOT
Figure 42. LDO Adjustable Output Voltage Configuration
Figure 40. Power-Good Setup
To calculate the LDO output voltage, use the following
equation:
OUTPUT VOLTAGE OF THE BUCK REGULATOR
The output voltage on the buck regulator is adjustable through
an external resistor divider. When using adaptive mode, the
ADP5003 controls the buck output voltage.
RBOT
RTOP + RBOT
VPVOUT2 = VREFOUT ALDO
(3)
The adjustable output voltage configuration is shown in Figure 41.
where ALDO is the LDO gain.
SW1
PVOUT1
PVIN1
VOLTAGE CONVERSION LIMITATIONS
REFOUT
VOUT1
For a given input voltage and switching frequency, an upper
and lower limitation on the output voltage exists due to the
minimum on time and minimum off time. The minimum on
time limits the minimum output voltage for a given input
voltage and switching frequency.
BUCK
R
TOP
VSET1
R
BOT
If the minimum on time is exceeded, the ADP5003 may not
switch at a fixed frequency because the device can switch at an
effective zero on time, resulting in unpredictable switching
frequencies and unwanted noise. To avoid noise, select the
switching frequency carefully.
Figure 41. Buck Regulator Adjustable Output Voltage
To calculate the buck output voltage, use the following equation:
RBOT
RTOP + RBOT
To calculate the minimum output voltage for a given input
voltage and fixed switching frequency, use the following
equation:
V
PVOUT1 = VREFOUT ABUCK
(2)
where:
V
OUT_MIN = VPVIN1 × tMIN_ON × fSW − (RPFET – RNFET) ×
OUT_MIN × tMIN_ON × fSW − (RNFET + RL) × IOUT_MIN (4)
V
A
REFOUT is the REFOUT output voltage.
BUCK is the buck regulator gain.
I
R
R
BOT is the bottom feedback resistor.
TOP is the top feedback resistor.
where:
VOUT_MIN is the minimum output voltage.
PVIN1 is the input voltage.
V
t
MIN_ON is the minimum on time.
fSW is the switching frequency.
R
R
PFET is the high-side MOSFET on resistance.
NFET is the low-side MOSFET on resistance.
I
OUT_MIN is the minimum output current.
RL is the resistance of the output inductor.
Rev. 0 | Page 17 of 29
ADP5003
Data Sheet
The minimum off time limits the maximum duty cycle which
in turn limits the maximum output voltage for a given input
voltage and switching frequency. Calculate the maximum output
voltage for a given input voltage and switching frequency by
using the following equation:
Use the following equation to calculate the worst case capacitance,
accounting for capacitor variation over temperature, component
tolerance, and voltage:
C
EFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) ×
(1 − Tolerance) (6)
V
OUT_MAX = VPVIN1 × (1 − tMIN_OFF × fSW) − (RPFET – RNFET) × IOUT_MAX
(1 − tMIN_OFF × fSW) − (RNFET + RL) × IOUT_MAX
×
(5)
where:
CEFFECTIVE is the effective capacitance at the operating voltage.
where:
OUT_MAX is the maximum output voltage.
OUT_MAX is the maximum output current.
MIN_OFF is the minimum off time.
C
NOMINAL is the nominal data sheet capacitance.
V
I
t
TEMPCO is the worst case capacitor temperature coefficient.
DCBIASCO is the dc bias derating at the output voltage.
Tolerance is the worst case component tolerance.
As shown in Equation 4 and Equation 5, reducing the switching
frequency eases the minimum on time and minimum off time
limitations.
To guarantee the performance of the device, it is imperative to
evaluate the dc bias effects, temperature, and tolerances on the
behavior of the capacitors for each application.
Capacitors with lower effective series resistance (ESR) and
effective series inductance (ESL) are preferred to minimize
output voltage ripple.
COMPONENT SELECTION
Output Capacitors
Higher output capacitor values reduce the output voltage ripple
and improve the load transient response.
Use the following equation to calculate the minimum
capacitance needed for a specific output voltage ripple:
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure
the minimum capacitance over the necessary temperature range
and dc bias conditions. X5R or X7R dielectrics with a voltage
rating of 25 V are recommended for best performance. Y5V
and Z5U dielectrics are not recommended for use with any dc-
to-dc converter because of their poor temperature and dc bias
characteristics.
ΔIL
COUT_MIN
≅
(7)
8× fSW ×(VRIPPLE
—
ΔIL ×RESR )
where:
ΔIL is the current ripple.
SW is the switching frequency.
f
V
R
RIPPLE is the allowed peak-to-peak voltage ripple.
ESR is the effective series resistance of the capacitor.
The minimum capacitance needed for stability considering
temperature and dc bias effects is 22 µF.
The minimum capacitance recommended for the LDO is 10 µF.
Table 8. Recommended Capacitors
Vendor
Part No.
Value (µF)
Type
X7R
X7R
X5R
X5R
X7R
X7R
X7R
Voltage Rating (V)
Case
0805
1210
1210
1210
0805
1210
1210
Wurth
885 012 207 026
885 012 209 006
885 012 109 012
885 012 109 004
GRM21BR71A106KE51
GRM32ER71C226KEA8
GRM32ER71A476KE15
10
22
47
100
10
22
47
10
10
25
6.3
10
16
10
Murata
Rev. 0 | Page 18 of 29
Data Sheet
ADP5003
Input Capacitor
To calculate the inductor value, L, use the following equation:
The input current to the buck converter pulsates from zero to
approximately equal to the load current. Because these current
pulses occur at reasonably high frequencies (0.3 MHz to
2.5 MHz), the input bypass capacitor provides most of the high
frequency current while the input power source supplies only the
average current. Higher value input capacitors reduce the input
voltage ripple and improve transient response.
L = ((VPVIN1 − VVOUT1) × D)/(ΔIL × fSW)
(8)
where:
PVIN1 is the input voltage.
VOUT1 is the output voltage.
D is the duty cycle (D = VVOUT1/VPVIN1).
ΔIL is the inductor ripple current.
V
V
f
SW is the switching frequency.
To minimize supply noise, it is recommended to place a low
ESR capacitor as close as possible to the relevant supply.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. Use the following equation to
calculate the inductor peak current:
Inductor
The high switching frequency of the ADP5003 buck allows the
selection of small chip inductors. A small inductor leads to larger
inductor current ripple that provides excellent transient response
but degrades efficiency. The sizing of the inductor is a trade-off
between efficiency and transient response. As a guideline, the
inductor peak-to-peak, current ripple is typically set to 1/3 of
the maximum load current for optimal transient response and
efficiency.
I
PEAK = IVOUT1 + (ΔIL/2)
where:
VOUT1 is the output current.
ΔIL is the inductor ripple current.
(9)
I
Inductor conduction losses are minimized by using larger sized
inductors that have smaller dc resistance; this in turn improves
efficiency at the cost of solution size. Due to the high switching
frequency of the ADP5003, shielded ferrite core material is
recommended for its low core losses and low electromagnetic
interference (EMI).
Table 9. Recommended Inductors
Vendor
Part No.
Value (µH) Saturation Current, ISAT (A)
RMS Current, IRMS (A)
DC Resistance (mΩ)
Size (mm)
5 × 5
5 × 5
5 × 5
5 × 5
5 × 5
5 × 5
6 × 6
6 × 6
6 × 6
6 × 6
6 × 6
6 × 6
6 × 6
6 × 6
6 × 6
4 × 4
4 × 4
4 × 4
4 × 4
4 × 4
Coilcraft XAL5030-102
XAL5030-122
XAL5030-222
XAL5030-332
XAL5030-562
XAL5030-682
XEL6030-102
XEL6030-152
XEL6030-222
XEL6030-332
XEL6060-472
XAL6060-562
XEL6060-682
XEL6060-822
XAL6060-103
1
14
8.7
7.9
7.2
5.9
5.3
4.7
12
10
7
6
9
7.5
7.3
7
8.5
1.2
2.2
3.3
5.6
6.8
1
1.5
2.2
3.3
4.7
5.6
6.8
8.2
10
1
12.5
9.2
8.7
6.3
6
18.5
14.9
12.6
10
11.4
9.9
7.9
7.6
7.6
9.6
8.8
8.5
8
11.4
13.2
21.2
23.45
26.75
6.32
9.57
12.7
19.92
13.65
14.46
20.82
22.71
27
5
Wurth
744 383 570 10
744 383 570 12
744 383 570 15
744 383 570 18
744 383 570 22
7.4
7
6.2
5.8
5.2
11.6
13.4
17.1
18
1.2
1.5
1.8
2.2
7
22
Rev. 0 | Page 19 of 29
ADP5003
Data Sheet
COMPENSATION COMPONENTS DESIGN
JUNCTION TEMPERATURE
For the peak current mode control architecture, the power stage
can be simplified as a voltage controlled current source that
supplies current to the output capacitor and load resistor. The
simplified loop is composed of one dominant pole and a zero
contributed by the output capacitor ESR.
In cases where the ambient temperature (TA) is known, the
thermal resistance parameter (θJA) can estimate the junction
temperature rise (TJ). TJ is calculated with TA and the power
dissipation (PD) using the following formula:
TJ = TA + (PD × θJA)
(13)
The ADP5003 uses a transconductance amplifier as the error
amplifier to compensate the system. Figure 43 shows the
simplified peak current mode control, small signal circuit.
The typical θJA value for the 32-lead, 5 mm × 5 mm LFCSP is
46.91°C/W. An important factor to consider is that θJA is based
on a 4-layer, 4 inches × 3 inches, 2.5 ounces copper PCB, as per
the JEDEC standard, and applications may use different sizes
and layers. It is important to maximize the copper used to
remove the heat from the device. Copper exposed to air
dissipates heat better than copper used in the inner layers.
Connect the exposed pad to the ground plane with several vias.
V
V
V
REFOUT
VOUT1
VOUT1
R
TOP
C
V
OUT
ESR
–
gm
COMP
+
–
A
VI
V
A
BUCK
SET1
R
+
R
C
C
CP
R
R
BOT
C
If the case temperature can be measured, the junction
temperature is calculated by
C
TJ = TC + (PD × θJC)
where:
TC is the case temperature.
(14)
Figure 43. Simplified Peak Current Mode Control, Small Signal Circuit
The compensation components, RC and CC, contribute a zero,
and the optional CCP and RC contribute an optional pole.
θJC is the junction to case thermal resistance provided in Table 6.
The following procedure shows how to select the compensation
components (RC, CC, and CCP) for ceramic output capacitor
applications:
To achieve reliable operation of the buck converter and LDO
regulator, the estimated die junction temperature of the
ADP5003 must be less than 125°C. Reliability and mean time
between failures (MTBF) is highly affected by increasing the
junction temperature. Additional information about product
reliability can be found in the Analog Devices, Inc., Reliability
Handbook at www.analog.com/reliability_handbook.
1. Determine the cross frequency (fC). Generally, fC is
between fSW/12 and fSW/6.
2. Use the following equation to calculate RC:
2× π× fC ×COUT × ABUCK
RC =
The total power dissipation in the ADP5003 simplifies to
gm × AVI
(10)
PD = PDBUCK + PDLDO
where:
(15)
where:
COUT is the output capacitance.
P
P
DBUCK = (VPVIN1 × IPVIN1) − (VVOUT1 × IVOUT1).
DLDO = ((VPVIN2 − VPVOUT2) × IPVOUT2) + (VPVIN2 × IGND).
AVI = 7 A /V.
3. Place the compensation zero at the domain pole (fP).
Determine CC as follows:
CC = ((R + RESR) × COUT)/RC
(11)
(12)
where:
RESR is the equivalent series resistance of the output
capacitor.
4.
C
CP is optional. It can cancel the zero caused by the ESR of
the output capacitor. Determine CCP as follows:
CCP = (RESR × COUT)/RC
Rev. 0 | Page 20 of 29
Data Sheet
ADP5003
BUCK REGULATOR DESIGN EXAMPLE
This section provides an example of the step by step design
procedures and the external components required for the buck
regulator. Table 10 lists the design requirements for this
example.
SELECTING THE INDUCTOR FOR THE BUCK
REGULATOR
The peak-to-peak inductor ripple current, ΔIL, is set to 35% of
the maximum output current. Use Equation 8 to estimate the
value of the inductor:
Table 10. Example Design Requirements for the Buck Regulator
Parameter
Specification
L = ((VPVIN1 − VVOUT1) × D)/(ΔIL × fSW)
Input Voltage
Output Voltage
Output Current
Output Ripple
Load Transient
VPVIN1 = 12 V
VVOUT1 = 2.5 V
IVOUT1 = 3 A
ΔVOUT1_RIPPLE = 25 mV
5% at 20% to 80% load transient
where:
V
V
PVIN1 = 12 V.
VOUT1 = 2.5 V.
D is the duty cycle (D = VVOUT1/VPVIN1).
ΔIL = 35% × 3 A = 1.05 A.
f
SW = 600 kHz.
SETTING THE SWITCHING FREQUENCY FOR THE
BUCK REGULATOR
The resulting value for L is 3.14 µH. The selected standard
inductor value is 3.3 µH; therefore, ΔIL is 1 A.
The first step is to determine the switching frequency for the
ADP5003 design. In general, higher switching frequencies
produce a smaller solution size due to the lower component
values required, whereas lower switching frequencies result in
higher conversion efficiency due to lower switching losses.
To calculate the peak inductor current (IPEAK), use Equation 9:
IPEAK = IVOUT1 + (ΔIL/2)
The calculated peak current for the inductor is 3.5 A.
SELECTING THE OUTPUT CAPACITOR FOR THE
BUCK REGULATOR
The switching frequency of the ADP5003 can be set from
0.3 MHz to 2.5 MHz by connecting a resistor from the RT pin
to ground. The selected resistor allows the user to make decisions
based on the trade-off between efficiency and solution size. (For
more information, see the Oscillator Frequency Control section.)
However, the highest supported switching frequency must be
assessed by checking the voltage conversion limitations enforced
by the minimum on time and the minimum off time (see the
Voltage Conversion Limitations section).
The output capacitor must meet the output voltage ripple and
load transient requirements. To meet the output voltage ripple
requirement, use Equation 7 to calculate the capacitance:
ΔIL
COUT_MIN
≅
8× fSW ×(VRIPPLE
—
ΔIL ×RESR )
The calculated capacitance, COUT_MIN, is 8.7 µF.
To meet the 5% overshoot and undershoot requirements, use
the following equations to calculate the capacitance:
In this design example, a switching frequency of 600 kHz is
used to achieve an ideal combination of small solution size and
high conversion efficiency. To set the switching frequency to
600 kHz, use Equation 1 to calculate the resistor value, RRT:
K
UV × ΔISTEP 2 ×L
COUT_UV
=
=
(17)
(18)
2× VPVIN1 − VVOUT1 × ΔVOUT_UV
R
RT (kΩ) = 1.78 × 1011/fSW (kHz)
K
OV × ΔISTEP 2 ×L
COUT_OV
2
2
Therefore, select standard resistor RT = 294 kΩ.
V
VOUT1 + ΔVOUT_OV
− VVOUT1
SETTING THE OUTPUT VOLTAGE FOR THE BUCK
REGULATOR
where:
UV and KOV are factors (typically set to 2).
ΔISTEP is the load step.
K
Select a value for the top resistor (RTOP) and then calculate the
bottom feedback (RBOT) resistor by using the following equation:
ΔVOUT_UV is the allowable undershoot on the output voltage.
ΔVOUT_OV is the allowable overshoot on the output voltage.
RBOT = (RTOP × VVOUT1)/((VREFOUT × ABUCK) − VVOUT1
)
(16)
For estimation purposes, use KOV = KUV = 2; therefore,
where:
C
OUT_OV = 33.4 µF and COUT_UV = 9 µF.
V
V
A
VOUT1 is the buck output voltage.
REFOUT is 2 V.
BUCK is the buck regulator gain.
It is recommended to use two 22 µF ceramic capacitors.
To set the output voltage to 2.5 V, RTOP is set to 100 kΩ, giving
an RBOT value of 100 kΩ.
Rev. 0 | Page 21 of 29
ADP5003
Data Sheet
Figure 45 shows the load transient waveform.
DESIGNING THE COMPENSATION NETWORK FOR
THE BUCK REGULATOR
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this example, fSW is set to 600 kHz;
therefore, fC is set to 60 kHz.
V
VOUT1
4
2 × π × 44 μF × 60 kHz ×2.5
RC =
CC =
= 9.87 kΩ
= 3.72 nF
600 μS × 7 A/V
I
VOUT1
(
)
0.833 Ω + 0.001 Ω × 44 μF
1
7.18 kΩ
0.001 Ω × 44 μF
= = 4.46 pF
CCP
7.18 kΩ
CH1 1.00AB CH4 100mV
200µs
T
A CH3
1.38A
B
W
W
508µs
Choose standard components: RC = 9.76 kΩ, CC = 4.7 nF,
CP = 4.7 pF.
Figure 45. 0.6 A to 2.4 A Load Transient for 2.5 V Output
C
Figure 44 shows the Bode plot for the 2.5 V output rail. The
cross frequency is 66.1 kHz, and the phase margin is 51.1°.
SELECTING THE INPUT CAPACITOR FOR THE BUCK
REGULATOR
200
150
100
50
100
For the input capacitor, select a ceramic capacitor with a
minimum capacitance of 10 µF. Place the input capacitor close
to the PVIN1 pin. In this example, one 10 µF, X5R, 25 V
ceramic capacitor is recommended.
80
60
40
51.1°
20
0
0
66.1kHz
–20
–40
–60
–80
–100
–50
–100
–150
–200
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 44. Bode Plot for 2.5 V Output Rail
Rev. 0 | Page 22 of 29
Data Sheet
ADP5003
ADAPTIVE HEADROOM CONTROL DESIGN EXAMPLE
This section provides an example of the step by step design
procedures and the external components required for the buck
regulator using adaptive headroom control. Table 11 lists the
design requirements for this example.
SELECTING THE INDUCTOR FOR THE BUCK
REGULATOR USING ADAPTIVE HEADROOM
CONTROL
The peak-to-peak inductor ripple current, ΔIL, is set to 35% of
the maximum output current. Use the Equation 8 to estimate
the value of the inductor:
Table 11. Example Design Requirements for the Buck
Regulator Using Adaptive Headroom Control
Parameter
Specification
L = ((VPVIN1 – VVOUT1) × D)/(ΔIL × fSW)
Input Voltage
VPVIN1 = 12 V
VPVOUT2 = 1.3 V
IVOUT1 = IPVOUT2 = 3 A
100 mV at 20% to 80% load transient
where:
Output Voltage
Output Current
Buck Load Transient
V
V
V
V
PVIN1 = 12 V.
VOUT1 = VPVOUT2 + VHR = 1.7 V.
PVOUT2 = 1.3 V.
HR is the adaptive headroom voltage at steady state current. See
SETTING THE SWITCHING FREQUENCY FOR THE
BUCK REGULATOR USING ADAPTIVE HEADROOM
CONTROL
Table 4 and Figure 24 for the approximate values of VHR vs. load
current. For this example, use VHR equal to 0.4 V for steady state
load current of 3 A.
D is the duty cycle (D = VVOUT1/VPVIN1).
ΔIL = 35% × 3 A = 1.05 A.
Similar to the buck design example, a switching frequency of
600 kHz is used to achieve a good combination of small solution
size and high conversion efficiency. To set the switching frequency
to 600 kHz, use Equation 1 to calculate the resistor value, RRT:
fSW = 600 kHz.
The resulting value for L is 2.32 µH. The selected standard
inductor value is 2.2 µH; therefore, ΔIL is 1.1 A.
R
RT (kΩ) = 1.78 × 1011/fSW (kHz)
Therefore, select standard resistor RT = 294 kΩ.
To calculate the peak inductor current (IPEAK), use Equation 9:
SETTING THE OUTPUT VOLTAGE FOR THE BUCK
REGULATOR USING ADAPTIVE HEADROOM
CONTROL
I
PEAK = IVOUT1 + (ΔIL/2)
The calculated peak current for the inductor is 3.55 A.
SELECTING THE OUTPUT CAPACITORS FOR THE
BUCK REGULATOR USING ADAPTIVE HEADROOM
CONTROL
Select a value for the top feedback resistor (RTOP) and then calculate
the bottom resistor (RBOT) by using the following equation:
RBOT = (RTOP × VPVOUT2)/((VREFOUT × ALDO) – VPVOUT2
)
(19)
To ensure that the LDO regulator does not track the buck
output, the undershoot voltage must be set to a value less than
the minimum adaptive headroom voltage. Use Equation 17 and
Equation 18 to calculate the capacitance.
where:
V
V
A
PVOUT2 is the LDO output voltage.
REFOUT is 2 V.
LDO is the LDO regulator gain.
For estimation purposes, use KOV = KUV = 2; therefore,
OUT_OV = 40.7 µF and COUT_UV = 6.92 µF.
To set the output voltage to 1.3 V, RTOP is set to 100 kΩ giving an
BOT value of 65 kΩ.
C
R
It is recommended to use a single 47 µF ceramic capacitor for the
output of the buck and a single 10 µF for the output of the LDO.
Rev. 0 | Page 23 of 29
ADP5003
Data Sheet
DESIGNING THE COMPENSATION NETWORK FOR
THE BUCK REGULATOR USING ADAPTIVE
HEADROOM CONTROL
I
PVOUT2
Due to the addition of the adaptive headroom scheme in the
feedback loop, a lower bandwidth is required. Set the crossover
frequency, fC, to fSW/60. In this example, fSW is set to 600 kHz;
therefore, fC is set to 10 kHz.
2
3
4
V
VOUT1
2 × π × 47 μF ×10 kHz ×2.5
V
PVOUT2
RC =
= 1.76 kΩ
= 15.2 nF
600 μS × 7 A/V
(
)
0.433 Ω + 0.001 Ω × 47 μF
CC =
B
CH2 1.00A
CH4 20.0mV
CH3 200mV
M200µs
A CH2
1.08A
1.76 kΩ
W
B
T
432.000µs
W
0.001 Ω × 47 μF
Figure 46. 0.6 A to 2.4 A Load Transient for 2.5 V Output
CCP
= = 26.7 pF
1.76 kΩ
SELECTING THE INPUT CAPACITOR FOR THE BUCK
REGULATOR USING ADAPTIVE HEADROOM
CONTROL
Choose standard components: RC = 1.74 kΩ, CC = 22 nF,
CP = 22 pF.
Figure 46 shows the load transient waveform.
C
For the input capacitor, select a ceramic capacitor with a
minimum value of 10 µF. Place the input capacitor close to the
PVIN1 pin. In this example, one 10 µF, X5R, 25 V ceramic
capacitor is recommended.
Rev. 0 | Page 24 of 29
Data Sheet
ADP5003
RECOMMENDED BUCK EXTERNAL COMPONENTS FOR THE BUCK REGULATOR
Table 12 lists the recommended buck external components for buck applications up to 3 A operation ( 5% tolerance at an ~60% step
transient), and Table 13 lists the recommended buck external components for adaptive headroom applications up to 3 A operation
(VPVOUT2 100 mV at an ~60% step transient).
Table 12. Recommended Buck External Components for Buck Applications up to 3 A Operation ( 5% Tolerance at an ~60% Step Transient)
fSW (kHz)
VIN (V)
12
12
12
12
12
12
12
5
5
5
5
5
VOUT (V)
L (µH)
3.3
4.7
4.7
5.6
6.8
8.2
10
COUT (µF)
210
204.7
147
110
69
RTOP1 (kΩ)
200
150
174
150
100
49.9
0
200
150
174
150
100
49.9
150
150
100
49.9
0
200
150
174
150
100
49.9
100
49.9
0
200
150
174
150
100
49.9
RBOT1 (kΩ)
49.9
47.5
75
84.5
100
97.6
open
49.9
47.5
75
84.5
100
97.6
84.5
84.5
100
97.6
Open
49.9
47.5
75
84.5
100
97.6
100
97.6
Open
49.9
47.5
75
RC (kΩ)
23.7
23.2
16.5
12.4
7.68
5.23
3.01
23.7
16.5
14.7
10.5
5.23
5.76
15.4
15.4
7.15
6.04
4.99
21
CC (nF)
3.3
3.3
4.7
4.7
6.8
10
CCP (pF)
300
1
10
10
10
10
10
10
10
10
10
10
10
10
1.2
1.5
1.8
2.5
3.3
5
47
26.7
210
147
132
94
47
51.7
69
69
32
26.7
22
94
147
49.2
47
23
24.2
22
22
22
69
47
15
1
3.3
3.3
4.7
4.7
4.7
4.7
2.2
3.3
3.3
4.7
5.6
1.5
1.8
1.8
2.2
2.2
2.2
2.2
3.3
3.3
1
3.3
3.3
4.7
4.7
6.8
10
1.2
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
5
5
10
600
12
12
12
12
12
5
5
5
5
5
2.2
2.2
3.3
4.7
6.8
1.5
1.5
2.2
2.2
3.3
4.7
2.2
3.3
4.7
1
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.7
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
1
1.2
1.5
1.8
2.5
3.3
2.5
3.3
5
33.2
11
10.5
5.11
5.49
8.25
8.25
8.25
25.5
17.4
12.1
8.66
8.25
8.25
5
1000
12
12
12
5
5
5
5
5
5
1
1.2
1.5
1.8
2.5
3.3
1
1
1.2
1.2
1.5
1.2
32
23
22
22
1.5
1.5
2.2
3.3
84.5
100
97.6
Table 13. Recommended Buck External Components for Adaptive Headroom Applications up to 3 A Operation (VPVOUT2 100 mV
at an ~60% Step Transient)
fSW (kHz)
VIN (V)
VOUT2 (V)
L (µH)
COUT1 (µF)
RC (kΩ)
1.74
1.65
2.15
1.74
1.74
1.65
1.21
1.21
1.65
1.65
CC (nF)
CCP (pF)
RTOP2 (kΩ)
Short
37.4
100
100
100
Short
37.4
100
100
RBOT2 (kΩ)
Open
118
121
64.9
49.9
Open
118
121
64.9
COUT2 (µF)
600
12
12
12
12
12
5
5
5
5
5
3.3
2.5
1.8
1.3
1.1
3.3
2.5
1.8
4.7
3.3
3.3
2.2
1.8
1.5
1.8
1.8
47
44
57
47
47
44
32
32
44
44
33
22
22
22
10
33
22
22
22
22
22
22
22
22
22
22
10
10
10
10
10
10
10
10
10
10
1.3
1.1
1.8
1.5
22
10
22
22
100
49.9
Rev. 0 | Page 25 of 29
ADP5003
Data Sheet
BUCK CONFIGURATIONS
INDEPENDENT
80
70
The buck and LDO regulators can operate independently of
each other (see Figure 48) to provide two voltage rails from a
single supply. In this way, the buck regulator can provide an
intermediate supply rail for the LDO regulator with a fixed
headroom voltage between the buck output voltage and the
LDO output voltage. The LDO regulator acts to filter the
voltage ripple and switching noise generated by the buck
regulator for noise sensitive supplies. Where additional filtering
is required, a second stage LC filter can be added between the
buck output and the LDO input. Because the regulators are
independently operated to provide a single voltage rail, the PSRR
and efficiency can be configured as required by the application
by either setting a lower headroom voltage for greater efficiency
or a higher headroom voltage for greater PSRR.
60
50
40
30
20
10
0
ADAPTIVE HEADROOM CONTROL
INDEPENDENT, 150mV HEADROOM
INDEPENDENT, 500mV HEADROOM
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (A)
Figure 47. Independent Efficiency vs. Load Current for
Adaptive Headroom Control
VPVIN1: 12V
PVIN1
EN1
10µF
VOUT1
SW1
4.7nF
9.76kΩ COMP1
BUCK
V
= 2.5V
33µH
44µF
PVOUT1
REGULATOR
3A
100kΩ
PGND1
VSET1
1µF
VREG
RT
294kΩ
1µF
VPVINSYS: 12V
PVINSYS
PWRGD
SYNC
SYSTEM
10µF
ANALOG DEVICES
RF TRANSCEIVER,
HIGH SPEED
ADC/DAC, CLOCK,
ASIC/PROCESSOR
REFOUT
100kΩ
PVIN2
VSET2
10µF
64.9kΩ
VBUF
LOW NOISE
LDO ACTIVE
FILTER
V
= 1.3V
PVOUT2
10µF
PVOUT2
0.1µF
3A
VREG_LDO
1µF
EN2
VFB2P
VFB2N
AGND1
AGND2
Figure 48. Independent Configuration (Dual Output)
Rev. 0 | Page 26 of 29
Data Sheet
ADP5003
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
ADAPTIVE HEADROOM
0.2V, 1A
LDO PSRR
= 12V, V
0.28V, 1.5A
0.35V, 2A
0.4V, 2.5A
0.4V, 3A
V
= 0.9V
PVOUT2
PVIN1
The ADP5003 features a scheme to control the buck regulator
output voltage and thus the LDO headroom voltage to provide
better efficiency with the same noise performance of a standalone
LDO regulator. When the buck regulator uses the adaptive
headroom control configuration, the ADP5003 manages the
buck regulator output voltage vs. the LDO load current (see
Figure 24). The adaptive headroom control also optimizes the
LDO headroom when the remote sense feedback corrects the
significant output voltage drop due to additional filtering or
the high trace impedance under the high load conditions. The
headroom profile of the adaptive headroom control is set to
deliver a consistent PSRR across the load range while optimizing
efficiency of the overall system (see Figure 49). To enable adaptive
headroom control, connect VSET1 to VREG (see Figure 50).
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 49. LDO PSRR vs. Frequency
V
PVIN1: 12V
PVIN1
PVIN1
10µF
EN1
VOUT1
L1
2.2µH
V
SW1
SW1
SW1
2.2nF
PVOUT1
(ADAPTIVE)
1.74kΩ
COMP1
VSET1
BUCK
REGULATOR
3A
47µF
PGND1
PGND1
PGND1
1µF
VREG
294kΩ
RT
VPVINSYS: 12V
PVINSYS
10µF
PWRGD
SYNC
SYSTEM
REFOUT
100kΩ
64.9kΩ
PVIN2
PVIN2
PVIN2
VSET2
VBUF
10µF
10µF
PVOUT2
PVOUT2
PVOUT2
LOW NOISE
LDO ACTIVE
FILTER
V
= 1.3V
VPOUT2
0.1µF
ANALOG DEVICES
RF TRANSCEIVER,
HIGH SPEED ADC/DAC,
CLOCK, ASIC/
3A
VREG_LDO
PROCESSOR
1µF
EN2
VFB2P
VFB2N
AGND1
AGND2
Figure 50. Adaptive Headroom Configuration
Rev. 0 | Page 27 of 29
ADP5003
Data Sheet
LAYOUT CONSIDERATIONS
Layout is important for all switching regulators but is
particularly important for regulators with high switching
frequencies. To achieve high efficiency, proper regulation,
stability, and low noise, a well designed PCB layout is required.
Follow these guidelines when designing PCBs:
Route the VFB2P and VFB2N LDO sense traces together
connecting them at the point of load. Keep them as short
as possible and away from noise sources.
Place the frequency setting resistor close to the RT pin.
Keep AGND1 and PGND1 separate on the top layer of the
board. This separation avoids pollution of AGND1 with
switching noise. Do not connect PGND1 to the EPAD on
the top layer of the layout. Connect both AGND1 and
PGND1 to the board ground plane with vias. Ideally,
connect PGND1 to the plane at a point between the input
and output capacitors.
Keep high current loops as short and wide as possible.
Keep the input bypass capacitors close to the PVIN1,
PVIN2, and PVINSYS pins.
Keep the inductor and output capacitor close to SW1
and PGND1.
Connect the negative terminal of CVBUF to the VFB2N pin.
13.2mm
L1
PVIN
C
PVINSYS
10µF
C
PVIN1
10µF
50V/X5R
1206
35V/X5R
0805
C
VREG
1µF
10V/X5R
0406
C
VOUT1
22µF
25V/X5R
1206
0201
24
1
2
3
23
22
21
0402
0402
4
5
ADP5003
20
19
18
17
6
7
0201
C
REFOUT
0.22µF
10V/X5R
0402
8
C
PVIN2
0201
10µF
50V/X5R
1206
C
1µF
PVOUT2
VREG_LDO
10V/X5R
0402
C
PVOUT2
10µF
25V/X5R
0805
C
0.1µF
VBUF
10V/X5R
0402
Figure 51. Example Outline Layout
Rev. 0 | Page 28 of 29
Data Sheet
ADP5003
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
25
24
32
1
INDICATOR
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
16
8
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 52. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
Package Description
Package Option
CP-32-7
ADP5003ACPZ-R7
ADP5003CP-EVALZ
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15021-0-11/17(0)
Rev. 0 | Page 29 of 29
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