EVAL-AD1833AEB [ADI]
24-Bit, 192 kHz, DAC; 24位192 kHz时， DAC
| 型号： | EVAL-AD1833AEB |
| 厂家： | 
ADI |
| 描述： | 24-Bit, 192 kHz, DAC |
| 文件： | 总20页 (文件大小：645K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multichannel,
24-Bit, 192 kHz, ꢀ-ꢁ DAC
AD1833A
FUNCTIONAL BLOCK DIAGRAM
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant Digital
Interface
ZERO FLAGS
AV
DD
DV
DV
DD2
DD1
Supports 96 kHz Sample Rates on 6 Channels and
192 kHz on 2 Channels
Supports 16-/20-/24-Bit Word Lengths
Multibit ꢀ-ꢁ Modulators with
OUTLP1
OUTLN1
CDATA
CLATCH
CCLK
INTERPOLATOR
DAC
DAC
DAC
DAC
SPI
PORT
OUTLP2
OUTLN2
INTERPOLATOR
Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least Sensitive to
Jitter
Differential Output for Optimum Performance
DACs Signal-to-Noise and Dynamic Range: 110 dB
–94 dB THD + N—6-Channel Mode
–95 dB THD + N—2-Channel Mode
On-Chip Volume Control per Channel with 1024-Step
Linear Scale
MCLK
OUTLP3
OUTLN3
INTERPOLATOR
INTERPOLATOR
INTERPOLATOR
INTERPOLATOR
RESET
FILTER
ENGINE
OUTRP3
OUTRN3
L/RCLK
BCLK
SDIN1
SDIN2
SDIN3
SOUT
OUTRP2
OUTRN2
DATA
PORT
DAC
DAC
OUTRP1
OUTRN1
AD1833A
Software Controllable Clickless Mute
Digital De-emphasis Processing
FILTR FILTD
DGND
AGND
Supports 256 ꢂ fS, 512 ꢂ fS, and 768 ꢂ fS Master
Clock Modes
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified,
Left-Justified, I2S Compatible, and DSP Serial Port Modes
Supports Packed Data Mode and TDM Mode
48-Lead LQFP Plastic Package
The AD1833A is fully compatible with all known DVD formats,
accommodating word lengths of up to 24 bits at sample rates of
48 kHz and 96 kHz on all six channels while supporting a 192 kHz
sample rate on two channels. It also provides the Redbook stan-
dard 50 ms/15 ms digital de-emphasis filters at sample rates of
32 kHz, 44.1 kHz, and 48 kHz.
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Set-Top Boxes
The AD1833A has a very flexible serial data input port that
allows glueless interconnection to a variety of ADCs, DSP chips,
AES/EBU receivers, and sample rate converters. It can be con-
figured in right-justified, left-justified, I2S, or DSP serial port
compatible modes. The AD1833A accepts serial audio data in MSB
first, twos complement format. The AD1833A can be operated
from a single 5 V power supply; it also features a separate supply
pin for its digital interface that allows it to be interfaced to devices
using 3.3 V power supplies.
Digital Audio Effects Processors
GENERAL DESCRIPTION
The AD1833A is a complete, high performance, single-chip,
multichannel, digital audio playback system. It features six audio
playback channels, each comprising a high performance digital
interpolation filter, a multibit S-D modulator featuring Analog
Devices’ patented technology, and a continuous-time voltage-out
analog DAC section. Other features include an on-chip clickless
attenuator and mute capability for each channel, programmed
through an SPI compatible serial control port.
The AD1833A is fabricated on a single monolithic integrated
circuit and is housed in a 48-lead LQFP package for operation
from –40∞C to +85∞C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD1833A–SPECIFICATIONS
TEST CONDITIONS, UNLESS OTHERWISE NOTED*
Supply Voltages (AVDD, DVDDX
Ambient Temperature
Input Clock
)
5 V
25∞C
12.288 MHz, (8ꢂ Mode)
Nominally 1 kHz, 0 dBFS
(Full-Scale)
48 kHz
20 Hz to 20 kHz
24 Bits
Input Signal
Input Sample Rate
Measurement Bandwidth
Word Width
Load Capacitance
Load Impedance
100 pF
10 kW
*Performance is identical for all channels (except for the Interchannel Gain
Mismatch and Interchannel Phase Deviation specifications).
Parameter
Min
Typ
Max
Unit
Test Conditions
ANALOG PERFORMANCE
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input)
with A-Weighted Filter
AD1833AA
AD1833AA
AD1833AC
Total Harmonic Distortion + Noise
106.5
110.0
110.5
107.0
–95
–94
–95
–94
110
108
dB
dB
dB
dB
dB
dB
dB
dB
dB
fS = 96 kHz
–89
Two channels active
Six channels active
96 kHz, two channels active
96 kHz, six channels active
SNR
Interchannel Isolation
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
± 3
%
%
ppm/∞C
0.2
80
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Volume Control Step Size (1023 Linear Steps)
Volume Control Range (Max Attenuation)
Mute Attenuation
–120
± 0.1
0.098
+63.5 (0.098)
–63.5 (0.098)
± 0.1
1 (2.8)
150
2.2
dB
Degrees
%
dB (%)
dB (%)
dB
V rms (V p-p)
De-emphasis Gain Error
Full-Scale Output Voltage at Each Pin (Single-Ended)
Output Resistance Measured Differentially
Common-Mode Output Volts
W
V
DAC INTERPOLATION FILTER—8ϫ Mode (48 kHz)
Pass Band
21.768 kHz
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
± 0.01
dB
kHz
dB
ms
24
70
510
DAC INTERPOLATION FILTER—4ϫ Mode (96 kHz)
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
37.7
kHz
dB
kHz
dB
± 0.03
55.034
70
Group Delay
160
ms
DAC INTERPOLATION FILTER—2ϫ Mode (192 kHz)
Pass Band
89.954 kHz
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
± 1
dB
kHz
dB
ms
104.85
70
Group Delay
140
REV. 0
–2–
AD1833A
Parameter
Min
Typ
Max
Unit
Test Conditions
DIGITAL I/O
Input Voltage HI
Input Voltage LO
Output Voltage HI
Output Voltage LO
2.4
V
V
V
V
0.8
0.4
DVDD2 – 0.4
POWER SUPPLIES
Supply Voltage (AVDD and DVDD1
Supply Voltage (DVDD2
Supply Current IANALOG
Supply Current IDIGITAL
)
4.5
3.3
5
5.5
DVDD1
42
V
V
mA
mA
mA
)
38.5
42
2
48
Active
Power-Down
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
–60
–50
dB
dB
Specifications subject to change without notice.
(Guaranteed over –40ꢃC to +85ꢃC, AV = DV = 5 V ꢄ 10%)
DIGITAL TIMING
DD
DD
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
tML
MCLK LO (All Modes)*
MCLK HI (All Modes)*
PD/RST LO
15
15
20
ns
ns
ns
24 MHz clock, clock doubler bypassed
24 MHz clock, clock doubler bypassed
tMH
tPDR
SPI PORT
tCCH
tCCL
tCCP
tCDS
tCDH
tCLS
tCLH
CCLK HI Pulsewidth
CCLK LO Pulsewidth
CCLK Period
CDATA Setup Time
CDATA Hold Time
CLATCH Setup
20
20
80
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK rising
CLATCH Hold
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDDS
tDDH
BCLK HI
BCLK LO
L/RCLK Setup
L/RCLK Hold
SDATA Setup
SDATA Hold
15
15
10
10
10
15
ns
ns
ns
ns
ns
ns
To BCLK rising
From BCLK rising
To BCLK rising
From BCLK rising
TDM MODE MASTER
tTMBD
BCLKTDM Delay
20
10
ns
ns
ns
ns
From MCLK rising
tTMFSD
tTMDDS
tTMDDH
FSTDM Delay
SDIN1 Setup
SDIN1 Hold
From BCLKTDM rising
To BCLKTDM falling
From BCLKTDM falling
15
15
TDM MODE SLAVE
fTSB
BCLKTDM Frequency
256 ϫ fS
20
20
10
10
tTSBCH
tTSBCL
tTSFS
tTSFH
tTSDDS
tTSDDH
BCLKTDM High
BCLKTDM Low
FSTDM Setup
FSTDM Hold
SDIN1 Setup
ns
ns
ns
ns
ns
ns
To BCLKTDM falling
From BCLKTDM falling
To BCLKTDM falling
From BCLKTDM falling
15
15
SDIN1 Hold
AUXILIARY INTERFACE
tAXLRD
tAXDD
tAXBD
L/RCLK Delay
Data Delay
AUXBCLK Delay
10
10
20
ns
ns
ns
From BCLK falling
From BCLK falling
From MCLK rising
*MCLK symmetry must be better than 60:40 or 40:60.
Specifications subject to change without notice.
REV. 0
–3–
AD1833A
tMH
MCLK
tML
PD/RST
tPDR
Figure 1. MCLK and RESET Timing
tCLS
tCLH
tCCH tCCL
tCCP
CLATCH
CCLK
CIN
tCDS tCDH
D9
D8
D15
D14
D0
Figure 2. SPI Port Timing
tDBH
BCLK
tDBL
tDLS
tDLH
L/RCLK
tDDS
SDATA
LEFT-JUSTIFIED
MODE
MSB
tDDH
MSB-1
tDDS
MSB
tDDH
SDATA
I2S MODE
tDDS
MSB
tDDH
tDDS
LSB
SDATA
RIGHT-JUSTIFIED
MODE
tDDH
Figure 3. Serial Port Timing
MCLK
tTMBD
tTSBCL
tTSBCH
BCLKTDM
tTMFSD
FSTDM
tTSFS
tTSFH
tTMDDS
tTMDDH
SDIN1
MSB
tTSDDS
tTSDDH
Figure 4. TDM Master and Slave Mode Timing
–4–
REV. 0
AD1833A
MCLK
tAXBD
AUXBCLK
tAXLRD
AUXL/RCLK
tAXDD
MSB
AUX DATA
Figure 5. Auxiliary Interface Timing
ABSOLUTE MAXIMUM RATINGS*
(TA = 25∞C, unless otherwise noted.)
LQFP, qJA Thermal Impedance . . . . . . . . . . . . . . . . . 91∞C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
AVDD, DVDDX to AGND, DGND . . . . . . . . –0.3 V to +6.5 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD2 + 0.3 V
Analog I/O Voltage to AGND . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ORDERING GUIDE
Package Description
Model
Temperature Range
Package Option
AD1833AAST
AD1833ACST
EVAL-AD1833AEB
AD1833AAST-REEL
AD1833ACST-REEL
–40∞C to +85∞C
–40∞C to +85∞C
Low Profile Quad Flat Package
Low Profile Quad Flat Package
Evaluation Board
Low Profile Quad Flat Package
Low Profile Quad Flat Package
ST-48
ST-48
–40∞C to +85∞C
–40∞C to +85∞C
ST-48
ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD1833A
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
REV. 0
–5–
AD1833A
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
2
OUTLP1
OUTLN1
36
35
34
33
32
31
30
29
28
27
26
25
OUTRP1
OUTRN1
PIN 1
IDENTIFIER
3
AV
DD
AV
DD
AGND
AGND
AGND
DGND
AV
DD
AV
DD
AGND
AGND
AGND
DGND
4
5
AD1833A
TOP VIEW
(Not to Scale)
6
7
8
9
DV
DV
DD1
DD2
10
11
12
ZEROA
ZERO3R
ZERO3L
RESET
ZERO1L
ZERO1R
13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Description
Pin No.
Mnemonic IN/OUT
1
2
OUTLP1
OUTLN1
AVDD
O
O
DAC 1 Left Channel Positive Output.
DAC 1 Left Channel Negative Output.
Analog Supply.
3, 4, 33, 34, 44
5, 6, 7, 30, 31, 32, 41 AGND
Analog Ground.
8, 29
9
DGND
DVDD1
Digital Ground.
Digital Supply to Core Logic.
10
11
12
13
14
15
16
17
ZEROA
ZERO3R
ZERO3L
ZERO2R
CLATCH
CDATA
CCLK
O
O
O
O
I
I
I
I/O
Flag to Indicate Zero Input on All Channels.
Flag to Indicate Zero Input on Channel 3 Right.
Flag to Indicate Zero Input on Channel 3 Left.
Flag to Indicate Zero Input on Channel 2 Right.
Latch Input for Control Data (SPI Port).
Serial Control Data Input (SPI Port).
Clock Input for Control Data (SPI Port).
L/RCLK
Left/Right Clock for DAC Data Input; FSTDM Input in TDM Slave Mode;
FSTDM Output in TDM Master Mode.
18
BCLK
I/O
Bit Clock for DAC Data Input; BCLKTDM Input in TDM Slave Mode; BCLKTDM
Output in TDM Master Mode.
19
20
21
MCLK
SDIN1
SDIN2
I
I
I/O
Master Clock Input.
Data Input for Channel 1 Left/Right (Data Stream Input in TDM and Packed Modes).
Data Input for Channel 2 Left/Right (L/RCLK Output to Auxiliary DAC in
TDM Mode).
22
23
24
25
26
27
28
35
36
37
38
39
SDIN3
SOUT
ZERO2L
ZERO1R
ZERO1L
RESET
I/O
O
O
O
O
I
Data Input for Channel 3 Left/Right (BCLK Output to Auxiliary DAC in TDM Mode).
Auxiliary I2S Output (Available in TDM Mode).
Flag to Indicate Zero Input on Channel 2 Left.
Flag to Indicate Zero Input on Channel 1 Right.
Flag to Indicate Zero Input on Channel 1 Left.
Power-Down and Reset Control.
Power Supply to Output Interface Logic.
DAC 1 Right Channel Negative Output.
DAC 1 Right Channel Positive Output.
DAC 2 Right Channel Negative Output.
DVDD2
OUTRN1
OUTRP1
OUTRN2
OUTRP2
OUTRN3
O
O
O
O
O
DAC 2 Right Channel Positive Output.
DAC 3 Right Channel Negative Output.
REV. 0
–6–
AD1833A
PIN FUNCTION DESCRIPTIONS (continued)
Pin No.
Mnemonic IN/OUT
Description
40
42
OUTRP3
FILTR
O
DAC 3 Right Channel Positive Output.
Reference/Filter Capacitor Connection. Recommend 0.1 mF/10 mF decouple to
analog ground.
43
45
46
47
48
FILTD
Filter Capacitor Connection. Recommend 0.1 mF/10 mF decouple to analog ground.
DAC 3 Left Channel Positive Output.
DAC 3 Left Channel Negative Output.
DAC 2 Left Channel Positive Output.
DAC 2 Left Channel Negative Output.
OUTLP3
OUTLN3
OUTLP2
OUTLN2
O
O
O
O
DEFINITION OF TERMS
Dynamic Range
Gain Error
With a near full-scale input, the ratio of actual output to expected
The ratio of a full-scale input signal to the integrated input noise in
the pass band (20 Hz to 20 kHz), expressed in decibels. Dynamic
range is measured with a –60 dB input signal and is equal to
(S/[THD + N]) +60 dB. Note that spurious harmonics are below
the noise with a –60 dB input, so the noise level establishes the
dynamic range. The dynamic range is specified with and without
an A-Weight filter applied.
output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
Gain Drift
Change in response to a nearly full-scale input with a change in
temperature, expressed as parts-per-million (ppm/∞C).
Signal to (Total Harmonic Distortion + Noise)
[S/(THD + N)]
The ratio of the root-mean-square (rms) value of the fundamental
input signal to the rms sum of all other spectral components in
the pass band, expressed in decibels.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply Rejection
Pass Band
With no analog input, signal present at the output when a
300 mV p-p signal is applied to the power supply pins, expressed
in decibels of full scale.
The region of the frequency spectrum unaffected by the attenuation
of the digital decimator’s filter.
Pass-Band Ripple
Group Delay
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band, expressed
in decibels.
Intuitively, the time interval required for an input pulse to appear
at the converter’s output, expressed in ms. More precisely, the
derivative of radian phase with respect to the radian frequency at
a given frequency.
Stop Band
The region of the frequency spectrum attenuated by the digital
decimator’s filter to the degree specified by stop-band attenuation.
Group Delay Variation
The difference in group delays at different input frequencies.
Specified as the difference between the largest and the smallest
group delays in the pass band, expressed in ms.
REV. 0
–7–
–Typical Performance Characteristics
AD1833A
0.010
0.008
0.006
0.004
0.002
0
0.10
0.08
0.06
0.04
0.02
0
–0.002
–0.004
–0.006
–0.008
–0.02
–0.04
–0.06
–0.08
–0.10
–0.010
0
0.2
0.4
0.6
0.8
1.0
Hz
1.2
1.4
1.6
1.8
2.0
4
0
0.5
1.0
1.5
2.0
Hz
2.5
3.0
3.5
4
ꢂ10
ꢂ10
TPC 1. Pass-Band Response, 8ϫ Mode
TPC 4. Pass-Band Response, 4ϫ Mode
10
0.5
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.5
1.0
1.5
2.0
Hz
2.5
3.0
3.5
4.0
4
2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50
4
ꢂ10
Hz
ꢂ10
TPC 2. Transition Band Response, 8ϫ Mode
TPC 5. 40 kHz Pass-Band Response, 4
ϫ
Mode
10
0
0
–20
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40
–60
–80
–100
–120
–140
–160
0
0.5
1.0
1.5
Hz
2.0
2.5
3.0
ꢂ10
4.0
4.2
4.4
4.6
4.8
5.0
Hz
5.2
5.4
5.6
5.8
6.0
4
5
ꢂ10
TPC 3. Complete Response, 8ϫ Mode
TPC 6. Transition Band Response, 4ϫ Mode
REV. 0
–8–
AD1833A
10
0
0
–20
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40
–60
–80
–100
–120
–140
–160
0
0.5
1.0
1.5
Hz
2.0
2.5
3.0
5
0.80
0.85
0.90
0.95
1.00
Hz
1.05
1.10
1.15
1.20
5
ꢂ10
ꢂ10
TPC 7. Complete Response, 4ϫ Mode
TPC 9. Transition Band Response, 2ϫ Mode
2.0
1.5
0
–20
1.0
–40
0.5
–60
0
–80
–0.5
–1.0
–1.5
–2.0
–100
–120
–140
–160
0
1
2
3
4
5
6
7
8
0
0.5
1.0
1.5
2.0
4
Hz
ꢂ10
5
ꢂ10
Hz
TPC 8. 80 kHz Pass-Band Response, 2ϫ Mode
TPC 10. Complete Response, 2ϫ Mode
REV. 0
–9–
AD1833A
FUNCTIONAL DESCRIPTION
rate, only one doubling stage is used. In each case, the input
sample frequency is increased to 384 kHz (IMCLK/64). The
ZOH holds the interpolator samples for upsampling by the
modulator. This is done at a rate 16 times the interpolator
output sample rate.
Device Architecture
The AD1833A is a six-channel audio DAC featuring multibit
sigma-delta (S-D) technology. The AD1833A features three stereo
converters (providing six channels); each stereo channel is con-
trolled by a common bit-clock (BCLK) and synchronization
signal (L/RCLK).
Modulator
The modulator is a 6-bit, second order implementation and uses
data scrambling techniques to achieve perfect linearity. The modu-
lator samples the output of the interpolator stage(s) at a rate of
(IMCLK/4).
General Overview
The AD1833A is designed to run with an internal MCLK
(IMCLK) of 24.576 MHz and a modulator rate of 6.144 MHz
(i.e., IMCLK/4). From this IMCLK frequency, sample rates of
48 kHz and 96 kHz can be achieved on six channels or 192 kHz
can be achieved on two channels. The internal clock should never
be run at a higher frequency but may be reduced to achieve
lower sampling rates, i.e., for a sample rate of 44.1 kHz, the appro-
priate internal MCLK is 22.5792 MHz. The modulator rate scales
in proportion with the MCLK scaling.
OPERATING FEATURES
SPI Register Definitions
The SPI port allows flexible control of the device’s programmable
functions. It is organized around nine registers: six individual channel
volume registers and three control registers. Each write operation
to the AD1833A SPI control port requires 16 bits of serial data
in MSB-first format. The four most significant bits are used to
select one of nine registers (seven register addresses are reserved),
and the bottom 10 bits are written to that register. This allows a
write to one of the nine registers in a single 16-bit transaction. The
SPI CCLK signal is used to clock in the data. The incoming
data should change on the falling edge of this signal and remain
valid during the rising edge. At the end of the 16 CCLK periods,
the CLATCH signal should rise to latch the data internally into
the AD1833A (see Figure 2).
Interpolator
The interpolator consists of as many as three stages of sample
rate doubling and half-band filtering followed by a 16-sample
zero order hold (ZOH). The sample rate doubling is achieved
by zero stuffing the input samples, and a digital half-band filter
is used to remove any images above the band of interest and to
bring the zero samples to their correct values.
The interpolator output must always be at a rate of IMCLK/64.
Depending on the interpolation rates selected, one, two, or all
three stages of doubling may be switched in. This allows for
three different sample rate inputs for any given IMCLK. For an
IMCLK of 24.576 MHz, all three doubling stages are used with
a 48 kHz input sample rate; with a 96 kHz input sample rate, only
two doubling stages are used; and with a 192 kHz input sample
The serial interface format used on the control port uses a 16-bit
serial word, as shown in Table I. The 16-bit word is divided into
several fields: Bits 15 through 12 define the register address, Bits 11
and 10 are reserved and must be programmed to 0, and Bits 9
through 0 are the data field (which has specific definitions,
depending on the register selected).
Table I. Control Port Map
Register Address
14 13
Reserved1
11 10
Data Field
152
12
9
8
7
6
5
4
3
2
1
0
NOTES
1Must be programmed to zero.
2Bit 15 = MSB.
Bit 15 Bit 14 Bit 13
Bit 12
Register Function
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC Control 1
DAC Control 2
DAC Volume 1
DAC Volume 2
DAC Volume 3
DAC Volume 4
DAC Volume 5
DAC Volume 6
DAC Control 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
REV. 0
–10–
AD1833A
Table II. DAC Control Register 1
Function
Data-Word
Width
Power-Down
RESET
Interpolator
Mode
Address
15–12
0000
Reserved1
De-emphasis
9–8
Serial Mode
7–5
000 = I2S
001 = RJ
010 = DSP
11
10
4–3
2
1–0
0
0
00 = None
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = Normal
1 = PWRDWN
00 = 8ϫ(48 kHz)2
01 = 2ϫ(192 kHz)2
10 = 4ϫ(96 kHz)2
11 = Reserved
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
011 = LJ
100 = Pack Mode 1 (256)
101 = Pack Mode 2 (128)
110 = TDM Mode
111 = Reserved
NOTES
1Must be programmed to zero.
2For IMCLK = 24.576 MHz.
DAC CONTROL REGISTER 1
DAC Word Width
De-emphasis
The AD1833A will accept input data in three separate word-
lengths—16 bits, 20 bits, and 24 bits. The word length may be
selected by writing to Control Bits 4 and 3 in DAC Control
Register 1 (see Table V).
The AD1833A has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
Redbook 50 ms/15 ms emphasis response curve. Three curves are
available, one each for 32 kHz, 44.1 kHz, and 48 kHz sampling
rates. The filters may be selected by writing to Control Bits 9
and 8 in DAC Control Register 1 (see Table III).
Table V. Word Length Settings
Bit 4
Bit 3
Word Length
Table III. De-emphasis Settings
0
0
1
1
0
1
0
1
24 Bits
20 Bits
16 Bits
Reserved
Bit 9
Bit 8
De-emphasis
0
0
1
1
0
1
0
1
Disabled
44.1 kHz
32 kHz
Power-Down Control
The AD1833A can be powered down by writing to Control Bit 2
in DAC Control Register 1 (see Table VI).
48 kHz
Data Serial Interface Mode
The AD1833A’s serial data interface is designed to accept data
in a wide range of popular formats including I2S, right-justified
(RJ), left-justified (LJ), and flexible DSP modes. The L/RCLK
pin acts as the word clock (or frame sync) to indicate sample
interval boundaries. The BCLK defines the serial data rate
while the data is input on the SDIN1–SDIN3 pins. The serial
mode settings may be selected by writing to Control Bits 7
through 5 in the DAC Control Register 1 (see Table IV).
Table VI. Power-Down Control
Bit 2
Power-Down Setting
0
1
Normal Operation
Power-Down Mode
Interpolator Mode
The AD1833A’s DAC interpolators can be operated in one of
three modes—8ϫ, 4ϫ, or 2ϫ— then correspond to 48 kHz, 96 kHz,
and 192 kHz modes, respectively(for IMCLK = 24.576 MHz). The
interpolator mode may be selected by writing to Control Bits 1
and 0 in DAC Control Register 1 (see Table VII).
Table IV. Data Serial Interface Mode Settings
Bit 7
Bit 6
Bit 5
Serial Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I2S
Table VII. Interpolator Mode Settings
Right Justify
DSP
Left Justify
Packed Mode 1 (256)
Packed Mode 2 (128)
TDM Mode
Reserved
Bit 1
Bit 0
Interpolator Mode
0
0
1
1
0
1
0
1
8x (48 kHz)*
2x (192 kHz)*
4x (96 kHz)*
Reserved
*For IMCLK = 24.576 MHz.
REV. 0
–11–
AD1833A
DAC CONTROL REGISTER 2
DAC CONTROL REGISTER 3
DAC Control Register 2 contains individual channel mute
controls for each of the six DACs. Default operation (bit = 0) is
muting off. Bits 9 through 6 of Control Register 2 are reserved
and should be programmed to zero (see Table VIII).
Stereo Replicate
The AD1833A allows the stereo information on Channel 1
(SDIN1—Left 1 and Right 1) to be copied to Channels 2 and 3
(Left/Right 2 and Left/Right 3). These signals can be used in an
external summing amplifier to increase potential signal SNR.
Stereo replicate mode can be enabled by writing to control Bit 5
(see Table XI). Note that replication is not reflected in the zero
flag status.
Table VIII. DAC Control Register 2
Function
Mute Control
Address
15–12
Reserved*
Reserved*
11
10
9–6
5
4
3
2
1
0
0001
0
0
0
Channel 6
Channel 5
Channel 4
Channel 3
Channel 2
Channel 1
0 = Mute Off
1 = Mute On
0 = Mute Off 0 = Mute Off 0 = Mute Off
1 = Mute On 1 = Mute On 1 = Mute On
0 = Mute Off 0 = Mute Off
1 = Mute On 1 = Mute On
*Must be programmed to zero.
Table IX. Muting Control
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Muting
X
X
X
X
X
1
X
X
X
X
1
X
X
X
1
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
Mute Channel 1
Mute Channel 2
Mute Channel 3
Mute Channel 4
Mute Channel 5
Mute Channel 6
X
X
X
X
X
X
Table X. DAC Control Register 3
Function
Stereo Replicate
(192 kHz)
Address
15–12
Reserved* Reserved
*
MCLK Select
4–3
Zero Detect
2
Reserved
*
TDM Mode
11 10
9–6
5
1
0
1000
0
0
0
0 = Normal
1 = Replicate
00 = IMCLK = MCLK
01 = IMCLK = MCLK
ϫ
ϫ
2
1
/
0 = Active High
1 = Active Low
0
0 = Master
1 = Slave
10 = IMCLK = MCLK ϫ 2
3
*Must be programmed to zero.
Table XI. Stereo Replicate
Stereo Mode
Normal
Bit 5
0
1
Channel 1 Data Replicated on Channels 2 and 3
REV. 0
–12–
AD1833A
MCLK Select
The AD1833A allows the matching of available external MCLK
frequencies to the required internal MCLK rate. The MCLK
modification factor can be selected from 2, 1, or 2/3 by writing to
Bit 4 and Bit 3 of Control Register 3. Internally, the AD1833A
requires an MCLK of 24.576 MHz for sample rates of 48 kHz,
96 kHz, and 192 kHz. In the case of 48 kHz data with an
MCLK of 256 ϫ fS, a clock doubler is used, whereas with an
MCLK of 768 ϫ fS, a divide-by-3 block (Ϭ3) is first implemented
followed by a clock doubler. With an MCLK of 512 ϫ fS, the
MCLK is passed through unmodified (see Table XII).
a global zero flag that indicates all channels contain zero data.
The polarity of the zero signal is programmable by writing to
Control Bit 2 (see Table XIII). In right-justified mode, the six
individual channel flags are best used as three stereo zero flags
by combining pairs of them through suitable logic gates. Then,
when both the left and right inputs are zero for 1024 clock cycles,
i.e., a stereo zero input for 1024 sample periods, the combined
result of the two individual flags will become active, indicat-
ing a stereo zero.
Table XIII. Zero Detect
Table XII. MCLK Settings
Bit 2
Channel Zero Status
Bit 4
Bit 3
Modification Factor
0
1
Active High
Active Low
0
0
1
1
0
1
0
1
MCLK ϫ 2 Internally
MCLK ϫ 1 Internally
2
DAC Volume Control Registers
MCLK ϫ /3 Internally
The AD1833A has six volume control registers, one for each of
the six DAC channels. Volume control is exercised by writing to
the relevant register associated with each DAC. This setting is
used to attenuate the DAC output. Full-scale setting (all 1s) is
equivalent to zero attenuation (see Table XV).
Reserved
Channel Zero Status
The AD1833A provides individual logic output status indicators
when zero data is sent to a channel for 1024 or more consecutive
sample periods in all modes except right-justified. There is also
Table XIV. MCLK vs. Sample Rate Selection
Suitable External MCLK Frequencies (MHz)
Sampling Rate
fS (kHz)
Interpolator Mode Internal MCLK
MCLK ꢂ 2
MCLK ꢂ 1
MCLK ꢂ 2/3
Required
Required (MHz)
32
64
128
8ϫ
4ϫ
2ϫ
16.384
8192
16.384
24.576
44.1
88.2
176.4
8ϫ
4ϫ
2ϫ
22.5792
24.576
11.2896
12.288
22.5792
24.576
33.8688
36.864
48
96
192
8ϫ
4ϫ
2ϫ
Table XV. Volume Control Registers
Address
15–12
Reserved*
Volume Control
9–0
11
10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
Channel 1 Volume Control (OUTL1)
Channel 2 Volume Control (OUTR1)
Channel 3 Volume Control (OUTL2)
Channel 4 Volume Control (OUTR2)
Channel 5 Volume Control (OUTL3)
Channel 6 Volume Control (OUTR3)
*Must be programmed to zero.
REV. 0
–13–
AD1833A
I2S Timing
to clock in the data. The first bit of data appears on the SDINx
lines when the L/RCLK toggles. The data is written MSB first
and is valid on the rising edge of the bit clock.
I2S timing uses an L/RCLK to define when the data being trans-
mitted is for the left channel and when it is for the right channel.
The L/RCLK is low for the left channel and high for the right
channel. A bit clock running at 64 ϫ fS is used to clock in the data.
There is a delay of 1 bit clock from the time the L/RCLK signal
changes state to the first bit of data on the SDINx lines. The data
is written MSB first and is valid on the rising edge of the bit clock.
Right-Justified Timing
Right-justified (RJ) timing uses an L/RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/RCLK is high for the left channel and
low for the right channel. A bit clock running at 64 ϫ fS is used
to clock in the data. The first bit of data appears on the SDINx
8-bit clock periods (for 24-bit data) after L/RCLK toggles. In RJ
mode, the LSB of data is always clocked by the last bit clock
before L/RCLK transitions. The data is written MSB first and is
valid on the rising edge of the bit clock.
Left-Justified Timing
Left-justified (LJ) timing uses an L/RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/RCLK is high for the left channel and
low for the right channel. A bit clock running at 64 ꢂ fS is used
L/RCLK
RIGHT CHANNEL
LEFT CHANNEL
INPUT
BCLK
INPUT
SDATA
INPUT
MSB MSB
–1 –2
LSB LSB
+2 +1
MSB MSB
–1 –2
LSB LSB
+2 +1
MSB
LSB
MSB
LSB
MSB
Figure 6. I 2S Timing Diagram
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB MSB
–1 –2
LSB LSB
+2 +1
MSB MSB
MSB
LSB LSB
+2 +1
MSB
–1
MSB
LSB
LSB
MSB
–1
–2
Figure 7. Left-Justified Timing Diagram
L/RCLK
INPUT
LEFT CHANNEL
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB MSB
–1 –2
LSB LSB
+2 +1
MSB MSB
MSB
LSB LSB
+2 +1
LSB
MSB
LSB
LSB
–1
–2
Figure 8. Right-Justified Timing Diagram
REV. 0
–14–
AD1833A
TDM Mode Timing—Interfacing to a SHARC®
DACR0. The data is written on the rising edge of the bit clock
and read by the AD1833A on the falling edge of the bit clock.
The left and right data destined for the auxiliary DAC is sent in
standard I2S format in the next frame using the SDIN2, SDIN3,
and SOUT pins as the L/RCLK, BCLK, and SDATA pins,
respectively, for communicating with the auxiliary DAC.
In TDM mode, the AD1833A can be the master or slave, depend-
ing on Bit 0 in Control Register 3. In master mode, it generates a
frame sync signal (FSTDM) on its L/RCLK pin and a bit clock
(BCLKTDM) on its BCLK pin, whereas in slave mode it expects
these signals to be provided. These signals are used to control
the data transmission from the SHARC. The bit clock must run
at a frequency of IMCLK/2 and the interpolation mode must be
set to 8ϫ, which limits TDM mode to frequencies of 48 kHz or
less. In this mode, all data is written on the rising edge of the bit
clock and read on the falling edge of the bit clock. The frame
starts with a frame sync at the rising edge of the bit clock. The
SHARC then starts outputting data on the next rising edge of
the bit clock. Each channel is given a 32-bit clock slot, and the
data is left-justified and uses 16, 20, or 24 of the 32 bits. An
enlarged diagram detailing this is provided (see Figure 9). The
data is sent from the SHARC to the AD1833A on the SDIN1
pin and provided in the following order: MSB first—Internal
DACL0, Internal DACL1, Internal DACL2, AUX DACL0,
Internal DACR0, Internal DACR1, Internal DACR2, and AUX
DSP Mode Timing
DSP mode timing uses the rising edge of the frame sync signal
on the L/RCLK pin to denote the start of the transmission of a
data-word. Note that for both left and right channels, a rising
edge is used; therefore in this mode, there is no way to determine
which data is intended for the left channel and which is intended
for the right. The DSP writes data on the rising edge of BCLK
and the AD1833A reads it on the falling edge. The DSP raises
the frame sync signal on the rising edge of BCLK and then proceeds
to transmit data, MSB first, on the next rising edge of BCLK.
The data length can be 16, 20, or 24 bits. The frame sync signal
can be brought low any time at or after the MSB is transmitted,
but must be brought low at least one BCLK period before the
start of the next channel transmission.
FSTDM
BCLKTDM
INTERNAL
DAC L0
INTERNAL
DAC L1
INTERNAL
DAC L2
AUXILIARY
DAC L0
INTERNAL
DAC R0
INTERNAL
DAC R1
INTERNAL
DAC R2
AUXILIARY
DAC R0
BCLKTDM
MSB
MSB MSB
–2 –3
MSB
–4
LSB
+8
LSB
+7
LSB
+6
LSB
+5
LSB
+4
LSB
+3
LSB
+2
LSB
+1
MSB
LSB
24-BIT DATA
–1
MSB
–1
MSB MSB
–2 –3
MSB
–4
LSB
+4
LSB
+3
LSB
+2
LSB
+1
20-BIT DATA
16-BIT DATA
MSB
MSB
LSB
MSB
–1
MSB MSB
MSB
–4
LSB
–2
–3
Figure 9. TDM Mode Timing
L/RCLK
BCLK
MSB
–1
MSB
–2
MSB
–3
MSB
–4
MSB
–5
MSB
–6
MSB
–1
MSB
–2
MSB
–3
MSB
–4
MSB
–5
MSB
–6
SDATA
MSB
MSB
MSB
32 BCLKs
32 BCLKs
Figure 10. DSP Mode Timing
–15–
REV. 0
AD1833A
Packed Mode 128
Packed Mode 256
In Packed Mode 128, all six data channels are packed into one
sample interval on one data pin. The BCLK runs at 128 ϫ fS;
therefore, there are 128 BCLK periods in each sample interval.
Each sample interval is broken into eight time slots: six slots of
20 BCLK and two of 4 BCLK. In this mode, the data length is
restricted to a maximum of 20 bits. The three left channels are
written first, MSB first, and the data is written on the falling
edge of BCLK. After the three left channels are written, there is
a space of four BCLK, and then the three right channels are writ-
ten. The L/RCLK defines the left and right data transmission; it
is high for the three left channels and low for the three right channels.
In Packed Mode 256, all six data channels are packed into one
sample interval on one data pin. The BCLK runs at 256 ϫ fS;
therefore, there are 256 BCLK periods in each sample interval, and
each sample interval is broken into eight time slots of 32 BCLK
each. The data length can be 16, 20, or 24 bits. The three left
channels are written first, MSB first, and the data is written on the
falling edge of BCLK with a one BCLK period delay from the
start of the slot. After the three left channels are written, there is
a space of 32 BCLK, and then the three right channels are written.
The L/RCLK defines the left and right data transmission; it is
low for the three left channels and high for the three right channels.
L/RCLK
BCLK
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
BLANK SLOT
4 SCLK
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
BLANK SLOT
4 SCLK
DATA
BCLK
MSB MSB
MSB MSB
–3 –4
LSB
+4
LSB
+3
LSB
+2
LSB
+1
MSB
MSB
LSB
20-BIT DATA
16-BIT DATA
–1
–2
MSB MSB
–1 –2
MSB MSB
–3 –4
LSB
Figure 11. Packed Mode 128
L/RCLK
BCLK
DATA
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
BCLK
MSB MSB
–1 –2
MSB MSB
–3 –4
LSB
+8
LSB
+7
LSB
+6
LSB
+5
LSB
+4
LSB
+3
LSB
+2
LSB
+1
MSB
LSB
24-BIT DATA
20-BIT DATA
MSB MSB
–1 –2
MSB MSB
–3 –4
LSB
+4
LSB
+3
LSB
+2
LSB
+1
MSB
MSB
LSB
MSB MSB
–1 –2
MSB MSB
–3 –4
LSB
16-BIT DATA
Figure 12. Packed Mode 256
–16–
REV. 0
AD1833A
0
68pF
NPO
11kꢅ
–20
V
OUT–
3.81kꢅ
11kꢅ
–40
–60
270pF
NPO
6
604ꢅ
7
100pF
NPO
OP275
VFILT
OUT
560pF
NPO
2.2nF
NPO
5
–80
1.50kꢅ
V
OUT+
5.62kꢅ
150pF
NPO
5.62kꢅ
–100
–120
–140
0
20
40
60
80
100
120
kHz
Figure 13. Suggested Output Filter Schematic
Figure 16. Dynamic Range for 37 kHz @ –60 dBFS,
110 dB, Triangular Dithered Input
0
0
–20
–20
–40
–60
–40
–60
–80
–80
–100
–100
–120
–140
–120
–140
0
20
40
60
80
100
120
0
2
4
6
8
10
12
14
16
18
20
kHz
kHz
Figure 14. Dynamic Range for 1 kHz @ –60 dBFS,
110 dB, Triangular Dithered Input
Figure 17. Input 0 dBFS @ 37 kHz, BW 20 Hz to
120 kHz, SR 96 kHz, THD + N –95 dBFS
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
–140
–140
–160
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
kHz
kHz
Figure 15. Input 0 dBFS @ 1 kHz, BW 20 Hz to
20 kHz, SR 48 kHz, THD + N –95 dBFS
Figure 18. Noise Floor for Zero Input, SR 48 kHz,
SNR 110 dBFS A-Weighted
REV. 0
–17–
AD1833A
–60
–20
–30
–40
–50
–70
–80
–60
–70
–90
–80
–100
–90
–100
–110
–120
–110
–120
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
dBFS
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
dBFS
0
Figure 19. THD + N Amplitude vs. Input Amplitude,
Input 1 kHz, SR 48 kHz, 24-Bit
Figure 20. THD + N Ratio vs. Input Amplitude,
Input 1 kHz, SR 48 kHz, 24-Bit
REV. 0
–18–
AD1833A
DV
–INTF
AV
5V
DD
DD
10ꢆF
5V
+
0.1ꢆF
10ꢆF
10ꢆF
+
0.1ꢆF
+
10ꢆF
0.1ꢆF
+
0.1ꢆF
10ꢆF
10ꢆF
10ꢆF
+
+
DV
DD
0.1ꢆF
+
0.1ꢆF
0.1ꢆF
AV
22
0.1ꢆF
DD
9 28
4 33 3 34 44
10ꢆF
14
15
16
1
2
47
48
45
46
CLATCH
CDATA
CCLK
CLATCH
CDATA
CCLK
OUTLP1
OUTLN1
L1+
L1–
L2+
L2–
L3+
L3–
7
OUTLP2
OUTLN2
10nF
10nF
26
11
12
19
9
SDATA
FSYNC
SCK
RXP
17
18
20
21
22
23
19
OUTLP3
OUTLN3
L/RCLK
BCLK
SDIN1
SDIN2
SDIN3
SOUT
MCLK
75RO
MCK
10
20
36
35
38
37
40
39
PAL
RXN
FILT
AD1833A
R1+
R1–
R2+
R2–
R3+
R3–
OUTRP1
OUTRN1
OUTRP2
OUTRN2
23
24
18
17
M0
M1
M2
M3
DIR-CS8414
OUTRP3
OUTRN3
1
1kꢅ
C
U
CBL
VERF
ERF
14
15
28
25
42
43
FILTR
FILTD
47nF
+
+
6
10ꢆF
0.1ꢆF
10ꢆF
0.1ꢆF
CO/EO
CA/E1
8
29
7 30 6 31 5 32 41
5
21
8
AGND
DGND
4
CB/E2
3
CC/F0
2
CD/F1
27
16
CE/F2
SEL
13
CS12/FCK
5V
L5
0.1ꢆF
10kꢅ
3
5
SHLD1
SHLD1
6
OUT
1
U5
TORX173
2
4
SHLD1
SHLD1
Figure 21. Example Digital Interface
REV. 0
–19–
AD1833A
OUTLINE DIMENSIONS
48-Lead Low Profile Quad Flat Package [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
1.60 MAX
PIN 1
INDICATOR
0.75
0.60
0.45
9.00 BSC
37
48
36
1
SEATING
PLANE
1.45
1.40
1.35
0.20
0.09
7.00
BSC
TOP VIEW
(PINS DOWN)
VIEW A
7ꢃ
3.5ꢃ
0ꢃ
0.15
0.05
25
12
SEATING
PLANE
24
0.08 MAX
13
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90ꢃ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
REV. 0
–20–
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